diff options
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/zynq/Makefile | 4 | ||||
| -rw-r--r-- | drivers/clk/zynq/clkc.c | 616 | ||||
| -rw-r--r-- | drivers/clk/zynq/pll.c | 230 | ||||
| -rw-r--r-- | drivers/clk/zynqmp/Kconfig | 10 | ||||
| -rw-r--r-- | drivers/clk/zynqmp/Makefile | 4 | ||||
| -rw-r--r-- | drivers/clk/zynqmp/clk-gate-zynqmp.c | 143 | ||||
| -rw-r--r-- | drivers/clk/zynqmp/clk-mux-zynqmp.c | 167 | ||||
| -rw-r--r-- | drivers/clk/zynqmp/clk-zynqmp.h | 97 | ||||
| -rw-r--r-- | drivers/clk/zynqmp/clkc.c | 803 | ||||
| -rw-r--r-- | drivers/clk/zynqmp/divider.c | 321 | ||||
| -rw-r--r-- | drivers/clk/zynqmp/pll.c | 347 |
11 files changed, 2742 insertions, 0 deletions
diff --git a/drivers/clk/zynq/Makefile b/drivers/clk/zynq/Makefile new file mode 100644 index 000000000..a5bb696de --- /dev/null +++ b/drivers/clk/zynq/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Zynq clock specific Makefile + +obj-y += clkc.o pll.o diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c new file mode 100644 index 000000000..7bdeaff2b --- /dev/null +++ b/drivers/clk/zynq/clkc.c @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Zynq clock controller + * + * Copyright (C) 2012 - 2013 Xilinx + * + * Sören Brinkmann <soren.brinkmann@xilinx.com> + */ + +#include <linux/clk/zynq.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/io.h> + +static void __iomem *zynq_clkc_base; + +#define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00) +#define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04) +#define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08) +#define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c) +#define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20) +#define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24) +#define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28) +#define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c) +#define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40) +#define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44) +#define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48) +#define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c) +#define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50) +#define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54) +#define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58) +#define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c) +#define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60) +#define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64) +#define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68) +#define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70) +#define SLCR_621_TRUE (zynq_clkc_base + 0xc4) +#define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204) + +#define NUM_MIO_PINS 54 + +#define DBG_CLK_CTRL_CLKACT_TRC BIT(0) +#define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1) + +enum zynq_clk { + armpll, ddrpll, iopll, + cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, + ddr2x, ddr3x, dci, + lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, + sdio0, sdio1, uart0, uart1, spi0, spi1, dma, + usb0_aper, usb1_aper, gem0_aper, gem1_aper, + sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, + i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, + smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; + +static struct clk *ps_clk; +static struct clk *clks[clk_max]; +static struct clk_onecell_data clk_data; + +static DEFINE_SPINLOCK(armpll_lock); +static DEFINE_SPINLOCK(ddrpll_lock); +static DEFINE_SPINLOCK(iopll_lock); +static DEFINE_SPINLOCK(armclk_lock); +static DEFINE_SPINLOCK(swdtclk_lock); +static DEFINE_SPINLOCK(ddrclk_lock); +static DEFINE_SPINLOCK(dciclk_lock); +static DEFINE_SPINLOCK(gem0clk_lock); +static DEFINE_SPINLOCK(gem1clk_lock); +static DEFINE_SPINLOCK(canclk_lock); +static DEFINE_SPINLOCK(canmioclk_lock); +static DEFINE_SPINLOCK(dbgclk_lock); +static DEFINE_SPINLOCK(aperclk_lock); + +static const char *const armpll_parents[] __initconst = {"armpll_int", + "ps_clk"}; +static const char *const ddrpll_parents[] __initconst = {"ddrpll_int", + "ps_clk"}; +static const char *const iopll_parents[] __initconst = {"iopll_int", + "ps_clk"}; +static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"}; +static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"}; +static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate", + "can0_mio_mux"}; +static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate", + "can1_mio_mux"}; +static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", + "dummy_name"}; + +static const char *const dbgtrc_emio_input_names[] __initconst = { + "trace_emio_clk"}; +static const char *const gem0_emio_input_names[] __initconst = { + "gem0_emio_clk"}; +static const char *const gem1_emio_input_names[] __initconst = { + "gem1_emio_clk"}; +static const char *const swdt_ext_clk_input_names[] __initconst = { + "swdt_ext_clk"}; + +static void __init zynq_clk_register_fclk(enum zynq_clk fclk, + const char *clk_name, void __iomem *fclk_ctrl_reg, + const char **parents, int enable) +{ + u32 enable_reg; + char *mux_name; + char *div0_name; + char *div1_name; + spinlock_t *fclk_lock; + spinlock_t *fclk_gate_lock; + void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; + + fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); + if (!fclk_lock) + goto err; + fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); + if (!fclk_gate_lock) + goto err_fclk_gate_lock; + spin_lock_init(fclk_lock); + spin_lock_init(fclk_gate_lock); + + mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); + if (!mux_name) + goto err_mux_name; + div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); + if (!div0_name) + goto err_div0_name; + div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); + if (!div1_name) + goto err_div1_name; + + clk_register_mux(NULL, mux_name, parents, 4, + CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, + fclk_lock); + + clk_register_divider(NULL, div0_name, mux_name, + 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, fclk_lock); + + clk_register_divider(NULL, div1_name, div0_name, + CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + fclk_lock); + + clks[fclk] = clk_register_gate(NULL, clk_name, + div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, + 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); + enable_reg = readl(fclk_gate_reg) & 1; + if (enable && !enable_reg) { + if (clk_prepare_enable(clks[fclk])) + pr_warn("%s: FCLK%u enable failed\n", __func__, + fclk - fclk0); + } + kfree(mux_name); + kfree(div0_name); + kfree(div1_name); + + return; + +err_div1_name: + kfree(div0_name); +err_div0_name: + kfree(mux_name); +err_mux_name: + kfree(fclk_gate_lock); +err_fclk_gate_lock: + kfree(fclk_lock); +err: + clks[fclk] = ERR_PTR(-ENOMEM); +} + +static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, + enum zynq_clk clk1, const char *clk_name0, + const char *clk_name1, void __iomem *clk_ctrl, + const char **parents, unsigned int two_gates) +{ + char *mux_name; + char *div_name; + spinlock_t *lock; + + lock = kmalloc(sizeof(*lock), GFP_KERNEL); + if (!lock) + goto err; + spin_lock_init(lock); + + mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); + div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); + + clk_register_mux(NULL, mux_name, parents, 4, + CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); + + clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); + + clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, + CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); + if (two_gates) + clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, + CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); + + kfree(mux_name); + kfree(div_name); + + return; + +err: + clks[clk0] = ERR_PTR(-ENOMEM); + if (two_gates) + clks[clk1] = ERR_PTR(-ENOMEM); +} + +static void __init zynq_clk_setup(struct device_node *np) +{ + int i; + u32 tmp; + int ret; + char *clk_name; + unsigned int fclk_enable = 0; + const char *clk_output_name[clk_max]; + const char *cpu_parents[4]; + const char *periph_parents[4]; + const char *swdt_ext_clk_mux_parents[2]; + const char *can_mio_mux_parents[NUM_MIO_PINS]; + const char *dummy_nm = "dummy_name"; + + pr_info("Zynq clock init\n"); + + /* get clock output names from DT */ + for (i = 0; i < clk_max; i++) { + if (of_property_read_string_index(np, "clock-output-names", + i, &clk_output_name[i])) { + pr_err("%s: clock output name not in DT\n", __func__); + BUG(); + } + } + cpu_parents[0] = clk_output_name[armpll]; + cpu_parents[1] = clk_output_name[armpll]; + cpu_parents[2] = clk_output_name[ddrpll]; + cpu_parents[3] = clk_output_name[iopll]; + periph_parents[0] = clk_output_name[iopll]; + periph_parents[1] = clk_output_name[iopll]; + periph_parents[2] = clk_output_name[armpll]; + periph_parents[3] = clk_output_name[ddrpll]; + + of_property_read_u32(np, "fclk-enable", &fclk_enable); + + /* ps_clk */ + ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); + if (ret) { + pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); + tmp = 33333333; + } + ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp); + + /* PLLs */ + clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, + SLCR_PLL_STATUS, 0, &armpll_lock); + clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], + armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, + SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); + + clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, + SLCR_PLL_STATUS, 1, &ddrpll_lock); + clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], + ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, + SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); + + clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, + SLCR_PLL_STATUS, 2, &iopll_lock); + clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], + iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, + SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); + + /* CPU clocks */ + tmp = readl(SLCR_621_TRUE) & 1; + clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, + CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, + &armclk_lock); + clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, + SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); + + clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], + "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); + + clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, + 1, 2); + clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], + "cpu_3or2x_div", CLK_IGNORE_UNUSED, + SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); + + clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, + 2 + tmp); + clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], + "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, + 26, 0, &armclk_lock); + clk_prepare_enable(clks[cpu_2x]); + + clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, + 4 + 2 * tmp); + clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], + "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, + 0, &armclk_lock); + + /* Timers */ + swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; + for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { + int idx = of_property_match_string(np, "clock-names", + swdt_ext_clk_input_names[i]); + if (idx >= 0) + swdt_ext_clk_mux_parents[i + 1] = + of_clk_get_parent_name(np, idx); + else + swdt_ext_clk_mux_parents[i + 1] = dummy_nm; + } + clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], + swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, + &swdtclk_lock); + + /* DDR clocks */ + clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, + SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); + clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], + "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); + clk_prepare_enable(clks[ddr2x]); + clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, + SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); + clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], + "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); + clk_prepare_enable(clks[ddr3x]); + + clk_register_divider(NULL, "dci_div0", "ddrpll", 0, + SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); + clk_register_divider(NULL, "dci_div1", "dci_div0", + CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &dciclk_lock); + clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", + CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, + &dciclk_lock); + clk_prepare_enable(clks[dci]); + + /* Peripheral clocks */ + for (i = fclk0; i <= fclk3; i++) { + int enable = !!(fclk_enable & BIT(i - fclk0)); + + zynq_clk_register_fclk(i, clk_output_name[i], + SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), + periph_parents, enable); + } + + zynq_clk_register_periph_clk(lqspi, clk_max, clk_output_name[lqspi], NULL, + SLCR_LQSPI_CLK_CTRL, periph_parents, 0); + + zynq_clk_register_periph_clk(smc, clk_max, clk_output_name[smc], NULL, + SLCR_SMC_CLK_CTRL, periph_parents, 0); + + zynq_clk_register_periph_clk(pcap, clk_max, clk_output_name[pcap], NULL, + SLCR_PCAP_CLK_CTRL, periph_parents, 0); + + zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], + clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, + periph_parents, 1); + + zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], + clk_output_name[uart1], SLCR_UART_CLK_CTRL, + periph_parents, 1); + + zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], + clk_output_name[spi1], SLCR_SPI_CLK_CTRL, + periph_parents, 1); + + for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { + int idx = of_property_match_string(np, "clock-names", + gem0_emio_input_names[i]); + if (idx >= 0) + gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, + idx); + } + clk_register_mux(NULL, "gem0_mux", periph_parents, 4, + CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, + &gem0clk_lock); + clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, + SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); + clk_register_divider(NULL, "gem0_div1", "gem0_div0", + CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &gem0clk_lock); + clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + SLCR_GEM0_CLK_CTRL, 6, 1, 0, + &gem0clk_lock); + clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], + "gem0_emio_mux", CLK_SET_RATE_PARENT, + SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); + + for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { + int idx = of_property_match_string(np, "clock-names", + gem1_emio_input_names[i]); + if (idx >= 0) + gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, + idx); + } + clk_register_mux(NULL, "gem1_mux", periph_parents, 4, + CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, + &gem1clk_lock); + clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, + SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); + clk_register_divider(NULL, "gem1_div1", "gem1_div0", + CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &gem1clk_lock); + clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + SLCR_GEM1_CLK_CTRL, 6, 1, 0, + &gem1clk_lock); + clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], + "gem1_emio_mux", CLK_SET_RATE_PARENT, + SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); + + tmp = strlen("mio_clk_00x"); + clk_name = kmalloc(tmp, GFP_KERNEL); + for (i = 0; i < NUM_MIO_PINS; i++) { + int idx; + + snprintf(clk_name, tmp, "mio_clk_%2.2d", i); + idx = of_property_match_string(np, "clock-names", clk_name); + if (idx >= 0) + can_mio_mux_parents[i] = of_clk_get_parent_name(np, + idx); + else + can_mio_mux_parents[i] = dummy_nm; + } + kfree(clk_name); + clk_register_mux(NULL, "can_mux", periph_parents, 4, + CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, + &canclk_lock); + clk_register_divider(NULL, "can_div0", "can_mux", 0, + SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); + clk_register_divider(NULL, "can_div1", "can_div0", + CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &canclk_lock); + clk_register_gate(NULL, "can0_gate", "can_div1", + CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, + &canclk_lock); + clk_register_gate(NULL, "can1_gate", "can_div1", + CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, + &canclk_lock); + clk_register_mux(NULL, "can0_mio_mux", + can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, + &canmioclk_lock); + clk_register_mux(NULL, "can1_mio_mux", + can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, + 0, &canmioclk_lock); + clks[can0] = clk_register_mux(NULL, clk_output_name[can0], + can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, + &canmioclk_lock); + clks[can1] = clk_register_mux(NULL, clk_output_name[can1], + can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, + 0, &canmioclk_lock); + + for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { + int idx = of_property_match_string(np, "clock-names", + dbgtrc_emio_input_names[i]); + if (idx >= 0) + dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, + idx); + } + clk_register_mux(NULL, "dbg_mux", periph_parents, 4, + CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, + &dbgclk_lock); + clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, + SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); + clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, + CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, + &dbgclk_lock); + clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], + "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, + 0, 0, &dbgclk_lock); + clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], + clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, + &dbgclk_lock); + + /* leave debug clocks in the state the bootloader set them up to */ + tmp = readl(SLCR_DBG_CLK_CTRL); + if (tmp & DBG_CLK_CTRL_CLKACT_TRC) + if (clk_prepare_enable(clks[dbg_trc])) + pr_warn("%s: trace clk enable failed\n", __func__); + if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) + if (clk_prepare_enable(clks[dbg_apb])) + pr_warn("%s: debug APB clk enable failed\n", __func__); + + /* One gated clock for all APER clocks. */ + clks[dma] = clk_register_gate(NULL, clk_output_name[dma], + clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, + &aperclk_lock); + clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, + &aperclk_lock); + clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, + &aperclk_lock); + clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, + &aperclk_lock); + clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, + &aperclk_lock); + clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, + &aperclk_lock); + clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, + &aperclk_lock); + clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, + &aperclk_lock); + clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, + &aperclk_lock); + clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, + &aperclk_lock); + clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, + &aperclk_lock); + clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, + &aperclk_lock); + clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, + &aperclk_lock); + clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, + &aperclk_lock); + clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, + &aperclk_lock); + clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, + &aperclk_lock); + clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, + &aperclk_lock); + clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], + clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, + &aperclk_lock); + + for (i = 0; i < ARRAY_SIZE(clks); i++) { + if (IS_ERR(clks[i])) { + pr_err("Zynq clk %d: register failed with %ld\n", + i, PTR_ERR(clks[i])); + BUG(); + } + } + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} + +CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); + +void __init zynq_clock_init(void) +{ + struct device_node *np; + struct device_node *slcr; + struct resource res; + + np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc"); + if (!np) { + pr_err("%s: clkc node not found\n", __func__); + goto np_err; + } + + if (of_address_to_resource(np, 0, &res)) { + pr_err("%pOFn: failed to get resource\n", np); + goto np_err; + } + + slcr = of_get_parent(np); + + if (slcr->data) { + zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; + } else { + pr_err("%pOFn: Unable to get I/O memory\n", np); + of_node_put(slcr); + goto np_err; + } + + pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base); + + of_node_put(slcr); + of_node_put(np); + + return; + +np_err: + of_node_put(np); + BUG(); +} diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c new file mode 100644 index 000000000..e5f8fb704 --- /dev/null +++ b/drivers/clk/zynq/pll.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Zynq PLL driver + * + * Copyright (C) 2013 Xilinx + * + * Sören Brinkmann <soren.brinkmann@xilinx.com> + */ +#include <linux/clk/zynq.h> +#include <linux/clk-provider.h> +#include <linux/slab.h> +#include <linux/io.h> + +/** + * struct zynq_pll - pll clock + * @hw: Handle between common and hardware-specific interfaces + * @pll_ctrl: PLL control register + * @pll_status: PLL status register + * @lock: Register lock + * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status + * register. + */ +struct zynq_pll { + struct clk_hw hw; + void __iomem *pll_ctrl; + void __iomem *pll_status; + spinlock_t *lock; + u8 lockbit; +}; +#define to_zynq_pll(_hw) container_of(_hw, struct zynq_pll, hw) + +/* Register bitfield defines */ +#define PLLCTRL_FBDIV_MASK 0x7f000 +#define PLLCTRL_FBDIV_SHIFT 12 +#define PLLCTRL_BPQUAL_MASK (1 << 3) +#define PLLCTRL_PWRDWN_MASK 2 +#define PLLCTRL_PWRDWN_SHIFT 1 +#define PLLCTRL_RESET_MASK 1 +#define PLLCTRL_RESET_SHIFT 0 + +#define PLL_FBDIV_MIN 13 +#define PLL_FBDIV_MAX 66 + +/** + * zynq_pll_round_rate() - Round a clock frequency + * @hw: Handle between common and hardware-specific interfaces + * @rate: Desired clock frequency + * @prate: Clock frequency of parent clock + * Return: frequency closest to @rate the hardware can generate. + */ +static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u32 fbdiv; + + fbdiv = DIV_ROUND_CLOSEST(rate, *prate); + if (fbdiv < PLL_FBDIV_MIN) + fbdiv = PLL_FBDIV_MIN; + else if (fbdiv > PLL_FBDIV_MAX) + fbdiv = PLL_FBDIV_MAX; + + return *prate * fbdiv; +} + +/** + * zynq_pll_recalc_rate() - Recalculate clock frequency + * @hw: Handle between common and hardware-specific interfaces + * @parent_rate: Clock frequency of parent clock + * Return: current clock frequency. + */ +static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynq_pll *clk = to_zynq_pll(hw); + u32 fbdiv; + + /* + * makes probably sense to redundantly save fbdiv in the struct + * zynq_pll to save the IO access. + */ + fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> + PLLCTRL_FBDIV_SHIFT; + + return parent_rate * fbdiv; +} + +/** + * zynq_pll_is_enabled - Check if a clock is enabled + * @hw: Handle between common and hardware-specific interfaces + * Return: 1 if the clock is enabled, 0 otherwise. + * + * Not sure this is a good idea, but since disabled means bypassed for + * this clock implementation we say we are always enabled. + */ +static int zynq_pll_is_enabled(struct clk_hw *hw) +{ + unsigned long flags = 0; + u32 reg; + struct zynq_pll *clk = to_zynq_pll(hw); + + spin_lock_irqsave(clk->lock, flags); + + reg = readl(clk->pll_ctrl); + + spin_unlock_irqrestore(clk->lock, flags); + + return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK)); +} + +/** + * zynq_pll_enable - Enable clock + * @hw: Handle between common and hardware-specific interfaces + * Return: 0 on success + */ +static int zynq_pll_enable(struct clk_hw *hw) +{ + unsigned long flags = 0; + u32 reg; + struct zynq_pll *clk = to_zynq_pll(hw); + + if (zynq_pll_is_enabled(hw)) + return 0; + + pr_info("PLL: enable\n"); + + /* Power up PLL and wait for lock */ + spin_lock_irqsave(clk->lock, flags); + + reg = readl(clk->pll_ctrl); + reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK); + writel(reg, clk->pll_ctrl); + while (!(readl(clk->pll_status) & (1 << clk->lockbit))) + ; + + spin_unlock_irqrestore(clk->lock, flags); + + return 0; +} + +/** + * zynq_pll_disable - Disable clock + * @hw: Handle between common and hardware-specific interfaces + * Returns 0 on success + */ +static void zynq_pll_disable(struct clk_hw *hw) +{ + unsigned long flags = 0; + u32 reg; + struct zynq_pll *clk = to_zynq_pll(hw); + + if (!zynq_pll_is_enabled(hw)) + return; + + pr_info("PLL: shutdown\n"); + + /* shut down PLL */ + spin_lock_irqsave(clk->lock, flags); + + reg = readl(clk->pll_ctrl); + reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK; + writel(reg, clk->pll_ctrl); + + spin_unlock_irqrestore(clk->lock, flags); +} + +static const struct clk_ops zynq_pll_ops = { + .enable = zynq_pll_enable, + .disable = zynq_pll_disable, + .is_enabled = zynq_pll_is_enabled, + .round_rate = zynq_pll_round_rate, + .recalc_rate = zynq_pll_recalc_rate +}; + +/** + * clk_register_zynq_pll() - Register PLL with the clock framework + * @name: PLL name + * @parent: Parent clock name + * @pll_ctrl: Pointer to PLL control register + * @pll_status: Pointer to PLL status register + * @lock_index: Bit index to this PLL's lock status bit in @pll_status + * @lock: Register lock + * Return: handle to the registered clock. + */ +struct clk *clk_register_zynq_pll(const char *name, const char *parent, + void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, + spinlock_t *lock) +{ + struct zynq_pll *pll; + struct clk *clk; + u32 reg; + const char *parent_arr[1] = {parent}; + unsigned long flags = 0; + struct clk_init_data initd = { + .name = name, + .parent_names = parent_arr, + .ops = &zynq_pll_ops, + .num_parents = 1, + .flags = 0 + }; + + pll = kmalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + /* Populate the struct */ + pll->hw.init = &initd; + pll->pll_ctrl = pll_ctrl; + pll->pll_status = pll_status; + pll->lockbit = lock_index; + pll->lock = lock; + + spin_lock_irqsave(pll->lock, flags); + + reg = readl(pll->pll_ctrl); + reg &= ~PLLCTRL_BPQUAL_MASK; + writel(reg, pll->pll_ctrl); + + spin_unlock_irqrestore(pll->lock, flags); + + clk = clk_register(NULL, &pll->hw); + if (WARN_ON(IS_ERR(clk))) + goto free_pll; + + return clk; + +free_pll: + kfree(pll); + + return clk; +} diff --git a/drivers/clk/zynqmp/Kconfig b/drivers/clk/zynqmp/Kconfig new file mode 100644 index 000000000..00df6be25 --- /dev/null +++ b/drivers/clk/zynqmp/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +config COMMON_CLK_ZYNQMP + bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers" + depends on ZYNQMP_FIRMWARE || COMPILE_TEST + default ZYNQMP_FIRMWARE + help + Support for the Zynqmp Ultrascale clock controller. + It has a dependency on the PMU firmware. + Say Y if you want to include clock support. diff --git a/drivers/clk/zynqmp/Makefile b/drivers/clk/zynqmp/Makefile new file mode 100644 index 000000000..0ec24bfe0 --- /dev/null +++ b/drivers/clk/zynqmp/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Zynq Ultrascale+ MPSoC clock specific Makefile + +obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c new file mode 100644 index 000000000..b89e55737 --- /dev/null +++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Zynq UltraScale+ MPSoC clock controller + * + * Copyright (C) 2016-2018 Xilinx + * + * Gated clock implementation + */ + +#include <linux/clk-provider.h> +#include <linux/slab.h> +#include "clk-zynqmp.h" + +/** + * struct zynqmp_clk_gate - gating clock + * @hw: handle between common and hardware-specific interfaces + * @flags: hardware-specific flags + * @clk_id: Id of clock + */ +struct zynqmp_clk_gate { + struct clk_hw hw; + u8 flags; + u32 clk_id; +}; + +#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw) + +/** + * zynqmp_clk_gate_enable() - Enable clock + * @hw: handle between common and hardware-specific interfaces + * + * Return: 0 on success else error code + */ +static int zynqmp_clk_gate_enable(struct clk_hw *hw) +{ + struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = gate->clk_id; + int ret; + + ret = zynqmp_pm_clock_enable(clk_id); + + if (ret) + pr_debug("%s() clock enable failed for %s (id %d), ret = %d\n", + __func__, clk_name, clk_id, ret); + + return ret; +} + +/* + * zynqmp_clk_gate_disable() - Disable clock + * @hw: handle between common and hardware-specific interfaces + */ +static void zynqmp_clk_gate_disable(struct clk_hw *hw) +{ + struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = gate->clk_id; + int ret; + + ret = zynqmp_pm_clock_disable(clk_id); + + if (ret) + pr_debug("%s() clock disable failed for %s (id %d), ret = %d\n", + __func__, clk_name, clk_id, ret); +} + +/** + * zynqmp_clk_gate_is_enabled() - Check clock state + * @hw: handle between common and hardware-specific interfaces + * + * Return: 1 if enabled, 0 if disabled else error code + */ +static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw) +{ + struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = gate->clk_id; + int state, ret; + + ret = zynqmp_pm_clock_getstate(clk_id, &state); + if (ret) { + pr_debug("%s() clock get state failed for %s, ret = %d\n", + __func__, clk_name, ret); + return -EIO; + } + + return state ? 1 : 0; +} + +static const struct clk_ops zynqmp_clk_gate_ops = { + .enable = zynqmp_clk_gate_enable, + .disable = zynqmp_clk_gate_disable, + .is_enabled = zynqmp_clk_gate_is_enabled, +}; + +/** + * zynqmp_clk_register_gate() - Register a gate clock with the clock framework + * @name: Name of this clock + * @clk_id: Id of this clock + * @parents: Name of this clock's parents + * @num_parents: Number of parents + * @nodes: Clock topology node + * + * Return: clock hardware of the registered clock gate + */ +struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes) +{ + struct zynqmp_clk_gate *gate; + struct clk_hw *hw; + int ret; + struct clk_init_data init; + + /* allocate the gate */ + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &zynqmp_clk_gate_ops; + + init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag); + + init.parent_names = parents; + init.num_parents = 1; + + /* struct clk_gate assignments */ + gate->flags = nodes->type_flag; + gate->hw.init = &init; + gate->clk_id = clk_id; + + hw = &gate->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(gate); + hw = ERR_PTR(ret); + } + + return hw; +} diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c new file mode 100644 index 000000000..9b5d3050b --- /dev/null +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Zynq UltraScale+ MPSoC mux + * + * Copyright (C) 2016-2018 Xilinx + */ + +#include <linux/clk-provider.h> +#include <linux/slab.h> +#include "clk-zynqmp.h" + +/* + * DOC: basic adjustable multiplexer clock that cannot gate + * + * Traits of this clock: + * prepare - clk_prepare only ensures that parents are prepared + * enable - clk_enable only ensures that parents are enabled + * rate - rate is only affected by parent switching. No clk_set_rate support + * parent - parent is adjustable through clk_set_parent + */ + +/** + * struct zynqmp_clk_mux - multiplexer clock + * + * @hw: handle between common and hardware-specific interfaces + * @flags: hardware-specific flags + * @clk_id: Id of clock + */ +struct zynqmp_clk_mux { + struct clk_hw hw; + u8 flags; + u32 clk_id; +}; + +#define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw) + +/** + * zynqmp_clk_mux_get_parent() - Get parent of clock + * @hw: handle between common and hardware-specific interfaces + * + * Return: Parent index on success or number of parents in case of error + */ +static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw) +{ + struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = mux->clk_id; + u32 val; + int ret; + + ret = zynqmp_pm_clock_getparent(clk_id, &val); + + if (ret) { + pr_debug("%s() getparent failed for clock: %s, ret = %d\n", + __func__, clk_name, ret); + /* + * clk_core_get_parent_by_index() takes num_parents as incorrect + * index which is exactly what I want to return here + */ + return clk_hw_get_num_parents(hw); + } + + return val; +} + +/** + * zynqmp_clk_mux_set_parent() - Set parent of clock + * @hw: handle between common and hardware-specific interfaces + * @index: Parent index + * + * Return: 0 on success else error+reason + */ +static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = mux->clk_id; + int ret; + + ret = zynqmp_pm_clock_setparent(clk_id, index); + + if (ret) + pr_debug("%s() set parent failed for clock: %s, ret = %d\n", + __func__, clk_name, ret); + + return ret; +} + +static const struct clk_ops zynqmp_clk_mux_ops = { + .get_parent = zynqmp_clk_mux_get_parent, + .set_parent = zynqmp_clk_mux_set_parent, + .determine_rate = __clk_mux_determine_rate_closest, +}; + +static const struct clk_ops zynqmp_clk_mux_ro_ops = { + .get_parent = zynqmp_clk_mux_get_parent, +}; + +static inline unsigned long zynqmp_clk_map_mux_ccf_flags( + const u32 zynqmp_type_flag) +{ + unsigned long ccf_flag = 0; + + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) + ccf_flag |= CLK_MUX_INDEX_ONE; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) + ccf_flag |= CLK_MUX_INDEX_BIT; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) + ccf_flag |= CLK_MUX_HIWORD_MASK; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_READ_ONLY) + ccf_flag |= CLK_MUX_READ_ONLY; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) + ccf_flag |= CLK_MUX_ROUND_CLOSEST; + if (zynqmp_type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) + ccf_flag |= CLK_MUX_BIG_ENDIAN; + + return ccf_flag; +} + +/** + * zynqmp_clk_register_mux() - Register a mux table with the clock + * framework + * @name: Name of this clock + * @clk_id: Id of this clock + * @parents: Name of this clock's parents + * @num_parents: Number of parents + * @nodes: Clock topology node + * + * Return: clock hardware of the registered clock mux + */ +struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes) +{ + struct zynqmp_clk_mux *mux; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + init.name = name; + if (nodes->type_flag & CLK_MUX_READ_ONLY) + init.ops = &zynqmp_clk_mux_ro_ops; + else + init.ops = &zynqmp_clk_mux_ops; + + init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag); + + init.parent_names = parents; + init.num_parents = num_parents; + mux->flags = zynqmp_clk_map_mux_ccf_flags(nodes->type_flag); + mux->hw.init = &init; + mux->clk_id = clk_id; + + hw = &mux->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(mux); + hw = ERR_PTR(ret); + } + + return hw; +} diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h new file mode 100644 index 000000000..60cbc0674 --- /dev/null +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2018 Xilinx + */ + +#ifndef __LINUX_CLK_ZYNQMP_H_ +#define __LINUX_CLK_ZYNQMP_H_ + +#include <linux/spinlock.h> + +#include <linux/firmware/xlnx-zynqmp.h> + +/* Common Flags */ +/* must be gated across rate change */ +#define ZYNQMP_CLK_SET_RATE_GATE BIT(0) +/* must be gated across re-parent */ +#define ZYNQMP_CLK_SET_PARENT_GATE BIT(1) +/* propagate rate change up one level */ +#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2) +/* do not gate even if unused */ +#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3) +/* don't re-parent on rate change */ +#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7) +/* do not gate, ever */ +#define ZYNQMP_CLK_IS_CRITICAL BIT(11) + +/* Type Flags for divider clock */ +#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0) +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3) +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) + +/* Type Flags for mux clock */ +#define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0) +#define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1) +#define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2) +#define ZYNQMP_CLK_MUX_READ_ONLY BIT(3) +#define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5) + +enum topology_type { + TYPE_INVALID, + TYPE_MUX, + TYPE_PLL, + TYPE_FIXEDFACTOR, + TYPE_DIV1, + TYPE_DIV2, + TYPE_GATE, +}; + +/** + * struct clock_topology - Clock topology + * @type: Type of topology + * @flag: Topology flags + * @type_flag: Topology type specific flag + * @custom_type_flag: Topology type specific custom flag + */ +struct clock_topology { + u32 type; + u32 flag; + u32 type_flag; + u8 custom_type_flag; +}; + +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag); + +struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes); + +struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes); + +struct clk_hw *zynqmp_clk_register_divider(const char *name, + u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes); + +struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes); + +struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, + u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes); + +#endif diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c new file mode 100644 index 000000000..5636ff1ce --- /dev/null +++ b/drivers/clk/zynqmp/clkc.c @@ -0,0 +1,803 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Zynq UltraScale+ MPSoC clock controller + * + * Copyright (C) 2016-2019 Xilinx + * + * Based on drivers/clk/zynq/clkc.c + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/slab.h> +#include <linux/string.h> + +#include "clk-zynqmp.h" + +#define MAX_PARENT 100 +#define MAX_NODES 6 +#define MAX_NAME_LEN 50 + +/* Flags for parents */ +#define PARENT_CLK_SELF 0 +#define PARENT_CLK_NODE1 1 +#define PARENT_CLK_NODE2 2 +#define PARENT_CLK_NODE3 3 +#define PARENT_CLK_NODE4 4 +#define PARENT_CLK_EXTERNAL 5 + +#define END_OF_CLK_NAME "END_OF_CLK" +#define END_OF_TOPOLOGY_NODE 1 +#define END_OF_PARENTS 1 +#define RESERVED_CLK_NAME "" + +#define CLK_GET_NAME_RESP_LEN 16 +#define CLK_GET_TOPOLOGY_RESP_WORDS 3 +#define CLK_GET_PARENTS_RESP_WORDS 3 +#define CLK_GET_ATTR_RESP_WORDS 1 + +enum clk_type { + CLK_TYPE_OUTPUT, + CLK_TYPE_EXTERNAL, +}; + +/** + * struct clock_parent - Clock parent + * @name: Parent name + * @id: Parent clock ID + * @flag: Parent flags + */ +struct clock_parent { + char name[MAX_NAME_LEN]; + int id; + u32 flag; +}; + +/** + * struct zynqmp_clock - Clock + * @clk_name: Clock name + * @valid: Validity flag of clock + * @type: Clock type (Output/External) + * @node: Clock topology nodes + * @num_nodes: Number of nodes present in topology + * @parent: Parent of clock + * @num_parents: Number of parents of clock + * @clk_id: Clock id + */ +struct zynqmp_clock { + char clk_name[MAX_NAME_LEN]; + u32 valid; + enum clk_type type; + struct clock_topology node[MAX_NODES]; + u32 num_nodes; + struct clock_parent parent[MAX_PARENT]; + u32 num_parents; + u32 clk_id; +}; + +struct name_resp { + char name[CLK_GET_NAME_RESP_LEN]; +}; + +struct topology_resp { +#define CLK_TOPOLOGY_TYPE GENMASK(3, 0) +#define CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS GENMASK(7, 4) +#define CLK_TOPOLOGY_FLAGS GENMASK(23, 8) +#define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24) + u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS]; +}; + +struct parents_resp { +#define NA_PARENT 0xFFFFFFFF +#define DUMMY_PARENT 0xFFFFFFFE +#define CLK_PARENTS_ID GENMASK(15, 0) +#define CLK_PARENTS_FLAGS GENMASK(31, 16) + u32 parents[CLK_GET_PARENTS_RESP_WORDS]; +}; + +struct attr_resp { +#define CLK_ATTR_VALID BIT(0) +#define CLK_ATTR_TYPE BIT(2) +#define CLK_ATTR_NODE_INDEX GENMASK(13, 0) +#define CLK_ATTR_NODE_TYPE GENMASK(19, 14) +#define CLK_ATTR_NODE_SUBCLASS GENMASK(25, 20) +#define CLK_ATTR_NODE_CLASS GENMASK(31, 26) + u32 attr[CLK_GET_ATTR_RESP_WORDS]; +}; + +static const char clk_type_postfix[][10] = { + [TYPE_INVALID] = "", + [TYPE_MUX] = "_mux", + [TYPE_GATE] = "", + [TYPE_DIV1] = "_div1", + [TYPE_DIV2] = "_div2", + [TYPE_FIXEDFACTOR] = "_ff", + [TYPE_PLL] = "" +}; + +static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes) + = { + [TYPE_INVALID] = NULL, + [TYPE_MUX] = zynqmp_clk_register_mux, + [TYPE_PLL] = zynqmp_clk_register_pll, + [TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor, + [TYPE_DIV1] = zynqmp_clk_register_divider, + [TYPE_DIV2] = zynqmp_clk_register_divider, + [TYPE_GATE] = zynqmp_clk_register_gate +}; + +static struct zynqmp_clock *clock; +static struct clk_hw_onecell_data *zynqmp_data; +static unsigned int clock_max_idx; + +/** + * zynqmp_is_valid_clock() - Check whether clock is valid or not + * @clk_id: Clock index + * + * Return: 1 if clock is valid, 0 if clock is invalid else error code + */ +static inline int zynqmp_is_valid_clock(u32 clk_id) +{ + if (clk_id >= clock_max_idx) + return -ENODEV; + + return clock[clk_id].valid; +} + +/** + * zynqmp_get_clock_name() - Get name of clock from Clock index + * @clk_id: Clock index + * @clk_name: Name of clock + * + * Return: 0 on success else error code + */ +static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) +{ + int ret; + + ret = zynqmp_is_valid_clock(clk_id); + if (ret == 1) { + strscpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); + return 0; + } + + return ret == 0 ? -EINVAL : ret; +} + +/** + * zynqmp_get_clock_type() - Get type of clock + * @clk_id: Clock index + * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL + * + * Return: 0 on success else error code + */ +static int zynqmp_get_clock_type(u32 clk_id, u32 *type) +{ + int ret; + + ret = zynqmp_is_valid_clock(clk_id); + if (ret == 1) { + *type = clock[clk_id].type; + return 0; + } + + return ret == 0 ? -EINVAL : ret; +} + +/** + * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system + * @nclocks: Number of clocks in system/board. + * + * Call firmware API to get number of clocks. + * + * Return: 0 on success else error code. + */ +static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS; + + ret = zynqmp_pm_query_data(qdata, ret_payload); + *nclocks = ret_payload[1]; + + return ret; +} + +/** + * zynqmp_pm_clock_get_name() - Get the name of clock for given id + * @clock_id: ID of the clock to be queried + * @response: Name of the clock with the given id + * + * This function is used to get name of clock specified by given + * clock ID. + * + * Return: 0 on success else error+reason + */ +static int zynqmp_pm_clock_get_name(u32 clock_id, + struct name_resp *response) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_NAME; + qdata.arg1 = clock_id; + + ret = zynqmp_pm_query_data(qdata, ret_payload); + if (ret) + return ret; + + memcpy(response, ret_payload, sizeof(*response)); + + return 0; +} + +/** + * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id + * @clock_id: ID of the clock to be queried + * @index: Node index of clock topology + * @response: Buffer used for the topology response + * + * This function is used to get topology information for the clock + * specified by given clock ID. + * + * This API will return 3 node of topology with a single response. To get + * other nodes, master should call same API in loop with new + * index till error is returned. E.g First call should have + * index 0 which will return nodes 0,1 and 2. Next call, index + * should be 3 which will return nodes 3,4 and 5 and so on. + * + * Return: 0 on success else error+reason + */ +static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, + struct topology_resp *response) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY; + qdata.arg1 = clock_id; + qdata.arg2 = index; + + ret = zynqmp_pm_query_data(qdata, ret_payload); + memcpy(response, &ret_payload[1], sizeof(*response)); + + return ret; +} + +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag) +{ + unsigned long ccf_flag = 0; + + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE) + ccf_flag |= CLK_SET_RATE_GATE; + if (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE) + ccf_flag |= CLK_SET_PARENT_GATE; + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT) + ccf_flag |= CLK_SET_RATE_PARENT; + if (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED) + ccf_flag |= CLK_IGNORE_UNUSED; + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT) + ccf_flag |= CLK_SET_RATE_NO_REPARENT; + if (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL) + ccf_flag |= CLK_IS_CRITICAL; + + return ccf_flag; +} + +/** + * zynqmp_clk_register_fixed_factor() - Register fixed factor with the + * clock framework + * @name: Name of this clock + * @clk_id: Clock ID + * @parents: Name of this clock's parents + * @num_parents: Number of parents + * @nodes: Clock topology node + * + * Return: clock hardware to the registered clock + */ +struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes) +{ + u32 mult, div; + struct clk_hw *hw; + struct zynqmp_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + unsigned long flag; + + qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS; + qdata.arg1 = clk_id; + + ret = zynqmp_pm_query_data(qdata, ret_payload); + if (ret) + return ERR_PTR(ret); + + mult = ret_payload[1]; + div = ret_payload[2]; + + flag = zynqmp_clk_map_common_ccf_flags(nodes->flag); + + hw = clk_hw_register_fixed_factor(NULL, name, + parents[0], + flag, mult, + div); + + return hw; +} + +/** + * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id + * @clock_id: Clock ID + * @index: Parent index + * @response: Parents of the given clock + * + * This function is used to get 3 parents for the clock specified by + * given clock ID. + * + * This API will return 3 parents with a single response. To get + * other parents, master should call same API in loop with new + * parent index till error is returned. E.g First call should have + * index 0 which will return parents 0,1 and 2. Next call, index + * should be 3 which will return parent 3,4 and 5 and so on. + * + * Return: 0 on success else error+reason + */ +static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, + struct parents_resp *response) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_PARENTS; + qdata.arg1 = clock_id; + qdata.arg2 = index; + + ret = zynqmp_pm_query_data(qdata, ret_payload); + memcpy(response, &ret_payload[1], sizeof(*response)); + + return ret; +} + +/** + * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id + * @clock_id: Clock ID + * @response: Clock attributes response + * + * This function is used to get clock's attributes(e.g. valid, clock type, etc). + * + * Return: 0 on success else error+reason + */ +static int zynqmp_pm_clock_get_attributes(u32 clock_id, + struct attr_resp *response) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES; + qdata.arg1 = clock_id; + + ret = zynqmp_pm_query_data(qdata, ret_payload); + memcpy(response, &ret_payload[1], sizeof(*response)); + + return ret; +} + +/** + * __zynqmp_clock_get_topology() - Get topology data of clock from firmware + * response data + * @topology: Clock topology + * @response: Clock topology data received from firmware + * @nnodes: Number of nodes + * + * Return: 0 on success else error+reason + */ +static int __zynqmp_clock_get_topology(struct clock_topology *topology, + struct topology_resp *response, + u32 *nnodes) +{ + int i; + u32 type; + + for (i = 0; i < ARRAY_SIZE(response->topology); i++) { + type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]); + if (type == TYPE_INVALID) + return END_OF_TOPOLOGY_NODE; + topology[*nnodes].type = type; + topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS, + response->topology[i]); + topology[*nnodes].type_flag = + FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS, + response->topology[i]); + topology[*nnodes].custom_type_flag = + FIELD_GET(CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS, + response->topology[i]); + (*nnodes)++; + } + + return 0; +} + +/** + * zynqmp_clock_get_topology() - Get topology of clock from firmware using + * PM_API + * @clk_id: Clock index + * @topology: Clock topology + * @num_nodes: Number of nodes + * + * Return: 0 on success else error+reason + */ +static int zynqmp_clock_get_topology(u32 clk_id, + struct clock_topology *topology, + u32 *num_nodes) +{ + int j, ret; + struct topology_resp response = { }; + + *num_nodes = 0; + for (j = 0; j <= MAX_NODES; j += ARRAY_SIZE(response.topology)) { + ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j, + &response); + if (ret) + return ret; + ret = __zynqmp_clock_get_topology(topology, &response, + num_nodes); + if (ret == END_OF_TOPOLOGY_NODE) + return 0; + } + + return 0; +} + +/** + * __zynqmp_clock_get_parents() - Get parents info of clock from firmware + * response data + * @parents: Clock parents + * @response: Clock parents data received from firmware + * @nparent: Number of parent + * + * Return: 0 on success else error+reason + */ +static int __zynqmp_clock_get_parents(struct clock_parent *parents, + struct parents_resp *response, + u32 *nparent) +{ + int i; + struct clock_parent *parent; + + for (i = 0; i < ARRAY_SIZE(response->parents); i++) { + if (response->parents[i] == NA_PARENT) + return END_OF_PARENTS; + + parent = &parents[i]; + parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]); + if (response->parents[i] == DUMMY_PARENT) { + strcpy(parent->name, "dummy_name"); + parent->flag = 0; + } else { + parent->flag = FIELD_GET(CLK_PARENTS_FLAGS, + response->parents[i]); + if (zynqmp_get_clock_name(parent->id, parent->name)) + continue; + } + *nparent += 1; + } + + return 0; +} + +/** + * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API + * @clk_id: Clock index + * @parents: Clock parents + * @num_parents: Total number of parents + * + * Return: 0 on success else error+reason + */ +static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents, + u32 *num_parents) +{ + int j = 0, ret; + struct parents_resp response = { }; + + *num_parents = 0; + do { + /* Get parents from firmware */ + ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j, + &response); + if (ret) + return ret; + + ret = __zynqmp_clock_get_parents(&parents[j], &response, + num_parents); + if (ret == END_OF_PARENTS) + return 0; + j += ARRAY_SIZE(response.parents); + } while (*num_parents <= MAX_PARENT); + + return 0; +} + +/** + * zynqmp_get_parent_list() - Create list of parents name + * @np: Device node + * @clk_id: Clock index + * @parent_list: List of parent's name + * @num_parents: Total number of parents + * + * Return: 0 on success else error+reason + */ +static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id, + const char **parent_list, u32 *num_parents) +{ + int i = 0, ret; + u32 total_parents = clock[clk_id].num_parents; + struct clock_topology *clk_nodes; + struct clock_parent *parents; + + clk_nodes = clock[clk_id].node; + parents = clock[clk_id].parent; + + for (i = 0; i < total_parents; i++) { + if (!parents[i].flag) { + parent_list[i] = parents[i].name; + } else if (parents[i].flag == PARENT_CLK_EXTERNAL) { + ret = of_property_match_string(np, "clock-names", + parents[i].name); + if (ret < 0) + strcpy(parents[i].name, "dummy_name"); + parent_list[i] = parents[i].name; + } else { + strcat(parents[i].name, + clk_type_postfix[clk_nodes[parents[i].flag - 1]. + type]); + parent_list[i] = parents[i].name; + } + } + + *num_parents = total_parents; + return 0; +} + +/** + * zynqmp_register_clk_topology() - Register clock topology + * @clk_id: Clock index + * @clk_name: Clock Name + * @num_parents: Total number of parents + * @parent_names: List of parents name + * + * Return: Returns either clock hardware or error+reason + */ +static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name, + int num_parents, + const char **parent_names) +{ + int j; + u32 num_nodes, clk_dev_id; + char *clk_out[MAX_NODES]; + struct clock_topology *nodes; + struct clk_hw *hw = NULL; + + nodes = clock[clk_id].node; + num_nodes = clock[clk_id].num_nodes; + clk_dev_id = clock[clk_id].clk_id; + + for (j = 0; j < num_nodes; j++) { + /* + * Clock name received from firmware is output clock name. + * Intermediate clock names are postfixed with type of clock. + */ + if (j != (num_nodes - 1)) { + clk_out[j] = kasprintf(GFP_KERNEL, "%s%s", clk_name, + clk_type_postfix[nodes[j].type]); + } else { + clk_out[j] = kasprintf(GFP_KERNEL, "%s", clk_name); + } + + if (!clk_topology[nodes[j].type]) + continue; + + hw = (*clk_topology[nodes[j].type])(clk_out[j], clk_dev_id, + parent_names, + num_parents, + &nodes[j]); + if (IS_ERR(hw)) + pr_warn_once("%s() 0x%x: %s register fail with %ld\n", + __func__, clk_dev_id, clk_name, + PTR_ERR(hw)); + + parent_names[0] = clk_out[j]; + } + + for (j = 0; j < num_nodes; j++) + kfree(clk_out[j]); + + return hw; +} + +/** + * zynqmp_register_clocks() - Register clocks + * @np: Device node + * + * Return: 0 on success else error code + */ +static int zynqmp_register_clocks(struct device_node *np) +{ + int ret; + u32 i, total_parents = 0, type = 0; + const char *parent_names[MAX_PARENT]; + + for (i = 0; i < clock_max_idx; i++) { + char clk_name[MAX_NAME_LEN]; + + /* get clock name, continue to next clock if name not found */ + if (zynqmp_get_clock_name(i, clk_name)) + continue; + + /* Check if clock is valid and output clock. + * Do not register invalid or external clock. + */ + ret = zynqmp_get_clock_type(i, &type); + if (ret || type != CLK_TYPE_OUTPUT) + continue; + + /* Get parents of clock*/ + if (zynqmp_get_parent_list(np, i, parent_names, + &total_parents)) { + WARN_ONCE(1, "No parents found for %s\n", + clock[i].clk_name); + continue; + } + + zynqmp_data->hws[i] = + zynqmp_register_clk_topology(i, clk_name, + total_parents, + parent_names); + } + + for (i = 0; i < clock_max_idx; i++) { + if (IS_ERR(zynqmp_data->hws[i])) { + pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n", + clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i])); + WARN_ON(1); + } + } + return 0; +} + +/** + * zynqmp_get_clock_info() - Get clock information from firmware using PM_API + */ +static void zynqmp_get_clock_info(void) +{ + int i, ret; + u32 type = 0; + u32 nodetype, subclass, class; + struct attr_resp attr; + struct name_resp name; + + for (i = 0; i < clock_max_idx; i++) { + ret = zynqmp_pm_clock_get_attributes(i, &attr); + if (ret) + continue; + + clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]); + /* skip query for Invalid clock */ + ret = zynqmp_is_valid_clock(i); + if (ret != CLK_ATTR_VALID) + continue; + + clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ? + CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT; + + nodetype = FIELD_GET(CLK_ATTR_NODE_TYPE, attr.attr[0]); + subclass = FIELD_GET(CLK_ATTR_NODE_SUBCLASS, attr.attr[0]); + class = FIELD_GET(CLK_ATTR_NODE_CLASS, attr.attr[0]); + + clock[i].clk_id = FIELD_PREP(CLK_ATTR_NODE_CLASS, class) | + FIELD_PREP(CLK_ATTR_NODE_SUBCLASS, subclass) | + FIELD_PREP(CLK_ATTR_NODE_TYPE, nodetype) | + FIELD_PREP(CLK_ATTR_NODE_INDEX, i); + + zynqmp_pm_clock_get_name(clock[i].clk_id, &name); + + /* + * Terminate with NULL character in case name provided by firmware + * is longer and truncated due to size limit. + */ + name.name[sizeof(name.name) - 1] = '\0'; + + if (!strcmp(name.name, RESERVED_CLK_NAME)) + continue; + strscpy(clock[i].clk_name, name.name, MAX_NAME_LEN); + } + + /* Get topology of all clock */ + for (i = 0; i < clock_max_idx; i++) { + ret = zynqmp_get_clock_type(i, &type); + if (ret || type != CLK_TYPE_OUTPUT) + continue; + + ret = zynqmp_clock_get_topology(i, clock[i].node, + &clock[i].num_nodes); + if (ret) + continue; + + ret = zynqmp_clock_get_parents(i, clock[i].parent, + &clock[i].num_parents); + if (ret) + continue; + } +} + +/** + * zynqmp_clk_setup() - Setup the clock framework and register clocks + * @np: Device node + * + * Return: 0 on success else error code + */ +static int zynqmp_clk_setup(struct device_node *np) +{ + int ret; + + ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx); + if (ret) + return ret; + + zynqmp_data = kzalloc(struct_size(zynqmp_data, hws, clock_max_idx), + GFP_KERNEL); + if (!zynqmp_data) + return -ENOMEM; + + clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL); + if (!clock) { + kfree(zynqmp_data); + return -ENOMEM; + } + + zynqmp_get_clock_info(); + zynqmp_register_clocks(np); + + zynqmp_data->num = clock_max_idx; + return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data); +} + +static int zynqmp_clock_probe(struct platform_device *pdev) +{ + int ret; + struct device *dev = &pdev->dev; + + ret = zynqmp_clk_setup(dev->of_node); + + return ret; +} + +static const struct of_device_id zynqmp_clock_of_match[] = { + {.compatible = "xlnx,zynqmp-clk"}, + {.compatible = "xlnx,versal-clk"}, + {}, +}; +MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match); + +static struct platform_driver zynqmp_clock_driver = { + .driver = { + .name = "zynqmp_clock", + .of_match_table = zynqmp_clock_of_match, + }, + .probe = zynqmp_clock_probe, +}; +module_platform_driver(zynqmp_clock_driver); diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c new file mode 100644 index 000000000..5a00487ae --- /dev/null +++ b/drivers/clk/zynqmp/divider.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Zynq UltraScale+ MPSoC Divider support + * + * Copyright (C) 2016-2019 Xilinx + * + * Adjustable divider clock implementation + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/slab.h> +#include "clk-zynqmp.h" + +/* + * DOC: basic adjustable divider clock that cannot gate + * + * Traits of this clock: + * prepare - clk_prepare only ensures that parents are prepared + * enable - clk_enable only ensures that parents are enabled + * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) + * parent - fixed parent. No clk_set_parent support + */ + +#define to_zynqmp_clk_divider(_hw) \ + container_of(_hw, struct zynqmp_clk_divider, hw) + +#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */ + +/** + * struct zynqmp_clk_divider - adjustable divider clock + * @hw: handle between common and hardware-specific interfaces + * @flags: Hardware specific flags + * @is_frac: The divider is a fractional divider + * @clk_id: Id of clock + * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) + * @max_div: maximum supported divisor (fetched from firmware) + */ +struct zynqmp_clk_divider { + struct clk_hw hw; + u8 flags; + bool is_frac; + u32 clk_id; + u32 div_type; + u16 max_div; +}; + +static inline int zynqmp_divider_get_val(unsigned long parent_rate, + unsigned long rate, u16 flags) +{ + int up, down; + unsigned long up_rate, down_rate; + + if (flags & CLK_DIVIDER_POWER_OF_TWO) { + up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate); + + up = __roundup_pow_of_two(up); + down = __rounddown_pow_of_two(down); + + up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); + down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); + + return (rate - up_rate) <= (down_rate - rate) ? up : down; + + } else { + return DIV_ROUND_CLOSEST(parent_rate, rate); + } +} + +/** + * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock + * @hw: handle between common and hardware-specific interfaces + * @parent_rate: rate of parent clock + * + * Return: 0 on success else error+reason + */ +static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = divider->clk_id; + u32 div_type = divider->div_type; + u32 div, value; + int ret; + + ret = zynqmp_pm_clock_getdivider(clk_id, &div); + + if (ret) + pr_debug("%s() get divider failed for %s, ret = %d\n", + __func__, clk_name, ret); + + if (div_type == TYPE_DIV1) + value = div & 0xFFFF; + else + value = div >> 16; + + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + value = 1 << value; + + if (!value) { + WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), + "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", + clk_name); + return parent_rate; + } + + return DIV_ROUND_UP_ULL(parent_rate, value); +} + +/** + * zynqmp_clk_divider_round_rate() - Round rate of divider clock + * @hw: handle between common and hardware-specific interfaces + * @rate: rate of clock to be set + * @prate: rate of parent clock + * + * Return: 0 on success else error+reason + */ +static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *prate) +{ + struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = divider->clk_id; + u32 div_type = divider->div_type; + u32 bestdiv; + int ret; + u8 width; + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv); + + if (ret) + pr_debug("%s() get divider failed for %s, ret = %d\n", + __func__, clk_name, ret); + if (div_type == TYPE_DIV1) + bestdiv = bestdiv & 0xFFFF; + else + bestdiv = bestdiv >> 16; + + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + bestdiv = 1 << bestdiv; + + return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); + } + + width = fls(divider->max_div); + + rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); + + if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) + *prate = rate; + + return rate; +} + +/** + * zynqmp_clk_divider_set_rate() - Set rate of divider clock + * @hw: handle between common and hardware-specific interfaces + * @rate: rate of clock to be set + * @parent_rate: rate of parent clock + * + * Return: 0 on success else error+reason + */ +static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = divider->clk_id; + u32 div_type = divider->div_type; + u32 value, div; + int ret; + + value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); + if (div_type == TYPE_DIV1) { + div = value & 0xFFFF; + div |= 0xffff << 16; + } else { + div = 0xffff; + div |= value << 16; + } + + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + div = __ffs(div); + + ret = zynqmp_pm_clock_setdivider(clk_id, div); + + if (ret) + pr_debug("%s() set divider failed for %s, ret = %d\n", + __func__, clk_name, ret); + + return ret; +} + +static const struct clk_ops zynqmp_clk_divider_ops = { + .recalc_rate = zynqmp_clk_divider_recalc_rate, + .round_rate = zynqmp_clk_divider_round_rate, + .set_rate = zynqmp_clk_divider_set_rate, +}; + +static const struct clk_ops zynqmp_clk_divider_ro_ops = { + .recalc_rate = zynqmp_clk_divider_recalc_rate, + .round_rate = zynqmp_clk_divider_round_rate, +}; + +/** + * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware. + * @clk_id: Id of clock + * @type: Divider type + * + * Return: Maximum divisor of a clock if query data is successful + * U16_MAX in case of query data is not success + */ +static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR; + qdata.arg1 = clk_id; + qdata.arg2 = type; + ret = zynqmp_pm_query_data(qdata, ret_payload); + /* + * To maintain backward compatibility return maximum possible value + * (0xFFFF) if query for max divisor is not successful. + */ + if (ret) + return U16_MAX; + + return ret_payload[1]; +} + +static inline unsigned long zynqmp_clk_map_divider_ccf_flags( + const u32 zynqmp_type_flag) +{ + unsigned long ccf_flag = 0; + + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) + ccf_flag |= CLK_DIVIDER_ONE_BASED; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) + ccf_flag |= CLK_DIVIDER_POWER_OF_TWO; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) + ccf_flag |= CLK_DIVIDER_ALLOW_ZERO; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) + ccf_flag |= CLK_DIVIDER_HIWORD_MASK; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) + ccf_flag |= CLK_DIVIDER_ROUND_CLOSEST; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) + ccf_flag |= CLK_DIVIDER_READ_ONLY; + if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) + ccf_flag |= CLK_DIVIDER_MAX_AT_ZERO; + + return ccf_flag; +} + +/** + * zynqmp_clk_register_divider() - Register a divider clock + * @name: Name of this clock + * @clk_id: Id of clock + * @parents: Name of this clock's parents + * @num_parents: Number of parents + * @nodes: Clock topology node + * + * Return: clock hardware to registered clock divider + */ +struct clk_hw *zynqmp_clk_register_divider(const char *name, + u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes) +{ + struct zynqmp_clk_divider *div; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + /* allocate the divider */ + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + init.name = name; + if (nodes->type_flag & CLK_DIVIDER_READ_ONLY) + init.ops = &zynqmp_clk_divider_ro_ops; + else + init.ops = &zynqmp_clk_divider_ops; + + init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag); + + init.parent_names = parents; + init.num_parents = 1; + + /* struct clk_divider assignments */ + div->is_frac = !!((nodes->flag & CLK_FRAC) | + (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); + div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag); + div->hw.init = &init; + div->clk_id = clk_id; + div->div_type = nodes->type; + + /* + * To achieve best possible rate, maximum limit of divider is required + * while computation. + */ + div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type); + + hw = &div->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(div); + hw = ERR_PTR(ret); + } + + return hw; +} diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c new file mode 100644 index 000000000..0d3e1377b --- /dev/null +++ b/drivers/clk/zynqmp/pll.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Zynq UltraScale+ MPSoC PLL driver + * + * Copyright (C) 2016-2018 Xilinx + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/slab.h> +#include "clk-zynqmp.h" + +/** + * struct zynqmp_pll - PLL clock + * @hw: Handle between common and hardware-specific interfaces + * @clk_id: PLL clock ID + * @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF + */ +struct zynqmp_pll { + struct clk_hw hw; + u32 clk_id; + bool set_pll_mode; +}; + +#define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw) + +#define PLL_FBDIV_MIN 25 +#define PLL_FBDIV_MAX 125 + +#define PS_PLL_VCO_MIN 1500000000 +#define PS_PLL_VCO_MAX 3000000000UL + +enum pll_mode { + PLL_MODE_INT = 0, + PLL_MODE_FRAC = 1, + PLL_MODE_ERROR = 2, +}; + +#define FRAC_OFFSET 0x8 +#define PLLFCFG_FRAC_EN BIT(31) +#define FRAC_DIV BIT(16) /* 2^16 */ + +/** + * zynqmp_pll_get_mode() - Get mode of PLL + * @hw: Handle between common and hardware-specific interfaces + * + * Return: Mode of PLL + */ +static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw) +{ + struct zynqmp_pll *clk = to_zynqmp_pll(hw); + u32 clk_id = clk->clk_id; + const char *clk_name = clk_hw_get_name(hw); + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload); + if (ret) { + pr_debug("%s() PLL get frac mode failed for %s, ret = %d\n", + __func__, clk_name, ret); + return PLL_MODE_ERROR; + } + + return ret_payload[1]; +} + +/** + * zynqmp_pll_set_mode() - Set the PLL mode + * @hw: Handle between common and hardware-specific interfaces + * @on: Flag to determine the mode + */ +static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on) +{ + struct zynqmp_pll *clk = to_zynqmp_pll(hw); + u32 clk_id = clk->clk_id; + const char *clk_name = clk_hw_get_name(hw); + int ret; + u32 mode; + + if (on) + mode = PLL_MODE_FRAC; + else + mode = PLL_MODE_INT; + + ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode); + if (ret) + pr_debug("%s() PLL set frac mode failed for %s, ret = %d\n", + __func__, clk_name, ret); + else + clk->set_pll_mode = true; +} + +/** + * zynqmp_pll_round_rate() - Round a clock frequency + * @hw: Handle between common and hardware-specific interfaces + * @rate: Desired clock frequency + * @prate: Clock frequency of parent clock + * + * Return: Frequency closest to @rate the hardware can generate + */ +static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u32 fbdiv; + u32 mult, div; + + /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */ + if (rate > PS_PLL_VCO_MAX) { + div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX); + rate = rate / div; + } + if (rate < PS_PLL_VCO_MIN) { + mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate); + rate = rate * mult; + } + + fbdiv = DIV_ROUND_CLOSEST(rate, *prate); + if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) { + fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); + rate = *prate * fbdiv; + } + + return rate; +} + +/** + * zynqmp_pll_recalc_rate() - Recalculate clock frequency + * @hw: Handle between common and hardware-specific interfaces + * @parent_rate: Clock frequency of parent clock + * + * Return: Current clock frequency or 0 in case of error + */ +static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct zynqmp_pll *clk = to_zynqmp_pll(hw); + u32 clk_id = clk->clk_id; + const char *clk_name = clk_hw_get_name(hw); + u32 fbdiv, data; + unsigned long rate, frac; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + enum pll_mode mode; + + ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); + if (ret) { + pr_debug("%s() get divider failed for %s, ret = %d\n", + __func__, clk_name, ret); + return 0ul; + } + + mode = zynqmp_pll_get_mode(hw); + if (mode == PLL_MODE_ERROR) + return 0ul; + + rate = parent_rate * fbdiv; + if (mode == PLL_MODE_FRAC) { + zynqmp_pm_get_pll_frac_data(clk_id, ret_payload); + data = ret_payload[1]; + frac = (parent_rate * data) / FRAC_DIV; + rate = rate + frac; + } + + return rate; +} + +/** + * zynqmp_pll_set_rate() - Set rate of PLL + * @hw: Handle between common and hardware-specific interfaces + * @rate: Frequency of clock to be set + * @parent_rate: Clock frequency of parent clock + * + * Set PLL divider to set desired rate. + * + * Returns: rate which is set on success else error code + */ +static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct zynqmp_pll *clk = to_zynqmp_pll(hw); + u32 clk_id = clk->clk_id; + const char *clk_name = clk_hw_get_name(hw); + u32 fbdiv; + long rate_div, frac, m, f; + int ret; + + rate_div = (rate * FRAC_DIV) / parent_rate; + f = rate_div % FRAC_DIV; + zynqmp_pll_set_mode(hw, !!f); + + if (f) { + m = rate_div / FRAC_DIV; + m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX)); + rate = parent_rate * m; + frac = (parent_rate * f) / FRAC_DIV; + + ret = zynqmp_pm_clock_setdivider(clk_id, m); + if (ret == -EUSERS) + WARN(1, "More than allowed devices are using the %s, which is forbidden\n", + clk_name); + else if (ret) + pr_debug("%s() set divider failed for %s, ret = %d\n", + __func__, clk_name, ret); + zynqmp_pm_set_pll_frac_data(clk_id, f); + + return rate + frac; + } + + fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); + fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); + ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv); + if (ret) + pr_debug("%s() set divider failed for %s, ret = %d\n", + __func__, clk_name, ret); + + return parent_rate * fbdiv; +} + +/** + * zynqmp_pll_is_enabled() - Check if a clock is enabled + * @hw: Handle between common and hardware-specific interfaces + * + * Return: 1 if the clock is enabled, 0 otherwise + */ +static int zynqmp_pll_is_enabled(struct clk_hw *hw) +{ + struct zynqmp_pll *clk = to_zynqmp_pll(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = clk->clk_id; + unsigned int state; + int ret; + + ret = zynqmp_pm_clock_getstate(clk_id, &state); + if (ret) { + pr_debug("%s() clock get state failed for %s, ret = %d\n", + __func__, clk_name, ret); + return -EIO; + } + + return state ? 1 : 0; +} + +/** + * zynqmp_pll_enable() - Enable clock + * @hw: Handle between common and hardware-specific interfaces + * + * Return: 0 on success else error code + */ +static int zynqmp_pll_enable(struct clk_hw *hw) +{ + struct zynqmp_pll *clk = to_zynqmp_pll(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = clk->clk_id; + int ret; + + /* + * Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request + * that has been sent to ATF. + */ + if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode)) + return 0; + + clk->set_pll_mode = false; + + ret = zynqmp_pm_clock_enable(clk_id); + if (ret) + pr_debug("%s() clock enable failed for %s, ret = %d\n", + __func__, clk_name, ret); + + return ret; +} + +/** + * zynqmp_pll_disable() - Disable clock + * @hw: Handle between common and hardware-specific interfaces + */ +static void zynqmp_pll_disable(struct clk_hw *hw) +{ + struct zynqmp_pll *clk = to_zynqmp_pll(hw); + const char *clk_name = clk_hw_get_name(hw); + u32 clk_id = clk->clk_id; + int ret; + + if (!zynqmp_pll_is_enabled(hw)) + return; + + ret = zynqmp_pm_clock_disable(clk_id); + if (ret) + pr_debug("%s() clock disable failed for %s, ret = %d\n", + __func__, clk_name, ret); +} + +static const struct clk_ops zynqmp_pll_ops = { + .enable = zynqmp_pll_enable, + .disable = zynqmp_pll_disable, + .is_enabled = zynqmp_pll_is_enabled, + .round_rate = zynqmp_pll_round_rate, + .recalc_rate = zynqmp_pll_recalc_rate, + .set_rate = zynqmp_pll_set_rate, +}; + +/** + * zynqmp_clk_register_pll() - Register PLL with the clock framework + * @name: PLL name + * @clk_id: Clock ID + * @parents: Name of this clock's parents + * @num_parents: Number of parents + * @nodes: Clock topology node + * + * Return: clock hardware to the registered clock + */ +struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, + const char * const *parents, + u8 num_parents, + const struct clock_topology *nodes) +{ + struct zynqmp_pll *pll; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + init.name = name; + init.ops = &zynqmp_pll_ops; + + init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag); + + init.parent_names = parents; + init.num_parents = 1; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->hw.init = &init; + pll->clk_id = clk_id; + + hw = &pll->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX); + + return hw; +} |