diff options
Diffstat (limited to 'drivers/media/dvb-frontends/drx39xyj')
| -rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/Makefile | 6 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/drx39xxj.h | 31 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h | 256 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 2328 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h | 72 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/drxj.c | 12400 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/drxj.h | 651 | ||||
| -rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/drxj_map.h | 15055 |
9 files changed, 30807 insertions, 0 deletions
diff --git a/drivers/media/dvb-frontends/drx39xyj/Kconfig b/drivers/media/dvb-frontends/drx39xyj/Kconfig new file mode 100644 index 000000000..e29c83517 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +config DVB_DRX39XYJ + tristate "Micronas DRX-J demodulator" + depends on DVB_CORE && I2C + default m if !MEDIA_SUBDRV_AUTOSELECT + help + An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want + to support this frontend. diff --git a/drivers/media/dvb-frontends/drx39xyj/Makefile b/drivers/media/dvb-frontends/drx39xyj/Makefile new file mode 100644 index 000000000..e97ab6130 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +drx39xyj-objs := drxj.o + +obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o + +ccflags-y += -I$(srctree)/drivers/media/tuners/ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h new file mode 100644 index 000000000..4d83ce5e8 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx39xxj.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Driver for Micronas DRX39xx family (drx3933j) + * + * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com> + */ + +#ifndef DRX39XXJ_H +#define DRX39XXJ_H + +#include <linux/dvb/frontend.h> +#include <media/dvb_frontend.h> +#include "drx_driver.h" + +struct drx39xxj_state { + struct i2c_adapter *i2c; + struct drx_demod_instance *demod; + struct dvb_frontend frontend; + unsigned int i2c_gate_open:1; + const struct firmware *fw; +}; + +#if IS_REACHABLE(CONFIG_DVB_DRX39XYJ) +struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c); +#else +static inline struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) { + return NULL; +}; +#endif + +#endif /* DVB_DUMMY_FE_H */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h new file mode 100644 index 000000000..739dc5590 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h @@ -0,0 +1,256 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/******************************************************************************* +* FILENAME: $Id: drx_dap_fasi.h,v 1.5 2009/07/07 14:21:40 justin Exp $ +* +* DESCRIPTION: +* Part of DRX driver. +* Data access protocol: Fast Access Sequential Interface (fasi) +* Fast access, because of short addressing format (16 instead of 32 bits addr) +* Sequential, because of I2C. +* +* USAGE: +* Include. +* +* NOTES: +* +* +*******************************************************************************/ + +/*-------- compilation control switches --------------------------------------*/ + +#ifndef __DRX_DAP_FASI_H__ +#define __DRX_DAP_FASI_H__ + +/*-------- Required includes -------------------------------------------------*/ + +#include "drx_driver.h" + +/*-------- Defines, configuring the API --------------------------------------*/ + +/******************************************** +* Allowed address formats +********************************************/ + +/* +* Comments about short/long addressing format: +* +* The DAP FASI offers long address format (4 bytes) and short address format +* (2 bytes). The DAP can operate in 3 modes: +* (1) only short +* (2) only long +* (3) both long and short but short preferred and long only when necessary +* +* These modes must be selected compile time via compile switches. +* Compile switch settings for the different modes: +* (1) DRXDAPFASI_LONG_ADDR_ALLOWED=0, DRXDAPFASI_SHORT_ADDR_ALLOWED=1 +* (2) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=0 +* (3) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=1 +* +* The default setting will be (3) both long and short. +* The default setting will need no compile switches. +* The default setting must be overridden if compile switches are already +* defined. +* +*/ + +/* set default */ +#if !defined(DRXDAPFASI_LONG_ADDR_ALLOWED) +#define DRXDAPFASI_LONG_ADDR_ALLOWED 1 +#endif + +/* set default */ +#if !defined(DRXDAPFASI_SHORT_ADDR_ALLOWED) +#define DRXDAPFASI_SHORT_ADDR_ALLOWED 1 +#endif + +/* check */ +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && \ + (DRXDAPFASI_SHORT_ADDR_ALLOWED == 0)) +#error At least one of short- or long-addressing format must be allowed. +*; /* illegal statement to force compiler error */ +#endif + +/******************************************** +* Single/master multi master setting +********************************************/ +/* +* Comments about SINGLE MASTER/MULTI MASTER modes: +* +* Consider the two sides:1) the master and 2)the slave. +* +* Master: +* Single/multimaster operation set via DRXDAP_SINGLE_MASTER compile switch +* + single master mode means no use of repeated starts +* + multi master mode means use of repeated starts +* Default is single master. +* Default can be overridden by setting the compile switch DRXDAP_SINGLE_MASTER. +* +* Slave: +* Single/multi master selected via the flags in the FASI protocol. +* + single master means remember memory address between i2c packets +* + multimaster means flush memory address between i2c packets +* Default is single master, DAP FASI changes multi-master setting silently +* into single master setting. This cannot be overridden. +* +*/ +/* set default */ +#ifndef DRXDAP_SINGLE_MASTER +#define DRXDAP_SINGLE_MASTER 0 +#endif + +/******************************************** +* Chunk/mode checking +********************************************/ +/* +* Comments about DRXDAP_MAX_WCHUNKSIZE in single or multi master mode and +* in combination with short and long addressing format. All text below +* assumes long addressing format. The table also includes information +* for short ADDRessing format. +* +* In single master mode, data can be written by sending the register address +* first, then two or four bytes of data in the next packet. +* Because the device address plus a register address equals five bytes, +* the minimum chunk size must be five. +* If ten-bit I2C device addresses are used, the minimum chunk size must be six, +* because the I2C device address will then occupy two bytes when writing. +* +* Data in single master mode is transferred as follows: +* <S> <devW> a0 a1 a2 a3 <P> +* <S> <devW> d0 d1 [d2 d3] <P> +* .. +* or +* .. +* <S> <devW> a0 a1 a2 a3 <P> +* <S> <devR> --- <P> +* +* In multi-master mode, the data must immediately follow the address (an I2C +* stop resets the internal address), and hence the minimum chunk size is +* 1 <I2C address> + 4 (register address) + 2 (data to send) = 7 bytes (8 if +* 10-bit I2C device addresses are used). +* +* The 7-bit or 10-bit i2c address parameters is a runtime parameter. +* The other parameters can be limited via compile time switches. +* +*------------------------------------------------------------------------------- +* +* Minimum chunk size table (in bytes): +* +* +----------------+----------------+ +* | 7b i2c addr | 10b i2c addr | +* +----------------+----------------+ +* | single | multi | single | multi | +* ------+--------+-------+--------+-------+ +* short | 3 | 5 | 4 | 6 | +* long | 5 | 7 | 6 | 8 | +* ------+--------+-------+--------+-------+ +* +*/ + +/* set default */ +#if !defined(DRXDAP_MAX_WCHUNKSIZE) +#define DRXDAP_MAX_WCHUNKSIZE 254 +#endif + +/* check */ +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) +#if DRXDAP_SINGLE_MASTER +#define DRXDAP_MAX_WCHUNKSIZE_MIN 3 +#else +#define DRXDAP_MAX_WCHUNKSIZE_MIN 5 +#endif +#else +#if DRXDAP_SINGLE_MASTER +#define DRXDAP_MAX_WCHUNKSIZE_MIN 5 +#else +#define DRXDAP_MAX_WCHUNKSIZE_MIN 7 +#endif +#endif + +#if DRXDAP_MAX_WCHUNKSIZE < DRXDAP_MAX_WCHUNKSIZE_MIN +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) +#if DRXDAP_SINGLE_MASTER +#error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode +*; /* illegal statement to force compiler error */ +#else +#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode +*; /* illegal statement to force compiler error */ +#endif +#else +#if DRXDAP_SINGLE_MASTER +#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode +*; /* illegal statement to force compiler error */ +#else +#error DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode +*; /* illegal statement to force compiler error */ +#endif +#endif +#endif + +/* set default */ +#if !defined(DRXDAP_MAX_RCHUNKSIZE) +#define DRXDAP_MAX_RCHUNKSIZE 254 +#endif + +/* check */ +#if DRXDAP_MAX_RCHUNKSIZE < 2 +#error DRXDAP_MAX_RCHUNKSIZE must be at least 2 +*; /* illegal statement to force compiler error */ +#endif + +/* check */ +#if DRXDAP_MAX_RCHUNKSIZE & 1 +#error DRXDAP_MAX_RCHUNKSIZE must be even +*; /* illegal statement to force compiler error */ +#endif + +/*-------- Public API functions ----------------------------------------------*/ + +extern struct drx_access_func drx_dap_fasi_funct_g; + +#define DRXDAP_FASI_RMW 0x10000000 +#define DRXDAP_FASI_BROADCAST 0x20000000 +#define DRXDAP_FASI_CLEARCRC 0x80000000 +#define DRXDAP_FASI_SINGLE_MASTER 0xC0000000 +#define DRXDAP_FASI_MULTI_MASTER 0x40000000 +#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */ +#define DRXDAP_FASI_MODEFLAGS 0xC0000000 +#define DRXDAP_FASI_FLAGS 0xF0000000 + +#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr)>>22)&0x3F) +#define DRXDAP_FASI_ADDR2BANK(addr) (((addr)>>16)&0x3F) +#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr)&0x7FFF) + +#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) +#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) +#define DRXDAP_FASI_OFFSET_TOO_LARGE(addr) (((addr) & 0x00008000) != 0) + +#endif /* __DRX_DAP_FASI_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h new file mode 100644 index 000000000..15f7e58c5 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -0,0 +1,2328 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef __DRXDRIVER_H__ +#define __DRXDRIVER_H__ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/firmware.h> +#include <linux/i2c.h> + +/* + * This structure contains the I2C address, the device ID and a user_data pointer. + * The user_data pointer can be used for application specific purposes. + */ +struct i2c_device_addr { + u16 i2c_addr; /* The I2C address of the device. */ + u16 i2c_dev_id; /* The device identifier. */ + void *user_data; /* User data pointer */ +}; + +/* +* \def IS_I2C_10BIT( addr ) +* \brief Determine if I2C address 'addr' is a 10 bits address or not. +* \param addr The I2C address. +* \return int. +* \retval 0 if address is not a 10 bits I2C address. +* \retval 1 if address is a 10 bits I2C address. +*/ +#define IS_I2C_10BIT(addr) \ + (((addr) & 0xF8) == 0xF0) + +/*------------------------------------------------------------------------------ +Exported FUNCTIONS +------------------------------------------------------------------------------*/ + +/* +* \fn drxbsp_i2c_init() +* \brief Initialize I2C communication module. +* \return int Return status. +* \retval 0 Initialization successful. +* \retval -EIO Initialization failed. +*/ +int drxbsp_i2c_init(void); + +/* +* \fn drxbsp_i2c_term() +* \brief Terminate I2C communication module. +* \return int Return status. +* \retval 0 Termination successful. +* \retval -EIO Termination failed. +*/ +int drxbsp_i2c_term(void); + +/* +* \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, +* u16 w_count, +* u8 * wData, +* struct i2c_device_addr *r_dev_addr, +* u16 r_count, +* u8 * r_data) +* \brief Read and/or write count bytes from I2C bus, store them in data[]. +* \param w_dev_addr The device i2c address and the device ID to write to +* \param w_count The number of bytes to write +* \param wData The array to write the data to +* \param r_dev_addr The device i2c address and the device ID to read from +* \param r_count The number of bytes to read +* \param r_data The array to read the data from +* \return int Return status. +* \retval 0 Success. +* \retval -EIO Failure. +* \retval -EINVAL Parameter 'wcount' is not zero but parameter +* 'wdata' contains NULL. +* Idem for 'rcount' and 'rdata'. +* Both w_dev_addr and r_dev_addr are NULL. +* +* This function must implement an atomic write and/or read action on the I2C bus +* No other process may use the I2C bus when this function is executing. +* The critical section of this function runs from and including the I2C +* write, up to and including the I2C read action. +* +* The device ID can be useful if several devices share an I2C address. +* It can be used to control a "switch" on the I2C bus to the correct device. +*/ +int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, + u8 *wData, + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data); + +/* +* \fn drxbsp_i2c_error_text() +* \brief Returns a human readable error. +* Counter part of numerical drx_i2c_error_g. +* +* \return char* Pointer to human readable error text. +*/ +char *drxbsp_i2c_error_text(void); + +/* +* \var drx_i2c_error_g; +* \brief I2C specific error codes, platform dependent. +*/ +extern int drx_i2c_error_g; + +#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ +#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ + +#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ +#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ +#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ +#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ +#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ +#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ +#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ + +#define TUNER_MODE_SUB_MAX 8 +#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ + TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ + TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ + TUNER_MODE_SUB6 | TUNER_MODE_SUB7) + + +enum tuner_lock_status { + TUNER_LOCKED, + TUNER_NOT_LOCKED +}; + +struct tuner_common { + char *name; /* Tuner brand & type name */ + s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ + s32 max_freq_rf; /* Highest RF input frequency, in kHz */ + + u8 sub_mode; /* Index to sub-mode in use */ + char ***sub_mode_descriptions; /* Pointer to description of sub-modes */ + u8 sub_modes; /* Number of available sub-modes */ + + /* The following fields will be either 0, NULL or false and do not need + initialisation */ + void *self_check; /* gives proof of initialization */ + bool programmed; /* only valid if self_check is OK */ + s32 r_ffrequency; /* only valid if programmed */ + s32 i_ffrequency; /* only valid if programmed */ + + void *my_user_data; /* pointer to associated demod instance */ + u16 my_capabilities; /* value for storing application flags */ +}; + +struct tuner_instance; + +typedef int(*tuner_open_func_t) (struct tuner_instance *tuner); +typedef int(*tuner_close_func_t) (struct tuner_instance *tuner); + +typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner, + u32 mode, + s32 + frequency); + +typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner, + u32 mode, + s32 * + r_ffrequency, + s32 * + i_ffrequency); + +typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner, + enum tuner_lock_status * + lock_stat); + +typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner, + struct i2c_device_addr * + w_dev_addr, u16 w_count, + u8 *wData, + struct i2c_device_addr * + r_dev_addr, u16 r_count, + u8 *r_data); + +struct tuner_ops { + tuner_open_func_t open_func; + tuner_close_func_t close_func; + tuner_set_frequency_func_t set_frequency_func; + tuner_get_frequency_func_t get_frequency_func; + tuner_lock_status_func_t lock_status_func; + tune_ri2c_write_read_func_t i2c_write_read_func; + +}; + +struct tuner_instance { + struct i2c_device_addr my_i2c_dev_addr; + struct tuner_common *my_common_attr; + void *my_ext_attr; + struct tuner_ops *my_funct; +}; + +int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, + u32 mode, + s32 frequency); + +int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, + u32 mode, + s32 *r_ffrequency, + s32 *i_ffrequency); + +int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, + struct i2c_device_addr *w_dev_addr, + u16 w_count, + u8 *wData, + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data); + +/************* +* +* This section configures the DRX Data Access Protocols (DAPs). +* +**************/ + +/* +* \def DRXDAP_SINGLE_MASTER +* \brief Enable I2C single or I2C multimaster mode on host. +* +* Set to 1 to enable single master mode +* Set to 0 to enable multi master mode +* +* The actual DAP implementation may be restricted to only one of the modes. +* A compiler warning or error will be generated if the DAP implementation +* overrides or cannot handle the mode defined below. +*/ +#ifndef DRXDAP_SINGLE_MASTER +#define DRXDAP_SINGLE_MASTER 1 +#endif + +/* +* \def DRXDAP_MAX_WCHUNKSIZE +* \brief Defines maximum chunksize of an i2c write action by host. +* +* This indicates the maximum size of data the I2C device driver is able to +* write at a time. This includes I2C device address and register addressing. +* +* This maximum size may be restricted by the actual DAP implementation. +* A compiler warning or error will be generated if the DAP implementation +* overrides or cannot handle the chunksize defined below. +* +* Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data +* buffer. Do not undefine or choose too large, unless your system is able to +* handle a stack buffer of that size. +* +*/ +#ifndef DRXDAP_MAX_WCHUNKSIZE +#define DRXDAP_MAX_WCHUNKSIZE 60 +#endif + +/* +* \def DRXDAP_MAX_RCHUNKSIZE +* \brief Defines maximum chunksize of an i2c read action by host. +* +* This indicates the maximum size of data the I2C device driver is able to read +* at a time. Minimum value is 2. Also, the read chunk size must be even. +* +* This maximum size may be restricted by the actual DAP implementation. +* A compiler warning or error will be generated if the DAP implementation +* overrides or cannot handle the chunksize defined below. +*/ +#ifndef DRXDAP_MAX_RCHUNKSIZE +#define DRXDAP_MAX_RCHUNKSIZE 60 +#endif + +/************* +* +* This section describes drxdriver defines. +* +**************/ + +/* +* \def DRX_UNKNOWN +* \brief Generic UNKNOWN value for DRX enumerated types. +* +* Used to indicate that the parameter value is unknown or not yet initialized. +*/ +#ifndef DRX_UNKNOWN +#define DRX_UNKNOWN (254) +#endif + +/* +* \def DRX_AUTO +* \brief Generic AUTO value for DRX enumerated types. +* +* Used to instruct the driver to automatically determine the value of the +* parameter. +*/ +#ifndef DRX_AUTO +#define DRX_AUTO (255) +#endif + +/************* +* +* This section describes flag definitions for the device capbilities. +* +**************/ + +/* +* \brief LNA capability flag +* +* Device has a Low Noise Amplifier +* +*/ +#define DRX_CAPABILITY_HAS_LNA (1UL << 0) +/* +* \brief OOB-RX capability flag +* +* Device has OOB-RX +* +*/ +#define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) +/* +* \brief ATV capability flag +* +* Device has ATV +* +*/ +#define DRX_CAPABILITY_HAS_ATV (1UL << 2) +/* +* \brief DVB-T capability flag +* +* Device has DVB-T +* +*/ +#define DRX_CAPABILITY_HAS_DVBT (1UL << 3) +/* +* \brief ITU-B capability flag +* +* Device has ITU-B +* +*/ +#define DRX_CAPABILITY_HAS_ITUB (1UL << 4) +/* +* \brief Audio capability flag +* +* Device has Audio +* +*/ +#define DRX_CAPABILITY_HAS_AUD (1UL << 5) +/* +* \brief SAW switch capability flag +* +* Device has SAW switch +* +*/ +#define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) +/* +* \brief GPIO1 capability flag +* +* Device has GPIO1 +* +*/ +#define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) +/* +* \brief GPIO2 capability flag +* +* Device has GPIO2 +* +*/ +#define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) +/* +* \brief IRQN capability flag +* +* Device has IRQN +* +*/ +#define DRX_CAPABILITY_HAS_IRQN (1UL << 9) +/* +* \brief 8VSB capability flag +* +* Device has 8VSB +* +*/ +#define DRX_CAPABILITY_HAS_8VSB (1UL << 10) +/* +* \brief SMA-TX capability flag +* +* Device has SMATX +* +*/ +#define DRX_CAPABILITY_HAS_SMATX (1UL << 11) +/* +* \brief SMA-RX capability flag +* +* Device has SMARX +* +*/ +#define DRX_CAPABILITY_HAS_SMARX (1UL << 12) +/* +* \brief ITU-A/C capability flag +* +* Device has ITU-A/C +* +*/ +#define DRX_CAPABILITY_HAS_ITUAC (1UL << 13) + +/*------------------------------------------------------------------------- +MACROS +-------------------------------------------------------------------------*/ +/* Macros to stringify the version number */ +#define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \ + DRX_VERSIONSTRING_HELP(MAJOR)"." \ + DRX_VERSIONSTRING_HELP(MINOR)"." \ + DRX_VERSIONSTRING_HELP(PATCH) +#define DRX_VERSIONSTRING_HELP(NUM) #NUM + +/* +* \brief Macro to create byte array elements from 16 bit integers. +* This macro is used to create byte arrays for block writes. +* Block writes speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +* x->lowbyte(x), highbyte(x) +*/ +#define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ + ((u8)((((u16)x)>>8)&0xFF)) + +/* +* \brief Macro to convert 16 bit register value to a s32 +*/ +#define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ + ((s32) \ + (((u32) x) | 0xFFFF0000)) : \ + ((s32) x)) + +/*------------------------------------------------------------------------- +ENUM +-------------------------------------------------------------------------*/ + +/* +* \enum enum drx_standard +* \brief Modulation standards. +*/ +enum drx_standard { + DRX_STANDARD_DVBT = 0, /*< Terrestrial DVB-T. */ + DRX_STANDARD_8VSB, /*< Terrestrial 8VSB. */ + DRX_STANDARD_NTSC, /*< Terrestrial\Cable analog NTSC. */ + DRX_STANDARD_PAL_SECAM_BG, + /*< Terrestrial analog PAL/SECAM B/G */ + DRX_STANDARD_PAL_SECAM_DK, + /*< Terrestrial analog PAL/SECAM D/K */ + DRX_STANDARD_PAL_SECAM_I, + /*< Terrestrial analog PAL/SECAM I */ + DRX_STANDARD_PAL_SECAM_L, + /*< Terrestrial analog PAL/SECAM L + with negative modulation */ + DRX_STANDARD_PAL_SECAM_LP, + /*< Terrestrial analog PAL/SECAM L + with positive modulation */ + DRX_STANDARD_ITU_A, /*< Cable ITU ANNEX A. */ + DRX_STANDARD_ITU_B, /*< Cable ITU ANNEX B. */ + DRX_STANDARD_ITU_C, /*< Cable ITU ANNEX C. */ + DRX_STANDARD_ITU_D, /*< Cable ITU ANNEX D. */ + DRX_STANDARD_FM, /*< Terrestrial\Cable FM radio */ + DRX_STANDARD_DTMB, /*< Terrestrial DTMB standard (China)*/ + DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, + /*< Standard unknown. */ + DRX_STANDARD_AUTO = DRX_AUTO + /*< Autodetect standard. */ +}; + +/* +* \enum enum drx_standard +* \brief Modulation sub-standards. +*/ +enum drx_substandard { + DRX_SUBSTANDARD_MAIN = 0, /*< Main subvariant of standard */ + DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, + DRX_SUBSTANDARD_ATV_DK_POLAND, + DRX_SUBSTANDARD_ATV_DK_CHINA, + DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, + /*< Sub-standard unknown. */ + DRX_SUBSTANDARD_AUTO = DRX_AUTO + /*< Auto (default) sub-standard */ +}; + +/* +* \enum enum drx_bandwidth +* \brief Channel bandwidth or channel spacing. +*/ +enum drx_bandwidth { + DRX_BANDWIDTH_8MHZ = 0, /*< Bandwidth 8 MHz. */ + DRX_BANDWIDTH_7MHZ, /*< Bandwidth 7 MHz. */ + DRX_BANDWIDTH_6MHZ, /*< Bandwidth 6 MHz. */ + DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, + /*< Bandwidth unknown. */ + DRX_BANDWIDTH_AUTO = DRX_AUTO + /*< Auto Set Bandwidth */ +}; + +/* +* \enum enum drx_mirror +* \brief Indicate if channel spectrum is mirrored or not. +*/ +enum drx_mirror { + DRX_MIRROR_NO = 0, /*< Spectrum is not mirrored. */ + DRX_MIRROR_YES, /*< Spectrum is mirrored. */ + DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, + /*< Unknown if spectrum is mirrored. */ + DRX_MIRROR_AUTO = DRX_AUTO + /*< Autodetect if spectrum is mirrored. */ +}; + +/* +* \enum enum drx_modulation +* \brief Constellation type of the channel. +*/ +enum drx_modulation { + DRX_CONSTELLATION_BPSK = 0, /*< Modulation is BPSK. */ + DRX_CONSTELLATION_QPSK, /*< Constellation is QPSK. */ + DRX_CONSTELLATION_PSK8, /*< Constellation is PSK8. */ + DRX_CONSTELLATION_QAM16, /*< Constellation is QAM16. */ + DRX_CONSTELLATION_QAM32, /*< Constellation is QAM32. */ + DRX_CONSTELLATION_QAM64, /*< Constellation is QAM64. */ + DRX_CONSTELLATION_QAM128, /*< Constellation is QAM128. */ + DRX_CONSTELLATION_QAM256, /*< Constellation is QAM256. */ + DRX_CONSTELLATION_QAM512, /*< Constellation is QAM512. */ + DRX_CONSTELLATION_QAM1024, /*< Constellation is QAM1024. */ + DRX_CONSTELLATION_QPSK_NR, /*< Constellation is QPSK_NR */ + DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, + /*< Constellation unknown. */ + DRX_CONSTELLATION_AUTO = DRX_AUTO + /*< Autodetect constellation. */ +}; + +/* +* \enum enum drx_hierarchy +* \brief Hierarchy of the channel. +*/ +enum drx_hierarchy { + DRX_HIERARCHY_NONE = 0, /*< None hierarchical channel. */ + DRX_HIERARCHY_ALPHA1, /*< Hierarchical channel, alpha=1. */ + DRX_HIERARCHY_ALPHA2, /*< Hierarchical channel, alpha=2. */ + DRX_HIERARCHY_ALPHA4, /*< Hierarchical channel, alpha=4. */ + DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, + /*< Hierarchy unknown. */ + DRX_HIERARCHY_AUTO = DRX_AUTO + /*< Autodetect hierarchy. */ +}; + +/* +* \enum enum drx_priority +* \brief Channel priority in case of hierarchical transmission. +*/ +enum drx_priority { + DRX_PRIORITY_LOW = 0, /*< Low priority channel. */ + DRX_PRIORITY_HIGH, /*< High priority channel. */ + DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN + /*< Priority unknown. */ +}; + +/* +* \enum enum drx_coderate +* \brief Channel priority in case of hierarchical transmission. +*/ +enum drx_coderate { + DRX_CODERATE_1DIV2 = 0, /*< Code rate 1/2nd. */ + DRX_CODERATE_2DIV3, /*< Code rate 2/3nd. */ + DRX_CODERATE_3DIV4, /*< Code rate 3/4nd. */ + DRX_CODERATE_5DIV6, /*< Code rate 5/6nd. */ + DRX_CODERATE_7DIV8, /*< Code rate 7/8nd. */ + DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, + /*< Code rate unknown. */ + DRX_CODERATE_AUTO = DRX_AUTO + /*< Autodetect code rate. */ +}; + +/* +* \enum enum drx_guard +* \brief Guard interval of a channel. +*/ +enum drx_guard { + DRX_GUARD_1DIV32 = 0, /*< Guard interval 1/32nd. */ + DRX_GUARD_1DIV16, /*< Guard interval 1/16th. */ + DRX_GUARD_1DIV8, /*< Guard interval 1/8th. */ + DRX_GUARD_1DIV4, /*< Guard interval 1/4th. */ + DRX_GUARD_UNKNOWN = DRX_UNKNOWN, + /*< Guard interval unknown. */ + DRX_GUARD_AUTO = DRX_AUTO + /*< Autodetect guard interval. */ +}; + +/* +* \enum enum drx_fft_mode +* \brief FFT mode. +*/ +enum drx_fft_mode { + DRX_FFTMODE_2K = 0, /*< 2K FFT mode. */ + DRX_FFTMODE_4K, /*< 4K FFT mode. */ + DRX_FFTMODE_8K, /*< 8K FFT mode. */ + DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, + /*< FFT mode unknown. */ + DRX_FFTMODE_AUTO = DRX_AUTO + /*< Autodetect FFT mode. */ +}; + +/* +* \enum enum drx_classification +* \brief Channel classification. +*/ +enum drx_classification { + DRX_CLASSIFICATION_GAUSS = 0, /*< Gaussion noise. */ + DRX_CLASSIFICATION_HVY_GAUSS, /*< Heavy Gaussion noise. */ + DRX_CLASSIFICATION_COCHANNEL, /*< Co-channel. */ + DRX_CLASSIFICATION_STATIC, /*< Static echo. */ + DRX_CLASSIFICATION_MOVING, /*< Moving echo. */ + DRX_CLASSIFICATION_ZERODB, /*< Zero dB echo. */ + DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, + /*< Unknown classification */ + DRX_CLASSIFICATION_AUTO = DRX_AUTO + /*< Autodetect classification. */ +}; + +/* +* /enum enum drx_interleave_mode +* /brief Interleave modes +*/ +enum drx_interleave_mode { + DRX_INTERLEAVEMODE_I128_J1 = 0, + DRX_INTERLEAVEMODE_I128_J1_V2, + DRX_INTERLEAVEMODE_I128_J2, + DRX_INTERLEAVEMODE_I64_J2, + DRX_INTERLEAVEMODE_I128_J3, + DRX_INTERLEAVEMODE_I32_J4, + DRX_INTERLEAVEMODE_I128_J4, + DRX_INTERLEAVEMODE_I16_J8, + DRX_INTERLEAVEMODE_I128_J5, + DRX_INTERLEAVEMODE_I8_J16, + DRX_INTERLEAVEMODE_I128_J6, + DRX_INTERLEAVEMODE_RESERVED_11, + DRX_INTERLEAVEMODE_I128_J7, + DRX_INTERLEAVEMODE_RESERVED_13, + DRX_INTERLEAVEMODE_I128_J8, + DRX_INTERLEAVEMODE_RESERVED_15, + DRX_INTERLEAVEMODE_I12_J17, + DRX_INTERLEAVEMODE_I5_J4, + DRX_INTERLEAVEMODE_B52_M240, + DRX_INTERLEAVEMODE_B52_M720, + DRX_INTERLEAVEMODE_B52_M48, + DRX_INTERLEAVEMODE_B52_M0, + DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, + /*< Unknown interleave mode */ + DRX_INTERLEAVEMODE_AUTO = DRX_AUTO + /*< Autodetect interleave mode */ +}; + +/* +* \enum enum drx_carrier_mode +* \brief Channel Carrier Mode. +*/ +enum drx_carrier_mode { + DRX_CARRIER_MULTI = 0, /*< Multi carrier mode */ + DRX_CARRIER_SINGLE, /*< Single carrier mode */ + DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, + /*< Carrier mode unknown. */ + DRX_CARRIER_AUTO = DRX_AUTO /*< Autodetect carrier mode */ +}; + +/* +* \enum enum drx_frame_mode +* \brief Channel Frame Mode. +*/ +enum drx_frame_mode { + DRX_FRAMEMODE_420 = 0, /*< 420 with variable PN */ + DRX_FRAMEMODE_595, /*< 595 */ + DRX_FRAMEMODE_945, /*< 945 with variable PN */ + DRX_FRAMEMODE_420_FIXED_PN, + /*< 420 with fixed PN */ + DRX_FRAMEMODE_945_FIXED_PN, + /*< 945 with fixed PN */ + DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, + /*< Frame mode unknown. */ + DRX_FRAMEMODE_AUTO = DRX_AUTO + /*< Autodetect frame mode */ +}; + +/* +* \enum enum drx_tps_frame +* \brief Frame number in current super-frame. +*/ +enum drx_tps_frame { + DRX_TPS_FRAME1 = 0, /*< TPS frame 1. */ + DRX_TPS_FRAME2, /*< TPS frame 2. */ + DRX_TPS_FRAME3, /*< TPS frame 3. */ + DRX_TPS_FRAME4, /*< TPS frame 4. */ + DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN + /*< TPS frame unknown. */ +}; + +/* +* \enum enum drx_ldpc +* \brief TPS LDPC . +*/ +enum drx_ldpc { + DRX_LDPC_0_4 = 0, /*< LDPC 0.4 */ + DRX_LDPC_0_6, /*< LDPC 0.6 */ + DRX_LDPC_0_8, /*< LDPC 0.8 */ + DRX_LDPC_UNKNOWN = DRX_UNKNOWN, + /*< LDPC unknown. */ + DRX_LDPC_AUTO = DRX_AUTO /*< Autodetect LDPC */ +}; + +/* +* \enum enum drx_pilot_mode +* \brief Pilot modes in DTMB. +*/ +enum drx_pilot_mode { + DRX_PILOT_ON = 0, /*< Pilot On */ + DRX_PILOT_OFF, /*< Pilot Off */ + DRX_PILOT_UNKNOWN = DRX_UNKNOWN, + /*< Pilot unknown. */ + DRX_PILOT_AUTO = DRX_AUTO /*< Autodetect Pilot */ +}; + +/* + * enum drxu_code_action - indicate if firmware has to be uploaded or verified. + * @UCODE_UPLOAD: Upload the microcode image to device + * @UCODE_VERIFY: Compare microcode image with code on device + */ +enum drxu_code_action { + UCODE_UPLOAD, + UCODE_VERIFY +}; + +/* +* \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. +* +* The generic lock states have device dependent semantics. + + DRX_NEVER_LOCK = 0, + **< Device will never lock on this signal * + DRX_NOT_LOCKED, + **< Device has no lock at all * + DRX_LOCK_STATE_1, + **< Generic lock state * + DRX_LOCK_STATE_2, + **< Generic lock state * + DRX_LOCK_STATE_3, + **< Generic lock state * + DRX_LOCK_STATE_4, + **< Generic lock state * + DRX_LOCK_STATE_5, + **< Generic lock state * + DRX_LOCK_STATE_6, + **< Generic lock state * + DRX_LOCK_STATE_7, + **< Generic lock state * + DRX_LOCK_STATE_8, + **< Generic lock state * + DRX_LOCK_STATE_9, + **< Generic lock state * + DRX_LOCKED **< Device is in lock * +*/ + +enum drx_lock_status { + DRX_NEVER_LOCK = 0, + DRX_NOT_LOCKED, + DRX_LOCK_STATE_1, + DRX_LOCK_STATE_2, + DRX_LOCK_STATE_3, + DRX_LOCK_STATE_4, + DRX_LOCK_STATE_5, + DRX_LOCK_STATE_6, + DRX_LOCK_STATE_7, + DRX_LOCK_STATE_8, + DRX_LOCK_STATE_9, + DRX_LOCKED +}; + +/* +* \enum enum drx_uio* \brief Used to address a User IO (UIO). +*/ +enum drx_uio { + DRX_UIO1, + DRX_UIO2, + DRX_UIO3, + DRX_UIO4, + DRX_UIO5, + DRX_UIO6, + DRX_UIO7, + DRX_UIO8, + DRX_UIO9, + DRX_UIO10, + DRX_UIO11, + DRX_UIO12, + DRX_UIO13, + DRX_UIO14, + DRX_UIO15, + DRX_UIO16, + DRX_UIO17, + DRX_UIO18, + DRX_UIO19, + DRX_UIO20, + DRX_UIO21, + DRX_UIO22, + DRX_UIO23, + DRX_UIO24, + DRX_UIO25, + DRX_UIO26, + DRX_UIO27, + DRX_UIO28, + DRX_UIO29, + DRX_UIO30, + DRX_UIO31, + DRX_UIO32, + DRX_UIO_MAX = DRX_UIO32 +}; + +/* +* \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. +* +* DRX_UIO_MODE_FIRMWARE is an old uio mode. +* It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. +* To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to +* DRX_UIO_MODE_FIRMWARE0. +*/ +enum drxuio_mode { + DRX_UIO_MODE_DISABLE = 0x01, + /*< not used, pin is configured as input */ + DRX_UIO_MODE_READWRITE = 0x02, + /*< used for read/write by application */ + DRX_UIO_MODE_FIRMWARE = 0x04, + /*< controlled by firmware, function 0 */ + DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, + /*< same as above */ + DRX_UIO_MODE_FIRMWARE1 = 0x08, + /*< controlled by firmware, function 1 */ + DRX_UIO_MODE_FIRMWARE2 = 0x10, + /*< controlled by firmware, function 2 */ + DRX_UIO_MODE_FIRMWARE3 = 0x20, + /*< controlled by firmware, function 3 */ + DRX_UIO_MODE_FIRMWARE4 = 0x40, + /*< controlled by firmware, function 4 */ + DRX_UIO_MODE_FIRMWARE5 = 0x80 + /*< controlled by firmware, function 5 */ +}; + +/* +* \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. +* +* Based on ANSI 55-1 and 55-2 +*/ +enum drxoob_downstream_standard { + DRX_OOB_MODE_A = 0, + /*< ANSI 55-1 */ + DRX_OOB_MODE_B_GRADE_A, + /*< ANSI 55-2 A */ + DRX_OOB_MODE_B_GRADE_B + /*< ANSI 55-2 B */ +}; + +/*------------------------------------------------------------------------- +STRUCTS +-------------------------------------------------------------------------*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL CFG related data structures ========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +#ifndef DRX_CFG_BASE +#define DRX_CFG_BASE 0 +#endif + +#define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ +#define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */ +#define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */ +#define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */ +#define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */ +#define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */ +#define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */ +#define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */ +#define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */ +#define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */ +#define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */ +#define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */ +#define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */ +#define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */ +#define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */ +#define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */ +#define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */ +#define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */ +#define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */ + +#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL related data structures ============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* + * struct drxu_code_info Parameters for microcode upload and verfiy. + * + * @mc_file: microcode file name + * + * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE + */ +struct drxu_code_info { + char *mc_file; +}; + +/* +* \struct drx_mc_version_rec_t +* \brief Microcode version record +* Version numbers are stored in BCD format, as usual: +* o major number = bits 31-20 (first three nibbles of MSW) +* o minor number = bits 19-16 (fourth nibble of MSW) +* o patch number = bits 15-0 (remaining nibbles in LSW) +* +* The device type indicates for which the device is meant. It is based on the +* JTAG ID, using everything except the bond ID and the metal fix. +* +* Special values: +* - mc_dev_type == 0 => any device allowed +* - mc_base_version == 0.0.0 => full microcode (mc_version is the version) +* - mc_base_version != 0.0.0 => patch microcode, the base microcode version +* (mc_version is the version) +*/ +#define AUX_VER_RECORD 0x8000 + +struct drx_mc_version_rec { + u16 aux_type; /* type of aux data - 0x8000 for version record */ + u32 mc_dev_type; /* device type, based on JTAG ID */ + u32 mc_version; /* version of microcode */ + u32 mc_base_version; /* in case of patch: the original microcode version */ +}; + +/*========================================*/ + +/* +* \struct drx_filter_info_t +* \brief Parameters for loading filter coefficients +* +* Used by DRX_CTRL_LOAD_FILTER +*/ +struct drx_filter_info { + u8 *data_re; + /*< pointer to coefficients for RE */ + u8 *data_im; + /*< pointer to coefficients for IM */ + u16 size_re; + /*< size of coefficients for RE */ + u16 size_im; + /*< size of coefficients for IM */ +}; + +/*========================================*/ + +/* +* \struct struct drx_channel * \brief The set of parameters describing a single channel. +* +* Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. +* Only certain fields need to be used for a specific standard. +* +*/ +struct drx_channel { + s32 frequency; + /*< frequency in kHz */ + enum drx_bandwidth bandwidth; + /*< bandwidth */ + enum drx_mirror mirror; /*< mirrored or not on RF */ + enum drx_modulation constellation; + /*< constellation */ + enum drx_hierarchy hierarchy; + /*< hierarchy */ + enum drx_priority priority; /*< priority */ + enum drx_coderate coderate; /*< coderate */ + enum drx_guard guard; /*< guard interval */ + enum drx_fft_mode fftmode; /*< fftmode */ + enum drx_classification classification; + /*< classification */ + u32 symbolrate; + /*< symbolrate in symbols/sec */ + enum drx_interleave_mode interleavemode; + /*< interleaveMode QAM */ + enum drx_ldpc ldpc; /*< ldpc */ + enum drx_carrier_mode carrier; /*< carrier */ + enum drx_frame_mode framemode; + /*< frame mode */ + enum drx_pilot_mode pilot; /*< pilot mode */ +}; + +/*========================================*/ + +enum drx_cfg_sqi_speed { + DRX_SQI_SPEED_FAST = 0, + DRX_SQI_SPEED_MEDIUM, + DRX_SQI_SPEED_SLOW, + DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN +}; + +/*========================================*/ + +/* +* \struct struct drx_complex * A complex number. +* +* Used by DRX_CTRL_CONSTEL. +*/ +struct drx_complex { + s16 im; + /*< Imaginary part. */ + s16 re; + /*< Real part. */ +}; + +/*========================================*/ + +/* +* \struct struct drx_frequency_plan * Array element of a frequency plan. +* +* Used by DRX_CTRL_SCAN_INIT. +*/ +struct drx_frequency_plan { + s32 first; + /*< First centre frequency in this band */ + s32 last; + /*< Last centre frequency in this band */ + s32 step; + /*< Stepping frequency in this band */ + enum drx_bandwidth bandwidth; + /*< Bandwidth within this frequency band */ + u16 ch_number; + /*< First channel number in this band, or first + index in ch_names */ + char **ch_names; + /*< Optional list of channel names in this + band */ +}; + +/*========================================*/ + +/* +* \struct struct drx_scan_param * Parameters for channel scan. +* +* Used by DRX_CTRL_SCAN_INIT. +*/ +struct drx_scan_param { + struct drx_frequency_plan *frequency_plan; + /*< Frequency plan (array)*/ + u16 frequency_plan_size; /*< Number of bands */ + u32 num_tries; /*< Max channels tried */ + s32 skip; /*< Minimum frequency step to take + after a channel is found */ + void *ext_params; /*< Standard specific params */ +}; + +/*========================================*/ + +/* +* \brief Scan commands. +* Used by scanning algorithms. +*/ +enum drx_scan_command { + DRX_SCAN_COMMAND_INIT = 0,/*< Initialize scanning */ + DRX_SCAN_COMMAND_NEXT, /*< Next scan */ + DRX_SCAN_COMMAND_STOP /*< Stop scanning */ +}; + +/*========================================*/ + +/* +* \brief Inner scan function prototype. +*/ +typedef int(*drx_scan_func_t) (void *scan_context, + enum drx_scan_command scan_command, + struct drx_channel *scan_channel, + bool *get_next_channel); + +/*========================================*/ + +/* +* \struct struct drxtps_info * TPS information, DVB-T specific. +* +* Used by DRX_CTRL_TPS_INFO. +*/ + struct drxtps_info { + enum drx_fft_mode fftmode; /*< Fft mode */ + enum drx_guard guard; /*< Guard interval */ + enum drx_modulation constellation; + /*< Constellation */ + enum drx_hierarchy hierarchy; + /*< Hierarchy */ + enum drx_coderate high_coderate; + /*< High code rate */ + enum drx_coderate low_coderate; + /*< Low cod rate */ + enum drx_tps_frame frame; /*< Tps frame */ + u8 length; /*< Length */ + u16 cell_id; /*< Cell id */ + }; + +/*========================================*/ + +/* +* \brief Power mode of device. +* +* Used by DRX_CTRL_SET_POWER_MODE. +*/ + enum drx_power_mode { + DRX_POWER_UP = 0, + /*< Generic , Power Up Mode */ + DRX_POWER_MODE_1, + /*< Device specific , Power Up Mode */ + DRX_POWER_MODE_2, + /*< Device specific , Power Up Mode */ + DRX_POWER_MODE_3, + /*< Device specific , Power Up Mode */ + DRX_POWER_MODE_4, + /*< Device specific , Power Up Mode */ + DRX_POWER_MODE_5, + /*< Device specific , Power Up Mode */ + DRX_POWER_MODE_6, + /*< Device specific , Power Up Mode */ + DRX_POWER_MODE_7, + /*< Device specific , Power Up Mode */ + DRX_POWER_MODE_8, + /*< Device specific , Power Up Mode */ + + DRX_POWER_MODE_9, + /*< Device specific , Power Down Mode */ + DRX_POWER_MODE_10, + /*< Device specific , Power Down Mode */ + DRX_POWER_MODE_11, + /*< Device specific , Power Down Mode */ + DRX_POWER_MODE_12, + /*< Device specific , Power Down Mode */ + DRX_POWER_MODE_13, + /*< Device specific , Power Down Mode */ + DRX_POWER_MODE_14, + /*< Device specific , Power Down Mode */ + DRX_POWER_MODE_15, + /*< Device specific , Power Down Mode */ + DRX_POWER_MODE_16, + /*< Device specific , Power Down Mode */ + DRX_POWER_DOWN = 255 + /*< Generic , Power Down Mode */ + }; + +/*========================================*/ + +/* +* \enum enum drx_module * \brief Software module identification. +* +* Used by DRX_CTRL_VERSION. +*/ + enum drx_module { + DRX_MODULE_DEVICE, + DRX_MODULE_MICROCODE, + DRX_MODULE_DRIVERCORE, + DRX_MODULE_DEVICEDRIVER, + DRX_MODULE_DAP, + DRX_MODULE_BSP_I2C, + DRX_MODULE_BSP_TUNER, + DRX_MODULE_BSP_HOST, + DRX_MODULE_UNKNOWN + }; + +/* +* \enum struct drx_version * \brief Version information of one software module. +* +* Used by DRX_CTRL_VERSION. +*/ + struct drx_version { + enum drx_module module_type; + /*< Type identifier of the module */ + char *module_name; + /*< Name or description of module */ + u16 v_major; /*< Major version number */ + u16 v_minor; /*< Minor version number */ + u16 v_patch; /*< Patch version number */ + char *v_string; /*< Version as text string */ + }; + +/* +* \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. +* +* Used by DRX_CTRL_VERSION. +*/ +struct drx_version_list { + struct drx_version *version;/*< Version information */ + struct drx_version_list *next; + /*< Next list element */ +}; + +/*========================================*/ + +/* +* \brief Parameters needed to confiugure a UIO. +* +* Used by DRX_CTRL_UIO_CFG. +*/ + struct drxuio_cfg { + enum drx_uio uio; + /*< UIO identifier */ + enum drxuio_mode mode; + /*< UIO operational mode */ + }; + +/*========================================*/ + +/* +* \brief Parameters needed to read from or write to a UIO. +* +* Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. +*/ + struct drxuio_data { + enum drx_uio uio; + /*< UIO identifier */ + bool value; + /*< UIO value (true=1, false=0) */ + }; + +/*========================================*/ + +/* +* \brief Parameters needed to configure OOB. +* +* Used by DRX_CTRL_SET_OOB. +*/ + struct drxoob { + s32 frequency; /*< Frequency in kHz */ + enum drxoob_downstream_standard standard; + /*< OOB standard */ + bool spectrum_inverted; /*< If true, then spectrum + is inverted */ + }; + +/*========================================*/ + +/* +* \brief Metrics from OOB. +* +* Used by DRX_CTRL_GET_OOB. +*/ + struct drxoob_status { + s32 frequency; /*< Frequency in Khz */ + enum drx_lock_status lock; /*< Lock status */ + u32 mer; /*< MER */ + s32 symbol_rate_offset; /*< Symbolrate offset in ppm */ + }; + +/*========================================*/ + +/* +* \brief Device dependent configuration data. +* +* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. +* A sort of nested drx_ctrl() functionality for device specific controls. +*/ + struct drx_cfg { + u32 cfg_type; + /*< Function identifier */ + void *cfg_data; + /*< Function data */ + }; + +/*========================================*/ + +/* +* /struct DRXMpegStartWidth_t +* MStart width [nr MCLK cycles] for serial MPEG output. +*/ + + enum drxmpeg_str_width { + DRX_MPEG_STR_WIDTH_1, + DRX_MPEG_STR_WIDTH_8 + }; + +/* CTRL CFG MPEG output */ +/* +* \struct struct drx_cfg_mpeg_output * \brief Configuration parameters for MPEG output control. +* +* Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and +* DRX_CTRL_GET_CFG. +*/ + + struct drx_cfg_mpeg_output { + bool enable_mpeg_output;/*< If true, enable MPEG output */ + bool insert_rs_byte; /*< If true, insert RS byte */ + bool enable_parallel; /*< If true, parallel out otherwise + serial */ + bool invert_data; /*< If true, invert DATA signals */ + bool invert_err; /*< If true, invert ERR signal */ + bool invert_str; /*< If true, invert STR signals */ + bool invert_val; /*< If true, invert VAL signals */ + bool invert_clk; /*< If true, invert CLK signals */ + bool static_clk; /*< If true, static MPEG clockrate + will be used, otherwise clockrate + will adapt to the bitrate of the + TS */ + u32 bitrate; /*< Maximum bitrate in b/s in case + static clockrate is selected */ + enum drxmpeg_str_width width_str; + /*< MPEG start width */ + }; + + +/*========================================*/ + +/* +* \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. +* +* Used by DRX_CTRL_I2C_READWRITE. +* If port_nr is equal to primairy port_nr BSPI2C will be used. +* +*/ + struct drxi2c_data { + u16 port_nr; /*< I2C port number */ + struct i2c_device_addr *w_dev_addr; + /*< Write device address */ + u16 w_count; /*< Size of write data in bytes */ + u8 *wData; /*< Pointer to write data */ + struct i2c_device_addr *r_dev_addr; + /*< Read device address */ + u16 r_count; /*< Size of data to read in bytes */ + u8 *r_data; /*< Pointer to read buffer */ + }; + +/*========================================*/ + +/* +* \enum enum drx_aud_standard * \brief Audio standard identifier. +* +* Used by DRX_CTRL_SET_AUD. +*/ + enum drx_aud_standard { + DRX_AUD_STANDARD_BTSC, /*< set BTSC standard (USA) */ + DRX_AUD_STANDARD_A2, /*< set A2-Korea FM Stereo */ + DRX_AUD_STANDARD_EIAJ, /*< set to Japanese FM Stereo */ + DRX_AUD_STANDARD_FM_STEREO,/*< set to FM-Stereo Radio */ + DRX_AUD_STANDARD_M_MONO, /*< for 4.5 MHz mono detected */ + DRX_AUD_STANDARD_D_K_MONO, /*< for 6.5 MHz mono detected */ + DRX_AUD_STANDARD_BG_FM, /*< set BG_FM standard */ + DRX_AUD_STANDARD_D_K1, /*< set D_K1 standard */ + DRX_AUD_STANDARD_D_K2, /*< set D_K2 standard */ + DRX_AUD_STANDARD_D_K3, /*< set D_K3 standard */ + DRX_AUD_STANDARD_BG_NICAM_FM, + /*< set BG_NICAM_FM standard */ + DRX_AUD_STANDARD_L_NICAM_AM, + /*< set L_NICAM_AM standard */ + DRX_AUD_STANDARD_I_NICAM_FM, + /*< set I_NICAM_FM standard */ + DRX_AUD_STANDARD_D_K_NICAM_FM, + /*< set D_K_NICAM_FM standard */ + DRX_AUD_STANDARD_NOT_READY,/*< used to detect audio standard */ + DRX_AUD_STANDARD_AUTO = DRX_AUTO, + /*< Automatic Standard Detection */ + DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN + /*< used as auto and for readback */ + }; + +/* CTRL_AUD_GET_STATUS - struct drx_aud_status */ +/* +* \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. +*/ + enum drx_aud_nicam_status { + DRX_AUD_NICAM_DETECTED = 0, + /*< NICAM carrier detected */ + DRX_AUD_NICAM_NOT_DETECTED, + /*< NICAM carrier not detected */ + DRX_AUD_NICAM_BAD /*< NICAM carrier bad quality */ + }; + +/* +* \struct struct drx_aud_status * \brief Audio status characteristics. +*/ + struct drx_aud_status { + bool stereo; /*< stereo detection */ + bool carrier_a; /*< carrier A detected */ + bool carrier_b; /*< carrier B detected */ + bool sap; /*< sap / bilingual detection */ + bool rds; /*< RDS data array present */ + enum drx_aud_nicam_status nicam_status; + /*< status of NICAM carrier */ + s8 fm_ident; /*< FM Identification value */ + }; + +/* CTRL_AUD_READ_RDS - DRXRDSdata_t */ + +/* +* \struct DRXRDSdata_t +* \brief Raw RDS data array. +*/ + struct drx_cfg_aud_rds { + bool valid; /*< RDS data validation */ + u16 data[18]; /*< data from one RDS data array */ + }; + +/* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ +/* +* \enum DRXAudAVCDecayTime_t +* \brief Automatic volume control configuration. +*/ + enum drx_aud_avc_mode { + DRX_AUD_AVC_OFF, /*< Automatic volume control off */ + DRX_AUD_AVC_DECAYTIME_8S, /*< level volume in 8 seconds */ + DRX_AUD_AVC_DECAYTIME_4S, /*< level volume in 4 seconds */ + DRX_AUD_AVC_DECAYTIME_2S, /*< level volume in 2 seconds */ + DRX_AUD_AVC_DECAYTIME_20MS/*< level volume in 20 millisec */ + }; + +/* +* /enum DRXAudMaxAVCGain_t +* /brief Automatic volume control max gain in audio baseband. +*/ + enum drx_aud_avc_max_gain { + DRX_AUD_AVC_MAX_GAIN_0DB, /*< maximum AVC gain 0 dB */ + DRX_AUD_AVC_MAX_GAIN_6DB, /*< maximum AVC gain 6 dB */ + DRX_AUD_AVC_MAX_GAIN_12DB /*< maximum AVC gain 12 dB */ + }; + +/* +* /enum DRXAudMaxAVCAtten_t +* /brief Automatic volume control max attenuation in audio baseband. +*/ + enum drx_aud_avc_max_atten { + DRX_AUD_AVC_MAX_ATTEN_12DB, + /*< maximum AVC attenuation 12 dB */ + DRX_AUD_AVC_MAX_ATTEN_18DB, + /*< maximum AVC attenuation 18 dB */ + DRX_AUD_AVC_MAX_ATTEN_24DB/*< maximum AVC attenuation 24 dB */ + }; +/* +* \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. +*/ + struct drx_cfg_aud_volume { + bool mute; /*< mute overrides volume setting */ + s16 volume; /*< volume, range -114 to 12 dB */ + enum drx_aud_avc_mode avc_mode; /*< AVC auto volume control mode */ + u16 avc_ref_level; /*< AVC reference level */ + enum drx_aud_avc_max_gain avc_max_gain; + /*< AVC max gain selection */ + enum drx_aud_avc_max_atten avc_max_atten; + /*< AVC max attenuation selection */ + s16 strength_left; /*< quasi-peak, left speaker */ + s16 strength_right; /*< quasi-peak, right speaker */ + }; + +/* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ +/* +* \enum enum drxi2s_mode * \brief I2S output mode. +*/ + enum drxi2s_mode { + DRX_I2S_MODE_MASTER, /*< I2S is in master mode */ + DRX_I2S_MODE_SLAVE /*< I2S is in slave mode */ + }; + +/* +* \enum enum drxi2s_word_length * \brief Width of I2S data. +*/ + enum drxi2s_word_length { + DRX_I2S_WORDLENGTH_32 = 0,/*< I2S data is 32 bit wide */ + DRX_I2S_WORDLENGTH_16 = 1 /*< I2S data is 16 bit wide */ + }; + +/* +* \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. +*/ + enum drxi2s_format { + DRX_I2S_FORMAT_WS_WITH_DATA, + /*< I2S data and wordstrobe are aligned */ + DRX_I2S_FORMAT_WS_ADVANCED + /*< I2S data one cycle after wordstrobe */ + }; + +/* +* \enum enum drxi2s_polarity * \brief Polarity of I2S data. +*/ + enum drxi2s_polarity { + DRX_I2S_POLARITY_RIGHT,/*< wordstrobe - right high, left low */ + DRX_I2S_POLARITY_LEFT /*< wordstrobe - right low, left high */ + }; + +/* +* \struct struct drx_cfg_i2s_output * \brief I2S output configuration. +*/ + struct drx_cfg_i2s_output { + bool output_enable; /*< I2S output enable */ + u32 frequency; /*< range from 8000-48000 Hz */ + enum drxi2s_mode mode; /*< I2S mode, master or slave */ + enum drxi2s_word_length word_length; + /*< I2S wordlength, 16 or 32 bits */ + enum drxi2s_polarity polarity;/*< I2S wordstrobe polarity */ + enum drxi2s_format format; /*< I2S wordstrobe delay to data */ + }; + +/* ------------------------------expert interface-----------------------------*/ +/* +* /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. +* +*/ + enum drx_aud_fm_deemphasis { + DRX_AUD_FM_DEEMPH_50US, + DRX_AUD_FM_DEEMPH_75US, + DRX_AUD_FM_DEEMPH_OFF + }; + +/* +* /enum DRXAudDeviation_t +* setting for deviation mode in audio demodulator. +* +*/ + enum drx_cfg_aud_deviation { + DRX_AUD_DEVIATION_NORMAL, + DRX_AUD_DEVIATION_HIGH + }; + +/* +* /enum enum drx_no_carrier_option * setting for carrier, mute/noise. +* +*/ + enum drx_no_carrier_option { + DRX_NO_CARRIER_MUTE, + DRX_NO_CARRIER_NOISE + }; + +/* +* \enum DRXAudAutoSound_t +* \brief Automatic Sound +*/ + enum drx_cfg_aud_auto_sound { + DRX_AUD_AUTO_SOUND_OFF = 0, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF + }; + +/* +* \enum DRXAudASSThres_t +* \brief Automatic Sound Select Thresholds +*/ + struct drx_cfg_aud_ass_thres { + u16 a2; /* A2 Threshold for ASS configuration */ + u16 btsc; /* BTSC Threshold for ASS configuration */ + u16 nicam; /* Nicam Threshold for ASS configuration */ + }; + +/* +* \struct struct drx_aud_carrier * \brief Carrier detection related parameters +*/ + struct drx_aud_carrier { + u16 thres; /* carrier detetcion threshold for primary carrier (A) */ + enum drx_no_carrier_option opt; /* Mute or noise at no carrier detection (A) */ + s32 shift; /* DC level of incoming signal (A) */ + s32 dco; /* frequency adjustment (A) */ + }; + +/* +* \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct +*/ + struct drx_cfg_aud_carriers { + struct drx_aud_carrier a; + struct drx_aud_carrier b; + }; + +/* +* /enum enum drx_aud_i2s_src * Selection of audio source +*/ + enum drx_aud_i2s_src { + DRX_AUD_SRC_MONO, + DRX_AUD_SRC_STEREO_OR_AB, + DRX_AUD_SRC_STEREO_OR_A, + DRX_AUD_SRC_STEREO_OR_B}; + +/* +* \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. +*/ + enum drx_aud_i2s_matrix { + DRX_AUD_I2S_MATRIX_A_MONO, + /*< A sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_B_MONO, + /*< B sound only, stereo or mono */ + DRX_AUD_I2S_MATRIX_STEREO, + /*< A+B sound, transparent */ + DRX_AUD_I2S_MATRIX_MONO /*< A+B mixed to mono sum, (L+R)/2 */}; + +/* +* /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. +* +*/ + enum drx_aud_fm_matrix { + DRX_AUD_FM_MATRIX_NO_MATRIX, + DRX_AUD_FM_MATRIX_GERMAN, + DRX_AUD_FM_MATRIX_KOREAN, + DRX_AUD_FM_MATRIX_SOUND_A, + DRX_AUD_FM_MATRIX_SOUND_B}; + +/* +* \struct DRXAudMatrices_t +* \brief Mixer settings +*/ +struct drx_cfg_aud_mixer { + enum drx_aud_i2s_src source_i2s; + enum drx_aud_i2s_matrix matrix_i2s; + enum drx_aud_fm_matrix matrix_fm; +}; + +/* +* \enum DRXI2SVidSync_t +* \brief Audio/video synchronization, interacts with I2S mode. +* AUTO_1 and AUTO_2 are for automatic video standard detection with preference +* for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) +*/ + enum drx_cfg_aud_av_sync { + DRX_AUD_AVSYNC_OFF,/*< audio/video synchronization is off */ + DRX_AUD_AVSYNC_NTSC, + /*< it is an NTSC system */ + DRX_AUD_AVSYNC_MONOCHROME, + /*< it is a MONOCHROME system */ + DRX_AUD_AVSYNC_PAL_SECAM + /*< it is a PAL/SECAM system */}; + +/* +* \struct struct drx_cfg_aud_prescale * \brief Prescalers +*/ +struct drx_cfg_aud_prescale { + u16 fm_deviation; + s16 nicam_gain; +}; + +/* +* \struct struct drx_aud_beep * \brief Beep +*/ +struct drx_aud_beep { + s16 volume; /* dB */ + u16 frequency; /* Hz */ + bool mute; +}; + +/* +* \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode +*/ + enum drx_aud_btsc_detect { + DRX_BTSC_STEREO, + DRX_BTSC_MONO_AND_SAP}; + +/* +* \struct struct drx_aud_data * \brief Audio data structure +*/ +struct drx_aud_data { + /* audio storage */ + bool audio_is_active; + enum drx_aud_standard audio_standard; + struct drx_cfg_i2s_output i2sdata; + struct drx_cfg_aud_volume volume; + enum drx_cfg_aud_auto_sound auto_sound; + struct drx_cfg_aud_ass_thres ass_thresholds; + struct drx_cfg_aud_carriers carriers; + struct drx_cfg_aud_mixer mixer; + enum drx_cfg_aud_deviation deviation; + enum drx_cfg_aud_av_sync av_sync; + struct drx_cfg_aud_prescale prescale; + enum drx_aud_fm_deemphasis deemph; + enum drx_aud_btsc_detect btsc_detect; + /* rds */ + u16 rds_data_counter; + bool rds_data_present; +}; + +/* +* \enum enum drx_qam_lock_range * \brief QAM lock range mode +*/ + enum drx_qam_lock_range { + DRX_QAM_LOCKRANGE_NORMAL, + DRX_QAM_LOCKRANGE_EXTENDED}; + +/*============================================================================*/ +/*============================================================================*/ +/*== Data access structures ==================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* Address on device */ + typedef u32 dr_xaddr_t, *pdr_xaddr_t; + +/* Protocol specific flags */ + typedef u32 dr_xflags_t, *pdr_xflags_t; + +/* Write block of data to device */ + typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u16 datasize, /* size of data in bytes */ + u8 *data, /* data to send */ + u32 flags); + +/* Read block of data from device */ + typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u16 datasize, /* size of data in bytes */ + u8 *data, /* receive buffer */ + u32 flags); + +/* Write 8-bits value to device */ + typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u8 data, /* data to send */ + u32 flags); + +/* Read 8-bits value to device */ + typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u8 *data, /* receive buffer */ + u32 flags); + +/* Read modify write 8-bits value to device */ + typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 waddr, /* write address of register */ + u32 raddr, /* read address of register */ + u8 wdata, /* data to write */ + u8 *rdata); /* data to read */ + +/* Write 16-bits value to device */ + typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u16 data, /* data to send */ + u32 flags); + +/* Read 16-bits value to device */ + typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u16 *data, /* receive buffer */ + u32 flags); + +/* Read modify write 16-bits value to device */ + typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 waddr, /* write address of register */ + u32 raddr, /* read address of register */ + u16 wdata, /* data to write */ + u16 *rdata); /* data to read */ + +/* Write 32-bits value to device */ + typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u32 data, /* data to send */ + u32 flags); + +/* Read 32-bits value to device */ + typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 addr, /* address of register/memory */ + u32 *data, /* receive buffer */ + u32 flags); + +/* Read modify write 32-bits value to device */ + typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ + u32 waddr, /* write address of register */ + u32 raddr, /* read address of register */ + u32 wdata, /* data to write */ + u32 *rdata); /* data to read */ + +/* +* \struct struct drx_access_func * \brief Interface to an access protocol. +*/ +struct drx_access_func { + drx_write_block_func_t write_block_func; + drx_read_block_func_t read_block_func; + drx_write_reg8func_t write_reg8func; + drx_read_reg8func_t read_reg8func; + drx_read_modify_write_reg8func_t read_modify_write_reg8func; + drx_write_reg16func_t write_reg16func; + drx_read_reg16func_t read_reg16func; + drx_read_modify_write_reg16func_t read_modify_write_reg16func; + drx_write_reg32func_t write_reg32func; + drx_read_reg32func_t read_reg32func; + drx_read_modify_write_reg32func_t read_modify_write_reg32func; +}; + +/* Register address and data for register dump function */ +struct drx_reg_dump { + u32 address; + u32 data; +}; + +/*============================================================================*/ +/*============================================================================*/ +/*== Demod instance data structures ==========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* +* \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. +*/ + struct drx_common_attr { + /* Microcode (firmware) attributes */ + char *microcode_file; /*< microcode filename */ + bool verify_microcode; + /*< Use microcode verify or not. */ + struct drx_mc_version_rec mcversion; + /*< Version record of microcode from file */ + + /* Clocks and tuner attributes */ + s32 intermediate_freq; + /*< IF,if tuner instance not used. (kHz)*/ + s32 sys_clock_freq; + /*< Systemclock frequency. (kHz) */ + s32 osc_clock_freq; + /*< Oscillator clock frequency. (kHz) */ + s16 osc_clock_deviation; + /*< Oscillator clock deviation. (ppm) */ + bool mirror_freq_spect; + /*< Mirror IF frequency spectrum or not.*/ + + /* Initial MPEG output attributes */ + struct drx_cfg_mpeg_output mpeg_cfg; + /*< MPEG configuration */ + + bool is_opened; /*< if true instance is already opened. */ + + /* Channel scan */ + struct drx_scan_param *scan_param; + /*< scan parameters */ + u16 scan_freq_plan_index; + /*< next index in freq plan */ + s32 scan_next_frequency; + /*< next freq to scan */ + bool scan_ready; /*< scan ready flag */ + u32 scan_max_channels;/*< number of channels in freqplan */ + u32 scan_channels_scanned; + /*< number of channels scanned */ + /* Channel scan - inner loop: demod related */ + drx_scan_func_t scan_function; + /*< function to check channel */ + /* Channel scan - inner loop: SYSObj related */ + void *scan_context; /*< Context Pointer of SYSObj */ + /* Channel scan - parameters for default DTV scan function in core driver */ + u16 scan_demod_lock_timeout; + /*< millisecs to wait for lock */ + enum drx_lock_status scan_desired_lock; + /*< lock requirement for channel found */ + /* scan_active can be used by SetChannel to decide how to program the tuner, + fast or slow (but stable). Usually fast during scan. */ + bool scan_active; /*< true when scan routines are active */ + + /* Power management */ + enum drx_power_mode current_power_mode; + /*< current power management mode */ + + /* Tuner */ + u8 tuner_port_nr; /*< nr of I2C port to which tuner is */ + s32 tuner_min_freq_rf; + /*< minimum RF input frequency, in kHz */ + s32 tuner_max_freq_rf; + /*< maximum RF input frequency, in kHz */ + bool tuner_rf_agc_pol; /*< if true invert RF AGC polarity */ + bool tuner_if_agc_pol; /*< if true invert IF AGC polarity */ + bool tuner_slow_mode; /*< if true invert IF AGC polarity */ + + struct drx_channel current_channel; + /*< current channel parameters */ + enum drx_standard current_standard; + /*< current standard selection */ + enum drx_standard prev_standard; + /*< previous standard selection */ + enum drx_standard di_cache_standard; + /*< standard in DI cache if available */ + bool use_bootloader; /*< use bootloader in open */ + u32 capabilities; /*< capabilities flags */ + u32 product_id; /*< product ID inc. metal fix number */}; + +/* +* Generic functions for DRX devices. +*/ + +struct drx_demod_instance; + +/* +* \struct struct drx_demod_instance * \brief Top structure of demodulator instance. +*/ +struct drx_demod_instance { + /*< data access protocol functions */ + struct i2c_device_addr *my_i2c_dev_addr; + /*< i2c address and device identifier */ + struct drx_common_attr *my_common_attr; + /*< common DRX attributes */ + void *my_ext_attr; /*< device specific attributes */ + /* generic demodulator data */ + + struct i2c_adapter *i2c; + const struct firmware *firmware; +}; + +/*------------------------------------------------------------------------- +MACROS +Conversion from enum values to human readable form. +-------------------------------------------------------------------------*/ + +/* standard */ + +#define DRX_STR_STANDARD(x) ( \ + (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ + (x == DRX_STANDARD_8VSB) ? "8VSB" : \ + (x == DRX_STANDARD_NTSC) ? "NTSC" : \ + (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ + (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ + (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ + (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ + (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ + (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ + (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ + (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ + (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ + (x == DRX_STANDARD_FM) ? "FM" : \ + (x == DRX_STANDARD_DTMB) ? "DTMB" : \ + (x == DRX_STANDARD_AUTO) ? "Auto" : \ + (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +/* channel */ + +#define DRX_STR_BANDWIDTH(x) ( \ + (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ + (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ + (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ + (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ + (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_FFTMODE(x) ( \ + (x == DRX_FFTMODE_2K) ? "2k" : \ + (x == DRX_FFTMODE_4K) ? "4k" : \ + (x == DRX_FFTMODE_8K) ? "8k" : \ + (x == DRX_FFTMODE_AUTO) ? "Auto" : \ + (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_GUARD(x) ( \ + (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ + (x == DRX_GUARD_1DIV16) ? "1/16th" : \ + (x == DRX_GUARD_1DIV8) ? "1/8th" : \ + (x == DRX_GUARD_1DIV4) ? "1/4th" : \ + (x == DRX_GUARD_AUTO) ? "Auto" : \ + (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_CONSTELLATION(x) ( \ + (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ + (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ + (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ + (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ + (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ + (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ + (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ + (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ + (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ + (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ + (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ + (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ + (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_CODERATE(x) ( \ + (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ + (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ + (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ + (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ + (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ + (x == DRX_CODERATE_AUTO) ? "Auto" : \ + (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_HIERARCHY(x) ( \ + (x == DRX_HIERARCHY_NONE) ? "None" : \ + (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ + (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ + (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ + (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ + (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_PRIORITY(x) ( \ + (x == DRX_PRIORITY_LOW) ? "Low" : \ + (x == DRX_PRIORITY_HIGH) ? "High" : \ + (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_MIRROR(x) ( \ + (x == DRX_MIRROR_NO) ? "Normal" : \ + (x == DRX_MIRROR_YES) ? "Mirrored" : \ + (x == DRX_MIRROR_AUTO) ? "Auto" : \ + (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_CLASSIFICATION(x) ( \ + (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ + (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ + (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ + (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ + (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ + (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ + (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ + (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ + "(Invalid)") + +#define DRX_STR_INTERLEAVEMODE(x) ( \ + (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ + (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ + (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ + (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ + (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ + (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ + (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ + (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ + (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ + (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ + (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ + (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ + (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ + (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ + (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ + (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ + (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ + (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ + (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ + (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ + (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ + (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ + "(Invalid)") + +#define DRX_STR_LDPC(x) ( \ + (x == DRX_LDPC_0_4) ? "0.4" : \ + (x == DRX_LDPC_0_6) ? "0.6" : \ + (x == DRX_LDPC_0_8) ? "0.8" : \ + (x == DRX_LDPC_AUTO) ? "Auto" : \ + (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +#define DRX_STR_CARRIER(x) ( \ + (x == DRX_CARRIER_MULTI) ? "Multi" : \ + (x == DRX_CARRIER_SINGLE) ? "Single" : \ + (x == DRX_CARRIER_AUTO) ? "Auto" : \ + (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +#define DRX_STR_FRAMEMODE(x) ( \ + (x == DRX_FRAMEMODE_420) ? "420" : \ + (x == DRX_FRAMEMODE_595) ? "595" : \ + (x == DRX_FRAMEMODE_945) ? "945" : \ + (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ + (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ + (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ + (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +#define DRX_STR_PILOT(x) ( \ + (x == DRX_PILOT_ON) ? "On" : \ + (x == DRX_PILOT_OFF) ? "Off" : \ + (x == DRX_PILOT_AUTO) ? "Auto" : \ + (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +/* TPS */ + +#define DRX_STR_TPS_FRAME(x) ( \ + (x == DRX_TPS_FRAME1) ? "Frame1" : \ + (x == DRX_TPS_FRAME2) ? "Frame2" : \ + (x == DRX_TPS_FRAME3) ? "Frame3" : \ + (x == DRX_TPS_FRAME4) ? "Frame4" : \ + (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +/* lock status */ + +#define DRX_STR_LOCKSTATUS(x) ( \ + (x == DRX_NEVER_LOCK) ? "Never" : \ + (x == DRX_NOT_LOCKED) ? "No" : \ + (x == DRX_LOCKED) ? "Locked" : \ + (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ + (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ + (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ + (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ + (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ + (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ + (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ + (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ + (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ + "(Invalid)") + +/* version information , modules */ +#define DRX_STR_MODULE(x) ( \ + (x == DRX_MODULE_DEVICE) ? "Device" : \ + (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ + (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ + (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ + (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ + (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ + (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ + (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ + (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ + "(Invalid)") + +#define DRX_STR_POWER_MODE(x) ( \ + (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ + (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ + (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ + (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ + (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ + (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ + (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ + (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ + (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ + (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ + (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ + (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ + (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ + (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ + (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ + (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ + (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ + (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ + "(Invalid)") + +#define DRX_STR_OOB_STANDARD(x) ( \ + (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ + (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ + (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ + "(Invalid)") + +#define DRX_STR_AUD_STANDARD(x) ( \ + (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ + (x == DRX_AUD_STANDARD_A2) ? "A2" : \ + (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ + (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ + (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ + (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ + (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ + (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ + (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ + (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ + (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ + (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ + "(Invalid)") +#define DRX_STR_AUD_STEREO(x) ( \ + (x == true) ? "Stereo" : \ + (x == false) ? "Mono" : \ + "(Invalid)") + +#define DRX_STR_AUD_SAP(x) ( \ + (x == true) ? "Present" : \ + (x == false) ? "Not present" : \ + "(Invalid)") + +#define DRX_STR_AUD_CARRIER(x) ( \ + (x == true) ? "Present" : \ + (x == false) ? "Not present" : \ + "(Invalid)") + +#define DRX_STR_AUD_RDS(x) ( \ + (x == true) ? "Available" : \ + (x == false) ? "Not Available" : \ + "(Invalid)") + +#define DRX_STR_AUD_NICAM_STATUS(x) ( \ + (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ + (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ + (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ + "(Invalid)") + +#define DRX_STR_RDS_VALID(x) ( \ + (x == true) ? "Valid" : \ + (x == false) ? "Not Valid" : \ + "(Invalid)") + +/*------------------------------------------------------------------------- +Access macros +-------------------------------------------------------------------------*/ + +/* +* \brief Create a compilable reference to the microcode attribute +* \param d pointer to demod instance +* +* Used as main reference to an attribute field. +* Used by both macro implementation and function implementation. +* These macros are defined to avoid duplication of code in macro and function +* definitions that handle access of demod common or extended attributes. +* +*/ + +#define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion) +#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect) +#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode) +#define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened) +#define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader) +#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard) +#define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard) +#define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard) +#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel) +#define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode) +#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode) +#define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities) +#define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id) +#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq) +#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq) +#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol) +#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol) +#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode) +#define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr) +#define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) +#define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) +#define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) + +/*************************/ + +/* Macros with device-specific handling are converted to CFG functions */ + +#define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ + do { \ + struct drx_cfg config; \ + data_type cfg_data; \ + config.cfg_type = cfg_name; \ + config.cfg_data = &cfg_data; \ + cfg_data = value; \ + drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ + } while (0) + +#define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ + do { \ + int cfg_status; \ + struct drx_cfg config; \ + data_type cfg_data; \ + config.cfg_type = cfg_name; \ + config.cfg_data = &cfg_data; \ + cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ + if (cfg_status == 0) { \ + value = cfg_data; \ + } else { \ + value = (data_type)error_value; \ + } \ + } while (0) + +/* Configuration functions for usage by Access (XS) Macros */ + +#ifndef DRX_XS_CFG_BASE +#define DRX_XS_CFG_BASE (500) +#endif + +#define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0) +#define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1) +#define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2) + +/* Access Macros with device-specific handling */ + +#define DRX_SET_PRESET(d, x) \ + DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) +#define DRX_GET_PRESET(d, x) \ + DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") + +#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect) +#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \ + DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN) + +#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range) +#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ + DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) + +/* +* \brief Macro to check if std is an ATV standard +* \retval true std is an ATV standard +* \retval false std is an ATV standard +*/ +#define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \ + ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ + ((std) == DRX_STANDARD_PAL_SECAM_I) || \ + ((std) == DRX_STANDARD_PAL_SECAM_L) || \ + ((std) == DRX_STANDARD_PAL_SECAM_LP) || \ + ((std) == DRX_STANDARD_NTSC) || \ + ((std) == DRX_STANDARD_FM)) + +/* +* \brief Macro to check if std is an QAM standard +* \retval true std is an QAM standards +* \retval false std is an QAM standards +*/ +#define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \ + ((std) == DRX_STANDARD_ITU_B) || \ + ((std) == DRX_STANDARD_ITU_C) || \ + ((std) == DRX_STANDARD_ITU_D)) + +/* +* \brief Macro to check if std is VSB standard +* \retval true std is VSB standard +* \retval false std is not VSB standard +*/ +#define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) + +/* +* \brief Macro to check if std is DVBT standard +* \retval true std is DVBT standard +* \retval false std is not DVBT standard +*/ +#define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT) + +/*------------------------------------------------------------------------- +THE END +-------------------------------------------------------------------------*/ +#endif /* __DRXDRIVER_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h new file mode 100644 index 000000000..ff05a4ffb --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h @@ -0,0 +1,72 @@ +/* + ******************************************************************************* + * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE + * + * Filename: drx_driver_version.h + * Generated on: Mon Jan 18 12:09:23 2010 + * Generated by: IDF:x 1.3.0 + * Generated from: ../../../device/drxj/version + * Output start: [entry point] + * + * filename last modified re-use + * + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* ----------------------------------------------------- + * version.idf Mon Jan 18 11:56:10 2010 - + * + */ + +#ifndef __DRX_DRIVER_VERSION__H__ +#define __DRX_DRIVER_VERSION__H__ INCLUDED + +#ifdef _REGISTERTABLE_ +#include <registertable.h> + extern register_table_t drx_driver_version[]; + extern register_table_info_t drx_driver_version_info[]; +#endif /* _REGISTERTABLE_ */ + +/* + *============================================================================== + * VERSION + * version@/var/cvs/projects/drxj.cvsroot/hostcode/drxdriver/device/drxj + *============================================================================== + */ + +#define VERSION__A 0x0 +#define VERSION_MAJOR 1 +#define VERSION_MINOR 0 +#define VERSION_PATCH 56 + +#endif /* __DRX_DRIVER_VERSION__H__ */ +/* + * End of file (drx_driver_version.h) + ******************************************************************************* + */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c new file mode 100644 index 000000000..88860d08f --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -0,0 +1,12400 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + DRXJ specific implementation of DRX driver + authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen + + The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was + written by Devin Heitmueller <devin.heitmueller@kernellabs.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +/*----------------------------------------------------------------------------- +INCLUDE FILES +----------------------------------------------------------------------------*/ + +#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <asm/div64.h> + +#include <media/dvb_frontend.h> +#include "drx39xxj.h" + +#include "drxj.h" +#include "drxj_map.h" + +/*============================================================================*/ +/*=== DEFINES ================================================================*/ +/*============================================================================*/ + +#define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw" + +/* +* \brief Maximum u32 value. +*/ +#ifndef MAX_U32 +#define MAX_U32 ((u32) (0xFFFFFFFFL)) +#endif + +/* Customer configurable hardware settings, etc */ +#ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH +#define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 +#endif + +#ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH +#define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02 +#endif + +#ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH +#define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06 +#endif + +#ifndef OOB_CRX_DRIVE_STRENGTH +#define OOB_CRX_DRIVE_STRENGTH 0x02 +#endif + +#ifndef OOB_DRX_DRIVE_STRENGTH +#define OOB_DRX_DRIVE_STRENGTH 0x02 +#endif +/*** START DJCOMBO patches to DRXJ registermap constants *********************/ +/*** registermap 200706071303 from drxj **************************************/ +#define ATV_TOP_CR_AMP_TH_FM 0x0 +#define ATV_TOP_CR_AMP_TH_L 0xA +#define ATV_TOP_CR_AMP_TH_LP 0xA +#define ATV_TOP_CR_AMP_TH_BG 0x8 +#define ATV_TOP_CR_AMP_TH_DK 0x8 +#define ATV_TOP_CR_AMP_TH_I 0x8 +#define ATV_TOP_CR_CONT_CR_D_MN 0x18 +#define ATV_TOP_CR_CONT_CR_D_FM 0x0 +#define ATV_TOP_CR_CONT_CR_D_L 0x20 +#define ATV_TOP_CR_CONT_CR_D_LP 0x20 +#define ATV_TOP_CR_CONT_CR_D_BG 0x18 +#define ATV_TOP_CR_CONT_CR_D_DK 0x18 +#define ATV_TOP_CR_CONT_CR_D_I 0x18 +#define ATV_TOP_CR_CONT_CR_I_MN 0x80 +#define ATV_TOP_CR_CONT_CR_I_FM 0x0 +#define ATV_TOP_CR_CONT_CR_I_L 0x80 +#define ATV_TOP_CR_CONT_CR_I_LP 0x80 +#define ATV_TOP_CR_CONT_CR_I_BG 0x80 +#define ATV_TOP_CR_CONT_CR_I_DK 0x80 +#define ATV_TOP_CR_CONT_CR_I_I 0x80 +#define ATV_TOP_CR_CONT_CR_P_MN 0x4 +#define ATV_TOP_CR_CONT_CR_P_FM 0x0 +#define ATV_TOP_CR_CONT_CR_P_L 0x4 +#define ATV_TOP_CR_CONT_CR_P_LP 0x4 +#define ATV_TOP_CR_CONT_CR_P_BG 0x4 +#define ATV_TOP_CR_CONT_CR_P_DK 0x4 +#define ATV_TOP_CR_CONT_CR_P_I 0x4 +#define ATV_TOP_CR_OVM_TH_MN 0xA0 +#define ATV_TOP_CR_OVM_TH_FM 0x0 +#define ATV_TOP_CR_OVM_TH_L 0xA0 +#define ATV_TOP_CR_OVM_TH_LP 0xA0 +#define ATV_TOP_CR_OVM_TH_BG 0xA0 +#define ATV_TOP_CR_OVM_TH_DK 0xA0 +#define ATV_TOP_CR_OVM_TH_I 0xA0 +#define ATV_TOP_EQU0_EQU_C0_FM 0x0 +#define ATV_TOP_EQU0_EQU_C0_L 0x3 +#define ATV_TOP_EQU0_EQU_C0_LP 0x3 +#define ATV_TOP_EQU0_EQU_C0_BG 0x7 +#define ATV_TOP_EQU0_EQU_C0_DK 0x0 +#define ATV_TOP_EQU0_EQU_C0_I 0x3 +#define ATV_TOP_EQU1_EQU_C1_FM 0x0 +#define ATV_TOP_EQU1_EQU_C1_L 0x1F6 +#define ATV_TOP_EQU1_EQU_C1_LP 0x1F6 +#define ATV_TOP_EQU1_EQU_C1_BG 0x197 +#define ATV_TOP_EQU1_EQU_C1_DK 0x198 +#define ATV_TOP_EQU1_EQU_C1_I 0x1F6 +#define ATV_TOP_EQU2_EQU_C2_FM 0x0 +#define ATV_TOP_EQU2_EQU_C2_L 0x28 +#define ATV_TOP_EQU2_EQU_C2_LP 0x28 +#define ATV_TOP_EQU2_EQU_C2_BG 0xC5 +#define ATV_TOP_EQU2_EQU_C2_DK 0xB0 +#define ATV_TOP_EQU2_EQU_C2_I 0x28 +#define ATV_TOP_EQU3_EQU_C3_FM 0x0 +#define ATV_TOP_EQU3_EQU_C3_L 0x192 +#define ATV_TOP_EQU3_EQU_C3_LP 0x192 +#define ATV_TOP_EQU3_EQU_C3_BG 0x12E +#define ATV_TOP_EQU3_EQU_C3_DK 0x18E +#define ATV_TOP_EQU3_EQU_C3_I 0x192 +#define ATV_TOP_STD_MODE_MN 0x0 +#define ATV_TOP_STD_MODE_FM 0x1 +#define ATV_TOP_STD_MODE_L 0x0 +#define ATV_TOP_STD_MODE_LP 0x0 +#define ATV_TOP_STD_MODE_BG 0x0 +#define ATV_TOP_STD_MODE_DK 0x0 +#define ATV_TOP_STD_MODE_I 0x0 +#define ATV_TOP_STD_VID_POL_MN 0x0 +#define ATV_TOP_STD_VID_POL_FM 0x0 +#define ATV_TOP_STD_VID_POL_L 0x2 +#define ATV_TOP_STD_VID_POL_LP 0x2 +#define ATV_TOP_STD_VID_POL_BG 0x0 +#define ATV_TOP_STD_VID_POL_DK 0x0 +#define ATV_TOP_STD_VID_POL_I 0x0 +#define ATV_TOP_VID_AMP_MN 0x380 +#define ATV_TOP_VID_AMP_FM 0x0 +#define ATV_TOP_VID_AMP_L 0xF50 +#define ATV_TOP_VID_AMP_LP 0xF50 +#define ATV_TOP_VID_AMP_BG 0x380 +#define ATV_TOP_VID_AMP_DK 0x394 +#define ATV_TOP_VID_AMP_I 0x3D8 +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 +/*** END DJCOMBO patches to DRXJ registermap *********************************/ + +#include "drx_driver_version.h" + +/* #define DRX_DEBUG */ +#ifdef DRX_DEBUG +#include <stdio.h> +#endif + +/*----------------------------------------------------------------------------- +ENUMS +----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- +DEFINES +----------------------------------------------------------------------------*/ +#ifndef DRXJ_WAKE_UP_KEY +#define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr) +#endif + +/* +* \def DRXJ_DEF_I2C_ADDR +* \brief Default I2C address of a demodulator instance. +*/ +#define DRXJ_DEF_I2C_ADDR (0x52) + +/* +* \def DRXJ_DEF_DEMOD_DEV_ID +* \brief Default device identifier of a demodultor instance. +*/ +#define DRXJ_DEF_DEMOD_DEV_ID (1) + +/* +* \def DRXJ_SCAN_TIMEOUT +* \brief Timeout value for waiting on demod lock during channel scan (millisec). +*/ +#define DRXJ_SCAN_TIMEOUT 1000 + +/* +* \def HI_I2C_DELAY +* \brief HI timing delay for I2C timing (in nano seconds) +* +* Used to compute HI_CFG_DIV +*/ +#define HI_I2C_DELAY 42 + +/* +* \def HI_I2C_BRIDGE_DELAY +* \brief HI timing delay for I2C timing (in nano seconds) +* +* Used to compute HI_CFG_BDL +*/ +#define HI_I2C_BRIDGE_DELAY 750 + +/* +* \brief Time Window for MER and SER Measurement in Units of Segment duration. +*/ +#define VSB_TOP_MEASUREMENT_PERIOD 64 +#define SYMBOLS_PER_SEGMENT 832 + +/* +* \brief bit rate and segment rate constants used for SER and BER. +*/ +/* values taken from the QAM microcode */ +#define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0 +#define DRXJ_QAM_SL_SIG_POWER_QPSK 32768 +#define DRXJ_QAM_SL_SIG_POWER_QAM8 24576 +#define DRXJ_QAM_SL_SIG_POWER_QAM16 40960 +#define DRXJ_QAM_SL_SIG_POWER_QAM32 20480 +#define DRXJ_QAM_SL_SIG_POWER_QAM64 43008 +#define DRXJ_QAM_SL_SIG_POWER_QAM128 20992 +#define DRXJ_QAM_SL_SIG_POWER_QAM256 43520 +/* +* \brief Min supported symbolrates. +*/ +#ifndef DRXJ_QAM_SYMBOLRATE_MIN +#define DRXJ_QAM_SYMBOLRATE_MIN (520000) +#endif + +/* +* \brief Max supported symbolrates. +*/ +#ifndef DRXJ_QAM_SYMBOLRATE_MAX +#define DRXJ_QAM_SYMBOLRATE_MAX (7233000) +#endif + +/* +* \def DRXJ_QAM_MAX_WAITTIME +* \brief Maximal wait time for QAM auto constellation in ms +*/ +#ifndef DRXJ_QAM_MAX_WAITTIME +#define DRXJ_QAM_MAX_WAITTIME 900 +#endif + +#ifndef DRXJ_QAM_FEC_LOCK_WAITTIME +#define DRXJ_QAM_FEC_LOCK_WAITTIME 150 +#endif + +#ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME +#define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200 +#endif + +/* +* \def SCU status and results +* \brief SCU +*/ +#define DRX_SCU_READY 0 +#define DRXJ_MAX_WAITTIME 100 /* ms */ +#define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */ +#define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */ + +/* +* \def DRX_AUD_MAX_DEVIATION +* \brief Needed for calculation of prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_FM_DEVIATION +#define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */ +#endif + +/* +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_NICAM_PRESCALE +#define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#endif + +/* +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRXJ_AUD_MAX_WAITTIME +#define DRXJ_AUD_MAX_WAITTIME 250 /* ms */ +#endif + +/* ATV config changed flags */ +#define DRXJ_ATV_CHANGED_COEF (0x00000001UL) +#define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL) +#define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL) +#define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL) +#define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL) + +/* UIO define */ +#define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0 +#define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1 + +/* + * MICROCODE RELATED DEFINES + */ + +/* Magic word for checking correct Endianness of microcode data */ +#define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L')) + +/* CRC flag in ucode header, flags field. */ +#define DRX_UCODE_CRC_FLAG (0x0001) + +/* + * Maximum size of buffer used to verify the microcode. + * Must be an even number + */ +#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE) + +#if DRX_UCODE_MAX_BUF_SIZE & 1 +#error DRX_UCODE_MAX_BUF_SIZE must be an even number +#endif + +/* + * Power mode macros + */ + +#define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \ + (mode == DRX_POWER_MODE_10) || \ + (mode == DRX_POWER_MODE_11) || \ + (mode == DRX_POWER_MODE_12) || \ + (mode == DRX_POWER_MODE_13) || \ + (mode == DRX_POWER_MODE_14) || \ + (mode == DRX_POWER_MODE_15) || \ + (mode == DRX_POWER_MODE_16) || \ + (mode == DRX_POWER_DOWN)) + +/* Pin safe mode macro */ +#define DRXJ_PIN_SAFE_MODE 0x0000 +/*============================================================================*/ +/*=== GLOBAL VARIABLEs =======================================================*/ +/*============================================================================*/ +/* +*/ + +/* +* \brief Temporary register definitions. +* (register definitions that are not yet available in register master) +*/ + +/*****************************************************************************/ +/* Audio block 0x103 is write only. To avoid shadowing in driver accessing */ +/* RAM addresses directly. This must be READ ONLY to avoid problems. */ +/* Writing to the interface addresses are more than only writing the RAM */ +/* locations */ +/*****************************************************************************/ +/* +* \brief RAM location of MODUS registers +*/ +#define AUD_DEM_RAM_MODUS_HI__A 0x10204A3 +#define AUD_DEM_RAM_MODUS_HI__M 0xF000 + +#define AUD_DEM_RAM_MODUS_LO__A 0x10204A4 +#define AUD_DEM_RAM_MODUS_LO__M 0x0FFF + +/* +* \brief RAM location of I2S config registers +*/ +#define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1 +#define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2 + +/* +* \brief RAM location of DCO config registers +*/ +#define AUD_DEM_RAM_DCO_B_HI__A 0x1020461 +#define AUD_DEM_RAM_DCO_B_LO__A 0x1020462 +#define AUD_DEM_RAM_DCO_A_HI__A 0x1020463 +#define AUD_DEM_RAM_DCO_A_LO__A 0x1020464 + +/* +* \brief RAM location of Threshold registers +*/ +#define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A +#define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB +#define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6 + +/* +* \brief RAM location of Carrier Threshold registers +*/ +#define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF +#define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0 + +/* +* \brief FM Matrix register fix +*/ +#ifdef AUD_DEM_WR_FM_MATRIX__A +#undef AUD_DEM_WR_FM_MATRIX__A +#endif +#define AUD_DEM_WR_FM_MATRIX__A 0x105006F + +/*============================================================================*/ +/* +* \brief Defines required for audio +*/ +#define AUD_VOLUME_ZERO_DB 115 +#define AUD_VOLUME_DB_MIN -60 +#define AUD_VOLUME_DB_MAX 12 +#define AUD_CARRIER_STRENGTH_QP_0DB 0x4000 +#define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421 +#define AUD_MAX_AVC_REF_LEVEL 15 +#define AUD_I2S_FREQUENCY_MAX 48000UL +#define AUD_I2S_FREQUENCY_MIN 12000UL +#define AUD_RDS_ARRAY_SIZE 18 + +/* +* \brief Needed for calculation of prescale feature in AUD +*/ +#ifndef DRX_AUD_MAX_FM_DEVIATION +#define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */ +#endif + +/* +* \brief Needed for calculation of NICAM prescale feature in AUD +*/ +#ifndef DRX_AUD_MAX_NICAM_PRESCALE +#define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */ +#endif + +/*============================================================================*/ +/* Values for I2S Master/Slave pin configurations */ +#define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004 +#define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004 +#define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000 + +#define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003 +#define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003 +#define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008 + +#define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004 +#define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008 +#define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004 +#define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000 + +/*============================================================================*/ +/*=== REGISTER ACCESS MACROS =================================================*/ +/*============================================================================*/ + +/* +* This macro is used to create byte arrays for block writes. +* Block writes speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +* x -> lowbyte(x), highbyte(x) +*/ +#define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ + ((u8)((((u16)x)>>8)&0xFF)) +/* +* This macro is used to convert byte array to 16 bit register value for block read. +* Block read speed up I2C traffic between host and demod. +* The macro takes care of the required byte order in a 16 bits word. +*/ +#define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8))) + +/*============================================================================*/ +/*=== MISC DEFINES ===========================================================*/ +/*============================================================================*/ + +/*============================================================================*/ +/*=== HI COMMAND RELATED DEFINES =============================================*/ +/*============================================================================*/ + +/* +* \brief General maximum number of retries for ucode command interfaces +*/ +#define DRXJ_MAX_RETRIES (100) + +/*============================================================================*/ +/*=== STANDARD RELATED MACROS ================================================*/ +/*============================================================================*/ + +#define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \ + (std == DRX_STANDARD_PAL_SECAM_DK) || \ + (std == DRX_STANDARD_PAL_SECAM_I) || \ + (std == DRX_STANDARD_PAL_SECAM_L) || \ + (std == DRX_STANDARD_PAL_SECAM_LP) || \ + (std == DRX_STANDARD_NTSC) || \ + (std == DRX_STANDARD_FM)) + +#define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \ + (std == DRX_STANDARD_ITU_B) || \ + (std == DRX_STANDARD_ITU_C) || \ + (std == DRX_STANDARD_ITU_D)) + +/*----------------------------------------------------------------------------- +GLOBAL VARIABLES +----------------------------------------------------------------------------*/ +/* + * DRXJ DAP structures + */ + +static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags); + + +static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata); + +static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 *data, u32 flags); + +static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 *data, u32 flags); + +static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags); + +static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 data, u32 flags); + +static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 data, u32 flags); + +static struct drxj_data drxj_data_g = { + false, /* has_lna : true if LNA (aka PGA) present */ + false, /* has_oob : true if OOB supported */ + false, /* has_ntsc: true if NTSC supported */ + false, /* has_btsc: true if BTSC supported */ + false, /* has_smatx: true if SMA_TX pin is available */ + false, /* has_smarx: true if SMA_RX pin is available */ + false, /* has_gpio : true if GPIO pin is available */ + false, /* has_irqn : true if IRQN pin is available */ + 0, /* mfx A1/A2/A... */ + + /* tuner settings */ + false, /* tuner mirrors RF signal */ + /* standard/channel settings */ + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_CONSTELLATION_AUTO, /* constellation */ + 0, /* frequency in KHz */ + DRX_BANDWIDTH_UNKNOWN, /* curr_bandwidth */ + DRX_MIRROR_NO, /* mirror */ + + /* signal quality information: */ + /* default values taken from the QAM Programming guide */ + /* fec_bits_desired should not be less than 4000000 */ + 4000000, /* fec_bits_desired */ + 5, /* fec_vd_plen */ + 4, /* qam_vd_prescale */ + 0xFFFF, /* qamVDPeriod */ + 204 * 8, /* fec_rs_plen annex A */ + 1, /* fec_rs_prescale */ + FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */ + true, /* reset_pkt_err_acc */ + 0, /* pkt_err_acc_start */ + + /* HI configuration */ + 0, /* hi_cfg_timing_div */ + 0, /* hi_cfg_bridge_delay */ + 0, /* hi_cfg_wake_up_key */ + 0, /* hi_cfg_ctrl */ + 0, /* HICfgTimeout */ + /* UIO configuration */ + DRX_UIO_MODE_DISABLE, /* uio_sma_rx_mode */ + DRX_UIO_MODE_DISABLE, /* uio_sma_tx_mode */ + DRX_UIO_MODE_DISABLE, /* uioASELMode */ + DRX_UIO_MODE_DISABLE, /* uio_irqn_mode */ + /* FS setting */ + 0UL, /* iqm_fs_rate_ofs */ + false, /* pos_image */ + /* RC setting */ + 0UL, /* iqm_rc_rate_ofs */ + /* AUD information */ +/* false, * flagSetAUDdone */ +/* false, * detectedRDS */ +/* true, * flagASDRequest */ +/* false, * flagHDevClear */ +/* false, * flagHDevSet */ +/* (u16) 0xFFF, * rdsLastCount */ + + /* ATV configuration */ + 0UL, /* flags cfg changes */ + /* shadow of ATV_TOP_EQU0__A */ + {-5, + ATV_TOP_EQU0_EQU_C0_FM, + ATV_TOP_EQU0_EQU_C0_L, + ATV_TOP_EQU0_EQU_C0_LP, + ATV_TOP_EQU0_EQU_C0_BG, + ATV_TOP_EQU0_EQU_C0_DK, + ATV_TOP_EQU0_EQU_C0_I}, + /* shadow of ATV_TOP_EQU1__A */ + {-50, + ATV_TOP_EQU1_EQU_C1_FM, + ATV_TOP_EQU1_EQU_C1_L, + ATV_TOP_EQU1_EQU_C1_LP, + ATV_TOP_EQU1_EQU_C1_BG, + ATV_TOP_EQU1_EQU_C1_DK, + ATV_TOP_EQU1_EQU_C1_I}, + /* shadow of ATV_TOP_EQU2__A */ + {210, + ATV_TOP_EQU2_EQU_C2_FM, + ATV_TOP_EQU2_EQU_C2_L, + ATV_TOP_EQU2_EQU_C2_LP, + ATV_TOP_EQU2_EQU_C2_BG, + ATV_TOP_EQU2_EQU_C2_DK, + ATV_TOP_EQU2_EQU_C2_I}, + /* shadow of ATV_TOP_EQU3__A */ + {-160, + ATV_TOP_EQU3_EQU_C3_FM, + ATV_TOP_EQU3_EQU_C3_L, + ATV_TOP_EQU3_EQU_C3_LP, + ATV_TOP_EQU3_EQU_C3_BG, + ATV_TOP_EQU3_EQU_C3_DK, + ATV_TOP_EQU3_EQU_C3_I}, + false, /* flag: true=bypass */ + ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */ + ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */ + true, /* flag CVBS output enable */ + false, /* flag SIF output enable */ + DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */ + { /* qam_rf_agc_cfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ + 0x0000, /* speed */ + 0x0000, /* top */ + 0x0000 /* c.o.c. */ + }, + { /* qam_if_agc_cfg */ + DRX_STANDARD_ITU_B, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsb_rf_agc_cfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + { /* vsb_if_agc_cfg */ + DRX_STANDARD_8VSB, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level */ + 0xFFFF, /* max_output_level */ + 0x0000, /* speed */ + 0x0000, /* top (don't care) */ + 0x0000 /* c.o.c. (don't care) */ + }, + 0, /* qam_pga_cfg */ + 0, /* vsb_pga_cfg */ + { /* qam_pre_saw_cfg */ + DRX_STANDARD_ITU_B, /* standard */ + 0, /* reference */ + false /* use_pre_saw */ + }, + { /* vsb_pre_saw_cfg */ + DRX_STANDARD_8VSB, /* standard */ + 0, /* reference */ + false /* use_pre_saw */ + }, + + /* Version information */ +#ifndef _CH_ + { + "01234567890", /* human readable version microcode */ + "01234567890" /* human readable version device specific code */ + }, + { + { /* struct drx_version for microcode */ + DRX_MODULE_UNKNOWN, + (char *)(NULL), + 0, + 0, + 0, + (char *)(NULL) + }, + { /* struct drx_version for device specific code */ + DRX_MODULE_UNKNOWN, + (char *)(NULL), + 0, + 0, + 0, + (char *)(NULL) + } + }, + { + { /* struct drx_version_list for microcode */ + (struct drx_version *) (NULL), + (struct drx_version_list *) (NULL) + }, + { /* struct drx_version_list for device specific code */ + (struct drx_version *) (NULL), + (struct drx_version_list *) (NULL) + } + }, +#endif + false, /* smart_ant_inverted */ + /* Tracking filter setting for OOB */ + { + 12000, + 9300, + 6600, + 5280, + 3700, + 3000, + 2000, + 0}, + false, /* oob_power_on */ + 0, /* mpeg_ts_static_bitrate */ + false, /* disable_te_ihandling */ + false, /* bit_reverse_mpeg_outout */ + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpeg_output_clock_rate */ + DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpeg_start_width */ + + /* Pre SAW & Agc configuration for ATV */ + { + DRX_STANDARD_NTSC, /* standard */ + 7, /* reference */ + true /* use_pre_saw */ + }, + { /* ATV RF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level (d.c.) */ + 0, /* max_output_level (d.c.) */ + 3, /* speed */ + 9500, /* top */ + 4000 /* cut-off current */ + }, + { /* ATV IF-AGC */ + DRX_STANDARD_NTSC, /* standard */ + DRX_AGC_CTRL_AUTO, /* ctrl_mode */ + 0, /* output_level */ + 0, /* min_output_level (d.c.) */ + 0, /* max_output_level (d.c.) */ + 3, /* speed */ + 2400, /* top */ + 0 /* c.o.c. (d.c.) */ + }, + 140, /* ATV PGA config */ + 0, /* curr_symbol_rate */ + + false, /* pdr_safe_mode */ + SIO_PDR_GPIO_CFG__PRE, /* pdr_safe_restore_val_gpio */ + SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */ + SIO_PDR_SMA_RX_CFG__PRE, /* pdr_safe_restore_val_sma_rx */ + SIO_PDR_SMA_TX_CFG__PRE, /* pdr_safe_restore_val_sma_tx */ + + 4, /* oob_pre_saw */ + DRXJ_OOB_LO_POW_MINUS10DB, /* oob_lo_pow */ + { + false /* aud_data, only first member */ + }, +}; + +/* +* \var drxj_default_addr_g +* \brief Default I2C address and device identifier. +*/ +static struct i2c_device_addr drxj_default_addr_g = { + DRXJ_DEF_I2C_ADDR, /* i2c address */ + DRXJ_DEF_DEMOD_DEV_ID /* device id */ +}; + +/* +* \var drxj_default_comm_attr_g +* \brief Default common attributes of a drxj demodulator instance. +*/ +static struct drx_common_attr drxj_default_comm_attr_g = { + NULL, /* ucode file */ + true, /* ucode verify switch */ + {0}, /* version record */ + + 44000, /* IF in kHz in case no tuner instance is used */ + (151875 - 0), /* system clock frequency in kHz */ + 0, /* oscillator frequency kHz */ + 0, /* oscillator deviation in ppm, signed */ + false, /* If true mirror frequency spectrum */ + { + /* MPEG output configuration */ + true, /* If true, enable MPEG output */ + false, /* If true, insert RS byte */ + false, /* If true, parallel out otherwise serial */ + false, /* If true, invert DATA signals */ + false, /* If true, invert ERR signal */ + false, /* If true, invert STR signals */ + false, /* If true, invert VAL signals */ + false, /* If true, invert CLK signals */ + true, /* If true, static MPEG clockrate will + be used, otherwise clockrate will + adapt to the bitrate of the TS */ + 19392658UL, /* Maximum bitrate in b/s in case + static clockrate is selected */ + DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */ + }, + /* Initilisations below can be omitted, they require no user input and + are initially 0, NULL or false. The compiler will initialize them to these + values when omitted. */ + false, /* is_opened */ + + /* SCAN */ + NULL, /* no scan params yet */ + 0, /* current scan index */ + 0, /* next scan frequency */ + false, /* scan ready flag */ + 0, /* max channels to scan */ + 0, /* nr of channels scanned */ + NULL, /* default scan function */ + NULL, /* default context pointer */ + 0, /* millisec to wait for demod lock */ + DRXJ_DEMOD_LOCK, /* desired lock */ + false, + + /* Power management */ + DRX_POWER_UP, + + /* Tuner */ + 1, /* nr of I2C port to which tuner is */ + 0L, /* minimum RF input frequency, in kHz */ + 0L, /* maximum RF input frequency, in kHz */ + false, /* Rf Agc Polarity */ + false, /* If Agc Polarity */ + false, /* tuner slow mode */ + + { /* current channel (all 0) */ + 0UL /* channel.frequency */ + }, + DRX_STANDARD_UNKNOWN, /* current standard */ + DRX_STANDARD_UNKNOWN, /* previous standard */ + DRX_STANDARD_UNKNOWN, /* di_cache_standard */ + false, /* use_bootloader */ + 0UL, /* capabilities */ + 0 /* mfx */ +}; + +/* +* \var drxj_default_demod_g +* \brief Default drxj demodulator instance. +*/ +static struct drx_demod_instance drxj_default_demod_g = { + &drxj_default_addr_g, /* i2c address & device id */ + &drxj_default_comm_attr_g, /* demod common attributes */ + &drxj_data_g /* demod device specific attributes */ +}; + +/* +* \brief Default audio data structure for DRK demodulator instance. +* +* This structure is DRXK specific. +* +*/ +static struct drx_aud_data drxj_default_aud_data_g = { + false, /* audio_is_active */ + DRX_AUD_STANDARD_AUTO, /* audio_standard */ + + /* i2sdata */ + { + false, /* output_enable */ + 48000, /* frequency */ + DRX_I2S_MODE_MASTER, /* mode */ + DRX_I2S_WORDLENGTH_32, /* word_length */ + DRX_I2S_POLARITY_RIGHT, /* polarity */ + DRX_I2S_FORMAT_WS_WITH_DATA /* format */ + }, + /* volume */ + { + true, /* mute; */ + 0, /* volume */ + DRX_AUD_AVC_OFF, /* avc_mode */ + 0, /* avc_ref_level */ + DRX_AUD_AVC_MAX_GAIN_12DB, /* avc_max_gain */ + DRX_AUD_AVC_MAX_ATTEN_24DB, /* avc_max_atten */ + 0, /* strength_left */ + 0 /* strength_right */ + }, + DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */ + /* ass_thresholds */ + { + 440, /* A2 */ + 12, /* BTSC */ + 700, /* NICAM */ + }, + /* carrier */ + { + /* a */ + { + 42, /* thres */ + DRX_NO_CARRIER_NOISE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + /* b */ + { + 42, /* thres */ + DRX_NO_CARRIER_MUTE, /* opt */ + 0, /* shift */ + 0 /* dco */ + }, + + }, + /* mixer */ + { + DRX_AUD_SRC_STEREO_OR_A, /* source_i2s */ + DRX_AUD_I2S_MATRIX_STEREO, /* matrix_i2s */ + DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */ + }, + DRX_AUD_DEVIATION_NORMAL, /* deviation */ + DRX_AUD_AVSYNC_OFF, /* av_sync */ + + /* prescale */ + { + DRX_AUD_MAX_FM_DEVIATION, /* fm_deviation */ + DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */ + }, + DRX_AUD_FM_DEEMPH_75US, /* deemph */ + DRX_BTSC_STEREO, /* btsc_detect */ + 0, /* rds_data_counter */ + false /* rds_data_present */ +}; + +/*----------------------------------------------------------------------------- +STRUCTURES +----------------------------------------------------------------------------*/ +struct drxjeq_stat { + u16 eq_mse; + u8 eq_mode; + u8 eq_ctrl; + u8 eq_stat; +}; + +/* HI command */ +struct drxj_hi_cmd { + u16 cmd; + u16 param1; + u16 param2; + u16 param3; + u16 param4; + u16 param5; + u16 param6; +}; + +/*============================================================================*/ +/*=== MICROCODE RELATED STRUCTURES ===========================================*/ +/*============================================================================*/ + +/* + * struct drxu_code_block_hdr - Structure of the microcode block headers + * + * @addr: Destination address of the data in this block + * @size: Size of the block data following this header counted in + * 16 bits words + * @CRC: CRC value of the data block, only valid if CRC flag is + * set. + */ +struct drxu_code_block_hdr { + u32 addr; + u16 size; + u16 flags; + u16 CRC; +}; + +/*----------------------------------------------------------------------------- +FUNCTIONS +----------------------------------------------------------------------------*/ +/* Some prototypes */ +static int +hi_command(struct i2c_device_addr *dev_addr, + const struct drxj_hi_cmd *cmd, u16 *result); + +static int +ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat); + +static int +ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode); + +static int power_down_aud(struct drx_demod_instance *demod); + +static int +ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw); + +static int +ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain); + +/*============================================================================*/ +/*============================================================================*/ +/*== HELPER FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + + +/*============================================================================*/ + +/* +* \fn u32 frac28(u32 N, u32 D) +* \brief Compute: (1<<28)*N/D +* \param N 32 bits +* \param D 32 bits +* \return (1<<28)*N/D +* This function is used to avoid floating-point calculations as they may +* not be present on the target platform. + +* frac28 performs an unsigned 28/28 bits division to 32-bit fixed point +* fraction used for setting the Frequency Shifter registers. +* N and D can hold numbers up to width: 28-bits. +* The 4 bits integer part and the 28 bits fractional part are calculated. + +* Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999 + +* N: 0...(1<<28)-1 = 268435454 +* D: 0...(1<<28)-1 +* Q: 0...(1<<32)-1 +*/ +static u32 frac28(u32 N, u32 D) +{ + int i = 0; + u32 Q1 = 0; + u32 R0 = 0; + + R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ + Q1 = N / D; /* integer part, only the 4 least significant bits + will be visible in the result */ + + /* division using radix 16, 7 nibbles in the result */ + for (i = 0; i < 7; i++) { + Q1 = (Q1 << 4) | R0 / D; + R0 = (R0 % D) << 4; + } + /* rounding */ + if ((R0 >> 3) >= D) + Q1++; + + return Q1; +} + +/* +* \fn u32 log1_times100( u32 x) +* \brief Compute: 100*log10(x) +* \param x 32 bits +* \return 100*log10(x) +* +* 100*log10(x) +* = 100*(log2(x)/log2(10))) +* = (100*(2^15)*log2(x))/((2^15)*log2(10)) +* = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2 +* = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2 +* = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2 +* +* where y = 2^k and 1<= (x/y) < 2 +*/ + +static u32 log1_times100(u32 x) +{ + static const u8 scale = 15; + static const u8 index_width = 5; + /* + log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n )) + 0 <= n < ((1<<INDEXWIDTH)+1) + */ + + static const u32 log2lut[] = { + 0, /* 0.000000 */ + 290941, /* 290941.300628 */ + 573196, /* 573196.476418 */ + 847269, /* 847269.179851 */ + 1113620, /* 1113620.489452 */ + 1372674, /* 1372673.576986 */ + 1624818, /* 1624817.752104 */ + 1870412, /* 1870411.981536 */ + 2109788, /* 2109787.962654 */ + 2343253, /* 2343252.817465 */ + 2571091, /* 2571091.461923 */ + 2793569, /* 2793568.696416 */ + 3010931, /* 3010931.055901 */ + 3223408, /* 3223408.452106 */ + 3431216, /* 3431215.635215 */ + 3634553, /* 3634553.498355 */ + 3833610, /* 3833610.244726 */ + 4028562, /* 4028562.434393 */ + 4219576, /* 4219575.925308 */ + 4406807, /* 4406806.721144 */ + 4590402, /* 4590401.736809 */ + 4770499, /* 4770499.491025 */ + 4947231, /* 4947230.734179 */ + 5120719, /* 5120719.018555 */ + 5291081, /* 5291081.217197 */ + 5458428, /* 5458427.996830 */ + 5622864, /* 5622864.249668 */ + 5784489, /* 5784489.488298 */ + 5943398, /* 5943398.207380 */ + 6099680, /* 6099680.215452 */ + 6253421, /* 6253420.939751 */ + 6404702, /* 6404701.706649 */ + 6553600, /* 6553600.000000 */ + }; + + u8 i = 0; + u32 y = 0; + u32 d = 0; + u32 k = 0; + u32 r = 0; + + if (x == 0) + return 0; + + /* Scale x (normalize) */ + /* computing y in log(x/y) = log(x) - log(y) */ + if ((x & (((u32) (-1)) << (scale + 1))) == 0) { + for (k = scale; k > 0; k--) { + if (x & (((u32) 1) << scale)) + break; + x <<= 1; + } + } else { + for (k = scale; k < 31; k++) { + if ((x & (((u32) (-1)) << (scale + 1))) == 0) + break; + x >>= 1; + } + } + /* + Now x has binary point between bit[scale] and bit[scale-1] + and 1.0 <= x < 2.0 */ + + /* correction for division: log(x) = log(x/y)+log(y) */ + y = k * ((((u32) 1) << scale) * 200); + + /* remove integer part */ + x &= ((((u32) 1) << scale) - 1); + /* get index */ + i = (u8) (x >> (scale - index_width)); + /* compute delta (x-a) */ + d = x & ((((u32) 1) << (scale - index_width)) - 1); + /* compute log, multiplication ( d* (.. )) must be within range ! */ + y += log2lut[i] + + ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width)); + /* Conver to log10() */ + y /= 108853; /* (log2(10) << scale) */ + r = (y >> 1); + /* rounding */ + if (y & ((u32)1)) + r++; + + return r; + +} + +/* +* \fn u32 frac_times1e6( u16 N, u32 D) +* \brief Compute: (N/D) * 1000000. +* \param N nominator 16-bits. +* \param D denominator 32-bits. +* \return u32 +* \retval ((N/D) * 1000000), 32 bits +* +* No check on D=0! +*/ +static u32 frac_times1e6(u32 N, u32 D) +{ + u32 remainder = 0; + u32 frac = 0; + + /* + frac = (N * 1000000) / D + To let it fit in a 32 bits computation: + frac = (N * (1000000 >> 4)) / (D >> 4) + This would result in a problem in case D < 16 (div by 0). + So we do it more elaborate as shown below. + */ + frac = (((u32) N) * (1000000 >> 4)) / D; + frac <<= 4; + remainder = (((u32) N) * (1000000 >> 4)) % D; + remainder <<= 4; + frac += remainder / D; + remainder = remainder % D; + if ((remainder * 2) > D) + frac++; + + return frac; +} + +/*============================================================================*/ + + +/* +* \brief Values for NICAM prescaler gain. Computed from dB to integer +* and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20). +* +*/ +#if 0 +/* Currently, unused as we lack support for analog TV */ +static const u16 nicam_presc_table_val[43] = { + 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, + 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16, + 18, 20, 23, 25, 28, 32, 36, 40, 45, + 51, 57, 64, 71, 80, 90, 101, 113, 127 +}; +#endif + +/*============================================================================*/ +/*== END HELPER FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== DRXJ DAP FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* + This layer takes care of some device specific register access protocols: + -conversion to short address format + -access to audio block + This layer is placed between the drx_dap_fasi and the rest of the drxj + specific implementation. This layer can use address map knowledge whereas + dap_fasi may not use memory map knowledge. + + * For audio currently only 16 bits read and write register access is + supported. More is not needed. RMW and 32 or 8 bit access on audio + registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast + single/multi master) will be ignored. + + TODO: check ignoring single/multimaster is ok for AUD access ? +*/ + +#define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false) +#define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */ +/*============================================================================*/ + +/* +* \fn bool is_handled_by_aud_tr_if( u32 addr ) +* \brief Check if this address is handled by the audio token ring interface. +* \param addr +* \return bool +* \retval true Yes, handled by audio token ring interface +* \retval false No, not handled by audio token ring interface +* +*/ +static +bool is_handled_by_aud_tr_if(u32 addr) +{ + bool retval = false; + + if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) && + (DRXDAP_FASI_ADDR2BANK(addr) > 1) && + (DRXDAP_FASI_ADDR2BANK(addr) < 6)) { + retval = true; + } + + return retval; +} + +/*============================================================================*/ + +int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, + u16 w_count, + u8 *wData, + struct i2c_device_addr *r_dev_addr, + u16 r_count, u8 *r_data) +{ + struct drx39xxj_state *state; + struct i2c_msg msg[2]; + unsigned int num_msgs; + + if (w_dev_addr == NULL) { + /* Read only */ + state = r_dev_addr->user_data; + msg[0].addr = r_dev_addr->i2c_addr >> 1; + msg[0].flags = I2C_M_RD; + msg[0].buf = r_data; + msg[0].len = r_count; + num_msgs = 1; + } else if (r_dev_addr == NULL) { + /* Write only */ + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + num_msgs = 1; + } else { + /* Both write and read */ + state = w_dev_addr->user_data; + msg[0].addr = w_dev_addr->i2c_addr >> 1; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + msg[1].addr = r_dev_addr->i2c_addr >> 1; + msg[1].flags = I2C_M_RD; + msg[1].buf = r_data; + msg[1].len = r_count; + num_msgs = 2; + } + + if (state->i2c == NULL) { + pr_err("i2c was zero, aborting\n"); + return 0; + } + if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { + pr_warn("drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } + +#ifdef DJH_DEBUG + if (w_dev_addr == NULL || r_dev_addr == NULL) + return 0; + + state = w_dev_addr->user_data; + + if (state->i2c == NULL) + return 0; + + msg[0].addr = w_dev_addr->i2c_addr; + msg[0].flags = 0; + msg[0].buf = wData; + msg[0].len = w_count; + msg[1].addr = r_dev_addr->i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].buf = r_data; + msg[1].len = r_count; + num_msgs = 2; + + pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", + w_dev_addr->i2c_addr, state->i2c, w_count, r_count); + + if (i2c_transfer(state->i2c, msg, 2) != 2) { + pr_warn("drx3933: I2C write/read failed\n"); + return -EREMOTEIO; + } +#endif + return 0; +} + +/*============================================================================*/ + +/***************************** +* +* int drxdap_fasi_read_block ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 datasize, -- number of bytes to read +* u8 *data, -- data to receive +* u32 flags) -- special device flags +* +* Read block data from chip address. Because the chip is word oriented, +* the number of bytes to read must be even. +* +* Make sure that the buffer to receive the data is large enough. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data read back is NOT translated to the endianness of +* the target platform. +* +* Output: +* - 0 if reading was successful +* in that case: data read is in *data. +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags) +{ + u8 buf[4]; + u16 bufx; + int rc; + u16 overhead_size = 0; + + /* Check parameters ******************************************************* */ + if (dev_addr == NULL) + return -EINVAL; + + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); + + if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || + ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && + DRXDAP_FASI_LONG_FORMAT(addr)) || + (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { + return -EINVAL; + } + + /* ReadModifyWrite & mode flag bits are not allowed */ + flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS); +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Read block from I2C **************************************************** */ + do { + u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ? + datasize : DRXDAP_MAX_RCHUNKSIZE); + + bufx = 0; + + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; + +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) + /* short format address preferred but long format otherwise */ + if (DRXDAP_FASI_LONG_FORMAT(addr)) { +#endif +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) + buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8) ((addr >> 7) & 0xFF); +#endif +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) + } else { +#endif +#if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) + buf[bufx++] = (u8) ((addr << 1) & 0xFF); + buf[bufx++] = + (u8) (((addr >> 16) & 0x0F) | + ((addr >> 18) & 0xF0)); +#endif +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)) + } +#endif + +#if DRXDAP_SINGLE_MASTER + /* + * In single master mode, split the read and write actions. + * No special action is needed for write chunks here. + */ + rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, + NULL, 0, NULL); + if (rc == 0) + rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data); +#else + /* In multi master mode, do everything in one RW action */ + rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, + data); +#endif + data += todo; + addr += (todo >> 1); + datasize -= todo; + } while (datasize && rc == 0); + + return rc; +} + + +/***************************** +* +* int drxdap_fasi_read_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 *data, -- data to receive +* u32 flags) -- special device flags +* +* Read one 16-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - 0 if reading was successful +* in that case: read data is at *data +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 *data, u32 flags) +{ + u8 buf[sizeof(*data)]; + int rc; + + if (!data) + return -EINVAL; + + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); + *data = buf[0] + (((u16) buf[1]) << 8); + return rc; +} + +/***************************** +* +* int drxdap_fasi_read_reg32 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u32 *data, -- data to receive +* u32 flags) -- special device flags +* +* Read one 32-bit register or memory location. The data received back is +* converted back to the target platform's endianness. +* +* Output: +* - 0 if reading was successful +* in that case: read data is at *data +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 *data, u32 flags) +{ + u8 buf[sizeof(*data)]; + int rc; + + if (!data) + return -EINVAL; + + rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); + *data = (((u32) buf[0]) << 0) + + (((u32) buf[1]) << 8) + + (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); + return rc; +} + +/***************************** +* +* int drxdap_fasi_write_block ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 datasize, -- number of bytes to read +* u8 *data, -- data to receive +* u32 flags) -- special device flags +* +* Write block data to chip address. Because the chip is word oriented, +* the number of bytes to write must be even. +* +* Although this function expects an even number of bytes, it is still byte +* oriented, and the data being written is NOT translated from the endianness of +* the target platform. +* +* Output: +* - 0 if writing was successful +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, u32 flags) +{ + u8 buf[DRXDAP_MAX_WCHUNKSIZE]; + int st = -EIO; + int first_err = 0; + u16 overhead_size = 0; + u16 block_size = 0; + + /* Check parameters ******************************************************* */ + if (dev_addr == NULL) + return -EINVAL; + + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + + (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); + + if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || + ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && + DRXDAP_FASI_LONG_FORMAT(addr)) || + (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) || + ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) + return -EINVAL; + + flags &= DRXDAP_FASI_FLAGS; + flags &= ~DRXDAP_FASI_MODEFLAGS; +#if DRXDAP_SINGLE_MASTER + flags |= DRXDAP_FASI_SINGLE_MASTER; +#endif + + /* Write block to I2C ***************************************************** */ + block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1; + do { + u16 todo = 0; + u16 bufx = 0; + + /* Buffer device address */ + addr &= ~DRXDAP_FASI_FLAGS; + addr |= flags; +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) + /* short format address preferred but long format otherwise */ + if (DRXDAP_FASI_LONG_FORMAT(addr)) { +#endif +#if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) + buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01); + buf[bufx++] = (u8) ((addr >> 16) & 0xFF); + buf[bufx++] = (u8) ((addr >> 24) & 0xFF); + buf[bufx++] = (u8) ((addr >> 7) & 0xFF); +#endif +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) + } else { +#endif +#if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) + buf[bufx++] = (u8) ((addr << 1) & 0xFF); + buf[bufx++] = + (u8) (((addr >> 16) & 0x0F) | + ((addr >> 18) & 0xF0)); +#endif +#if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)) + } +#endif + + /* + In single master mode block_size can be 0. In such a case this I2C + sequense will be visible: (1) write address {i2c addr, + 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } + (3) write address (4) write data etc... + Address must be rewritten because HI is reset after data transport and + expects an address. + */ + todo = (block_size < datasize ? block_size : datasize); + if (todo == 0) { + u16 overhead_size_i2c_addr = 0; + u16 data_block_size = 0; + + overhead_size_i2c_addr = + (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); + data_block_size = + (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1; + + /* write device address */ + st = drxbsp_i2c_write_read(dev_addr, + (u16) (bufx), + buf, + (struct i2c_device_addr *)(NULL), + 0, (u8 *)(NULL)); + + if ((st != 0) && (first_err == 0)) { + /* at the end, return the first error encountered */ + first_err = st; + } + bufx = 0; + todo = + (data_block_size < + datasize ? data_block_size : datasize); + } + memcpy(&buf[bufx], data, todo); + /* write (address if can do and) data */ + st = drxbsp_i2c_write_read(dev_addr, + (u16) (bufx + todo), + buf, + (struct i2c_device_addr *)(NULL), + 0, (u8 *)(NULL)); + + if ((st != 0) && (first_err == 0)) { + /* at the end, return the first error encountered */ + first_err = st; + } + datasize -= todo; + data += todo; + addr += (todo >> 1); + } while (datasize); + + return first_err; +} + +/***************************** +* +* int drxdap_fasi_write_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u16 data, -- data to send +* u32 flags) -- special device flags +* +* Write one 16-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - 0 if writing was successful +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 data, u32 flags) +{ + u8 buf[sizeof(data)]; + + buf[0] = (u8) ((data >> 0) & 0xFF); + buf[1] = (u8) ((data >> 8) & 0xFF); + + return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); +} + +/***************************** +* +* int drxdap_fasi_read_modify_write_reg16 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 waddr, -- address of chip register/memory +* u32 raddr, -- chip address to read back from +* u16 wdata, -- data to send +* u16 *rdata) -- data to receive back +* +* Write 16-bit data, then read back the original contents of that location. +* Requires long addressing format to be allowed. +* +* Before sending data, the data is converted to little endian. The +* data received back is converted back to the target platform's endianness. +* +* WARNING: This function is only guaranteed to work if there is one +* master on the I2C bus. +* +* Output: +* - 0 if reading was successful +* in that case: read back data is at *rdata +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata) +{ + int rc = -EIO; + +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) + if (rdata == NULL) + return -EINVAL; + + rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); + if (rc == 0) + rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); +#endif + + return rc; +} + +/***************************** +* +* int drxdap_fasi_write_reg32 ( +* struct i2c_device_addr *dev_addr, -- address of I2C device +* u32 addr, -- address of chip register/memory +* u32 data, -- data to send +* u32 flags) -- special device flags +* +* Write one 32-bit register or memory location. The data being written is +* converted from the target platform's endianness to little endian. +* +* Output: +* - 0 if writing was successful +* - -EIO if anything went wrong +* +******************************/ + +static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 data, u32 flags) +{ + u8 buf[sizeof(data)]; + + buf[0] = (u8) ((data >> 0) & 0xFF); + buf[1] = (u8) ((data >> 8) & 0xFF); + buf[2] = (u8) ((data >> 16) & 0xFF); + buf[3] = (u8) ((data >> 24) & 0xFF); + + return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags); +} + +/*============================================================================*/ + +/* +* \fn int drxj_dap_rm_write_reg16short +* \brief Read modify write 16 bits audio register using short format only. +* \param dev_addr +* \param waddr Address to write to +* \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A) +* \param wdata Data to write +* \param rdata Buffer for data to read +* \return int +* \retval 0 Success +* \retval -EIO Timeout, I2C error, illegal bank +* +* 16 bits register read modify write access using short addressing format only. +* Requires knowledge of the registermap, thus device dependent. +* Using DAP FASI directly to avoid endless recursion of RMWs to audio registers. +* +*/ + +/* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) + See comments drxj_dap_read_modify_write_reg16 */ +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0) +static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata) +{ + int rc; + + if (rdata == NULL) + return -EINVAL; + + /* Set RMW flag */ + rc = drxdap_fasi_write_reg16(dev_addr, + SIO_HI_RA_RAM_S0_FLG_ACC__A, + SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M, + 0x0000); + if (rc == 0) { + /* Write new data: triggers RMW */ + rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, + 0x0000); + } + if (rc == 0) { + /* Read old data */ + rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, + 0x0000); + } + if (rc == 0) { + /* Reset RMW flag */ + rc = drxdap_fasi_write_reg16(dev_addr, + SIO_HI_RA_RAM_S0_FLG_ACC__A, + 0, 0x0000); + } + + return rc; +} +#endif + +/*============================================================================*/ + +static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr, + u32 waddr, + u32 raddr, + u16 wdata, u16 *rdata) +{ + /* TODO: correct short/long addressing format decision, + now long format has higher prio then short because short also + needs virt bnks (not impl yet) for certain audio registers */ +#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1) + return drxdap_fasi_read_modify_write_reg16(dev_addr, + waddr, + raddr, wdata, rdata); +#else + return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata); +#endif +} + + +/*============================================================================*/ + +/* +* \fn int drxj_dap_read_aud_reg16 +* \brief Read 16 bits audio register +* \param dev_addr +* \param addr +* \param data +* \return int +* \retval 0 Success +* \retval -EIO Timeout, I2C error, illegal bank +* +* 16 bits register read access via audio token ring interface. +* +*/ +static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr, + u32 addr, u16 *data) +{ + u32 start_timer = 0; + u32 current_timer = 0; + u32 delta_timer = 0; + u16 tr_status = 0; + int stat = -EIO; + + /* No read possible for bank 3, return with error */ + if (DRXDAP_FASI_ADDR2BANK(addr) == 3) { + stat = -EINVAL; + } else { + const u32 write_bit = ((dr_xaddr_t) 1) << 16; + + /* Force reset write bit */ + addr &= (~write_bit); + + /* Set up read */ + start_timer = jiffies_to_msecs(jiffies); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = drxj_dap_read_modify_write_reg16(dev_addr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, &tr_status); + + if (stat != 0) + break; + + current_timer = jiffies_to_msecs(jiffies); + delta_timer = current_timer - start_timer; + if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + stat = -EIO; + break; + } + + } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || + ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL)); + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */ + + /* Wait for read ready status or timeout */ + if (stat == 0) { + start_timer = jiffies_to_msecs(jiffies); + + while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) != + AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) { + stat = drxj_dap_read_reg16(dev_addr, + AUD_TOP_TR_CTR__A, + &tr_status, 0x0000); + if (stat != 0) + break; + + current_timer = jiffies_to_msecs(jiffies); + delta_timer = current_timer - start_timer; + if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + stat = -EIO; + break; + } + } /* while ( ... ) */ + } + + /* Read value */ + if (stat == 0) + stat = drxj_dap_read_modify_write_reg16(dev_addr, + AUD_TOP_TR_RD_REG__A, + SIO_HI_RA_RAM_S0_RMWBUF__A, + 0x0000, data); + return stat; +} + +/*============================================================================*/ + +static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 *data, u32 flags) +{ + int stat = -EIO; + + /* Check param */ + if ((dev_addr == NULL) || (data == NULL)) + return -EINVAL; + + if (is_handled_by_aud_tr_if(addr)) + stat = drxj_dap_read_aud_reg16(dev_addr, addr, data); + else + stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags); + + return stat; +} +/*============================================================================*/ + +/* +* \fn int drxj_dap_write_aud_reg16 +* \brief Write 16 bits audio register +* \param dev_addr +* \param addr +* \param data +* \return int +* \retval 0 Success +* \retval -EIO Timeout, I2C error, illegal bank +* +* 16 bits register write access via audio token ring interface. +* +*/ +static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr, + u32 addr, u16 data) +{ + int stat = -EIO; + + /* No write possible for bank 2, return with error */ + if (DRXDAP_FASI_ADDR2BANK(addr) == 2) { + stat = -EINVAL; + } else { + u32 start_timer = 0; + u32 current_timer = 0; + u32 delta_timer = 0; + u16 tr_status = 0; + const u32 write_bit = ((dr_xaddr_t) 1) << 16; + + /* Force write bit */ + addr |= write_bit; + start_timer = jiffies_to_msecs(jiffies); + do { + /* RMW to aud TR IF until request is granted or timeout */ + stat = drxj_dap_read_modify_write_reg16(dev_addr, + addr, + SIO_HI_RA_RAM_S0_RMWBUF__A, + data, &tr_status); + if (stat != 0) + break; + + current_timer = jiffies_to_msecs(jiffies); + delta_timer = current_timer - start_timer; + if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) { + stat = -EIO; + break; + } + + } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) == + AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) || + ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) == + AUD_TOP_TR_CTR_FIFO_FULL_FULL)); + + } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */ + + return stat; +} + +/*============================================================================*/ + +static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 data, u32 flags) +{ + int stat = -EIO; + + /* Check param */ + if (dev_addr == NULL) + return -EINVAL; + + if (is_handled_by_aud_tr_if(addr)) + stat = drxj_dap_write_aud_reg16(dev_addr, addr, data); + else + stat = drxdap_fasi_write_reg16(dev_addr, + addr, data, flags); + + return stat; +} + +/*============================================================================*/ + +/* Free data ram in SIO HI */ +#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 +#define SIO_HI_RA_RAM_USR_END__A 0x420060 + +#define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) +#define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) +#define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ +#define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE + +/* +* \fn int drxj_dap_atomic_read_write_block() +* \brief Basic access routine for atomic read or write access +* \param dev_addr pointer to i2c dev address +* \param addr destination/source address +* \param datasize size of data buffer in bytes +* \param data pointer to data buffer +* \return int +* \retval 0 Success +* \retval -EIO Timeout, I2C error, illegal bank +* +*/ +static +int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr, + u32 addr, + u16 datasize, + u8 *data, bool read_flag) +{ + struct drxj_hi_cmd hi_cmd; + int rc; + u16 word; + u16 dummy = 0; + u16 i = 0; + + /* Parameter check */ + if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8)) + return -EINVAL; + + /* Set up HI parameters to read or write n bytes */ + hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY; + hi_cmd.param1 = + (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) + + DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START)); + hi_cmd.param2 = + (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START); + hi_cmd.param3 = (u16) ((datasize / 2) - 1); + if (!read_flag) + hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE; + else + hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ; + hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) + + DRXDAP_FASI_ADDR2BANK(addr)); + hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr); + + if (!read_flag) { + /* write data to buffer */ + for (i = 0; i < (datasize / 2); i++) { + + word = ((u16) data[2 * i]); + word += (((u16) data[(2 * i) + 1]) << 8); + drxj_dap_write_reg16(dev_addr, + (DRXJ_HI_ATOMIC_BUF_START + i), + word, 0); + } + } + + rc = hi_command(dev_addr, &hi_cmd, &dummy); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (read_flag) { + /* read data from buffer */ + for (i = 0; i < (datasize / 2); i++) { + rc = drxj_dap_read_reg16(dev_addr, + (DRXJ_HI_ATOMIC_BUF_START + i), + &word, 0); + if (rc) { + pr_err("error %d\n", rc); + goto rw_error; + } + data[2 * i] = (u8) (word & 0xFF); + data[(2 * i) + 1] = (u8) (word >> 8); + } + } + + return 0; + +rw_error: + return rc; + +} + +/*============================================================================*/ + +/* +* \fn int drxj_dap_atomic_read_reg32() +* \brief Atomic read of 32 bits words +*/ +static +int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr, + u32 addr, + u32 *data, u32 flags) +{ + u8 buf[sizeof(*data)] = { 0 }; + int rc; + u32 word = 0; + + if (!data) + return -EINVAL; + + rc = drxj_dap_atomic_read_write_block(dev_addr, addr, + sizeof(*data), buf, true); + + if (rc < 0) + return 0; + + word = (u32) buf[3]; + word <<= 8; + word |= (u32) buf[2]; + word <<= 8; + word |= (u32) buf[1]; + word <<= 8; + word |= (u32) buf[0]; + + *data = word; + + return rc; +} + +/*============================================================================*/ + +/*============================================================================*/ +/*== END DRXJ DAP FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== HOST INTERFACE FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* +* \fn int hi_cfg_command() +* \brief Configure HI with settings stored in the demod structure. +* \param demod Demodulator. +* \return int. +* +* This routine was created because to much orthogonal settings have +* been put into one HI API function (configure). Especially the I2C bridge +* enable/disable should not need re-configuration of the HI. +* +*/ +static int hi_cfg_command(const struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct drxj_hi_cmd hi_cmd; + u16 result = 0; + int rc; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG; + hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + hi_cmd.param2 = ext_attr->hi_cfg_timing_div; + hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay; + hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key; + hi_cmd.param5 = ext_attr->hi_cfg_ctrl; + hi_cmd.param6 = ext_attr->hi_cfg_transmit; + + rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Reset power down flag (set one call only) */ + ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); + + return 0; + +rw_error: + return rc; +} + +/* +* \fn int hi_command() +* \brief Configure HI with settings stored in the demod structure. +* \param dev_addr I2C address. +* \param cmd HI command. +* \param result HI command result. +* \return int. +* +* Sends command to HI +* +*/ +static int +hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result) +{ + u16 wait_cmd = 0; + u16 nr_retries = 0; + bool powerdown_cmd = false; + int rc; + + /* Write parameters */ + switch (cmd->cmd) { + + case SIO_HI_RA_RAM_CMD_CONFIG: + case SIO_HI_RA_RAM_CMD_ATOMIC_COPY: + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case SIO_HI_RA_RAM_CMD_BRDCTRL: + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case SIO_HI_RA_RAM_CMD_NULL: + /* No parameters */ + break; + + default: + return -EINVAL; + } + + /* Write command */ + rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) + msleep(1); + + /* Detect power down to omit reading result */ + powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && + (((cmd-> + param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) + == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); + if (!powerdown_cmd) { + /* Wait until command rdy */ + do { + nr_retries++; + if (nr_retries > DRXJ_MAX_RETRIES) { + pr_err("timeout\n"); + goto rw_error; + } + + rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } while (wait_cmd != 0); + + /* Read result */ + rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + } + /* if ( powerdown_cmd == true ) */ + return 0; +rw_error: + return rc; +} + +/* +* \fn int init_hi( const struct drx_demod_instance *demod ) +* \brief Initialise and configurate HI. +* \param demod pointer to demod data. +* \return int Return status. +* \retval 0 Success. +* \retval -EIO Failure. +* +* Needs to know Psys (System Clock period) and Posc (Osc Clock period) +* Need to store configuration in driver because of the way I2C +* bridging is controlled. +* +*/ +static int init_hi(const struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + + /* PATCH for bug 5003, HI ucode v3.1.0 */ + rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Timing div, 250ns/Psys */ + /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ + ext_attr->hi_cfg_timing_div = + (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000; + /* Clipping */ + if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) + ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; + /* Bridge delay, uses oscilator clock */ + /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ + /* SDA brdige delay */ + ext_attr->hi_cfg_bridge_delay = + (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) / + 1000; + /* Clipping */ + if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) + ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; + /* SCL bridge delay, same as SDA for now */ + ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) << + SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B); + /* Wakeup key, setting the read flag (as suggest in the documentation) does + not always result into a working solution (barebones worked VI2C failed). + Not setting the bit works in all cases . */ + ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY; + /* port/bridge/power down ctrl */ + ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE); + /* transit mode time out delay and watch dog divider */ + ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE; + + rc = hi_cfg_command(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; + +rw_error: + return rc; +} + +/*============================================================================*/ +/*== END HOST INTERFACE FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== AUXILIARY FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* +* \fn int get_device_capabilities() +* \brief Get and store device capabilities. +* \param demod Pointer to demodulator instance. +* \return int. +* \return 0 Success +* \retval -EIO Failure +* +* Depending on pulldowns on MDx pins the following internals are set: +* * common_attr->osc_clock_freq +* * ext_attr->has_lna +* * ext_attr->has_ntsc +* * ext_attr->has_btsc +* * ext_attr->has_oob +* +*/ +static int get_device_capabilities(struct drx_demod_instance *demod) +{ + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + struct drxj_data *ext_attr = (struct drxj_data *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + u16 sio_pdr_ohw_cfg = 0; + u32 sio_top_jtagid_lo = 0; + u16 bid = 0; + int rc; + + common_attr = (struct drx_common_attr *) demod->my_common_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; + + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { + case 0: + /* ignore (bypass ?) */ + break; + case 1: + /* 27 MHz */ + common_attr->osc_clock_freq = 27000; + break; + case 2: + /* 20.25 MHz */ + common_attr->osc_clock_freq = 20250; + break; + case 3: + /* 4 MHz */ + common_attr->osc_clock_freq = 4000; + break; + default: + return -EIO; + } + + /* + Determine device capabilities + Based on pinning v47 + */ + rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF); + + switch ((sio_top_jtagid_lo >> 12) & 0xFF) { + case 0x31: + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + bid = (bid >> 10) & 0xf; + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->has_lna = true; + ext_attr->has_ntsc = false; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = false; + ext_attr->has_gpio = false; + ext_attr->has_irqn = false; + break; + case 0x33: + ext_attr->has_lna = false; + ext_attr->has_ntsc = false; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = false; + ext_attr->has_gpio = false; + ext_attr->has_irqn = false; + break; + case 0x45: + ext_attr->has_lna = true; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; + break; + case 0x46: + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = false; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; + break; + case 0x41: + ext_attr->has_lna = true; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; + break; + case 0x43: + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = false; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = false; + break; + case 0x32: + ext_attr->has_lna = true; + ext_attr->has_ntsc = false; + ext_attr->has_btsc = false; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; + break; + case 0x34: + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; + break; + case 0x42: + ext_attr->has_lna = true; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; + break; + case 0x44: + ext_attr->has_lna = false; + ext_attr->has_ntsc = true; + ext_attr->has_btsc = true; + ext_attr->has_oob = true; + ext_attr->has_smatx = true; + ext_attr->has_smarx = true; + ext_attr->has_gpio = true; + ext_attr->has_irqn = true; + break; + default: + /* Unknown device variant */ + return -EIO; + break; + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn int power_up_device() +* \brief Power up device. +* \param demod Pointer to demodulator instance. +* \return int. +* \return 0 Success +* \retval -EIO Failure, I2C or max retries reached +* +*/ + +#ifndef DRXJ_MAX_RETRIES_POWERUP +#define DRXJ_MAX_RETRIES_POWERUP 10 +#endif + +static int power_up_device(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + u8 data = 0; + u16 retry_count = 0; + struct i2c_device_addr wake_up_addr; + + dev_addr = demod->my_i2c_dev_addr; + wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY; + wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id; + wake_up_addr.user_data = dev_addr->user_data; + /* + * I2C access may fail in this case: no ack + * dummy write must be used to wake uop device, dummy read must be used to + * reset HI state machine (avoiding actual writes) + */ + do { + data = 0; + drxbsp_i2c_write_read(&wake_up_addr, 1, &data, + (struct i2c_device_addr *)(NULL), 0, + (u8 *)(NULL)); + msleep(10); + retry_count++; + } while ((drxbsp_i2c_write_read + ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1, + &data) + != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP)); + + /* Need some recovery time .... */ + msleep(10); + + if (retry_count == DRXJ_MAX_RETRIES_POWERUP) + return -EIO; + + return 0; +} + +/*----------------------------------------------------------------------------*/ +/* MPEG Output Configuration Functions - begin */ +/*----------------------------------------------------------------------------*/ +/* +* \fn int ctrl_set_cfg_mpeg_output() +* \brief Set MPEG output configuration of the device. +* \param devmod Pointer to demodulator instance. +* \param cfg_data Pointer to mpeg output configuaration. +* \return int. +* +* Configure MPEG output parameters. +* +*/ +static int +ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data) +{ + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL); + int rc; + u16 fec_oc_reg_mode = 0; + u16 fec_oc_reg_ipr_mode = 0; + u16 fec_oc_reg_ipr_invert = 0; + u32 max_bit_rate = 0; + u32 rcn_rate = 0; + u32 nr_bits = 0; + u16 sio_pdr_md_cfg = 0; + /* data mask for the output data byte */ + u16 invert_data_mask = + FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | + FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | + FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | + FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; + + /* check arguments */ + if ((demod == NULL) || (cfg_data == NULL)) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + + if (cfg_data->enable_mpeg_output == true) { + /* quick and dirty patch to set MPEG in case current std is not + producing MPEG */ + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + break; + default: + return 0; + } + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* 2048 bytes fifo ram */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Low Water Mark for synchronization */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* High Water Mark for synchronization */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + switch (ext_attr->constellation) { + case DRX_CONSTELLATION_QAM256: + nr_bits = 8; + break; + case DRX_CONSTELLATION_QAM128: + nr_bits = 7; + break; + case DRX_CONSTELLATION_QAM64: + nr_bits = 6; + break; + case DRX_CONSTELLATION_QAM32: + nr_bits = 5; + break; + case DRX_CONSTELLATION_QAM16: + nr_bits = 4; + break; + default: + return -EIO; + } /* ext_attr->constellation */ + /* max_bit_rate = symbol_rate * nr_bits * coef */ + /* coef = 188/204 */ + max_bit_rate = + (ext_attr->curr_symbol_rate / 8) * nr_bits * 188; + fallthrough; /* as b/c Annex A/C need following settings */ + case DRX_STANDARD_ITU_B: + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cfg_data->static_clk == true) { + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + break; + } /* switch (standard) */ + + /* Check insertion of the Reed-Solomon parity bytes */ + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cfg_data->insert_rs_byte == true) { + /* enable parity symbol forward */ + fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; + /* MVAL disable during parity bytes */ + fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + rcn_rate = 0x004854D3; + break; + case DRX_STANDARD_ITU_B: + fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M; + switch (ext_attr->constellation) { + case DRX_CONSTELLATION_QAM256: + rcn_rate = 0x008945E7; + break; + case DRX_CONSTELLATION_QAM64: + rcn_rate = 0x005F64D4; + break; + default: + return -EIO; + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */ + rcn_rate = + (frac28 + (max_bit_rate, + (u32) (common_attr->sys_clock_freq / 8))) / + 188; + break; + default: + return -EIO; + } /* ext_attr->standard */ + } else { /* insert_rs_byte == false */ + + /* disable parity symbol forward */ + fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M); + /* MVAL enable during parity bytes */ + fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + rcn_rate = 0x0041605C; + break; + case DRX_STANDARD_ITU_B: + fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M); + switch (ext_attr->constellation) { + case DRX_CONSTELLATION_QAM256: + rcn_rate = 0x0082D6A0; + break; + case DRX_CONSTELLATION_QAM64: + rcn_rate = 0x005AEC1A; + break; + default: + return -EIO; + } + break; + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */ + rcn_rate = + (frac28 + (max_bit_rate, + (u32) (common_attr->sys_clock_freq / 8))) / + 204; + break; + default: + return -EIO; + } /* ext_attr->standard */ + } + + if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */ + fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); + } else { /* MPEG data output is serial -> set ipr_mode[0] */ + fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M; + } + + /* Control slective inversion of output bits */ + if (cfg_data->invert_data == true) + fec_oc_reg_ipr_invert |= invert_data_mask; + else + fec_oc_reg_ipr_invert &= (~(invert_data_mask)); + + if (cfg_data->invert_err == true) + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; + else + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); + + if (cfg_data->invert_str == true) + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; + else + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); + + if (cfg_data->invert_val == true) + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; + else + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); + + if (cfg_data->invert_clk == true) + fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; + else + fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + + + if (cfg_data->static_clk == true) { /* Static mode */ + u32 dto_rate = 0; + u32 bit_rate = 0; + u16 fec_oc_dto_burst_len = 0; + u16 fec_oc_dto_period = 0; + + fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE; + + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + fec_oc_dto_period = 4; + if (cfg_data->insert_rs_byte == true) + fec_oc_dto_burst_len = 208; + break; + case DRX_STANDARD_ITU_A: + { + u32 symbol_rate_th = 6400000; + if (cfg_data->insert_rs_byte == true) { + fec_oc_dto_burst_len = 204; + symbol_rate_th = 5900000; + } + if (ext_attr->curr_symbol_rate >= + symbol_rate_th) { + fec_oc_dto_period = 0; + } else { + fec_oc_dto_period = 1; + } + } + break; + case DRX_STANDARD_ITU_B: + fec_oc_dto_period = 1; + if (cfg_data->insert_rs_byte == true) + fec_oc_dto_burst_len = 128; + break; + case DRX_STANDARD_ITU_C: + fec_oc_dto_period = 1; + if (cfg_data->insert_rs_byte == true) + fec_oc_dto_burst_len = 204; + break; + default: + return -EIO; + } + bit_rate = + common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + + 2); + dto_rate = + frac28(bit_rate, common_attr->sys_clock_freq * 1000); + dto_rate >>= 3; + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) + fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { /* Dynamic mode */ + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Write appropriate registers with requested configuration */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* enabling for both parallel and serial now */ + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Set MPEG TS pads to outputmode */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + sio_pdr_md_cfg = + MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH << + SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B; + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to output mode */ + sio_pdr_md_cfg = + MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH << + SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << + SIO_PDR_MD0_CFG_MODE__B; + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + /* Enable Monitor Bus output over MPEG pads and ctl input */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Write nomagic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Set MPEG TS pads to inputmode */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Enable Monitor Bus output over MPEG pads and ctl input */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Write nomagic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* save values for restore after re-acquire */ + common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output; + + return 0; +rw_error: + return rc; +} + +/*----------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------*/ +/* MPEG Output Configuration Functions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* miscellaneous configurations - begin */ +/*----------------------------------------------------------------------------*/ + +/* +* \fn int set_mpegtei_handling() +* \brief Activate MPEG TEI handling settings. +* \param devmod Pointer to demodulator instance. +* \return int. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static int set_mpegtei_handling(struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; + u16 fec_oc_dpr_mode = 0; + u16 fec_oc_snc_mode = 0; + u16 fec_oc_ems_mode = 0; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* reset to default, allow TEI bit to be changed */ + fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M); + fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M | + FEC_OC_SNC_MODE_CORR_DISABLE__M)); + fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M); + + if (ext_attr->disable_te_ihandling) { + /* do not change TEI bit */ + fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M; + fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M | + ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B)); + fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B)); + } + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*----------------------------------------------------------------------------*/ +/* +* \fn int bit_reverse_mpeg_output() +* \brief Set MPEG output bit-endian settings. +* \param devmod Pointer to demodulator instance. +* \return int. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static int bit_reverse_mpeg_output(struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + int rc; + u16 fec_oc_ipr_mode = 0; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* reset to default (normal bit order) */ + fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M); + + if (ext_attr->bit_reverse_mpeg_outout) + fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M; + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*----------------------------------------------------------------------------*/ +/* +* \fn int set_mpeg_start_width() +* \brief Set MPEG start width. +* \param devmod Pointer to demodulator instance. +* \return int. +* +* This routine should be called during a set channel of QAM/VSB +* +*/ +static int set_mpeg_start_width(struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL); + struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; + int rc; + u16 fec_oc_comm_mb = 0; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = demod->my_common_attr; + + if ((common_attr->mpeg_cfg.static_clk == true) + && (common_attr->mpeg_cfg.enable_parallel == false)) { + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON; + if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) + fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON; + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + return 0; +rw_error: + return rc; +} + +/*----------------------------------------------------------------------------*/ +/* miscellaneous configurations - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* UIO Configuration Functions - begin */ +/*----------------------------------------------------------------------------*/ +/* +* \fn int ctrl_set_uio_cfg() +* \brief Configure modus oprandi UIO. +* \param demod Pointer to demodulator instance. +* \param uio_cfg Pointer to a configuration setting for a certain UIO. +* \return int. +*/ +static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; + + if ((uio_cfg == NULL) || (demod == NULL)) + return -EINVAL; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + switch (uio_cfg->uio) { + /*====================================================================*/ + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (!ext_attr->has_smatx) + return -EIO; + switch (uio_cfg->mode) { + case DRX_UIO_MODE_FIRMWARE_SMA: + case DRX_UIO_MODE_FIRMWARE_SAW: + case DRX_UIO_MODE_READWRITE: + ext_attr->uio_sma_tx_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + ext_attr->uio_sma_tx_mode = uio_cfg->mode; + /* pad configuration register is set 0 - input mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + } /* switch ( uio_cfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (!ext_attr->has_smarx) + return -EIO; + switch (uio_cfg->mode) { + case DRX_UIO_MODE_FIRMWARE0: + case DRX_UIO_MODE_READWRITE: + ext_attr->uio_sma_rx_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + ext_attr->uio_sma_rx_mode = uio_cfg->mode; + /* pad configuration register is set 0 - input mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + } /* switch ( uio_cfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO3: + /* DRX_UIO3: GPIO UIO-3 */ + if (!ext_attr->has_gpio) + return -EIO; + switch (uio_cfg->mode) { + case DRX_UIO_MODE_FIRMWARE0: + case DRX_UIO_MODE_READWRITE: + ext_attr->uio_gpio_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + ext_attr->uio_gpio_mode = uio_cfg->mode; + /* pad configuration register is set 0 - input mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + } /* switch ( uio_cfg->mode ) */ + break; + /*====================================================================*/ + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (!ext_attr->has_irqn) + return -EIO; + switch (uio_cfg->mode) { + case DRX_UIO_MODE_READWRITE: + ext_attr->uio_irqn_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_DISABLE: + /* pad configuration register is set 0 - input mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->uio_irqn_mode = uio_cfg->mode; + break; + case DRX_UIO_MODE_FIRMWARE0: + default: + return -EINVAL; + } /* switch ( uio_cfg->mode ) */ + break; + /*====================================================================*/ + default: + return -EINVAL; + } /* switch ( uio_cfg->uio ) */ + + /* Write magic word to disable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn int ctrl_uio_write() +* \brief Write to a UIO. +* \param demod Pointer to demodulator instance. +* \param uio_data Pointer to data container for a certain UIO. +* \return int. +*/ +static int +ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data) +{ + struct drxj_data *ext_attr = (struct drxj_data *) (NULL); + int rc; + u16 pin_cfg_value = 0; + u16 value = 0; + + if ((uio_data == NULL) || (demod == NULL)) + return -EINVAL; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + switch (uio_data->uio) { + /*====================================================================*/ + case DRX_UIO1: + /* DRX_UIO1: SMA_TX UIO-1 */ + if (!ext_attr->has_smatx) + return -EIO; + if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) + && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) { + return -EIO; + } + pin_cfg_value = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pin_cfg_value |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* use corresponding bit in io data output registar */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!uio_data->value) + value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ + else + value |= 0x8000; /* write one to 15th bit - 1st UIO */ + + /* write back to io data output register */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + /*======================================================================*/ + case DRX_UIO2: + /* DRX_UIO2: SMA_RX UIO-2 */ + if (!ext_attr->has_smarx) + return -EIO; + if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) + return -EIO; + + pin_cfg_value = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pin_cfg_value |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* use corresponding bit in io data output registar */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!uio_data->value) + value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ + else + value |= 0x4000; /* write one to 14th bit - 2nd UIO */ + + /* write back to io data output register */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + /*====================================================================*/ + case DRX_UIO3: + /* DRX_UIO3: ASEL UIO-3 */ + if (!ext_attr->has_gpio) + return -EIO; + if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) + return -EIO; + + pin_cfg_value = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pin_cfg_value |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* use corresponding bit in io data output registar */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!uio_data->value) + value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ + else + value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ + + /* write back to io data output register */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + /*=====================================================================*/ + case DRX_UIO4: + /* DRX_UIO4: IRQN UIO-4 */ + if (!ext_attr->has_irqn) + return -EIO; + + if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) + return -EIO; + + pin_cfg_value = 0; + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + pin_cfg_value |= 0x0113; + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + + /* write to io pad configuration register - output mode */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* use corresponding bit in io data output registar */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (uio_data->value == false) + value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ + else + value |= 0x1000; /* write one to 12th bit - 4th UIO */ + + /* write back to io data output register */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + /*=====================================================================*/ + default: + return -EINVAL; + } /* switch ( uio_data->uio ) */ + + /* Write magic word to disable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*---------------------------------------------------------------------------*/ +/* UIO Configuration Functions - end */ +/*---------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* I2C Bridge Functions - begin */ +/*----------------------------------------------------------------------------*/ +/* +* \fn int ctrl_i2c_bridge() +* \brief Open or close the I2C switch to tuner. +* \param demod Pointer to demodulator instance. +* \param bridge_closed Pointer to bool indication if bridge is closed not. +* \return int. + +*/ +static int +ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed) +{ + struct drxj_hi_cmd hi_cmd; + u16 result = 0; + + /* check arguments */ + if (bridge_closed == NULL) + return -EINVAL; + + hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL; + hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY; + if (*bridge_closed) + hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED; + else + hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN; + + return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); +} + +/*----------------------------------------------------------------------------*/ +/* I2C Bridge Functions - end */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* Smart antenna Functions - begin */ +/*----------------------------------------------------------------------------*/ +/* +* \fn int smart_ant_init() +* \brief Initialize Smart Antenna. +* \param pointer to struct drx_demod_instance. +* \return int. +* +*/ +static int smart_ant_init(struct drx_demod_instance *demod) +{ + struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA }; + int rc; + u16 data = 0; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* init smart antenna */ + rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (ext_attr->smart_ant_inverted) { + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* config SMA_TX pin to smart antenna mode */ + rc = ctrl_set_uio_cfg(demod, &uio_cfg); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Write magic word to disable pdr reg write */ + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd) +{ + int rc; + u16 cur_cmd = 0; + unsigned long timeout; + + /* Check param */ + if (cmd == NULL) + return -EINVAL; + + /* Wait until SCU command interface is ready to receive command */ + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cur_cmd != DRX_SCU_READY) + return -EIO; + + switch (cmd->parameter_len) { + case 5: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case 4: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case 3: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case 2: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case 1: + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return -EIO; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Wait until SCU has processed command */ + timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME); + while (time_is_after_jiffies(timeout)) { + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (cur_cmd == DRX_SCU_READY) + break; + usleep_range(1000, 2000); + } + + if (cur_cmd != DRX_SCU_READY) + return -EIO; + + /* read results */ + if ((cmd->result_len > 0) && (cmd->result != NULL)) { + s16 err; + + switch (cmd->result_len) { + case 4: + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case 3: + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case 2: + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case 1: + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + fallthrough; + case 0: + /* do nothing */ + break; + default: + /* this number of parameters is not supported */ + return -EIO; + } + + /* Check if an error was reported by SCU */ + err = cmd->result[0]; + + /* check a few fixed error codes */ + if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD) + || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD) + || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR) + || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE) + ) { + return -EINVAL; + } + /* here it is assumed that negative means error, and positive no error */ + else if (err < 0) + return -EIO; + else + return 0; + } + + return 0; + +rw_error: + return rc; +} + +/* +* \fn int DRXJ_DAP_SCUAtomicReadWriteBlock() +* \brief Basic access routine for SCU atomic read or write access +* \param dev_addr pointer to i2c dev address +* \param addr destination/source address +* \param datasize size of data buffer in bytes +* \param data pointer to data buffer +* \return int +* \retval 0 Success +* \retval -EIO Timeout, I2C error, illegal bank +* +*/ +#define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2) +static +int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */ + u8 *data, bool read_flag) +{ + struct drxjscu_cmd scu_cmd; + int rc; + u16 set_param_parameters[18]; + u16 cmd_result[15]; + + /* Parameter check */ + if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16)) + return -EINVAL; + + set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr); + if (read_flag) { /* read */ + set_param_parameters[0] = ((~(0x0080)) & datasize); + scu_cmd.parameter_len = 2; + scu_cmd.result_len = datasize / 2 + 2; + } else { + int i = 0; + + set_param_parameters[0] = 0x0080 | datasize; + for (i = 0; i < (datasize / 2); i++) { + set_param_parameters[i + 2] = + (data[2 * i] | (data[(2 * i) + 1] << 8)); + } + scu_cmd.parameter_len = datasize / 2 + 2; + scu_cmd.result_len = 1; + } + + scu_cmd.command = + SCU_RAM_COMMAND_STANDARD_TOP | + SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS; + scu_cmd.result = cmd_result; + scu_cmd.parameter = set_param_parameters; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (read_flag) { + int i = 0; + /* read data from buffer */ + for (i = 0; i < (datasize / 2); i++) { + data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF); + data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8); + } + } + + return 0; + +rw_error: + return rc; + +} + +/*============================================================================*/ + +/* +* \fn int DRXJ_DAP_AtomicReadReg16() +* \brief Atomic read of 16 bits words +*/ +static +int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 *data, u32 flags) +{ + u8 buf[2] = { 0 }; + int rc; + u16 word = 0; + + if (!data) + return -EINVAL; + + rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); + if (rc < 0) + return rc; + + word = (u16) (buf[0] + (buf[1] << 8)); + + *data = word; + + return rc; +} + +/*============================================================================*/ +/* +* \fn int drxj_dap_scu_atomic_write_reg16() +* \brief Atomic read of 16 bits words +*/ +static +int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr, + u32 addr, + u16 data, u32 flags) +{ + u8 buf[2]; + int rc; + + buf[0] = (u8) (data & 0xff); + buf[1] = (u8) ((data >> 8) & 0xff); + + rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false); + + return rc; +} + +/* -------------------------------------------------------------------------- */ +/* +* \brief Measure result of ADC synchronisation +* \param demod demod instance +* \param count (returned) count +* \return int. +* \retval 0 Success +* \retval -EIO Failure: I2C error +* +*/ +static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count) +{ + struct i2c_device_addr *dev_addr = NULL; + int rc; + u16 data = 0; + + dev_addr = demod->my_i2c_dev_addr; + + /* Start measurement */ + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */ + msleep(1); + + *count = 0; + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (data == 127) + *count = *count + 1; + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (data == 127) + *count = *count + 1; + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (data == 127) + *count = *count + 1; + + return 0; +rw_error: + return rc; +} + +/* +* \brief Synchronize analog and digital clock domains +* \param demod demod instance +* \return int. +* \retval 0 Success +* \retval -EIO Failure: I2C error or failure to synchronize +* +* An IQM reset will also reset the results of this synchronization. +* After an IQM reset this routine needs to be called again. +* +*/ + +static int adc_synchronization(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + int rc; + u16 count = 0; + + dev_addr = demod->my_i2c_dev_addr; + + rc = adc_sync_measurement(demod, &count); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (count == 1) { + /* Try sampling on a different edge */ + u16 clk_neg = 0; + + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = adc_sync_measurement(demod, &count); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* TODO: implement fallback scenarios */ + if (count < 2) + return -EIO; + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ +/*== END AUXILIARY FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ +/* +* \fn int init_agc () +* \brief Initialize AGC for all standards. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return int. +*/ +static int init_agc(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drx_common_attr *common_attr = NULL; + struct drxj_data *ext_attr = NULL; + struct drxj_cfg_agc *p_agc_rf_settings = NULL; + struct drxj_cfg_agc *p_agc_if_settings = NULL; + int rc; + u16 ingain_tgt_max = 0; + u16 clp_dir_to = 0; + u16 sns_sum_max = 0; + u16 clp_sum_max = 0; + u16 sns_dir_to = 0; + u16 ki_innergain_min = 0; + u16 agc_ki = 0; + u16 ki_max = 0; + u16 if_iaccu_hi_tgt_min = 0; + u16 data = 0; + u16 agc_ki_dgain = 0; + u16 ki_min = 0; + u16 clp_ctrl_mode = 0; + u16 agc_rf = 0; + u16 agc_if = 0; + + dev_addr = demod->my_i2c_dev_addr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + switch (ext_attr->standard) { + case DRX_STANDARD_8VSB: + clp_sum_max = 1023; + clp_dir_to = (u16) (-9); + sns_sum_max = 1023; + sns_dir_to = (u16) (-9); + ki_innergain_min = (u16) (-32768); + ki_max = 0x032C; + agc_ki_dgain = 0xC; + if_iaccu_hi_tgt_min = 2047; + ki_min = 0x0117; + ingain_tgt_max = 16383; + clp_ctrl_mode = 0; + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg); + p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg); + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + case DRX_STANDARD_ITU_B: + ingain_tgt_max = 5119; + clp_sum_max = 1023; + clp_dir_to = (u16) (-5); + sns_sum_max = 127; + sns_dir_to = (u16) (-3); + ki_innergain_min = 0; + ki_max = 0x0657; + if_iaccu_hi_tgt_min = 2047; + agc_ki_dgain = 0x7; + ki_min = 0x0117; + clp_ctrl_mode = 0; + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); + p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + agc_ki &= 0xf000; + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#endif + default: + return -EINVAL; + } + + /* for new AGC interface */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Gain fed from inner to outer AGC */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set to p_agc_settings->top before */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + agc_rf = 0x800 + p_agc_rf_settings->cut_off_current; + if (common_attr->tuner_rf_agc_pol == true) + agc_rf = 0x87ff - agc_rf; + + agc_if = 0x800; + if (common_attr->tuner_if_agc_pol == true) + agc_rf = 0x87ff - agc_rf; + + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Set/restore Ki DGAIN factor */ + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_DGAIN__M; + data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn int set_frequency () +* \brief Set frequency shift. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \param tuner_freq_offset residual frequency from tuner. +* \return int. +*/ +static int +set_frequency(struct drx_demod_instance *demod, + struct drx_channel *channel, s32 tuner_freq_offset) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + int rc; + s32 sampling_frequency = 0; + s32 frequency_shift = 0; + s32 if_freq_actual = 0; + s32 rf_freq_residual = -1 * tuner_freq_offset; + s32 adc_freq = 0; + s32 intermediate_freq = 0; + u32 iqm_fs_rate_ofs = 0; + bool adc_flip = true; + bool select_pos_image = false; + bool rf_mirror; + bool tuner_mirror; + bool image_to_select; + s32 fm_frequency_shift = 0; + + rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false; + tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true; + /* + Program frequency shifter + No need to account for mirroring on RF + */ + switch (ext_attr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_8VSB: + select_pos_image = true; + break; + case DRX_STANDARD_FM: + /* After IQM FS sound carrier must appear at 4 Mhz in spect. + Sound carrier is already 3Mhz above centre frequency due + to tuner setting so now add an extra shift of 1MHz... */ + fm_frequency_shift = 1000; + fallthrough; + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + select_pos_image = false; + break; + default: + return -EINVAL; + } + intermediate_freq = demod->my_common_attr->intermediate_freq; + sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; + if (tuner_mirror) + if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift; + else + if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift; + if (if_freq_actual > sampling_frequency / 2) { + /* adc mirrors */ + adc_freq = sampling_frequency - if_freq_actual; + adc_flip = true; + } else { + /* adc doesn't mirror */ + adc_freq = if_freq_actual; + adc_flip = false; + } + + frequency_shift = adc_freq; + image_to_select = + (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image); + iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency); + + if (image_to_select) + iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1; + + /* Program frequency shifter with tuner offset compensation */ + /* frequency_shift += tuner_freq_offset; TODO */ + rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; + ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); + + return 0; +rw_error: + return rc; +} + +/* +* \fn int get_acc_pkt_err() +* \brief Retrieve signal strength for VSB and QAM. +* \param demod Pointer to demod instance +* \param packet_err Pointer to packet error +* \return int. +* \retval 0 sig_strength contains valid data. +* \retval -EINVAL sig_strength is NULL. +* \retval -EIO Erroneous data, sig_strength contains invalid data. +*/ +#ifdef DRXJ_SIGNAL_ACCUM_ERR +static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err) +{ + int rc; + static u16 pkt_err; + static u16 last_pkt_err; + u16 data = 0; + struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; + + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (ext_attr->reset_pkt_err_acc) { + last_pkt_err = data; + pkt_err = 0; + ext_attr->reset_pkt_err_acc = false; + } + + if (data < last_pkt_err) { + pkt_err += 0xffff - last_pkt_err; + pkt_err += data; + } else { + pkt_err += (data - last_pkt_err); + } + *packet_err = pkt_err; + last_pkt_err = data; + + return 0; +rw_error: + return rc; +} +#endif + + +/*============================================================================*/ + +/* +* \fn int set_agc_rf () +* \brief Configure RF AGC +* \param demod instance of demodulator. +* \param agc_settings AGC configuration structure +* \return int. +*/ +static int +set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + struct drxj_cfg_agc *p_agc_settings = NULL; + struct drx_common_attr *common_attr = NULL; + int rc; + drx_write_reg16func_t scu_wr16 = NULL; + drx_read_reg16func_t scu_rr16 = NULL; + + common_attr = (struct drx_common_attr *) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + if (atomic) { + scu_rr16 = drxj_dap_scu_atomic_read_reg16; + scu_wr16 = drxj_dap_scu_atomic_write_reg16; + } else { + scu_rr16 = drxj_dap_read_reg16; + scu_wr16 = drxj_dap_write_reg16; + } + + /* Configure AGC only if standard is currently active */ + if ((ext_attr->standard == agc_settings->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(agc_settings->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(agc_settings->standard))) { + u16 data = 0; + + switch (agc_settings->ctrl_mode) { + case DRX_AGC_CTRL_AUTO: + + /* Enable RF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Enable SCU RF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RF__M; + if (ext_attr->standard == DRX_STANDARD_8VSB) + data |= (2 << SCU_RAM_AGC_KI_RF__B); + else if (DRXJ_ISQAMSTD(ext_attr->standard)) + data |= (5 << SCU_RAM_AGC_KI_RF__B); + else + data |= (4 << SCU_RAM_AGC_KI_RF__B); + + if (common_attr->tuner_rf_agc_pol) + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Set speed ( using complementary reduction value ) */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (agc_settings->standard == DRX_STANDARD_8VSB) + p_agc_settings = &(ext_attr->vsb_if_agc_cfg); + else if (DRXJ_ISQAMSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->qam_if_agc_cfg); + else if (DRXJ_ISATVSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->atv_if_agc_cfg); + else + return -EINVAL; + + /* Set TOP, only if IF-AGC is in AUTO mode */ + if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* Cut-Off current */ + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_AGC_CTRL_USER: + + /* Enable RF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Disable SCU RF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RF__M; + if (common_attr->tuner_rf_agc_pol) + data |= SCU_RAM_AGC_KI_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Write value to output pin */ + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_AGC_CTRL_OFF: + + /* Disable RF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Disable SCU RF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RF__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + } /* switch ( agcsettings->ctrl_mode ) */ + } + + /* Store rf agc settings */ + switch (agc_settings->standard) { + case DRX_STANDARD_8VSB: + ext_attr->vsb_rf_agc_cfg = *agc_settings; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + ext_attr->qam_rf_agc_cfg = *agc_settings; + break; +#endif + default: + return -EIO; + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn int set_agc_if () +* \brief Configure If AGC +* \param demod instance of demodulator. +* \param agc_settings AGC configuration structure +* \return int. +*/ +static int +set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + struct drxj_cfg_agc *p_agc_settings = NULL; + struct drx_common_attr *common_attr = NULL; + drx_write_reg16func_t scu_wr16 = NULL; + drx_read_reg16func_t scu_rr16 = NULL; + int rc; + + common_attr = (struct drx_common_attr *) demod->my_common_attr; + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + if (atomic) { + scu_rr16 = drxj_dap_scu_atomic_read_reg16; + scu_wr16 = drxj_dap_scu_atomic_write_reg16; + } else { + scu_rr16 = drxj_dap_read_reg16; + scu_wr16 = drxj_dap_write_reg16; + } + + /* Configure AGC only if standard is currently active */ + if ((ext_attr->standard == agc_settings->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(agc_settings->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(agc_settings->standard))) { + u16 data = 0; + + switch (agc_settings->ctrl_mode) { + case DRX_AGC_CTRL_AUTO: + /* Enable IF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Enable SCU IF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data &= ~SCU_RAM_AGC_KI_IF__M; + if (ext_attr->standard == DRX_STANDARD_8VSB) + data |= (3 << SCU_RAM_AGC_KI_IF__B); + else if (DRXJ_ISQAMSTD(ext_attr->standard)) + data |= (6 << SCU_RAM_AGC_KI_IF__B); + else + data |= (5 << SCU_RAM_AGC_KI_IF__B); + + if (common_attr->tuner_if_agc_pol) + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Set speed (using complementary reduction value) */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; + rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (agc_settings->standard == DRX_STANDARD_8VSB) + p_agc_settings = &(ext_attr->vsb_rf_agc_cfg); + else if (DRXJ_ISQAMSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->qam_rf_agc_cfg); + else if (DRXJ_ISATVSTD(agc_settings->standard)) + p_agc_settings = &(ext_attr->atv_rf_agc_cfg); + else + return -EINVAL; + + /* Restore TOP */ + if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + break; + + case DRX_AGC_CTRL_USER: + + /* Enable IF AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE; + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Disable SCU IF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + if (common_attr->tuner_if_agc_pol) + data |= SCU_RAM_AGC_KI_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Write value to output pin */ + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + + case DRX_AGC_CTRL_OFF: + + /* Disable If AGC DAC */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Disable SCU IF AGC loop */ + rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M; + rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EINVAL; + } /* switch ( agcsettings->ctrl_mode ) */ + + /* always set the top to support configurations without if-loop */ + rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* Store if agc settings */ + switch (agc_settings->standard) { + case DRX_STANDARD_8VSB: + ext_attr->vsb_if_agc_cfg = *agc_settings; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + ext_attr->qam_if_agc_cfg = *agc_settings; + break; +#endif + default: + return -EIO; + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn int set_iqm_af () +* \brief Configure IQM AF registers +* \param demod instance of demodulator. +* \param active +* \return int. +*/ +static int set_iqm_af(struct drx_demod_instance *demod, bool active) +{ + u16 data = 0; + struct i2c_device_addr *dev_addr = NULL; + int rc; + + dev_addr = demod->my_i2c_dev_addr; + + /* Configure IQM */ + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!active) + data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE)); + else + data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE); + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ +/*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== 8VSB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* +* \fn int power_down_vsb () +* \brief Powr down QAM related blocks. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return int. +*/ +static int power_down_vsb(struct drx_demod_instance *demod, bool primary) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + struct drx_cfg_mpeg_output cfg_mpeg_output; + int rc; + u16 cmd_result = 0; + + /* + STOP demodulator + reset of FEC and VSB HW + */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* stop all comm_exec */ + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (primary) { + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_iqm_af(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + cfg_mpeg_output.enable_mpeg_output = false; + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn int set_vsb_leak_n_gain () +* \brief Set ATSC demod. +* \param demod instance of demodulator. +* \return int. +*/ +static int set_vsb_leak_n_gain(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + int rc; + + static const u8 vsb_ffe_leak_gain_ram0[] = { + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO4 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO5 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO6 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO7 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO8 */ + DRXJ_16TO8(0xf), /* FFETRAINLKRATIO9 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO10 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO11 */ + DRXJ_16TO8(0x8), /* FFETRAINLKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO12 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO1 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO2 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO3 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO4 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO5 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO6 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO7 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO8 */ + DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO9 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO10 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO11 */ + DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO12 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO1 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO2 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO3 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO4 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO5 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO6 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO7 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO8 */ + DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO9 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO10 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO11 */ + DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO12 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO1 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO2 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO3 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO4 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO5 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO6 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO7 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO8 */ + DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO9 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO10 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO11 */ + DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO12 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO1 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO2 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO3 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO4 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO5 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO6 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO7 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO8 */ + DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO9 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO10 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO11 */ + DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO12 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO1 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO2 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO3 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO4 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO5 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO6 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO7 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO8 */ + DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO9 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO10 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO11 */ + DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO12 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN1 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN2 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN3 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN4 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN5 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN6 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN7 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN8 */ + DRXJ_16TO8(0x4040), /* FIRTRAINGAIN9 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN10 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN11 */ + DRXJ_16TO8(0x2020), /* FIRTRAINGAIN12 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN1 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN2 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN3 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN4 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN5 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN6 */ + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN7 */ + DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */ + }; + + static const u8 vsb_ffe_leak_gain_ram1[] = { + DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */ + DRXJ_16TO8(0x0808), /* FIRRCA1GAIN12 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN1 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN2 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN3 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN4 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN5 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN6 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN7 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN8 */ + DRXJ_16TO8(0x1010), /* FIRRCA2GAIN9 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN10 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN11 */ + DRXJ_16TO8(0x0808), /* FIRRCA2GAIN12 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN1 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN2 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN3 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN4 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN5 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN6 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN7 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN8 */ + DRXJ_16TO8(0x0606), /* FIRDDM1GAIN9 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN10 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN11 */ + DRXJ_16TO8(0x0303), /* FIRDDM1GAIN12 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN1 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN2 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN3 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN4 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN5 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN6 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN7 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN8 */ + DRXJ_16TO8(0x0505), /* FIRDDM2GAIN9 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN10 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN11 */ + DRXJ_16TO8(0x0303), /* FIRDDM2GAIN12 */ + DRXJ_16TO8(0x001f), /* DFETRAINLKRATIO */ + DRXJ_16TO8(0x01ff), /* DFERCA1TRAINLKRATIO */ + DRXJ_16TO8(0x01ff), /* DFERCA1DATALKRATIO */ + DRXJ_16TO8(0x004f), /* DFERCA2TRAINLKRATIO */ + DRXJ_16TO8(0x004f), /* DFERCA2DATALKRATIO */ + DRXJ_16TO8(0x01ff), /* DFEDDM1TRAINLKRATIO */ + DRXJ_16TO8(0x01ff), /* DFEDDM1DATALKRATIO */ + DRXJ_16TO8(0x0352), /* DFEDDM2TRAINLKRATIO */ + DRXJ_16TO8(0x0352), /* DFEDDM2DATALKRATIO */ + DRXJ_16TO8(0x0000), /* DFETRAINGAIN */ + DRXJ_16TO8(0x2020), /* DFERCA1GAIN */ + DRXJ_16TO8(0x1010), /* DFERCA2GAIN */ + DRXJ_16TO8(0x1818), /* DFEDDM1GAIN */ + DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */ + }; + + dev_addr = demod->my_i2c_dev_addr; + rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn int set_vsb() +* \brief Set 8VSB demod. +* \param demod instance of demodulator. +* \return int. +* +*/ +static int set_vsb(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + int rc; + struct drx_common_attr *common_attr = NULL; + struct drxjscu_cmd cmd_scu; + struct drxj_data *ext_attr = NULL; + u16 cmd_result = 0; + u16 cmd_param = 0; + static const u8 vsb_taps_re[] = { + DRXJ_16TO8(-2), /* re0 */ + DRXJ_16TO8(4), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(-4), /* re3 */ + DRXJ_16TO8(1), /* re4 */ + DRXJ_16TO8(4), /* re5 */ + DRXJ_16TO8(-3), /* re6 */ + DRXJ_16TO8(-3), /* re7 */ + DRXJ_16TO8(6), /* re8 */ + DRXJ_16TO8(1), /* re9 */ + DRXJ_16TO8(-9), /* re10 */ + DRXJ_16TO8(3), /* re11 */ + DRXJ_16TO8(12), /* re12 */ + DRXJ_16TO8(-9), /* re13 */ + DRXJ_16TO8(-15), /* re14 */ + DRXJ_16TO8(17), /* re15 */ + DRXJ_16TO8(19), /* re16 */ + DRXJ_16TO8(-29), /* re17 */ + DRXJ_16TO8(-22), /* re18 */ + DRXJ_16TO8(45), /* re19 */ + DRXJ_16TO8(25), /* re20 */ + DRXJ_16TO8(-70), /* re21 */ + DRXJ_16TO8(-28), /* re22 */ + DRXJ_16TO8(111), /* re23 */ + DRXJ_16TO8(30), /* re24 */ + DRXJ_16TO8(-201), /* re25 */ + DRXJ_16TO8(-31), /* re26 */ + DRXJ_16TO8(629) /* re27 */ + }; + + dev_addr = demod->my_i2c_dev_addr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* stop all comm_exec */ + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* reset demodulator */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; + rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* set higher threshold */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* burst detection on */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* drop thresholds by 1 dB */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* drop thresholds by 2 dB */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* cma on */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* GPIO */ + + /* Initialize the FEC Subsystem */ + rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + u16 fec_oc_snc_mode = 0; + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* output data even when not locked */ + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* set clip */ + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no transparent, no A&C framing; parity is set in mpegoutput */ + { + u16 fec_oc_reg_mode = 0; + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* timeout counter for restarting */ + rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* bypass disabled */ + /* initialize RS packet error measurement parameters */ + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* init measurement period of MER/SER */ + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* B-Input to ADC, PGA+filter in standby */ + if (!ext_attr->has_lna) { + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* turn on IQMAF. It has to be in front of setAgc**() */ + rc = set_iqm_af(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = adc_synchronization(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = init_agc(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead + of only the gain */ + struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 }; + + vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; + rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Mpeg output has to be in front of FEC active */ + rc = set_mpegtei_handling(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = bit_reverse_mpeg_output(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_mpeg_start_width(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + /* TODO: move to set_standard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + struct drx_cfg_mpeg_output cfg_mpeg_output; + + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); + cfg_mpeg_output.enable_mpeg_output = true; + + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* TBD: what parameters should be set */ + cmd_param = 0x00; /* Default mode AGC on, etc */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmd_scu.parameter_len = 1; + cmd_scu.result_len = 1; + cmd_scu.parameter = &cmd_param; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* start demodulator */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs) +* \brief Get the values of packet error in 8VSB mode +* \return Error code +*/ +static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, + u32 *pck_errs, u32 *pck_count) +{ + int rc; + u16 data = 0; + u16 period = 0; + u16 prescale = 0; + u16 packet_errors_mant = 0; + u16 packet_errors_exp = 0; + + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M; + packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M) + >> FEC_RS_NR_FAILURES_EXP__B; + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + /* packet error rate = (error packet number) per second */ + /* 77.3 us is time for per packet */ + if (period * prescale == 0) { + pr_err("error: period and/or prescale is zero!\n"); + return -EIO; + } + *pck_errs = packet_errors_mant * (1 << packet_errors_exp); + *pck_count = period * prescale * 77; + + return 0; +rw_error: + return rc; +} + +/* +* \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr, + u32 *ber, u32 *cnt) +{ + int rc; + u16 data = 0; + u16 period = 0; + u16 prescale = 0; + u16 bit_errors_mant = 0; + u16 bit_errors_exp = 0; + + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + period = FEC_RS_MEASUREMENT_PERIOD; + prescale = FEC_RS_MEASUREMENT_PRESCALE; + + bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M; + bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M) + >> FEC_RS_NR_BIT_ERRORS_EXP__B; + + *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8); + + if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700) + *ber = (*cnt) * 26570; + else { + if (period * prescale == 0) { + pr_err("error: period and/or prescale is zero!\n"); + return -EIO; + } + *ber = bit_errors_mant << ((bit_errors_exp > 2) ? + (bit_errors_exp - 3) : bit_errors_exp); + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber) +* \brief Get the values of ber in VSB mode +* \return Error code +*/ +static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, + u32 *ber, u32 *cnt) +{ + u16 data = 0; + int rc; + + rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + return -EIO; + } + *ber = data; + *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT; + + return 0; +} + +/* +* \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) +* \brief Get the values of MER +* \return Error code +*/ +static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer) +{ + int rc; + u16 data_hi = 0; + + rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + *mer = + (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); + + return 0; +rw_error: + return rc; +} + + +/*============================================================================*/ +/*== END 8VSB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== QAM DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* +* \fn int power_down_qam () +* \brief Powr down QAM related blocks. +* \param demod instance of demodulator. +* \param channel pointer to channel data. +* \return int. +*/ +static int power_down_qam(struct drx_demod_instance *demod, bool primary) +{ + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + int rc; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drx_cfg_mpeg_output cfg_mpeg_output; + struct drx_common_attr *common_attr = demod->my_common_attr; + u16 cmd_result = 0; + + /* + STOP demodulator + resets IQM, QAM and FEC HW blocks + */ + /* stop all comm_exec */ + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (primary) { + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_iqm_af(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); + cfg_mpeg_output.enable_mpeg_output = false; + + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \fn int set_qam_measurement () +* \brief Setup of the QAM Measuremnt intervals for signal quality +* \param demod instance of demod. +* \param constellation current constellation. +* \return int. +* +* NOTE: +* Take into account that for certain settings the errorcounters can overflow. +* The implementation does not check this. +* +* TODO: overriding the ext_attr->fec_bits_desired by constellation dependent +* constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired +* field ? +* +*/ +#ifndef DRXJ_VSB_ONLY +static int +set_qam_measurement(struct drx_demod_instance *demod, + enum drx_modulation constellation, u32 symbol_rate) +{ + struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */ + struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specific data */ + int rc; + u32 fec_bits_desired = 0; /* BER accounting period */ + u16 fec_rs_plen = 0; /* defines RS BER measurement period */ + u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ + u32 fec_rs_period = 0; /* Value for corresponding I2C register */ + u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */ + u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */ + u32 qam_vd_period = 0; /* Value for corresponding I2C register */ + u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */ + u16 fec_vd_plen = 0; /* no of trellis symbols: VD SER measur period */ + u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */ + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + fec_bits_desired = ext_attr->fec_bits_desired; + fec_rs_prescale = ext_attr->fec_rs_prescale; + + switch (constellation) { + case DRX_CONSTELLATION_QAM16: + fec_bits_desired = 4 * symbol_rate; + break; + case DRX_CONSTELLATION_QAM32: + fec_bits_desired = 5 * symbol_rate; + break; + case DRX_CONSTELLATION_QAM64: + fec_bits_desired = 6 * symbol_rate; + break; + case DRX_CONSTELLATION_QAM128: + fec_bits_desired = 7 * symbol_rate; + break; + case DRX_CONSTELLATION_QAM256: + fec_bits_desired = 8 * symbol_rate; + break; + default: + return -EINVAL; + } + + /* Parameters for Reed-Solomon Decoder */ + /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */ + /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */ + switch (ext_attr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + fec_rs_plen = 204 * 8; + break; + case DRX_STANDARD_ITU_B: + fec_rs_plen = 128 * 7; + break; + default: + return -EINVAL; + } + + ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ + fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */ + if (fec_rs_bit_cnt == 0) { + pr_err("error: fec_rs_bit_cnt is zero!\n"); + return -EIO; + } + fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */ + if (ext_attr->standard != DRX_STANDARD_ITU_B) + fec_oc_snc_fail_period = fec_rs_period; + + /* limit to max 16 bit value (I2C register width) if needed */ + if (fec_rs_period > 0xFFFF) + fec_rs_period = 0xFFFF; + + /* write corresponding registers */ + switch (ext_attr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_C: + break; + case DRX_STANDARD_ITU_B: + switch (constellation) { + case DRX_CONSTELLATION_QAM64: + fec_rs_period = 31581; + fec_oc_snc_fail_period = 17932; + break; + case DRX_CONSTELLATION_QAM256: + fec_rs_period = 45446; + fec_oc_snc_fail_period = 25805; + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->fec_rs_period = (u16) fec_rs_period; + ext_attr->fec_rs_prescale = fec_rs_prescale; + rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + /* Parameters for Viterbi Decoder */ + /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */ + /* (qamvd_prescale*plen*(qam_constellation+1))) */ + /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */ + /* result is within 32 bit arithmetic -> */ + /* no need for mult or frac functions */ + + /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */ + fec_vd_plen = ext_attr->fec_vd_plen; + qam_vd_prescale = ext_attr->qam_vd_prescale; + qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */ + + switch (constellation) { + case DRX_CONSTELLATION_QAM64: + /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */ + qam_vd_period = + qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1) + * (QAM_TOP_CONSTELLATION_QAM64 + 1); + break; + case DRX_CONSTELLATION_QAM256: + /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */ + qam_vd_period = + qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1) + * (QAM_TOP_CONSTELLATION_QAM256 + 1); + break; + default: + return -EINVAL; + } + if (qam_vd_period == 0) { + pr_err("error: qam_vd_period is zero!\n"); + return -EIO; + } + qam_vd_period = fec_bits_desired / qam_vd_period; + /* limit to max 16 bit value (I2C register width) if needed */ + if (qam_vd_period > 0xFFFF) + qam_vd_period = 0xFFFF; + + /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */ + qam_vd_bit_cnt *= qam_vd_period; + + rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->qam_vd_period = (u16) qam_vd_period; + ext_attr->qam_vd_prescale = qam_vd_prescale; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \fn int set_qam16 () +* \brief QAM16 specific setup +* \param demod instance of demod. +* \return int. +*/ +static int set_qam16(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + static const u8 qam_dq_qual_fun[] = { + DRXJ_16TO8(2), /* fun0 */ + DRXJ_16TO8(2), /* fun1 */ + DRXJ_16TO8(2), /* fun2 */ + DRXJ_16TO8(2), /* fun3 */ + DRXJ_16TO8(3), /* fun4 */ + DRXJ_16TO8(3), /* fun5 */ + }; + static const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(13517), /* RAD0 */ + DRXJ_16TO8(13517), /* RAD1 */ + DRXJ_16TO8(13517), /* RAD2 */ + DRXJ_16TO8(13517), /* RAD3 */ + DRXJ_16TO8(13517), /* RAD4 */ + DRXJ_16TO8(13517), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \fn int set_qam32 () +* \brief QAM32 specific setup +* \param demod instance of demod. +* \return int. +*/ +static int set_qam32(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + static const u8 qam_dq_qual_fun[] = { + DRXJ_16TO8(3), /* fun0 */ + DRXJ_16TO8(3), /* fun1 */ + DRXJ_16TO8(3), /* fun2 */ + DRXJ_16TO8(3), /* fun3 */ + DRXJ_16TO8(4), /* fun4 */ + DRXJ_16TO8(4), /* fun5 */ + }; + static const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(6707), /* RAD0 */ + DRXJ_16TO8(6707), /* RAD1 */ + DRXJ_16TO8(6707), /* RAD2 */ + DRXJ_16TO8(6707), /* RAD3 */ + DRXJ_16TO8(6707), /* RAD4 */ + DRXJ_16TO8(6707), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \fn int set_qam64 () +* \brief QAM64 specific setup +* \param demod instance of demod. +* \return int. +*/ +static int set_qam64(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + static const u8 qam_dq_qual_fun[] = { + /* this is hw reset value. no necessary to re-write */ + DRXJ_16TO8(4), /* fun0 */ + DRXJ_16TO8(4), /* fun1 */ + DRXJ_16TO8(4), /* fun2 */ + DRXJ_16TO8(4), /* fun3 */ + DRXJ_16TO8(6), /* fun4 */ + DRXJ_16TO8(6), /* fun5 */ + }; + static const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(13336), /* RAD0 */ + DRXJ_16TO8(12618), /* RAD1 */ + DRXJ_16TO8(11988), /* RAD2 */ + DRXJ_16TO8(13809), /* RAD3 */ + DRXJ_16TO8(13809), /* RAD4 */ + DRXJ_16TO8(15609), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \fn int set_qam128 () +* \brief QAM128 specific setup +* \param demod: instance of demod. +* \return int. +*/ +static int set_qam128(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + static const u8 qam_dq_qual_fun[] = { + DRXJ_16TO8(6), /* fun0 */ + DRXJ_16TO8(6), /* fun1 */ + DRXJ_16TO8(6), /* fun2 */ + DRXJ_16TO8(6), /* fun3 */ + DRXJ_16TO8(9), /* fun4 */ + DRXJ_16TO8(9), /* fun5 */ + }; + static const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(6164), /* RAD0 */ + DRXJ_16TO8(6598), /* RAD1 */ + DRXJ_16TO8(6394), /* RAD2 */ + DRXJ_16TO8(6409), /* RAD3 */ + DRXJ_16TO8(6656), /* RAD4 */ + DRXJ_16TO8(7238), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \fn int set_qam256 () +* \brief QAM256 specific setup +* \param demod: instance of demod. +* \return int. +*/ +static int set_qam256(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + static const u8 qam_dq_qual_fun[] = { + DRXJ_16TO8(8), /* fun0 */ + DRXJ_16TO8(8), /* fun1 */ + DRXJ_16TO8(8), /* fun2 */ + DRXJ_16TO8(8), /* fun3 */ + DRXJ_16TO8(12), /* fun4 */ + DRXJ_16TO8(12), /* fun5 */ + }; + static const u8 qam_eq_cma_rad[] = { + DRXJ_16TO8(12345), /* RAD0 */ + DRXJ_16TO8(12345), /* RAD1 */ + DRXJ_16TO8(13626), /* RAD2 */ + DRXJ_16TO8(12931), /* RAD3 */ + DRXJ_16TO8(14719), /* RAD4 */ + DRXJ_16TO8(15356), /* RAD5 */ + }; + + rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ +#define QAM_SET_OP_ALL 0x1 +#define QAM_SET_OP_CONSTELLATION 0x2 +#define QAM_SET_OP_SPECTRUM 0X4 + +/* +* \fn int set_qam () +* \brief Set QAM demod. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return int. +*/ +static int +set_qam(struct drx_demod_instance *demod, + struct drx_channel *channel, s32 tuner_freq_offset, u32 op) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + struct drx_common_attr *common_attr = NULL; + int rc; + u32 adc_frequency = 0; + u32 iqm_rc_rate = 0; + u16 cmd_result = 0; + u16 lc_symbol_freq = 0; + u16 iqm_rc_stretch = 0; + u16 set_env_parameters = 0; + u16 set_param_parameters[2] = { 0 }; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* parameter */ NULL, + /* result */ NULL + }; + static const u8 qam_a_taps[] = { + DRXJ_16TO8(-1), /* re0 */ + DRXJ_16TO8(1), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(-1), /* re3 */ + DRXJ_16TO8(-1), /* re4 */ + DRXJ_16TO8(2), /* re5 */ + DRXJ_16TO8(1), /* re6 */ + DRXJ_16TO8(-2), /* re7 */ + DRXJ_16TO8(0), /* re8 */ + DRXJ_16TO8(3), /* re9 */ + DRXJ_16TO8(-1), /* re10 */ + DRXJ_16TO8(-3), /* re11 */ + DRXJ_16TO8(4), /* re12 */ + DRXJ_16TO8(1), /* re13 */ + DRXJ_16TO8(-8), /* re14 */ + DRXJ_16TO8(4), /* re15 */ + DRXJ_16TO8(13), /* re16 */ + DRXJ_16TO8(-13), /* re17 */ + DRXJ_16TO8(-19), /* re18 */ + DRXJ_16TO8(28), /* re19 */ + DRXJ_16TO8(25), /* re20 */ + DRXJ_16TO8(-53), /* re21 */ + DRXJ_16TO8(-31), /* re22 */ + DRXJ_16TO8(96), /* re23 */ + DRXJ_16TO8(37), /* re24 */ + DRXJ_16TO8(-190), /* re25 */ + DRXJ_16TO8(-40), /* re26 */ + DRXJ_16TO8(619) /* re27 */ + }; + static const u8 qam_b64_taps[] = { + DRXJ_16TO8(0), /* re0 */ + DRXJ_16TO8(-2), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(2), /* re3 */ + DRXJ_16TO8(-2), /* re4 */ + DRXJ_16TO8(0), /* re5 */ + DRXJ_16TO8(4), /* re6 */ + DRXJ_16TO8(-2), /* re7 */ + DRXJ_16TO8(-4), /* re8 */ + DRXJ_16TO8(4), /* re9 */ + DRXJ_16TO8(3), /* re10 */ + DRXJ_16TO8(-6), /* re11 */ + DRXJ_16TO8(0), /* re12 */ + DRXJ_16TO8(6), /* re13 */ + DRXJ_16TO8(-5), /* re14 */ + DRXJ_16TO8(-3), /* re15 */ + DRXJ_16TO8(11), /* re16 */ + DRXJ_16TO8(-4), /* re17 */ + DRXJ_16TO8(-19), /* re18 */ + DRXJ_16TO8(19), /* re19 */ + DRXJ_16TO8(28), /* re20 */ + DRXJ_16TO8(-45), /* re21 */ + DRXJ_16TO8(-36), /* re22 */ + DRXJ_16TO8(90), /* re23 */ + DRXJ_16TO8(42), /* re24 */ + DRXJ_16TO8(-185), /* re25 */ + DRXJ_16TO8(-46), /* re26 */ + DRXJ_16TO8(614) /* re27 */ + }; + static const u8 qam_b256_taps[] = { + DRXJ_16TO8(-2), /* re0 */ + DRXJ_16TO8(4), /* re1 */ + DRXJ_16TO8(1), /* re2 */ + DRXJ_16TO8(-4), /* re3 */ + DRXJ_16TO8(0), /* re4 */ + DRXJ_16TO8(4), /* re5 */ + DRXJ_16TO8(-2), /* re6 */ + DRXJ_16TO8(-4), /* re7 */ + DRXJ_16TO8(5), /* re8 */ + DRXJ_16TO8(2), /* re9 */ + DRXJ_16TO8(-8), /* re10 */ + DRXJ_16TO8(2), /* re11 */ + DRXJ_16TO8(11), /* re12 */ + DRXJ_16TO8(-8), /* re13 */ + DRXJ_16TO8(-15), /* re14 */ + DRXJ_16TO8(16), /* re15 */ + DRXJ_16TO8(19), /* re16 */ + DRXJ_16TO8(-27), /* re17 */ + DRXJ_16TO8(-22), /* re18 */ + DRXJ_16TO8(44), /* re19 */ + DRXJ_16TO8(26), /* re20 */ + DRXJ_16TO8(-69), /* re21 */ + DRXJ_16TO8(-28), /* re22 */ + DRXJ_16TO8(110), /* re23 */ + DRXJ_16TO8(31), /* re24 */ + DRXJ_16TO8(-201), /* re25 */ + DRXJ_16TO8(-32), /* re26 */ + DRXJ_16TO8(628) /* re27 */ + }; + static const u8 qam_c_taps[] = { + DRXJ_16TO8(-3), /* re0 */ + DRXJ_16TO8(3), /* re1 */ + DRXJ_16TO8(2), /* re2 */ + DRXJ_16TO8(-4), /* re3 */ + DRXJ_16TO8(0), /* re4 */ + DRXJ_16TO8(4), /* re5 */ + DRXJ_16TO8(-1), /* re6 */ + DRXJ_16TO8(-4), /* re7 */ + DRXJ_16TO8(3), /* re8 */ + DRXJ_16TO8(3), /* re9 */ + DRXJ_16TO8(-5), /* re10 */ + DRXJ_16TO8(0), /* re11 */ + DRXJ_16TO8(9), /* re12 */ + DRXJ_16TO8(-4), /* re13 */ + DRXJ_16TO8(-12), /* re14 */ + DRXJ_16TO8(10), /* re15 */ + DRXJ_16TO8(16), /* re16 */ + DRXJ_16TO8(-21), /* re17 */ + DRXJ_16TO8(-20), /* re18 */ + DRXJ_16TO8(37), /* re19 */ + DRXJ_16TO8(25), /* re20 */ + DRXJ_16TO8(-62), /* re21 */ + DRXJ_16TO8(-28), /* re22 */ + DRXJ_16TO8(105), /* re23 */ + DRXJ_16TO8(31), /* re24 */ + DRXJ_16TO8(-197), /* re25 */ + DRXJ_16TO8(-33), /* re26 */ + DRXJ_16TO8(626) /* re27 */ + }; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM256: + iqm_rc_rate = 0x00AE3562; + lc_symbol_freq = + QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256; + channel->symbolrate = 5360537; + iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256; + break; + case DRX_CONSTELLATION_QAM64: + iqm_rc_rate = 0x00C05A0E; + lc_symbol_freq = 409; + channel->symbolrate = 5056941; + iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64; + break; + default: + return -EINVAL; + } + } else { + adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; + if (channel->symbolrate == 0) { + pr_err("error: channel symbolrate is zero!\n"); + return -EIO; + } + iqm_rc_rate = + (adc_frequency / channel->symbolrate) * (1 << 21) + + (frac28 + ((adc_frequency % channel->symbolrate), + channel->symbolrate) >> 7) - (1 << 23); + lc_symbol_freq = + (u16) (frac28 + (channel->symbolrate + + (adc_frequency >> 13), + adc_frequency) >> 16); + if (lc_symbol_freq > 511) + lc_symbol_freq = 511; + + iqm_rc_stretch = 21; + } + + if (ext_attr->standard == DRX_STANDARD_ITU_A) { + set_env_parameters = QAM_TOP_ANNEX_A; /* annex */ + set_param_parameters[0] = channel->constellation; /* constellation */ + set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { + set_env_parameters = QAM_TOP_ANNEX_B; /* annex */ + set_param_parameters[0] = channel->constellation; /* constellation */ + set_param_parameters[1] = channel->interleavemode; /* interleave mode */ + } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { + set_env_parameters = QAM_TOP_ANNEX_C; /* annex */ + set_param_parameters[0] = channel->constellation; /* constellation */ + set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */ + } else { + return -EINVAL; + } + } + + if (op & QAM_SET_OP_ALL) { + /* + STEP 1: reset demodulator + resets IQM, QAM and FEC HW blocks + resets SCU variables + */ + /* stop all comm_exec */ + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_RESET; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + /* + STEP 2: configure demodulator + -set env + -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) + */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + cmd_scu.parameter_len = 1; + cmd_scu.result_len = 1; + cmd_scu.parameter = &set_env_parameters; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM; + cmd_scu.parameter_len = 2; + cmd_scu.result_len = 1; + cmd_scu.parameter = set_param_parameters; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* set symbol rate */ + rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->iqm_rc_rate_ofs = iqm_rc_rate; + rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + /* STEP 3: enable the system in a mode where the ADC provides valid signal + setup constellation independent registers */ + /* from qam_cmd.py script (qam_driver_b) */ + /* TODO: remove re-writes of HW reset values */ + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) { + rc = set_frequency(demod, channel, tuner_freq_offset); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if (op & QAM_SET_OP_ALL) { + if (!ext_attr->has_lna) { + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* scu temporary shut down agc */ + + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + } else { + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + case DRX_CONSTELLATION_QAM64: + case DRX_CONSTELLATION_QAM256: + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + break; + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM128: + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EIO; + } /* switch */ + } + + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /*! reset default val ! */ + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* No more resets of the IQM, current standard correctly set => + now AGCs can be configured. */ + /* turn on IQMAF. It has to be in front of setAgc**() */ + rc = set_iqm_af(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = adc_synchronization(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = init_agc(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead + of only the gain */ + struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 }; + + qam_pga_cfg.gain = ext_attr->qam_pga_cfg; + rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + if (ext_attr->standard == DRX_STANDARD_ITU_A) { + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM64: + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM256: + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EIO; + } + } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* SETP 4: constellation specific setup */ + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + rc = set_qam16(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM32: + rc = set_qam32(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM64: + rc = set_qam64(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM128: + rc = set_qam128(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_QAM256: + rc = set_qam256(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + return -EIO; + } /* switch */ + } + + if ((op & QAM_SET_OP_ALL)) { + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Mpeg output has to be in front of FEC active */ + rc = set_mpegtei_handling(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = bit_reverse_mpeg_output(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_mpeg_start_width(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + { + /* TODO: move to set_standard after hardware reset value problem is solved */ + /* Configure initial MPEG output */ + struct drx_cfg_mpeg_output cfg_mpeg_output; + + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); + cfg_mpeg_output.enable_mpeg_output = true; + + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + } + + if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) { + + /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_START; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ +static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod); + +static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + int rc; + u32 iqm_fs_rate_ofs = 0; + u32 iqm_fs_rate_lo = 0; + u16 qam_ctl_ena = 0; + u16 data = 0; + u16 equ_mode = 0; + u16 fsm_state = 0; + int i = 0; + int ofsofs = 0; + + /* Silence the controlling of lc, equ, and the acquisition state machine */ + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* freeze the frequency control loop */ + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs; + iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1; + iqm_fs_rate_ofs -= 2 * ofsofs; + + /* freeze dq/fq updating */ + rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + data = (data & 0xfff9); + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* lc_cp / _ci / _ca */ + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* flip the spec */ + rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; + ext_attr->pos_image = (ext_attr->pos_image) ? false : true; + + /* freeze dq/fq updating */ + rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + equ_mode = data; + data = (data & 0xfff9); + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + for (i = 0; i < 28; i++) { + rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + for (i = 0; i < 24; i++) { + rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + data = equ_mode; + rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + i = 0; + while ((fsm_state != 4) && (i++ < 100)) { + rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; + +} + +#define NO_LOCK 0x0 +#define DEMOD_LOCKED 0x1 +#define SYNC_FLIPPED 0x2 +#define SPEC_MIRRORED 0x4 +/* +* \fn int qam64auto () +* \brief auto do sync pattern switching and mirroring. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param tuner_freq_offset: tuner frequency offset. +* \param lock_status: pointer to lock status. +* \return int. +*/ +static int +qam64auto(struct drx_demod_instance *demod, + struct drx_channel *channel, + s32 tuner_freq_offset, enum drx_lock_status *lock_status) +{ + struct drxj_data *ext_attr = demod->my_ext_attr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; + int rc; + u32 lck_state = NO_LOCK; + u32 start_time = 0; + u32 d_locked_time = 0; + u32 timeout_ofs = 0; + u16 data = 0; + + /* external attributes for storing acquired channel constellation */ + *lock_status = DRX_NOT_LOCKED; + start_time = jiffies_to_msecs(jiffies); + lck_state = NO_LOCK; + do { + rc = ctrl_lock_status(demod, lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + switch (lck_state) { + case NO_LOCK: + if (*lock_status == DRXJ_DEMOD_LOCK) { + rc = ctrl_get_qam_sig_quality(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (p->cnr.stat[0].svalue > 20800) { + lck_state = DEMOD_LOCKED; + /* some delay to see if fec_lock possible TODO find the right value */ + timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */ + d_locked_time = jiffies_to_msecs(jiffies); + } + } + break; + case DEMOD_LOCKED: + if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ + ((jiffies_to_msecs(jiffies) - d_locked_time) > + DRXJ_QAM_FEC_LOCK_WAITTIME)) { + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + lck_state = SYNC_FLIPPED; + msleep(10); + } + break; + case SYNC_FLIPPED: + if (*lock_status == DRXJ_DEMOD_LOCK) { + if (channel->mirror == DRX_MIRROR_AUTO) { + /* flip sync pattern back */ + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* flip spectrum */ + ext_attr->mirror = DRX_MIRROR_YES; + rc = qam_flip_spec(demod, channel); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + lck_state = SPEC_MIRRORED; + /* reset timer TODO: still need 500ms? */ + start_time = d_locked_time = + jiffies_to_msecs(jiffies); + timeout_ofs = 0; + } else { /* no need to wait lock */ + + start_time = + jiffies_to_msecs(jiffies) - + DRXJ_QAM_MAX_WAITTIME - timeout_ofs; + } + } + break; + case SPEC_MIRRORED: + if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */ + ((jiffies_to_msecs(jiffies) - d_locked_time) > + DRXJ_QAM_FEC_LOCK_WAITTIME)) { + rc = ctrl_get_qam_sig_quality(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (p->cnr.stat[0].svalue > 20800) { + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no need to wait lock */ + start_time = + jiffies_to_msecs(jiffies) - + DRXJ_QAM_MAX_WAITTIME - timeout_ofs; + } + } + break; + default: + break; + } + msleep(10); + } while + ((*lock_status != DRX_LOCKED) && + (*lock_status != DRX_NEVER_LOCK) && + ((jiffies_to_msecs(jiffies) - start_time) < + (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)) + ); + /* Returning control to application ... */ + + return 0; +rw_error: + return rc; +} + +/* +* \fn int qam256auto () +* \brief auto do sync pattern switching and mirroring. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \param tuner_freq_offset: tuner frequency offset. +* \param lock_status: pointer to lock status. +* \return int. +*/ +static int +qam256auto(struct drx_demod_instance *demod, + struct drx_channel *channel, + s32 tuner_freq_offset, enum drx_lock_status *lock_status) +{ + struct drxj_data *ext_attr = demod->my_ext_attr; + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; + int rc; + u32 lck_state = NO_LOCK; + u32 start_time = 0; + u32 d_locked_time = 0; + u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; + + /* external attributes for storing acquired channel constellation */ + *lock_status = DRX_NOT_LOCKED; + start_time = jiffies_to_msecs(jiffies); + lck_state = NO_LOCK; + do { + rc = ctrl_lock_status(demod, lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + switch (lck_state) { + case NO_LOCK: + if (*lock_status == DRXJ_DEMOD_LOCK) { + rc = ctrl_get_qam_sig_quality(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (p->cnr.stat[0].svalue > 26800) { + lck_state = DEMOD_LOCKED; + timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */ + d_locked_time = jiffies_to_msecs(jiffies); + } + } + break; + case DEMOD_LOCKED: + if (*lock_status == DRXJ_DEMOD_LOCK) { + if ((channel->mirror == DRX_MIRROR_AUTO) && + ((jiffies_to_msecs(jiffies) - d_locked_time) > + DRXJ_QAM_FEC_LOCK_WAITTIME)) { + ext_attr->mirror = DRX_MIRROR_YES; + rc = qam_flip_spec(demod, channel); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + lck_state = SPEC_MIRRORED; + /* reset timer TODO: still need 300ms? */ + start_time = jiffies_to_msecs(jiffies); + timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2; + } + } + break; + case SPEC_MIRRORED: + break; + default: + break; + } + msleep(10); + } while + ((*lock_status < DRX_LOCKED) && + (*lock_status != DRX_NEVER_LOCK) && + ((jiffies_to_msecs(jiffies) - start_time) < + (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))); + + return 0; +rw_error: + return rc; +} + +/* +* \fn int set_qam_channel () +* \brief Set QAM channel according to the requested constellation. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return int. +*/ +static int +set_qam_channel(struct drx_demod_instance *demod, + struct drx_channel *channel, s32 tuner_freq_offset) +{ + struct drxj_data *ext_attr = NULL; + int rc; + enum drx_lock_status lock_status = DRX_NOT_LOCKED; + bool auto_flag = false; + + /* external attributes for storing acquired channel constellation */ + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* set QAM channel constellation */ + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM128: + return -EINVAL; + case DRX_CONSTELLATION_QAM64: + case DRX_CONSTELLATION_QAM256: + if (ext_attr->standard != DRX_STANDARD_ITU_B) + return -EINVAL; + + ext_attr->constellation = channel->constellation; + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + + rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (channel->constellation == DRX_CONSTELLATION_QAM64) + rc = qam64auto(demod, channel, tuner_freq_offset, + &lock_status); + else + rc = qam256auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_CONSTELLATION_AUTO: /* for channel scan */ + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + u16 qam_ctl_ena = 0; + + auto_flag = true; + + /* try to lock default QAM constellation: QAM256 */ + channel->constellation = DRX_CONSTELLATION_QAM256; + ext_attr->constellation = DRX_CONSTELLATION_QAM256; + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + rc = set_qam(demod, channel, tuner_freq_offset, + QAM_SET_OP_ALL); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = qam256auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (lock_status >= DRX_LOCKED) { + channel->constellation = DRX_CONSTELLATION_AUTO; + break; + } + + /* QAM254 not locked. Try QAM64 constellation */ + channel->constellation = DRX_CONSTELLATION_QAM64; + ext_attr->constellation = DRX_CONSTELLATION_QAM64; + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + &qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_FSM_STATE_TGT__A, + 0x2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* force to rate hunting */ + + rc = set_qam(demod, channel, tuner_freq_offset, + QAM_SET_OP_CONSTELLATION); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = qam64auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + channel->constellation = DRX_CONSTELLATION_AUTO; + } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { + u16 qam_ctl_ena = 0; + + channel->constellation = DRX_CONSTELLATION_QAM64; + ext_attr->constellation = DRX_CONSTELLATION_QAM64; + auto_flag = true; + + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + &qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_FSM_STATE_TGT__A, + 0x2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* force to rate hunting */ + + rc = set_qam(demod, channel, tuner_freq_offset, + QAM_SET_OP_CONSTELLATION); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, + SCU_RAM_QAM_CTL_ENA__A, + qam_ctl_ena, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = qam64auto(demod, channel, tuner_freq_offset, + &lock_status); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + channel->constellation = DRX_CONSTELLATION_AUTO; + } else { + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + return 0; +rw_error: + /* restore starting value */ + if (auto_flag) + channel->constellation = DRX_CONSTELLATION_AUTO; + return rc; +} + +/*============================================================================*/ + +/* +* \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr) +* \brief Get RS error count in QAM mode (used for post RS BER calculation) +* \return Error code +* +* precondition: measurement period & measurement prescale must be set +* +*/ +static int +get_qamrs_err_count(struct i2c_device_addr *dev_addr, + struct drxjrs_errors *rs_errors) +{ + int rc; + u16 nr_bit_errors = 0, + nr_symbol_errors = 0, + nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0; + + /* check arguments */ + if (dev_addr == NULL) + return -EINVAL; + + /* all reported errors are received in the */ + /* most recently finished measurement period */ + /* no of pre RS bit errors */ + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no of symbol errors */ + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no of packet errors */ + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no of failures to decode */ + rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* no of post RS bit erros */ + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* TODO: NOTE */ + /* These register values are fetched in non-atomic fashion */ + /* It is possible that the read values contain unrelated information */ + + rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M; + rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M; + rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M; + rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M; + rs_errors->nr_snc_par_fail_count = + nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M; + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* + * \fn int get_sig_strength() + * \brief Retrieve signal strength for VSB and QAM. + * \param demod Pointer to demod instance + * \param u16-t Pointer to signal strength data; range 0, .. , 100. + * \return int. + * \retval 0 sig_strength contains valid data. + * \retval -EINVAL sig_strength is NULL. + * \retval -EIO Erroneous data, sig_strength contains invalid data. + */ +#define DRXJ_AGC_TOP 0x2800 +#define DRXJ_AGC_SNS 0x1600 +#define DRXJ_RFAGC_MAX 0x3fff +#define DRXJ_RFAGC_MIN 0x800 + +static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 rf_gain = 0; + u16 if_gain = 0; + u16 if_agc_sns = 0; + u16 if_agc_top = 0; + u16 rf_agc_max = 0; + u16 rf_agc_min = 0; + + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if_gain &= IQM_AF_AGC_IF__M; + rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rf_gain &= IQM_AF_AGC_RF__M; + + if_agc_sns = DRXJ_AGC_SNS; + if_agc_top = DRXJ_AGC_TOP; + rf_agc_max = DRXJ_RFAGC_MAX; + rf_agc_min = DRXJ_RFAGC_MIN; + + if (if_gain > if_agc_top) { + if (rf_gain > rf_agc_max) + *sig_strength = 100; + else if (rf_gain > rf_agc_min) { + if (rf_agc_max == rf_agc_min) { + pr_err("error: rf_agc_max == rf_agc_min\n"); + return -EIO; + } + *sig_strength = + 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - + rf_agc_min); + } else + *sig_strength = 75; + } else if (if_gain > if_agc_sns) { + if (if_agc_top == if_agc_sns) { + pr_err("error: if_agc_top == if_agc_sns\n"); + return -EIO; + } + *sig_strength = + 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); + } else { + if (!if_agc_sns) { + pr_err("error: if_agc_sns is zero!\n"); + return -EIO; + } + *sig_strength = (20 * if_gain / if_agc_sns); + } + + if (*sig_strength <= 7) + *sig_strength = 0; + + return 0; +rw_error: + return rc; +} + +/* +* \fn int ctrl_get_qam_sig_quality() +* \brief Retrieve QAM signal quality from device. +* \param devmod Pointer to demodulator instance. +* \param sig_quality Pointer to signal quality data. +* \return int. +* \retval 0 sig_quality contains valid data. +* \retval -EINVAL sig_quality is NULL. +* \retval -EIO Erroneous data, sig_quality contains invalid data. + +* Pre-condition: Device must be started and in lock. +*/ +static int +ctrl_get_qam_sig_quality(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; + struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 }; + enum drx_modulation constellation = ext_attr->constellation; + int rc; + + u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */ + u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */ + u32 pkt_errs = 0; /* no of packet errors in RS */ + u16 qam_sl_err_power = 0; /* accumulated error between raw and sliced symbols */ + u16 qsym_err_vd = 0; /* quadrature symbol errors in QAM_VD */ + u16 fec_oc_period = 0; /* SNC sync failure measurement period */ + u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ + u16 fec_rs_period = 0; /* Value for corresponding I2C register */ + /* calculation constants */ + u32 rs_bit_cnt = 0; /* RedSolomon Bit Count */ + u32 qam_sl_sig_power = 0; /* used for MER, depends of QAM constellation */ + /* intermediate results */ + u32 e = 0; /* exponent value used for QAM BER/SER */ + u32 m = 0; /* mantisa value used for QAM BER/SER */ + u32 ber_cnt = 0; /* BER count */ + /* signal quality info */ + u32 qam_sl_mer = 0; /* QAM MER */ + u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */ + u32 qam_post_rs_ber = 0; /* Post RedSolomon BER */ + u32 qam_vd_ser = 0; /* ViterbiDecoder SER */ + u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */ + u16 qam_vd_period = 0; /* Viterbi Measurement period */ + u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */ + + p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + + /* read the physical registers */ + /* Get the RS error data */ + rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* get the register value needed for MER */ + rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* get the register value needed for post RS BER */ + rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* get constants needed for signal quality calculation */ + fec_rs_period = ext_attr->fec_rs_period; + fec_rs_prescale = ext_attr->fec_rs_prescale; + rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen; + qam_vd_period = ext_attr->qam_vd_period; + qam_vd_prescale = ext_attr->qam_vd_prescale; + vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen; + + /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */ + switch (constellation) { + case DRX_CONSTELLATION_QAM16: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2; + break; + case DRX_CONSTELLATION_QAM32: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2; + break; + case DRX_CONSTELLATION_QAM64: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2; + break; + case DRX_CONSTELLATION_QAM128: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2; + break; + case DRX_CONSTELLATION_QAM256: + qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2; + break; + default: + return -EIO; + } + + /* ------------------------------ */ + /* MER Calculation */ + /* ------------------------------ */ + /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */ + + /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */ + if (qam_sl_err_power == 0) + qam_sl_mer = 0; + else + qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power); + + /* ----------------------------------------- */ + /* Pre Viterbi Symbol Error Rate Calculation */ + /* ----------------------------------------- */ + /* pre viterbi SER is good if it is below 0.025 */ + + /* get the register value */ + /* no of quadrature symbol errors */ + rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Extract the Exponent and the Mantisa */ + /* of number of quadrature symbol errors */ + e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >> + QAM_VD_NR_QSYM_ERRORS_EXP__B; + m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >> + QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B; + + if ((m << e) >> 3 > 549752) + qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; + else + qam_vd_ser = m << ((e > 2) ? (e - 3) : e); + + /* --------------------------------------- */ + /* pre and post RedSolomon BER Calculation */ + /* --------------------------------------- */ + /* pre RS BER is good if it is below 3.5e-4 */ + + /* get the register values */ + pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors; + pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count; + + /* Extract the Exponent and the Mantisa of the */ + /* pre Reed-Solomon bit error count */ + e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >> + FEC_RS_NR_BIT_ERRORS_EXP__B; + m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >> + FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B; + + ber_cnt = m << e; + + /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */ + if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0) + qam_pre_rs_ber = 500000 * rs_bit_cnt >> e; + else + qam_pre_rs_ber = ber_cnt; + + /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */ + /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */ + /* + => c = (1000000*100*11.17)/1504 = + post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) / + (100 * FEC_OC_SNC_FAIL_PERIOD__A) + *100 and /100 is for more precision. + => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation + + Precision errors still possible. + */ + if (!fec_oc_period) { + qam_post_rs_ber = 0xFFFFFFFF; + } else { + e = post_bit_err_rs * 742686; + m = fec_oc_period * 100; + qam_post_rs_ber = e / m; + } + + /* fill signal quality data structure */ + p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->block_error.stat[0].scale = FE_SCALE_COUNTER; + p->cnr.stat[0].scale = FE_SCALE_DECIBEL; + + p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100; + if (ext_attr->standard == DRX_STANDARD_ITU_B) { + p->pre_bit_error.stat[0].uvalue += qam_vd_ser; + p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; + } else { + p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber; + p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e; + } + + p->post_bit_error.stat[0].uvalue += qam_post_rs_ber; + p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e; + + p->block_error.stat[0].uvalue += pkt_errs; + +#ifdef DRXJ_SIGNAL_ACCUM_ERR + rc = get_acc_pkt_err(demod, &sig_quality->packet_error); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } +#endif + + return 0; +rw_error: + p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + + return rc; +} + +#endif /* #ifndef DRXJ_VSB_ONLY */ + +/*============================================================================*/ +/*== END QAM DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== ATV DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ +/*============================================================================*/ + +/* + Implementation notes. + + NTSC/FM AGCs + + Four AGCs are used for NTSC: + (1) RF (used to attenuate the input signal in case of to much power) + (2) IF (used to attenuate the input signal in case of to much power) + (3) Video AGC (used to amplify the output signal in case input to low) + (4) SIF AGC (used to amplify the output signal in case input to low) + + Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed + that the coupling between Video AGC and the RF and IF AGCs also works in + favor of the SIF AGC. + + Three AGCs are used for FM: + (1) RF (used to attenuate the input signal in case of to much power) + (2) IF (used to attenuate the input signal in case of to much power) + (3) SIF AGC (used to amplify the output signal in case input to low) + + The SIF AGC is now coupled to the RF/IF AGCs. + The SIF AGC is needed for both SIF output and the internal SIF signal to + the AUD block. + + RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of + the ATV block. The AGC control algorithms are all implemented in + microcode. + + ATV SETTINGS + + (Shadow settings will not be used for now, they will be implemented + later on because of the schedule) + + Several HW/SCU "settings" can be used for ATV. The standard selection + will reset most of these settings. To avoid that the end user application + has to perform these settings each time the ATV or FM standards is + selected the driver will shadow these settings. This enables the end user + to perform the settings only once after a drx_open(). The driver must + write the shadow settings to HW/SCU in case: + ( setstandard FM/ATV) || + ( settings have changed && FM/ATV standard is active) + The shadow settings will be stored in the device specific data container. + A set of flags will be defined to flag changes in shadow settings. + A routine will be implemented to write all changed shadow settings to + HW/SCU. + + The "settings" will consist of: AGC settings, filter settings etc. + + Disadvantage of use of shadow settings: + Direct changes in HW/SCU registers will not be reflected in the + shadow settings and these changes will be overwritten during a next + update. This can happen during evaluation. This will not be a problem + for normal customer usage. +*/ +/* -------------------------------------------------------------------------- */ + +/* +* \fn int power_down_atv () +* \brief Power down ATV. +* \param demod instance of demodulator +* \param standard either NTSC or FM (sub strandard for ATV ) +* \return int. +* +* Stops and thus resets ATV and IQM block +* SIF and CVBS ADC are powered down +* Calls audio power down +*/ +static int +power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + int rc; + u16 cmd_result = 0; + + /* ATV NTSC */ + + /* Stop ATV SCU (will reset ATV and IQM hardware */ + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV | + SCU_RAM_COMMAND_CMD_DEMOD_STOP; + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 1; + cmd_scu.parameter = NULL; + cmd_scu.result = &cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Disable ATV outputs (ATV reset enables CVBS, undo this) */ + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (primary) { + rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_iqm_af(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } else { + rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = power_down_aud(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \brief Power up AUD. +* \param demod instance of demodulator +* \return int. +* +*/ +static int power_down_aud(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + int rc; + + dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->aud_data.audio_is_active = false; + + return 0; +rw_error: + return rc; +} + +/* +* \fn int set_orx_nsu_aox() +* \brief Configure OrxNsuAox for OOB +* \param demod instance of demodulator. +* \param active +* \return int. +*/ +static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 data = 0; + + /* Configure NSU_AOX */ + rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (!active) + data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON)); + else + data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON); + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + return 0; +rw_error: + return rc; +} + +/* +* \fn int ctrl_set_oob() +* \brief Set OOB channel to be used. +* \param demod instance of demodulator +* \param oob_param OOB parameters for channel setting. +* \frequency should be in KHz +* \return int. +* +* Accepts only. Returns error otherwise. +* Demapper value is written after scu_command START +* because START command causes COMM_EXEC transition +* from 0 to 1 which causes all registers to be +* overwritten with initial value +* +*/ + +/* Nyquist filter impulse response */ +#define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */ +#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */ +#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */ + +/* Coefficients for the nyquist filter (total: 27 taps) */ +#define NYQFILTERLEN 27 + +static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param) +{ + int rc; + s32 freq = 0; /* KHz */ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + u16 i = 0; + bool mirror_freq_spect_oob = false; + u16 trk_filter_value = 0; + struct drxjscu_cmd scu_cmd; + u16 set_param_parameters[3]; + u16 cmd_result[2] = { 0, 0 }; + s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = { + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */ + IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */ + IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */ + IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */ + }; + u8 mode_val[4] = { 2, 2, 0, 1 }; + u8 pfi_coeffs[4][6] = { + {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */ + {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */ + }; + u16 mode_index; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob; + + /* Check parameters */ + if (oob_param == NULL) { + /* power off oob module */ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_orx_nsu_aox(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->oob_power_on = false; + return 0; + } + + freq = oob_param->frequency; + if ((freq < 70000) || (freq > 130000)) + return -EIO; + freq = (freq - 50000) / 50; + + { + u16 index = 0; + u16 remainder = 0; + u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg; + + index = (u16) ((freq - 400) / 200); + remainder = (u16) ((freq - 400) % 200); + trk_filter_value = + trk_filtercfg[index] - (trk_filtercfg[index] - + trk_filtercfg[index + + 1]) / 10 * remainder / + 20; + } + + /********/ + /* Stop */ + /********/ + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_STOP; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /********/ + /* Reset */ + /********/ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_RESET; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /**********/ + /* SET_ENV */ + /**********/ + /* set frequency, spectrum inversion and data rate */ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV; + scu_cmd.parameter_len = 3; + /* 1-data rate;2-frequency */ + switch (oob_param->standard) { + case DRX_OOB_MODE_A: + if ( + /* signal is transmitted inverted */ + ((oob_param->spectrum_inverted == true) && + /* and tuner is not mirroring the signal */ + (!mirror_freq_spect_oob)) | + /* or */ + /* signal is transmitted noninverted */ + ((oob_param->spectrum_inverted == false) && + /* and tuner is mirroring the signal */ + (mirror_freq_spect_oob)) + ) + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC; + else + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_A: + if ( + /* signal is transmitted inverted */ + ((oob_param->spectrum_inverted == true) && + /* and tuner is not mirroring the signal */ + (!mirror_freq_spect_oob)) | + /* or */ + /* signal is transmitted noninverted */ + ((oob_param->spectrum_inverted == false) && + /* and tuner is mirroring the signal */ + (mirror_freq_spect_oob)) + ) + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC; + else + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC; + break; + case DRX_OOB_MODE_B_GRADE_B: + default: + if ( + /* signal is transmitted inverted */ + ((oob_param->spectrum_inverted == true) && + /* and tuner is not mirroring the signal */ + (!mirror_freq_spect_oob)) | + /* or */ + /* signal is transmitted noninverted */ + ((oob_param->spectrum_inverted == false) && + /* and tuner is mirroring the signal */ + (mirror_freq_spect_oob)) + ) + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC; + else + set_param_parameters[0] = + SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC; + break; + } + set_param_parameters[1] = (u16) (freq & 0xFFFF); + set_param_parameters[2] = trk_filter_value; + scu_cmd.parameter = set_param_parameters; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6]; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write magic word to enable pdr reg write */ + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } /* Write magic word to disable pdr reg write */ + + rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* ddc */ + rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* nsu */ + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* initialization for target mode */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Reset bits for timing and freq. recovery */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* PRE-Filter coefficients (PFI) */ + rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* NYQUIST-Filter coefficients (NYQ) */ + for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) { + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /********/ + /* Start */ + /********/ + scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB + | SCU_RAM_COMMAND_CMD_DEMOD_START; + scu_cmd.parameter_len = 0; + scu_cmd.result_len = 1; + scu_cmd.result = cmd_result; + rc = scu_command(dev_addr, &scu_cmd); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = set_orx_nsu_aox(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->oob_power_on = true; + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ +/*== END OOB DATAPATH FUNCTIONS ==*/ +/*============================================================================*/ + +/*============================================================================= + ===== MC command related functions ========================================== + ===========================================================================*/ + +/*============================================================================= + ===== ctrl_set_channel() ========================================================== + ===========================================================================*/ +/* +* \fn int ctrl_set_channel() +* \brief Select a new transmission channel. +* \param demod instance of demod. +* \param channel Pointer to channel data. +* \return int. +* +* In case the tuner module is not used and in case of NTSC/FM the pogrammer +* must tune the tuner to the centre frequency of the NTSC/FM channel. +* +*/ +static int +ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) +{ + int rc; + s32 tuner_freq_offset = 0; + struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + enum drx_standard standard = DRX_STANDARD_UNKNOWN; +#ifndef DRXJ_VSB_ONLY + u32 min_symbol_rate = 0; + u32 max_symbol_rate = 0; + int bandwidth_temp = 0; + int bandwidth = 0; +#endif + /*== check arguments ======================================================*/ + if ((demod == NULL) || (channel == NULL)) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + standard = ext_attr->standard; + + /* check valid standards */ + switch (standard) { + case DRX_STANDARD_8VSB: +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: +#endif /* DRXJ_VSB_ONLY */ + break; + case DRX_STANDARD_UNKNOWN: + default: + return -EINVAL; + } + + /* check bandwidth QAM annex B, NTSC and 8VSB */ + if ((standard == DRX_STANDARD_ITU_B) || + (standard == DRX_STANDARD_8VSB) || + (standard == DRX_STANDARD_NTSC)) { + switch (channel->bandwidth) { + case DRX_BANDWIDTH_6MHZ: + case DRX_BANDWIDTH_UNKNOWN: + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + break; + case DRX_BANDWIDTH_8MHZ: + case DRX_BANDWIDTH_7MHZ: + default: + return -EINVAL; + } + } + + /* For QAM annex A and annex C: + -check symbolrate and constellation + -derive bandwidth from symbolrate (input bandwidth is ignored) + */ +#ifndef DRXJ_VSB_ONLY + if ((standard == DRX_STANDARD_ITU_A) || + (standard == DRX_STANDARD_ITU_C)) { + struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW }; + int bw_rolloff_factor = 0; + + bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113; + min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN; + max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX; + /* config SMA_TX pin to SAW switch mode */ + rc = ctrl_set_uio_cfg(demod, &uio_cfg); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if (channel->symbolrate < min_symbol_rate || + channel->symbolrate > max_symbol_rate) { + return -EINVAL; + } + + switch (channel->constellation) { + case DRX_CONSTELLATION_QAM16: + case DRX_CONSTELLATION_QAM32: + case DRX_CONSTELLATION_QAM64: + case DRX_CONSTELLATION_QAM128: + case DRX_CONSTELLATION_QAM256: + bandwidth_temp = channel->symbolrate * bw_rolloff_factor; + bandwidth = bandwidth_temp / 100; + + if ((bandwidth_temp % 100) >= 50) + bandwidth++; + + if (bandwidth <= 6100000) { + channel->bandwidth = DRX_BANDWIDTH_6MHZ; + } else if ((bandwidth > 6100000) + && (bandwidth <= 7100000)) { + channel->bandwidth = DRX_BANDWIDTH_7MHZ; + } else if (bandwidth > 7100000) { + channel->bandwidth = DRX_BANDWIDTH_8MHZ; + } + break; + default: + return -EINVAL; + } + } + + /* For QAM annex B: + -check constellation + */ + if (standard == DRX_STANDARD_ITU_B) { + switch (channel->constellation) { + case DRX_CONSTELLATION_AUTO: + case DRX_CONSTELLATION_QAM256: + case DRX_CONSTELLATION_QAM64: + break; + default: + return -EINVAL; + } + + switch (channel->interleavemode) { + case DRX_INTERLEAVEMODE_I128_J1: + case DRX_INTERLEAVEMODE_I128_J1_V2: + case DRX_INTERLEAVEMODE_I128_J2: + case DRX_INTERLEAVEMODE_I64_J2: + case DRX_INTERLEAVEMODE_I128_J3: + case DRX_INTERLEAVEMODE_I32_J4: + case DRX_INTERLEAVEMODE_I128_J4: + case DRX_INTERLEAVEMODE_I16_J8: + case DRX_INTERLEAVEMODE_I128_J5: + case DRX_INTERLEAVEMODE_I8_J16: + case DRX_INTERLEAVEMODE_I128_J6: + case DRX_INTERLEAVEMODE_I128_J7: + case DRX_INTERLEAVEMODE_I128_J8: + case DRX_INTERLEAVEMODE_I12_J17: + case DRX_INTERLEAVEMODE_I5_J4: + case DRX_INTERLEAVEMODE_B52_M240: + case DRX_INTERLEAVEMODE_B52_M720: + case DRX_INTERLEAVEMODE_UNKNOWN: + case DRX_INTERLEAVEMODE_AUTO: + break; + default: + return -EINVAL; + } + } + + if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { + /* SAW SW, user UIO is used for switchable SAW */ + struct drxuio_data uio1 = { DRX_UIO1, false }; + + switch (channel->bandwidth) { + case DRX_BANDWIDTH_8MHZ: + uio1.value = true; + break; + case DRX_BANDWIDTH_7MHZ: + uio1.value = false; + break; + case DRX_BANDWIDTH_6MHZ: + uio1.value = false; + break; + case DRX_BANDWIDTH_UNKNOWN: + default: + return -EINVAL; + } + + rc = ctrl_uio_write(demod, &uio1); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } +#endif /* DRXJ_VSB_ONLY */ + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + tuner_freq_offset = 0; + + /*== Setup demod for specific standard ====================================*/ + switch (standard) { + case DRX_STANDARD_8VSB: + if (channel->mirror == DRX_MIRROR_AUTO) + ext_attr->mirror = DRX_MIRROR_NO; + else + ext_attr->mirror = channel->mirror; + rc = set_vsb(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_frequency(demod, channel, tuner_freq_offset); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + rc = set_qam_channel(demod, channel, tuner_freq_offset); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#endif + case DRX_STANDARD_UNKNOWN: + default: + return -EIO; + } + + /* flag the packet error counter reset */ + ext_attr->reset_pkt_err_acc = true; + + return 0; +rw_error: + return rc; +} + +/*============================================================================= + ===== SigQuality() ========================================================== + ===========================================================================*/ + +/* +* \fn int ctrl_sig_quality() +* \brief Retrieve signal quality form device. +* \param devmod Pointer to demodulator instance. +* \param sig_quality Pointer to signal quality data. +* \return int. +* \retval 0 sig_quality contains valid data. +* \retval -EINVAL sig_quality is NULL. +* \retval -EIO Erroneous data, sig_quality contains invalid data. + +*/ +static int +ctrl_sig_quality(struct drx_demod_instance *demod, + enum drx_lock_status lock_status) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + struct drxj_data *ext_attr = demod->my_ext_attr; + struct drx39xxj_state *state = dev_addr->user_data; + struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; + enum drx_standard standard = ext_attr->standard; + int rc; + u32 ber, cnt, err, pkt; + u16 mer, strength = 0; + + rc = get_sig_strength(demod, &strength); + if (rc < 0) { + pr_err("error getting signal strength %d\n", rc); + p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->strength.stat[0].scale = FE_SCALE_RELATIVE; + p->strength.stat[0].uvalue = 65535UL * strength/ 100; + } + + switch (standard) { + case DRX_STANDARD_8VSB: +#ifdef DRXJ_SIGNAL_ACCUM_ERR + rc = get_acc_pkt_err(demod, &pkt); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } +#endif + if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) { + p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt); + if (rc != 0) { + pr_err("error %d getting UCB\n", rc); + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->block_error.stat[0].scale = FE_SCALE_COUNTER; + p->block_error.stat[0].uvalue += err; + p->block_count.stat[0].scale = FE_SCALE_COUNTER; + p->block_count.stat[0].uvalue += pkt; + } + + /* PostViterbi is compute in steps of 10^(-6) */ + rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt); + if (rc != 0) { + pr_err("error %d getting pre-ber\n", rc); + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_error.stat[0].uvalue += ber; + p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->pre_bit_count.stat[0].uvalue += cnt; + } + + rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt); + if (rc != 0) { + pr_err("error %d getting post-ber\n", rc); + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_error.stat[0].uvalue += ber; + p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; + p->post_bit_count.stat[0].uvalue += cnt; + } + rc = get_vsbmer(dev_addr, &mer); + if (rc != 0) { + pr_err("error %d getting MER\n", rc); + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } else { + p->cnr.stat[0].svalue = mer * 100; + p->cnr.stat[0].scale = FE_SCALE_DECIBEL; + } + } + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + rc = ctrl_get_qam_sig_quality(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#endif + default: + return -EIO; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \fn int ctrl_lock_status() +* \brief Retrieve lock status . +* \param dev_addr Pointer to demodulator device address. +* \param lock_stat Pointer to lock status structure. +* \return int. +* +*/ +static int +ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat) +{ + enum drx_standard standard = DRX_STANDARD_UNKNOWN; + struct drxj_data *ext_attr = NULL; + struct i2c_device_addr *dev_addr = NULL; + struct drxjscu_cmd cmd_scu = { /* command */ 0, + /* parameter_len */ 0, + /* result_len */ 0, + /* *parameter */ NULL, + /* *result */ NULL + }; + int rc; + u16 cmd_result[2] = { 0, 0 }; + u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED; + + /* check arguments */ + if ((demod == NULL) || (lock_stat == NULL)) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + standard = ext_attr->standard; + + *lock_stat = DRX_NOT_LOCKED; + + /* define the SCU command code */ + switch (standard) { + case DRX_STANDARD_8VSB: + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + demod_lock |= 0x6; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK; + break; +#endif + case DRX_STANDARD_UNKNOWN: + default: + return -EIO; + } + + /* define the SCU command parameters and execute the command */ + cmd_scu.parameter_len = 0; + cmd_scu.result_len = 2; + cmd_scu.parameter = NULL; + cmd_scu.result = cmd_result; + rc = scu_command(dev_addr, &cmd_scu); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* set the lock status */ + if (cmd_scu.result[1] < demod_lock) { + /* 0x0000 NOT LOCKED */ + *lock_stat = DRX_NOT_LOCKED; + } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) { + *lock_stat = DRXJ_DEMOD_LOCK; + } else if (cmd_scu.result[1] < + SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) { + /* 0x8000 DEMOD + FEC LOCKED (system lock) */ + *lock_stat = DRX_LOCKED; + } else { + /* 0xC000 NEVER LOCKED */ + /* (system will never be able to lock to the signal) */ + *lock_stat = DRX_NEVER_LOCK; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \fn int ctrl_set_standard() +* \brief Set modulation standard to be used. +* \param standard Modulation standard. +* \return int. +* +* Setup stuff for the desired demodulation standard. +* Disable and power down the previous selected demodulation standard +* +*/ +static int +ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) +{ + struct drxj_data *ext_attr = NULL; + int rc; + enum drx_standard prev_standard; + + /* check arguments */ + if ((standard == NULL) || (demod == NULL)) + return -EINVAL; + + ext_attr = (struct drxj_data *) demod->my_ext_attr; + prev_standard = ext_attr->standard; + + /* + Stop and power down previous standard + */ + switch (prev_standard) { +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + rc = power_down_qam(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; +#endif + case DRX_STANDARD_8VSB: + rc = power_down_vsb(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: + default: + return -EINVAL; + } + + /* + Initialize channel independent registers + Power up new standard + */ + ext_attr->standard = *standard; + + switch (*standard) { +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + do { + u16 dummy; + rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } while (0); + break; +#endif + case DRX_STANDARD_8VSB: + rc = set_vsb_leak_n_gain(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + default: + ext_attr->standard = DRX_STANDARD_UNKNOWN; + return -EINVAL; + } + + return 0; +rw_error: + /* Don't know what the standard is now ... try again */ + ext_attr->standard = DRX_STANDARD_UNKNOWN; + return rc; +} + +/*============================================================================*/ + +static void drxj_reset_mode(struct drxj_data *ext_attr) +{ + /* Initialize default AFE configuration for QAM */ + if (ext_attr->has_lna) { + /* IF AGC off, PGA active */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->qam_pga_cfg = 140 + (11 * 13); +#endif + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; + ext_attr->vsb_pga_cfg = 140 + (11 * 13); + } else { + /* IF AGC on, PGA not active */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_if_agc_cfg.min_output_level = 0; + ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_if_agc_cfg.speed = 3; + ext_attr->qam_if_agc_cfg.top = 1297; + ext_attr->qam_pga_cfg = 140; +#endif + ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_if_agc_cfg.min_output_level = 0; + ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_if_agc_cfg.speed = 3; + ext_attr->vsb_if_agc_cfg.top = 1024; + ext_attr->vsb_pga_cfg = 140; + } + /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */ + /* mc has not used them */ +#ifndef DRXJ_VSB_ONLY + ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->qam_rf_agc_cfg.min_output_level = 0; + ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->qam_rf_agc_cfg.speed = 3; + ext_attr->qam_rf_agc_cfg.top = 9500; + ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; + ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; + ext_attr->qam_pre_saw_cfg.reference = 0x07; + ext_attr->qam_pre_saw_cfg.use_pre_saw = true; +#endif + /* Initialize default AFE configuration for VSB */ + ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; + ext_attr->vsb_rf_agc_cfg.min_output_level = 0; + ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; + ext_attr->vsb_rf_agc_cfg.speed = 3; + ext_attr->vsb_rf_agc_cfg.top = 9500; + ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; + ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; + ext_attr->vsb_pre_saw_cfg.reference = 0x07; + ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; +} + +/* +* \fn int ctrl_power_mode() +* \brief Set the power mode of the device to the specified power mode +* \param demod Pointer to demodulator instance. +* \param mode Pointer to new power mode. +* \return int. +* \retval 0 Success +* \retval -EIO I2C error or other failure +* \retval -EINVAL Invalid mode argument. +* +* +*/ +static int +ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) +{ + struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL; + struct drxj_data *ext_attr = (struct drxj_data *) NULL; + struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL; + int rc; + u16 sio_cc_pwd_mode = 0; + + common_attr = (struct drx_common_attr *) demod->my_common_attr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + dev_addr = demod->my_i2c_dev_addr; + + /* Check arguments */ + if (mode == NULL) + return -EINVAL; + + /* If already in requested power mode, do nothing */ + if (common_attr->current_power_mode == *mode) + return 0; + + switch (*mode) { + case DRX_POWER_UP: + case DRXJ_POWER_DOWN_MAIN_PATH: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; + break; + case DRXJ_POWER_DOWN_CORE: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + break; + case DRXJ_POWER_DOWN_PLL: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; + break; + case DRX_POWER_DOWN: + sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; + break; + default: + /* Unknow sleep mode */ + return -EINVAL; + } + + /* Check if device needs to be powered up */ + if ((common_attr->current_power_mode != DRX_POWER_UP)) { + rc = power_up_device(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + if (*mode == DRX_POWER_UP) { + /* Restore analog & pin configuration */ + + /* Initialize default AFE configuration for VSB */ + drxj_reset_mode(ext_attr); + } else { + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + /* stop all comm_exec */ + /* + Stop and power down previous standard + */ + + switch (ext_attr->standard) { + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + rc = power_down_qam(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_8VSB: + rc = power_down_vsb(demod, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_PAL_SECAM_BG: + case DRX_STANDARD_PAL_SECAM_DK: + case DRX_STANDARD_PAL_SECAM_I: + case DRX_STANDARD_PAL_SECAM_L: + case DRX_STANDARD_PAL_SECAM_LP: + case DRX_STANDARD_NTSC: + case DRX_STANDARD_FM: + rc = power_down_atv(demod, ext_attr->standard, true); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + break; + case DRX_STANDARD_UNKNOWN: + /* Do nothing */ + break; + case DRX_STANDARD_AUTO: + default: + return -EIO; + } + ext_attr->standard = DRX_STANDARD_UNKNOWN; + } + + if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) { + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + if ((*mode != DRX_POWER_UP)) { + /* Initialize HI, wakeup key especially before put IC to sleep */ + rc = init_hi(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + rc = hi_cfg_command(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + } + + common_attr->current_power_mode = *mode; + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ +/*== CTRL Set/Get Config related functions ===================================*/ +/*============================================================================*/ + +/* +* \fn int ctrl_set_cfg_pre_saw() +* \brief Set Pre-saw reference. +* \param demod demod instance +* \param u16 * +* \return int. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static int +ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + int rc; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + /* check arguments */ + if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) + ) { + return -EINVAL; + } + + /* Only if standard is currently active */ + if ((ext_attr->standard == pre_saw->standard) || + (DRXJ_ISQAMSTD(ext_attr->standard) && + DRXJ_ISQAMSTD(pre_saw->standard)) || + (DRXJ_ISATVSTD(ext_attr->standard) && + DRXJ_ISATVSTD(pre_saw->standard))) { + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* Store pre-saw settings */ + switch (pre_saw->standard) { + case DRX_STANDARD_8VSB: + ext_attr->vsb_pre_saw_cfg = *pre_saw; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + ext_attr->qam_pre_saw_cfg = *pre_saw; + break; +#endif + default: + return -EINVAL; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + +/* +* \fn int ctrl_set_cfg_afe_gain() +* \brief Set AFE Gain. +* \param demod demod instance +* \param u16 * +* \return int. +* +* Check arguments +* Dispatch handling to standard specific function. +* +*/ +static int +ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + int rc; + u8 gain = 0; + + /* check arguments */ + if (afe_gain == NULL) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + + switch (afe_gain->standard) { + case DRX_STANDARD_8VSB: fallthrough; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: +#endif + /* Do nothing */ + break; + default: + return -EINVAL; + } + + /* TODO PGA gain is also written by microcode (at least by QAM and VSB) + So I (PJ) think interface requires choice between auto, user mode */ + + if (afe_gain->gain >= 329) + gain = 15; + else if (afe_gain->gain <= 147) + gain = 0; + else + gain = (afe_gain->gain - 140 + 6) / 13; + + /* Only if standard is currently active */ + if (ext_attr->standard == afe_gain->standard) { + rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + } + + /* Store AFE Gain settings */ + switch (afe_gain->standard) { + case DRX_STANDARD_8VSB: + ext_attr->vsb_pga_cfg = gain * 13 + 140; + break; +#ifndef DRXJ_VSB_ONLY + case DRX_STANDARD_ITU_A: + case DRX_STANDARD_ITU_B: + case DRX_STANDARD_ITU_C: + ext_attr->qam_pga_cfg = gain * 13 + 140; + break; +#endif + default: + return -EIO; + } + + return 0; +rw_error: + return rc; +} + +/*============================================================================*/ + + +/*============================================================================= +===== EXPORTED FUNCTIONS ====================================================*/ + +static int drx_ctrl_u_code(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, + enum drxu_code_action action); +static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state); + +/* +* \fn drxj_open() +* \brief Open the demod instance, configure device, configure drxdriver +* \return Status_t Return status. +* +* drxj_open() can be called with a NULL ucode image => no ucode upload. +* This means that drxj_open() must NOT contain SCU commands or, in general, +* rely on SCU or AUD ucode to be present. +* +*/ + +static int drxj_open(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = NULL; + struct drxj_data *ext_attr = NULL; + struct drx_common_attr *common_attr = NULL; + u32 driver_version = 0; + struct drxu_code_info ucode_info; + struct drx_cfg_mpeg_output cfg_mpeg_output; + int rc; + enum drx_power_mode power_mode = DRX_POWER_UP; + + if ((demod == NULL) || + (demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (demod->my_common_attr->is_opened)) { + return -EINVAL; + } + + /* Check arguments */ + if (demod->my_ext_attr == NULL) + return -EINVAL; + + dev_addr = demod->my_i2c_dev_addr; + ext_attr = (struct drxj_data *) demod->my_ext_attr; + common_attr = (struct drx_common_attr *) demod->my_common_attr; + + rc = ctrl_power_mode(demod, &power_mode); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + if (power_mode != DRX_POWER_UP) { + rc = -EINVAL; + pr_err("failed to powerup device\n"); + goto rw_error; + } + + /* has to be in front of setIqmAf and setOrxNsuAox */ + rc = get_device_capabilities(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* + * Soft reset of sys- and osc-clockdomain + * + * HACK: On windows, it writes a 0x07 here, instead of just 0x03. + * As we didn't load the firmware here yet, we should do the same. + * Btw, this is coherent with DRX-K, where we send reset codes + * for modulation (OFTM, in DRX-k), SYS and OSC clock domains. + */ + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + msleep(1); + + /* TODO first make sure that everything keeps working before enabling this */ + /* PowerDownAnalogBlocks() */ + rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = set_iqm_af(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = set_orx_nsu_aox(demod, false); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = init_hi(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* disable mpegoutput pins */ + memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); + cfg_mpeg_output.enable_mpeg_output = false; + + rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Stop AUD Inform SetAudio it will need to do all setting */ + rc = power_down_aud(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + /* Stop SCU */ + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Upload microcode */ + if (common_attr->microcode_file != NULL) { + /* Dirty trick to use common ucode upload & verify, + pretend device is already open */ + common_attr->is_opened = true; + ucode_info.mc_file = common_attr->microcode_file; + + if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) { + pr_err("Should powerup before loading the firmware."); + return -EINVAL; + } + + rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD); + if (rc != 0) { + pr_err("error %d while uploading the firmware\n", rc); + goto rw_error; + } + if (common_attr->verify_microcode == true) { + rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY); + if (rc != 0) { + pr_err("error %d while verifying the firmware\n", + rc); + goto rw_error; + } + } + common_attr->is_opened = false; + } + + /* Run SCU for a little while to initialize microcode version numbers */ + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Initialize scan timeout */ + common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT; + common_attr->scan_desired_lock = DRX_LOCKED; + + drxj_reset_mode(ext_attr); + ext_attr->standard = DRX_STANDARD_UNKNOWN; + + rc = smart_ant_init(demod); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* Stamp driver version number in SCU data RAM in BCD code + Done to enable field application engineers to retrieve drxdriver version + via I2C from SCU RAM + */ + driver_version = (VERSION_MAJOR / 100) % 10; + driver_version <<= 4; + driver_version += (VERSION_MAJOR / 10) % 10; + driver_version <<= 4; + driver_version += (VERSION_MAJOR % 10); + driver_version <<= 4; + driver_version += (VERSION_MINOR % 10); + driver_version <<= 4; + driver_version += (VERSION_PATCH / 1000) % 10; + driver_version <<= 4; + driver_version += (VERSION_PATCH / 100) % 10; + driver_version <<= 4; + driver_version += (VERSION_PATCH / 10) % 10; + driver_version <<= 4; + driver_version += (VERSION_PATCH % 10); + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = ctrl_set_oob(demod, NULL); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + /* refresh the audio data structure with default */ + ext_attr->aud_data = drxj_default_aud_data_g; + + demod->my_common_attr->is_opened = true; + drxj_set_lna_state(demod, false); + return 0; +rw_error: + common_attr->is_opened = false; + return rc; +} + +/*============================================================================*/ +/* +* \fn drxj_close() +* \brief Close the demod instance, power down the device +* \return Status_t Return status. +* +*/ +static int drxj_close(struct drx_demod_instance *demod) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + enum drx_power_mode power_mode = DRX_POWER_UP; + + if ((demod->my_common_attr == NULL) || + (demod->my_ext_attr == NULL) || + (demod->my_i2c_dev_addr == NULL) || + (!demod->my_common_attr->is_opened)) { + return -EINVAL; + } + + /* power up */ + rc = ctrl_power_mode(demod, &power_mode); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + power_mode = DRX_POWER_DOWN; + rc = ctrl_power_mode(demod, &power_mode); + if (rc != 0) { + pr_err("error %d\n", rc); + goto rw_error; + } + + DRX_ATTR_ISOPENED(demod) = false; + + return 0; +rw_error: + DRX_ATTR_ISOPENED(demod) = false; + + return rc; +} + +/* + * Microcode related functions + */ + +/* + * drx_u_code_compute_crc - Compute CRC of block of microcode data. + * @block_data: Pointer to microcode data. + * @nr_words: Size of microcode block (number of 16 bits words). + * + * returns The computed CRC residue. + */ +static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words) +{ + u16 i = 0; + u16 j = 0; + u32 crc_word = 0; + u32 carry = 0; + + while (i < nr_words) { + crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data)); + for (j = 0; j < 16; j++) { + crc_word <<= 1; + if (carry != 0) + crc_word ^= 0x80050000UL; + carry = crc_word & 0x80000000UL; + } + i++; + block_data += (sizeof(u16)); + } + return (u16)(crc_word >> 16); +} + +/* + * drx_check_firmware - checks if the loaded firmware is valid + * + * @demod: demod structure + * @mc_data: pointer to the start of the firmware + * @size: firmware size + */ +static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data, + unsigned size) +{ + struct drxu_code_block_hdr block_hdr; + int i; + unsigned count = 2 * sizeof(u16); + u32 mc_dev_type, mc_version, mc_base_version; + u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16))); + + /* + * Scan microcode blocks first for version info + * and firmware check + */ + + /* Clear version block */ + DRX_ATTR_MCRECORD(demod).aux_type = 0; + DRX_ATTR_MCRECORD(demod).mc_dev_type = 0; + DRX_ATTR_MCRECORD(demod).mc_version = 0; + DRX_ATTR_MCRECORD(demod).mc_base_version = 0; + + for (i = 0; i < mc_nr_of_blks; i++) { + if (count + 3 * sizeof(u16) + sizeof(u32) > size) + goto eof; + + /* Process block header */ + block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count)); + count += sizeof(u32); + block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count)); + count += sizeof(u16); + block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count)); + count += sizeof(u16); + block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count)); + count += sizeof(u16); + + pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", + count, block_hdr.addr, block_hdr.size, block_hdr.flags, + block_hdr.CRC); + + if (block_hdr.flags & 0x8) { + u8 *auxblk = ((void *)mc_data) + block_hdr.addr; + u16 auxtype; + + if (block_hdr.addr + sizeof(u16) > size) + goto eof; + + auxtype = be16_to_cpu(*(__be16 *)(auxblk)); + + /* Aux block. Check type */ + if (DRX_ISMCVERTYPE(auxtype)) { + if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size) + goto eof; + + auxblk += sizeof(u16); + mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk)); + auxblk += sizeof(u32); + mc_version = be32_to_cpu(*(__be32 *)(auxblk)); + auxblk += sizeof(u32); + mc_base_version = be32_to_cpu(*(__be32 *)(auxblk)); + + DRX_ATTR_MCRECORD(demod).aux_type = auxtype; + DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type; + DRX_ATTR_MCRECORD(demod).mc_version = mc_version; + DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version; + + pr_info("Firmware dev %x, ver %x, base ver %x\n", + mc_dev_type, mc_version, mc_base_version); + + } + } else if (count + block_hdr.size * sizeof(u16) > size) + goto eof; + + count += block_hdr.size * sizeof(u16); + } + return 0; +eof: + pr_err("Firmware is truncated at pos %u/%u\n", count, size); + return -EINVAL; +} + +/* + * drx_ctrl_u_code - Handle microcode upload or verify. + * @dev_addr: Address of device. + * @mc_info: Pointer to information about microcode data. + * @action: Either UCODE_UPLOAD or UCODE_VERIFY + * + * This function returns: + * 0: + * - In case of UCODE_UPLOAD: code is successfully uploaded. + * - In case of UCODE_VERIFY: image on device is equal to + * image provided to this control function. + * -EIO: + * - In case of UCODE_UPLOAD: I2C error. + * - In case of UCODE_VERIFY: I2C error or image on device + * is not equal to image provided to this control function. + * -EINVAL: + * - Invalid arguments. + * - Provided image is corrupt + */ +static int drx_ctrl_u_code(struct drx_demod_instance *demod, + struct drxu_code_info *mc_info, + enum drxu_code_action action) +{ + struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; + int rc; + u16 i = 0; + u16 mc_nr_of_blks = 0; + u16 mc_magic_word = 0; + const u8 *mc_data_init = NULL; + u8 *mc_data = NULL; + unsigned size; + char *mc_file; + + /* Check arguments */ + if (!mc_info || !mc_info->mc_file) + return -EINVAL; + + mc_file = mc_info->mc_file; + + if (!demod->firmware) { + const struct firmware *fw = NULL; + + rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); + if (rc < 0) { + pr_err("Couldn't read firmware %s\n", mc_file); + return rc; + } + demod->firmware = fw; + + if (demod->firmware->size < 2 * sizeof(u16)) { + rc = -EINVAL; + pr_err("Firmware is too short!\n"); + goto release; + } + + pr_info("Firmware %s, size %zu\n", + mc_file, demod->firmware->size); + } + + mc_data_init = demod->firmware->data; + size = demod->firmware->size; + + mc_data = (void *)mc_data_init; + /* Check data */ + mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data)); + mc_data += sizeof(u16); + mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data)); + mc_data += sizeof(u16); + + if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) { + rc = -EINVAL; + pr_err("Firmware magic word doesn't match\n"); + goto release; + } + + if (action == UCODE_UPLOAD) { + rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); + if (rc) + goto release; + pr_info("Uploading firmware %s\n", mc_file); + } else { + pr_info("Verifying if firmware upload was ok.\n"); + } + + /* Process microcode blocks */ + for (i = 0; i < mc_nr_of_blks; i++) { + struct drxu_code_block_hdr block_hdr; + u16 mc_block_nr_bytes = 0; + + /* Process block header */ + block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data)); + mc_data += sizeof(u32); + block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data)); + mc_data += sizeof(u16); + block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data)); + mc_data += sizeof(u16); + block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data)); + mc_data += sizeof(u16); + + pr_debug("%zd: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n", + (mc_data - mc_data_init), block_hdr.addr, + block_hdr.size, block_hdr.flags, block_hdr.CRC); + + /* Check block header on: + - data larger than 64Kb + - if CRC enabled check CRC + */ + if ((block_hdr.size > 0x7FFF) || + (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) && + (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size))) + ) { + /* Wrong data ! */ + rc = -EINVAL; + pr_err("firmware CRC is wrong\n"); + goto release; + } + + if (!block_hdr.size) + continue; + + mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16)); + + /* Perform the desired action */ + switch (action) { + case UCODE_UPLOAD: /* Upload microcode */ + if (drxdap_fasi_write_block(dev_addr, + block_hdr.addr, + mc_block_nr_bytes, + mc_data, 0x0000)) { + rc = -EIO; + pr_err("error writing firmware at pos %zd\n", + mc_data - mc_data_init); + goto release; + } + break; + case UCODE_VERIFY: { /* Verify uploaded microcode */ + int result = 0; + u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE]; + u32 bytes_to_comp = 0; + u32 bytes_left = mc_block_nr_bytes; + u32 curr_addr = block_hdr.addr; + u8 *curr_ptr = mc_data; + + while (bytes_left != 0) { + if (bytes_left > DRX_UCODE_MAX_BUF_SIZE) + bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE; + else + bytes_to_comp = bytes_left; + + if (drxdap_fasi_read_block(dev_addr, + curr_addr, + (u16)bytes_to_comp, + (u8 *)mc_data_buffer, + 0x0000)) { + pr_err("error reading firmware at pos %zd\n", + mc_data - mc_data_init); + return -EIO; + } + + result = memcmp(curr_ptr, mc_data_buffer, + bytes_to_comp); + + if (result) { + pr_err("error verifying firmware at pos %zd\n", + mc_data - mc_data_init); + return -EIO; + } + + curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2)); + curr_ptr =&(curr_ptr[bytes_to_comp]); + bytes_left -=((u32) bytes_to_comp); + } + break; + } + default: + return -EINVAL; + + } + mc_data += mc_block_nr_bytes; + } + + return 0; + +release: + release_firmware(demod->firmware); + demod->firmware = NULL; + + return rc; +} + +/* caller is expected to check if lna is supported before enabling */ +static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state) +{ + struct drxuio_cfg uio_cfg; + struct drxuio_data uio_data; + int result; + + uio_cfg.uio = DRX_UIO1; + uio_cfg.mode = DRX_UIO_MODE_READWRITE; + /* Configure user-I/O #3: enable read/write */ + result = ctrl_set_uio_cfg(demod, &uio_cfg); + if (result) { + pr_err("Failed to setup LNA GPIO!\n"); + return result; + } + + uio_data.uio = DRX_UIO1; + uio_data.value = state; + result = ctrl_uio_write(demod, &uio_data); + if (result != 0) { + pr_err("Failed to %sable LNA!\n", + state ? "en" : "dis"); + return result; + } + return 0; +} + +/* + * The Linux DVB Driver for Micronas DRX39xx family (drx3933j) + * + * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com> + */ + +static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + enum drx_power_mode power_mode; + + if (enable) + power_mode = DRX_POWER_UP; + else + power_mode = DRX_POWER_DOWN; + + result = ctrl_power_mode(demod, &power_mode); + if (result != 0) { + pr_err("Power state change failed\n"); + return 0; + } + + return 0; +} + +static int drx39xxj_read_status(struct dvb_frontend *fe, enum fe_status *status) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int result; + enum drx_lock_status lock_status; + + *status = 0; + + result = ctrl_lock_status(demod, &lock_status); + if (result != 0) { + pr_err("drx39xxj: could not get lock status!\n"); + *status = 0; + } + + switch (lock_status) { + case DRX_NEVER_LOCK: + *status = 0; + pr_err("drx says NEVER_LOCK\n"); + break; + case DRX_NOT_LOCKED: + *status = 0; + break; + case DRX_LOCK_STATE_1: + case DRX_LOCK_STATE_2: + case DRX_LOCK_STATE_3: + case DRX_LOCK_STATE_4: + case DRX_LOCK_STATE_5: + case DRX_LOCK_STATE_6: + case DRX_LOCK_STATE_7: + case DRX_LOCK_STATE_8: + case DRX_LOCK_STATE_9: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC; + break; + case DRX_LOCKED: + *status = FE_HAS_SIGNAL + | FE_HAS_CARRIER + | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; + break; + default: + pr_err("Lock state unknown %d\n", lock_status); + } + ctrl_sig_quality(demod, lock_status); + + return 0; +} + +static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + + if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + *ber = 0; + return 0; + } + + if (!p->pre_bit_count.stat[0].uvalue) { + if (!p->pre_bit_error.stat[0].uvalue) + *ber = 0; + else + *ber = 1000000; + } else { + *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue, + p->pre_bit_count.stat[0].uvalue); + } + return 0; +} + +static int drx39xxj_read_signal_strength(struct dvb_frontend *fe, + u16 *strength) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + + if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + *strength = 0; + return 0; + } + + *strength = p->strength.stat[0].uvalue; + return 0; +} + +static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + u64 tmp64; + + if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + *snr = 0; + return 0; + } + + tmp64 = p->cnr.stat[0].svalue; + do_div(tmp64, 10); + *snr = tmp64; + return 0; +} + +static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + + if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { + *ucb = 0; + return 0; + } + + *ucb = p->block_error.stat[0].uvalue; + return 0; +} + +static int drx39xxj_set_frontend(struct dvb_frontend *fe) +{ +#ifdef DJH_DEBUG + int i; +#endif + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + enum drx_standard standard = DRX_STANDARD_8VSB; + struct drx_channel channel; + int result; + static const struct drx_channel def_channel = { + /* frequency */ 0, + /* bandwidth */ DRX_BANDWIDTH_6MHZ, + /* mirror */ DRX_MIRROR_NO, + /* constellation */ DRX_CONSTELLATION_AUTO, + /* hierarchy */ DRX_HIERARCHY_UNKNOWN, + /* priority */ DRX_PRIORITY_UNKNOWN, + /* coderate */ DRX_CODERATE_UNKNOWN, + /* guard */ DRX_GUARD_UNKNOWN, + /* fftmode */ DRX_FFTMODE_UNKNOWN, + /* classification */ DRX_CLASSIFICATION_AUTO, + /* symbolrate */ 5057000, + /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN, + /* ldpc */ DRX_LDPC_UNKNOWN, + /* carrier */ DRX_CARRIER_UNKNOWN, + /* frame mode */ DRX_FRAMEMODE_UNKNOWN + }; + u32 constellation = DRX_CONSTELLATION_AUTO; + + /* Bring the demod out of sleep */ + drx39xxj_set_powerstate(fe, 1); + + if (fe->ops.tuner_ops.set_params) { + u32 int_freq; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + /* Set tuner to desired frequency and standard */ + fe->ops.tuner_ops.set_params(fe); + + /* Use the tuner's IF */ + if (fe->ops.tuner_ops.get_if_frequency) { + fe->ops.tuner_ops.get_if_frequency(fe, &int_freq); + demod->my_common_attr->intermediate_freq = int_freq / 1000; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + } + + switch (p->delivery_system) { + case SYS_ATSC: + standard = DRX_STANDARD_8VSB; + break; + case SYS_DVBC_ANNEX_B: + standard = DRX_STANDARD_ITU_B; + + switch (p->modulation) { + case QAM_64: + constellation = DRX_CONSTELLATION_QAM64; + break; + case QAM_256: + constellation = DRX_CONSTELLATION_QAM256; + break; + default: + constellation = DRX_CONSTELLATION_AUTO; + break; + } + break; + default: + return -EINVAL; + } + /* Set the standard (will be powered up if necessary */ + result = ctrl_set_standard(demod, &standard); + if (result != 0) { + pr_err("Failed to set standard! result=%02x\n", + result); + return -EINVAL; + } + + /* set channel parameters */ + channel = def_channel; + channel.frequency = p->frequency / 1000; + channel.bandwidth = DRX_BANDWIDTH_6MHZ; + channel.constellation = constellation; + + /* program channel */ + result = ctrl_set_channel(demod, &channel); + if (result != 0) { + pr_err("Failed to set channel!\n"); + return -EINVAL; + } + /* Just for giggles, let's shut off the LNA again.... */ + drxj_set_lna_state(demod, false); + + /* After set_frontend, except for strength, stats aren't available */ + p->strength.stat[0].scale = FE_SCALE_RELATIVE; + + return 0; +} + +static int drx39xxj_sleep(struct dvb_frontend *fe) +{ + /* power-down the demodulator */ + return drx39xxj_set_powerstate(fe, 0); +} + +static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + bool i2c_gate_state; + int result; + +#ifdef DJH_DEBUG + pr_debug("i2c gate call: enable=%d state=%d\n", enable, + state->i2c_gate_open); +#endif + + if (enable) + i2c_gate_state = true; + else + i2c_gate_state = false; + + if (state->i2c_gate_open == enable) { + /* We're already in the desired state */ + return 0; + } + + result = ctrl_i2c_bridge(demod, &i2c_gate_state); + if (result != 0) { + pr_err("drx39xxj: could not open i2c gate [%d]\n", + result); + dump_stack(); + } else { + state->i2c_gate_open = enable; + } + return 0; +} + +static int drx39xxj_init(struct dvb_frontend *fe) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + int rc = 0; + + if (fe->exit == DVB_FE_DEVICE_RESUME) { + /* so drxj_open() does what it needs to do */ + demod->my_common_attr->is_opened = false; + rc = drxj_open(demod); + if (rc != 0) + pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc); + } else + drx39xxj_set_powerstate(fe, 1); + + return rc; +} + +static int drx39xxj_set_lna(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + struct drxj_data *ext_attr = demod->my_ext_attr; + + if (c->lna) { + if (!ext_attr->has_lna) { + pr_err("LNA is not supported on this device!\n"); + return -EINVAL; + + } + } + + return drxj_set_lna_state(demod, c->lna); +} + +static int drx39xxj_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *tune) +{ + tune->min_delay_ms = 1000; + return 0; +} + +static void drx39xxj_release(struct dvb_frontend *fe) +{ + struct drx39xxj_state *state = fe->demodulator_priv; + struct drx_demod_instance *demod = state->demod; + + /* if device is removed don't access it */ + if (fe->exit != DVB_FE_DEVICE_REMOVED) + drxj_close(demod); + + kfree(demod->my_ext_attr); + kfree(demod->my_common_attr); + kfree(demod->my_i2c_dev_addr); + release_firmware(demod->firmware); + kfree(demod); + kfree(state); +} + +static const struct dvb_frontend_ops drx39xxj_ops; + +struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) +{ + struct drx39xxj_state *state = NULL; + struct i2c_device_addr *demod_addr = NULL; + struct drx_common_attr *demod_comm_attr = NULL; + struct drxj_data *demod_ext_attr = NULL; + struct drx_demod_instance *demod = NULL; + struct dtv_frontend_properties *p; + int result; + + /* allocate memory for the internal state */ + state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL); + if (state == NULL) + goto error; + + demod = kmemdup(&drxj_default_demod_g, + sizeof(struct drx_demod_instance), GFP_KERNEL); + if (demod == NULL) + goto error; + + demod_addr = kmemdup(&drxj_default_addr_g, + sizeof(struct i2c_device_addr), GFP_KERNEL); + if (demod_addr == NULL) + goto error; + + demod_comm_attr = kmemdup(&drxj_default_comm_attr_g, + sizeof(struct drx_common_attr), GFP_KERNEL); + if (demod_comm_attr == NULL) + goto error; + + demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data), + GFP_KERNEL); + if (demod_ext_attr == NULL) + goto error; + + /* setup the state */ + state->i2c = i2c; + state->demod = demod; + + /* setup the demod data */ + demod->my_i2c_dev_addr = demod_addr; + demod->my_common_attr = demod_comm_attr; + demod->my_i2c_dev_addr->user_data = state; + demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; + demod->my_common_attr->verify_microcode = true; + demod->my_common_attr->intermediate_freq = 5000; + demod->my_common_attr->current_power_mode = DRX_POWER_DOWN; + demod->my_ext_attr = demod_ext_attr; + ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; + demod->i2c = i2c; + + result = drxj_open(demod); + if (result != 0) { + pr_err("DRX open failed! Aborting\n"); + goto error; + } + + /* create dvb_frontend */ + memcpy(&state->frontend.ops, &drx39xxj_ops, + sizeof(struct dvb_frontend_ops)); + + state->frontend.demodulator_priv = state; + + /* Initialize stats - needed for DVBv5 stats to work */ + p = &state->frontend.dtv_property_cache; + p->strength.len = 1; + p->pre_bit_count.len = 1; + p->pre_bit_error.len = 1; + p->post_bit_count.len = 1; + p->post_bit_error.len = 1; + p->block_count.len = 1; + p->block_error.len = 1; + p->cnr.len = 1; + + p->strength.stat[0].scale = FE_SCALE_RELATIVE; + p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + + return &state->frontend; + +error: + kfree(demod_ext_attr); + kfree(demod_comm_attr); + kfree(demod_addr); + kfree(demod); + kfree(state); + + return NULL; +} +EXPORT_SYMBOL_GPL(drx39xxj_attach); + +static const struct dvb_frontend_ops drx39xxj_ops = { + .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, + .info = { + .name = "Micronas DRX39xxj family Frontend", + .frequency_min_hz = 51 * MHz, + .frequency_max_hz = 858 * MHz, + .frequency_stepsize_hz = 62500, + .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB + }, + + .init = drx39xxj_init, + .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl, + .sleep = drx39xxj_sleep, + .set_frontend = drx39xxj_set_frontend, + .get_tune_settings = drx39xxj_get_tune_settings, + .read_status = drx39xxj_read_status, + .read_ber = drx39xxj_read_ber, + .read_signal_strength = drx39xxj_read_signal_strength, + .read_snr = drx39xxj_read_snr, + .read_ucblocks = drx39xxj_read_ucblocks, + .release = drx39xxj_release, + .set_lna = drx39xxj_set_lna, +}; + +MODULE_DESCRIPTION("Micronas DRX39xxj Frontend"); +MODULE_AUTHOR("Devin Heitmueller"); +MODULE_LICENSE("GPL"); +MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE); diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.h b/drivers/media/dvb-frontends/drx39xyj/drxj.h new file mode 100644 index 000000000..232b3b0d6 --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.h @@ -0,0 +1,651 @@ + +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + DRXJ specific header file + + Authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen +*/ + +#ifndef __DRXJ_H__ +#define __DRXJ_H__ +/*------------------------------------------------------------------------- +INCLUDES +-------------------------------------------------------------------------*/ + +#include "drx_driver.h" +#include "drx_dap_fasi.h" + +/* Check DRX-J specific dap condition */ +/* Multi master mode and short addr format only will not work. + RMW, CRC reset, broadcast and switching back to single master mode + cannot be done with short addr only in multi master mode. */ +#if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) +#error "Multi master mode and short addressing only is an illegal combination" + *; /* Generate a fatal compiler error to make sure it stops here, + this is necessary because not all compilers stop after a #error. */ +#endif + +/*------------------------------------------------------------------------- +TYPEDEFS +-------------------------------------------------------------------------*/ +/*============================================================================*/ +/*============================================================================*/ +/*== code support ============================================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/*============================================================================*/ +/*============================================================================*/ +/*== SCU cmd if =============================================================*/ +/*============================================================================*/ +/*============================================================================*/ + + struct drxjscu_cmd { + u16 command; + /*< Command number */ + u16 parameter_len; + /*< Data length in byte */ + u16 result_len; + /*< result length in byte */ + u16 *parameter; + /*< General purpose param */ + u16 *result; + /*< General purpose param */}; + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL CFG related data structures ========================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* extra intermediate lock state for VSB,QAM,NTSC */ +#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) + +/* OOB lock states */ +#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ +#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ + +/* Intermediate powermodes for DRXJ */ +#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 +#define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 +#define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 + +/* supstition for GPIO FNC mux */ +#define APP_O (0x0000) + +/*#define DRX_CTRL_BASE (0x0000)*/ + +#define DRXJ_CTRL_CFG_BASE (0x1000) + enum drxj_cfg_type { + DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, + DRXJ_CFG_AGC_IF, + DRXJ_CFG_AGC_INTERNAL, + DRXJ_CFG_PRE_SAW, + DRXJ_CFG_AFE_GAIN, + DRXJ_CFG_SYMBOL_CLK_OFFSET, + DRXJ_CFG_ACCUM_CR_RS_CW_ERR, + DRXJ_CFG_FEC_MERS_SEQ_COUNT, + DRXJ_CFG_OOB_MISC, + DRXJ_CFG_SMART_ANT, + DRXJ_CFG_OOB_PRE_SAW, + DRXJ_CFG_VSB_MISC, + DRXJ_CFG_RESET_PACKET_ERR, + + /* ATV (FM) */ + DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ + DRXJ_CFG_ATV_MISC, + DRXJ_CFG_ATV_EQU_COEF, + DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ + + DRXJ_CFG_MPEG_OUTPUT_MISC, + DRXJ_CFG_HW_CFG, + DRXJ_CFG_OOB_LO_POW, + + DRXJ_CFG_MAX /* dummy, never to be used */}; + +/* +* /enum drxj_cfg_smart_ant_io * smart antenna i/o. +*/ +enum drxj_cfg_smart_ant_io { + DRXJ_SMT_ANT_OUTPUT = 0, + DRXJ_SMT_ANT_INPUT +}; + +/* +* /struct drxj_cfg_smart_ant * Set smart antenna. +*/ + struct drxj_cfg_smart_ant { + enum drxj_cfg_smart_ant_io io; + u16 ctrl_data; + }; + +/* +* /struct DRXJAGCSTATUS_t +* AGC status information from the DRXJ-IQM-AF. +*/ +struct drxj_agc_status { + u16 IFAGC; + u16 RFAGC; + u16 digital_agc; +}; + +/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ + +/* +* /enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ. +*/ + enum drxj_agc_ctrl_mode { + DRX_AGC_CTRL_AUTO = 0, + DRX_AGC_CTRL_USER, + DRX_AGC_CTRL_OFF}; + +/* +* /struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ. +*/ + struct drxj_cfg_agc { + enum drx_standard standard; /* standard for which these settings apply */ + enum drxj_agc_ctrl_mode ctrl_mode; /* off, user, auto */ + u16 output_level; /* range dependent on AGC */ + u16 min_output_level; /* range dependent on AGC */ + u16 max_output_level; /* range dependent on AGC */ + u16 speed; /* range dependent on AGC */ + u16 top; /* rf-agc take over point */ + u16 cut_off_current; /* rf-agc is accelerated if output current + is below cut-off current */}; + +/* DRXJ_CFG_PRE_SAW */ + +/* +* /struct drxj_cfg_pre_saw * Interface to configure pre SAW sense. +*/ + struct drxj_cfg_pre_saw { + enum drx_standard standard; /* standard to which these settings apply */ + u16 reference; /* pre SAW reference value, range 0 .. 31 */ + bool use_pre_saw; /* true algorithms must use pre SAW sense */}; + +/* DRXJ_CFG_AFE_GAIN */ + +/* +* /struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA). +*/ + struct drxj_cfg_afe_gain { + enum drx_standard standard; /* standard to which these settings apply */ + u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */}; + +/* +* /struct drxjrs_errors +* Available failure information in DRXJ_FEC_RS. +* +* Container for errors that are received in the most recently finished measurement period +* +*/ + struct drxjrs_errors { + u16 nr_bit_errors; + /*< no of pre RS bit errors */ + u16 nr_symbol_errors; + /*< no of pre RS symbol errors */ + u16 nr_packet_errors; + /*< no of pre RS packet errors */ + u16 nr_failures; + /*< no of post RS failures to decode */ + u16 nr_snc_par_fail_count; + /*< no of post RS bit erros */ + }; + +/* +* /struct drxj_cfg_vsb_misc * symbol error rate +*/ + struct drxj_cfg_vsb_misc { + u32 symb_error; + /*< symbol error rate sps */}; + +/* +* /enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. +* +*/ + enum drxj_mpeg_start_width { + DRXJ_MPEG_START_WIDTH_1CLKCYC, + DRXJ_MPEG_START_WIDTH_8CLKCYC}; + +/* +* /enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. +* +*/ + enum drxj_mpeg_output_clock_rate { + DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, + DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, + DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K}; + +/* +* /struct DRXJCfgMisc_t +* Change TEI bit of MPEG output +* reverse MPEG output bit order +* set MPEG output clock rate +*/ + struct drxj_cfg_mpeg_output_misc { + bool disable_tei_handling; /*< if true pass (not change) TEI bit */ + bool bit_reverse_mpeg_outout; /*< if true, parallel: msb on MD0; serial: lsb out first */ + enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; + /*< set MPEG output clock rate that overwirtes the derived one from symbol rate */ + enum drxj_mpeg_start_width mpeg_start_width; /*< set MPEG output start width */}; + +/* +* /enum drxj_xtal_freq * Supported external crystal reference frequency. +*/ + enum drxj_xtal_freq { + DRXJ_XTAL_FREQ_RSVD, + DRXJ_XTAL_FREQ_27MHZ, + DRXJ_XTAL_FREQ_20P25MHZ, + DRXJ_XTAL_FREQ_4MHZ}; + +/* +* /enum drxj_xtal_freq * Supported external crystal reference frequency. +*/ + enum drxji2c_speed { + DRXJ_I2C_SPEED_400KBPS, + DRXJ_I2C_SPEED_100KBPS}; + +/* +* /struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal +* reference frequency, I2C speed, etc... +*/ + struct drxj_cfg_hw_cfg { + enum drxj_xtal_freq xtal_freq; + /*< crystal reference frequency */ + enum drxji2c_speed i2c_speed; + /*< 100 or 400 kbps */}; + +/* + * DRXJ_CFG_ATV_MISC + */ + struct drxj_cfg_atv_misc { + s16 peak_filter; /* -8 .. 15 */ + u16 noise_filter; /* 0 .. 15 */}; + +/* + * struct drxj_cfg_oob_misc */ +#define DRXJ_OOB_STATE_RESET 0x0 +#define DRXJ_OOB_STATE_AGN_HUNT 0x1 +#define DRXJ_OOB_STATE_DGN_HUNT 0x2 +#define DRXJ_OOB_STATE_AGC_HUNT 0x3 +#define DRXJ_OOB_STATE_FRQ_HUNT 0x4 +#define DRXJ_OOB_STATE_PHA_HUNT 0x8 +#define DRXJ_OOB_STATE_TIM_HUNT 0x10 +#define DRXJ_OOB_STATE_EQU_HUNT 0x20 +#define DRXJ_OOB_STATE_EQT_HUNT 0x30 +#define DRXJ_OOB_STATE_SYNC 0x40 + +struct drxj_cfg_oob_misc { + struct drxj_agc_status agc; + bool eq_lock; + bool sym_timing_lock; + bool phase_lock; + bool freq_lock; + bool dig_gain_lock; + bool ana_gain_lock; + u8 state; +}; + +/* + * Index of in array of coef + */ + enum drxj_cfg_oob_lo_power { + DRXJ_OOB_LO_POW_MINUS0DB = 0, + DRXJ_OOB_LO_POW_MINUS5DB, + DRXJ_OOB_LO_POW_MINUS10DB, + DRXJ_OOB_LO_POW_MINUS15DB, + DRXJ_OOB_LO_POW_MAX}; + +/* + * DRXJ_CFG_ATV_EQU_COEF + */ + struct drxj_cfg_atv_equ_coef { + s16 coef0; /* -256 .. 255 */ + s16 coef1; /* -256 .. 255 */ + s16 coef2; /* -256 .. 255 */ + s16 coef3; /* -256 .. 255 */}; + +/* + * Index of in array of coef + */ + enum drxj_coef_array_index { + DRXJ_COEF_IDX_MN = 0, + DRXJ_COEF_IDX_FM, + DRXJ_COEF_IDX_L, + DRXJ_COEF_IDX_LP, + DRXJ_COEF_IDX_BG, + DRXJ_COEF_IDX_DK, + DRXJ_COEF_IDX_I, + DRXJ_COEF_IDX_MAX}; + +/* + * DRXJ_CFG_ATV_OUTPUT + */ + +/* +* /enum DRXJAttenuation_t +* Attenuation setting for SIF AGC. +* +*/ + enum drxjsif_attenuation { + DRXJ_SIF_ATTENUATION_0DB, + DRXJ_SIF_ATTENUATION_3DB, + DRXJ_SIF_ATTENUATION_6DB, + DRXJ_SIF_ATTENUATION_9DB}; + +/* +* /struct drxj_cfg_atv_output * SIF attenuation setting. +* +*/ +struct drxj_cfg_atv_output { + bool enable_cvbs_output; /* true= enabled */ + bool enable_sif_output; /* true= enabled */ + enum drxjsif_attenuation sif_attenuation; +}; + +/* + DRXJ_CFG_ATV_AGC_STATUS (get only) +*/ +/* TODO : AFE interface not yet finished, subject to change */ + struct drxj_cfg_atv_agc_status { + u16 rf_agc_gain; /* 0 .. 877 uA */ + u16 if_agc_gain; /* 0 .. 877 uA */ + s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */ + s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */ + u16 rf_agc_loop_gain; /* 0 .. 7 */ + u16 if_agc_loop_gain; /* 0 .. 7 */ + u16 video_agc_loop_gain; /* 0 .. 7 */}; + +/*============================================================================*/ +/*============================================================================*/ +/*== CTRL related data structures ============================================*/ +/*============================================================================*/ +/*============================================================================*/ + +/* NONE */ + +/*============================================================================*/ +/*============================================================================*/ + +/*========================================*/ +/* +* /struct struct drxj_data * DRXJ specific attributes. +* +* Global data container for DRXJ specific data. +* +*/ + struct drxj_data { + /* device capabilities (determined during drx_open()) */ + bool has_lna; /*< true if LNA (aka PGA) present */ + bool has_oob; /*< true if OOB supported */ + bool has_ntsc; /*< true if NTSC supported */ + bool has_btsc; /*< true if BTSC supported */ + bool has_smatx; /*< true if mat_tx is available */ + bool has_smarx; /*< true if mat_rx is available */ + bool has_gpio; /*< true if GPIO is available */ + bool has_irqn; /*< true if IRQN is available */ + /* A1/A2/A... */ + u8 mfx; /*< metal fix */ + + /* tuner settings */ + bool mirror_freq_spect_oob;/*< tuner inversion (true = tuner mirrors the signal */ + + /* standard/channel settings */ + enum drx_standard standard; /*< current standard information */ + enum drx_modulation constellation; + /*< current constellation */ + s32 frequency; /*< center signal frequency in KHz */ + enum drx_bandwidth curr_bandwidth; + /*< current channel bandwidth */ + enum drx_mirror mirror; /*< current channel mirror */ + + /* signal quality information */ + u32 fec_bits_desired; /*< BER accounting period */ + u16 fec_vd_plen; /*< no of trellis symbols: VD SER measurement period */ + u16 qam_vd_prescale; /*< Viterbi Measurement Prescale */ + u16 qam_vd_period; /*< Viterbi Measurement period */ + u16 fec_rs_plen; /*< defines RS BER measurement period */ + u16 fec_rs_prescale; /*< ReedSolomon Measurement Prescale */ + u16 fec_rs_period; /*< ReedSolomon Measurement period */ + bool reset_pkt_err_acc; /*< Set a flag to reset accumulated packet error */ + u16 pkt_err_acc_start; /*< Set a flag to reset accumulated packet error */ + + /* HI configuration */ + u16 hi_cfg_timing_div; /*< HI Configure() parameter 2 */ + u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 */ + u16 hi_cfg_wake_up_key; /*< HI Configure() parameter 4 */ + u16 hi_cfg_ctrl; /*< HI Configure() parameter 5 */ + u16 hi_cfg_transmit; /*< HI Configure() parameter 6 */ + + /* UIO configuration */ + enum drxuio_mode uio_sma_rx_mode;/*< current mode of SmaRx pin */ + enum drxuio_mode uio_sma_tx_mode;/*< current mode of SmaTx pin */ + enum drxuio_mode uio_gpio_mode; /*< current mode of ASEL pin */ + enum drxuio_mode uio_irqn_mode; /*< current mode of IRQN pin */ + + /* IQM fs frequency shift and inversion */ + u32 iqm_fs_rate_ofs; /*< frequency shifter setting after setchannel */ + bool pos_image; /*< True: positive image */ + /* IQM RC frequency shift */ + u32 iqm_rc_rate_ofs; /*< frequency shifter setting after setchannel */ + + /* ATV configuration */ + u32 atv_cfg_changed_flags; /*< flag: flags cfg changes */ + s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU0__A */ + s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU1__A */ + s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU2__A */ + s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU3__A */ + bool phase_correction_bypass;/*< flag: true=bypass */ + s16 atv_top_vid_peak; /*< shadow of ATV_TOP_VID_PEAK__A */ + u16 atv_top_noise_th; /*< shadow of ATV_TOP_NOISE_TH__A */ + bool enable_cvbs_output; /*< flag CVBS output enable */ + bool enable_sif_output; /*< flag SIF output enable */ + enum drxjsif_attenuation sif_attenuation; + /*< current SIF att setting */ + /* Agc configuration for QAM and VSB */ + struct drxj_cfg_agc qam_rf_agc_cfg; /*< qam RF AGC config */ + struct drxj_cfg_agc qam_if_agc_cfg; /*< qam IF AGC config */ + struct drxj_cfg_agc vsb_rf_agc_cfg; /*< vsb RF AGC config */ + struct drxj_cfg_agc vsb_if_agc_cfg; /*< vsb IF AGC config */ + + /* PGA gain configuration for QAM and VSB */ + u16 qam_pga_cfg; /*< qam PGA config */ + u16 vsb_pga_cfg; /*< vsb PGA config */ + + /* Pre SAW configuration for QAM and VSB */ + struct drxj_cfg_pre_saw qam_pre_saw_cfg; + /*< qam pre SAW config */ + struct drxj_cfg_pre_saw vsb_pre_saw_cfg; + /*< qam pre SAW config */ + + /* Version information */ + char v_text[2][12]; /*< allocated text versions */ + struct drx_version v_version[2]; /*< allocated versions structs */ + struct drx_version_list v_list_elements[2]; + /*< allocated version list */ + + /* smart antenna configuration */ + bool smart_ant_inverted; + + /* Tracking filter setting for OOB */ + u16 oob_trk_filter_cfg[8]; + bool oob_power_on; + + /* MPEG static bitrate setting */ + u32 mpeg_ts_static_bitrate; /*< bitrate static MPEG output */ + bool disable_te_ihandling; /*< MPEG TS TEI handling */ + bool bit_reverse_mpeg_outout;/*< MPEG output bit order */ + enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; + /*< MPEG output clock rate */ + enum drxj_mpeg_start_width mpeg_start_width; + /*< MPEG Start width */ + + /* Pre SAW & Agc configuration for ATV */ + struct drxj_cfg_pre_saw atv_pre_saw_cfg; + /*< atv pre SAW config */ + struct drxj_cfg_agc atv_rf_agc_cfg; /*< atv RF AGC config */ + struct drxj_cfg_agc atv_if_agc_cfg; /*< atv IF AGC config */ + u16 atv_pga_cfg; /*< atv pga config */ + + u32 curr_symbol_rate; + + /* pin-safe mode */ + bool pdr_safe_mode; /*< PDR safe mode activated */ + u16 pdr_safe_restore_val_gpio; + u16 pdr_safe_restore_val_v_sync; + u16 pdr_safe_restore_val_sma_rx; + u16 pdr_safe_restore_val_sma_tx; + + /* OOB pre-saw value */ + u16 oob_pre_saw; + enum drxj_cfg_oob_lo_power oob_lo_pow; + + struct drx_aud_data aud_data; + /*< audio storage */}; + +/*------------------------------------------------------------------------- +Access MACROS +-------------------------------------------------------------------------*/ +/* +* \brief Compilable references to attributes +* \param d pointer to demod instance +* +* Used as main reference to an attribute field. +* Can be used by both macro implementation and function implementation. +* These macros are defined to avoid duplication of code in macro and function +* definitions that handle access of demod common or extended attributes. +* +*/ + +#define DRXJ_ATTR_BTSC_DETECT(d) \ + (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect) + +/*------------------------------------------------------------------------- +DEFINES +-------------------------------------------------------------------------*/ + +/* +* \def DRXJ_NTSC_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For NTSC standard. +* NTSC channels are listed by their picture carrier frequency (Fpc). +* The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. +* In case the tuner module is not used the DRX-J requires that the tuner is +* tuned to the centre frequency of the channel: +* +* Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET +* +*/ +#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) + +/* +* \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - BG standard. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +* +*/ +#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) + +/* +* \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +* +*/ +#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) + +/* +* \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET +* \brief Offset from picture carrier to centre frequency in kHz, in RF domain +* +* For PAL/SECAM - LP standard. This define is needed in case the tuner module +* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). +* The DRX-J requires that the tuner is tuned to: +* Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET +* +* In case the tuner module is used the drxdriver takes care of this. +* In case the tuner module is NOT used the application programmer must take +* care of this. +*/ +#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) + +/* +* \def DRXJ_FM_CARRIER_FREQ_OFFSET +* \brief Offset from sound carrier to centre frequency in kHz, in RF domain +* +* For FM standard. +* FM channels are listed by their sound carrier frequency (Fsc). +* The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as +* input. +* In case the tuner module is not used the DRX-J requires that the tuner is +* tuned to the Ffm frequency of the channel. +* +* Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET +* +*/ +#define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000)) + +/* Revision types -------------------------------------------------------*/ + +#define DRXJ_TYPE_ID (0x3946000DUL) + +/* Macros ---------------------------------------------------------------*/ + +/* Convert OOB lock status to string */ +#define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ + (x == DRX_NEVER_LOCK) ? "Never" : \ + (x == DRX_NOT_LOCKED) ? "No" : \ + (x == DRX_LOCKED) ? "Locked" : \ + (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ + (x == DRX_LOCK_STATE_2) ? "sync lock" : \ + "(Invalid)") + +#endif /* __DRXJ_H__ */ diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj_map.h b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h new file mode 100644 index 000000000..0bbd4ae1f --- /dev/null +++ b/drivers/media/dvb-frontends/drx39xyj/drxj_map.h @@ -0,0 +1,15055 @@ +/* + Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Trident Microsystems nor Hauppauge Computer Works + nor the names of its contributors may be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* + *********************************************************************************************************************** + * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE + * + * Filename: drxj_map.h + * Generated on: Mon Jan 18 12:09:24 2010 + * Generated by: IDF:x 1.3.0 + * Generated from: reg_map + * Output start: [entry point] + * + * filename last modified re-use + * ----------------------------------------------------- + * reg_map.1.tmp Mon Jan 18 12:09:24 2010 - + * + */ + +#ifndef __DRXJ_MAP__H__ +#define __DRXJ_MAP__H__ INCLUDED + +#ifdef _REGISTERTABLE_ +#include <registertable.h> + extern register_table_t drxj_map[]; + extern register_table_info_t drxj_map_info[]; +#endif + +#define ATV_COMM_EXEC__A 0xC00000 +#define ATV_COMM_EXEC__W 2 +#define ATV_COMM_EXEC__M 0x3 +#define ATV_COMM_EXEC__PRE 0x0 +#define ATV_COMM_EXEC_STOP 0x0 +#define ATV_COMM_EXEC_ACTIVE 0x1 +#define ATV_COMM_EXEC_HOLD 0x2 + +#define ATV_COMM_STATE__A 0xC00001 +#define ATV_COMM_STATE__W 16 +#define ATV_COMM_STATE__M 0xFFFF +#define ATV_COMM_STATE__PRE 0x0 +#define ATV_COMM_MB__A 0xC00002 +#define ATV_COMM_MB__W 16 +#define ATV_COMM_MB__M 0xFFFF +#define ATV_COMM_MB__PRE 0x0 +#define ATV_COMM_INT_REQ__A 0xC00003 +#define ATV_COMM_INT_REQ__W 16 +#define ATV_COMM_INT_REQ__M 0xFFFF +#define ATV_COMM_INT_REQ__PRE 0x0 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__B 0 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__W 1 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__M 0x1 +#define ATV_COMM_INT_REQ_COMM_INT_REQ__PRE 0x0 + +#define ATV_COMM_INT_STA__A 0xC00005 +#define ATV_COMM_INT_STA__W 16 +#define ATV_COMM_INT_STA__M 0xFFFF +#define ATV_COMM_INT_STA__PRE 0x0 +#define ATV_COMM_INT_MSK__A 0xC00006 +#define ATV_COMM_INT_MSK__W 16 +#define ATV_COMM_INT_MSK__M 0xFFFF +#define ATV_COMM_INT_MSK__PRE 0x0 +#define ATV_COMM_INT_STM__A 0xC00007 +#define ATV_COMM_INT_STM__W 16 +#define ATV_COMM_INT_STM__M 0xFFFF +#define ATV_COMM_INT_STM__PRE 0x0 + +#define ATV_COMM_KEY__A 0xC0000F +#define ATV_COMM_KEY__W 16 +#define ATV_COMM_KEY__M 0xFFFF +#define ATV_COMM_KEY__PRE 0x0 +#define ATV_COMM_KEY_KEY 0xFABA +#define ATV_COMM_KEY_MIN 0x0 +#define ATV_COMM_KEY_MAX 0xFFFF + +#define ATV_TOP_COMM_EXEC__A 0xC10000 +#define ATV_TOP_COMM_EXEC__W 2 +#define ATV_TOP_COMM_EXEC__M 0x3 +#define ATV_TOP_COMM_EXEC__PRE 0x0 +#define ATV_TOP_COMM_EXEC_STOP 0x0 +#define ATV_TOP_COMM_EXEC_ACTIVE 0x1 +#define ATV_TOP_COMM_EXEC_HOLD 0x2 + +#define ATV_TOP_COMM_STATE__A 0xC10001 +#define ATV_TOP_COMM_STATE__W 16 +#define ATV_TOP_COMM_STATE__M 0xFFFF +#define ATV_TOP_COMM_STATE__PRE 0x0 +#define ATV_TOP_COMM_STATE_STATE__B 0 +#define ATV_TOP_COMM_STATE_STATE__W 16 +#define ATV_TOP_COMM_STATE_STATE__M 0xFFFF +#define ATV_TOP_COMM_STATE_STATE__PRE 0x0 + +#define ATV_TOP_COMM_MB__A 0xC10002 +#define ATV_TOP_COMM_MB__W 16 +#define ATV_TOP_COMM_MB__M 0xFFFF +#define ATV_TOP_COMM_MB__PRE 0x0 +#define ATV_TOP_COMM_MB_CTL__B 0 +#define ATV_TOP_COMM_MB_CTL__W 1 +#define ATV_TOP_COMM_MB_CTL__M 0x1 +#define ATV_TOP_COMM_MB_CTL__PRE 0x0 +#define ATV_TOP_COMM_MB_OBS__B 1 +#define ATV_TOP_COMM_MB_OBS__W 1 +#define ATV_TOP_COMM_MB_OBS__M 0x2 +#define ATV_TOP_COMM_MB_OBS__PRE 0x0 + +#define ATV_TOP_COMM_MB_MUX_CTRL__B 2 +#define ATV_TOP_COMM_MB_MUX_CTRL__W 4 +#define ATV_TOP_COMM_MB_MUX_CTRL__M 0x3C +#define ATV_TOP_COMM_MB_MUX_CTRL__PRE 0x0 +#define ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S 0x0 +#define ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN 0x4 +#define ATV_TOP_COMM_MB_MUX_CTRL_CORR_O 0x8 +#define ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O 0xC +#define ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ 0x10 +#define ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O 0x14 +#define ATV_TOP_COMM_MB_MUX_CTRL_SIF_O 0x18 +#define ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O 0x1C +#define ATV_TOP_COMM_MB_MUX_CTRL_POST_S 0x20 + +#define ATV_TOP_COMM_MB_MUX_OBS__B 6 +#define ATV_TOP_COMM_MB_MUX_OBS__W 4 +#define ATV_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define ATV_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define ATV_TOP_COMM_MB_MUX_OBS_PEAK_S 0x0 +#define ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN 0x40 +#define ATV_TOP_COMM_MB_MUX_OBS_CORR_O 0x80 +#define ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O 0xC0 +#define ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ 0x100 +#define ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O 0x140 +#define ATV_TOP_COMM_MB_MUX_OBS_SIF_O 0x180 +#define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0x1C0 +#define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0x200 + +#define ATV_TOP_COMM_INT_REQ__A 0xC10003 +#define ATV_TOP_COMM_INT_REQ__W 16 +#define ATV_TOP_COMM_INT_REQ__M 0xFFFF +#define ATV_TOP_COMM_INT_REQ__PRE 0x0 +#define ATV_TOP_COMM_INT_STA__A 0xC10005 +#define ATV_TOP_COMM_INT_STA__W 16 +#define ATV_TOP_COMM_INT_STA__M 0xFFFF +#define ATV_TOP_COMM_INT_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_FAGC_STA__B 0 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__W 1 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__M 0x1 +#define ATV_TOP_COMM_INT_STA_FAGC_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_OVM_STA__B 1 +#define ATV_TOP_COMM_INT_STA_OVM_STA__W 1 +#define ATV_TOP_COMM_INT_STA_OVM_STA__M 0x2 +#define ATV_TOP_COMM_INT_STA_OVM_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__B 2 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__W 1 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__M 0x4 +#define ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK__A 0xC10006 +#define ATV_TOP_COMM_INT_MSK__W 16 +#define ATV_TOP_COMM_INT_MSK__M 0xFFFF +#define ATV_TOP_COMM_INT_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__B 0 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__M 0x1 +#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__B 1 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0x2 +#define ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B 2 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W 1 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M 0x4 +#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM__A 0xC10007 +#define ATV_TOP_COMM_INT_STM__W 16 +#define ATV_TOP_COMM_INT_STM__M 0xFFFF +#define ATV_TOP_COMM_INT_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_FAGC_STM__B 0 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__W 1 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__M 0x1 +#define ATV_TOP_COMM_INT_STM_FAGC_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_OVM_STM__B 1 +#define ATV_TOP_COMM_INT_STM_OVM_STM__W 1 +#define ATV_TOP_COMM_INT_STM_OVM_STM__M 0x2 +#define ATV_TOP_COMM_INT_STM_OVM_STM__PRE 0x0 + +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__B 2 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__W 1 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__M 0x4 +#define ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE 0x0 + +#define ATV_TOP_COMM_KEY__A 0xC1000F +#define ATV_TOP_COMM_KEY__W 16 +#define ATV_TOP_COMM_KEY__M 0xFFFF +#define ATV_TOP_COMM_KEY__PRE 0x0 + +#define ATV_TOP_COMM_KEY_KEY__B 0 +#define ATV_TOP_COMM_KEY_KEY__W 16 +#define ATV_TOP_COMM_KEY_KEY__M 0xFFFF +#define ATV_TOP_COMM_KEY_KEY__PRE 0x0 +#define ATV_TOP_COMM_KEY_KEY_KEY 0xFABA +#define ATV_TOP_COMM_KEY_KEY_MIN 0x0 +#define ATV_TOP_COMM_KEY_KEY_MAX 0xFFFF + +#define ATV_TOP_CR_AMP_TH__A 0xC10010 +#define ATV_TOP_CR_AMP_TH__W 8 +#define ATV_TOP_CR_AMP_TH__M 0xFF +#define ATV_TOP_CR_AMP_TH__PRE 0x8 +#define ATV_TOP_CR_AMP_TH_MN 0x8 + +#define ATV_TOP_CR_CONT__A 0xC10011 +#define ATV_TOP_CR_CONT__W 9 +#define ATV_TOP_CR_CONT__M 0x1FF +#define ATV_TOP_CR_CONT__PRE 0x9C + +#define ATV_TOP_CR_CONT_CR_P__B 0 +#define ATV_TOP_CR_CONT_CR_P__W 3 +#define ATV_TOP_CR_CONT_CR_P__M 0x7 +#define ATV_TOP_CR_CONT_CR_P__PRE 0x4 +#define ATV_TOP_CR_CONT_CR_P_MN 0x4 +#define ATV_TOP_CR_CONT_CR_P_FM 0x0 + +#define ATV_TOP_CR_CONT_CR_D__B 3 +#define ATV_TOP_CR_CONT_CR_D__W 3 +#define ATV_TOP_CR_CONT_CR_D__M 0x38 +#define ATV_TOP_CR_CONT_CR_D__PRE 0x18 +#define ATV_TOP_CR_CONT_CR_D_MN 0x18 +#define ATV_TOP_CR_CONT_CR_D_FM 0x0 + +#define ATV_TOP_CR_CONT_CR_I__B 6 +#define ATV_TOP_CR_CONT_CR_I__W 3 +#define ATV_TOP_CR_CONT_CR_I__M 0x1C0 +#define ATV_TOP_CR_CONT_CR_I__PRE 0x80 +#define ATV_TOP_CR_CONT_CR_I_MN 0x80 +#define ATV_TOP_CR_CONT_CR_I_FM 0x0 + +#define ATV_TOP_CR_OVM_TH__A 0xC10012 +#define ATV_TOP_CR_OVM_TH__W 8 +#define ATV_TOP_CR_OVM_TH__M 0xFF +#define ATV_TOP_CR_OVM_TH__PRE 0xA0 +#define ATV_TOP_CR_OVM_TH_MN 0xA0 +#define ATV_TOP_CR_OVM_TH_FM 0x0 + +#define ATV_TOP_NOISE_TH__A 0xC10013 +#define ATV_TOP_NOISE_TH__W 4 +#define ATV_TOP_NOISE_TH__M 0xF +#define ATV_TOP_NOISE_TH__PRE 0x8 +#define ATV_TOP_NOISE_TH_MN 0x8 + +#define ATV_TOP_EQU0__A 0xC10014 +#define ATV_TOP_EQU0__W 9 +#define ATV_TOP_EQU0__M 0x1FF +#define ATV_TOP_EQU0__PRE 0x1FB + +#define ATV_TOP_EQU0_EQU_C0__B 0 +#define ATV_TOP_EQU0_EQU_C0__W 9 +#define ATV_TOP_EQU0_EQU_C0__M 0x1FF +#define ATV_TOP_EQU0_EQU_C0__PRE 0x1FB +#define ATV_TOP_EQU0_EQU_C0_MN 0xFB + +#define ATV_TOP_EQU1__A 0xC10015 +#define ATV_TOP_EQU1__W 9 +#define ATV_TOP_EQU1__M 0x1FF +#define ATV_TOP_EQU1__PRE 0x1CE + +#define ATV_TOP_EQU1_EQU_C1__B 0 +#define ATV_TOP_EQU1_EQU_C1__W 9 +#define ATV_TOP_EQU1_EQU_C1__M 0x1FF +#define ATV_TOP_EQU1_EQU_C1__PRE 0x1CE +#define ATV_TOP_EQU1_EQU_C1_MN 0xCE + +#define ATV_TOP_EQU2__A 0xC10016 +#define ATV_TOP_EQU2__W 9 +#define ATV_TOP_EQU2__M 0x1FF +#define ATV_TOP_EQU2__PRE 0xD2 + +#define ATV_TOP_EQU2_EQU_C2__B 0 +#define ATV_TOP_EQU2_EQU_C2__W 9 +#define ATV_TOP_EQU2_EQU_C2__M 0x1FF +#define ATV_TOP_EQU2_EQU_C2__PRE 0xD2 +#define ATV_TOP_EQU2_EQU_C2_MN 0xD2 + +#define ATV_TOP_EQU3__A 0xC10017 +#define ATV_TOP_EQU3__W 9 +#define ATV_TOP_EQU3__M 0x1FF +#define ATV_TOP_EQU3__PRE 0x160 + +#define ATV_TOP_EQU3_EQU_C3__B 0 +#define ATV_TOP_EQU3_EQU_C3__W 9 +#define ATV_TOP_EQU3_EQU_C3__M 0x1FF +#define ATV_TOP_EQU3_EQU_C3__PRE 0x160 +#define ATV_TOP_EQU3_EQU_C3_MN 0x60 + +#define ATV_TOP_ROT_MODE__A 0xC10018 +#define ATV_TOP_ROT_MODE__W 1 +#define ATV_TOP_ROT_MODE__M 0x1 +#define ATV_TOP_ROT_MODE__PRE 0x0 +#define ATV_TOP_ROT_MODE_AMPTH_DEPEND 0x0 +#define ATV_TOP_ROT_MODE_ALWAYS 0x1 + +#define ATV_TOP_MOD_CONTROL__A 0xC10019 +#define ATV_TOP_MOD_CONTROL__W 12 +#define ATV_TOP_MOD_CONTROL__M 0xFFF +#define ATV_TOP_MOD_CONTROL__PRE 0x5B1 + +#define ATV_TOP_MOD_CONTROL_MOD_IR__B 0 +#define ATV_TOP_MOD_CONTROL_MOD_IR__W 3 +#define ATV_TOP_MOD_CONTROL_MOD_IR__M 0x7 +#define ATV_TOP_MOD_CONTROL_MOD_IR__PRE 0x1 +#define ATV_TOP_MOD_CONTROL_MOD_IR_MN 0x1 +#define ATV_TOP_MOD_CONTROL_MOD_IR_FM 0x0 + +#define ATV_TOP_MOD_CONTROL_MOD_IF__B 3 +#define ATV_TOP_MOD_CONTROL_MOD_IF__W 4 +#define ATV_TOP_MOD_CONTROL_MOD_IF__M 0x78 +#define ATV_TOP_MOD_CONTROL_MOD_IF__PRE 0x30 +#define ATV_TOP_MOD_CONTROL_MOD_IF_MN 0x30 +#define ATV_TOP_MOD_CONTROL_MOD_IF_FM 0x0 + +#define ATV_TOP_MOD_CONTROL_MOD_MODE__B 7 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__W 1 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__M 0x80 +#define ATV_TOP_MOD_CONTROL_MOD_MODE__PRE 0x80 +#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE 0x0 +#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL 0x80 + +#define ATV_TOP_MOD_CONTROL_MOD_TH__B 8 +#define ATV_TOP_MOD_CONTROL_MOD_TH__W 4 +#define ATV_TOP_MOD_CONTROL_MOD_TH__M 0xF00 +#define ATV_TOP_MOD_CONTROL_MOD_TH__PRE 0x500 +#define ATV_TOP_MOD_CONTROL_MOD_TH_MN 0x500 +#define ATV_TOP_MOD_CONTROL_MOD_TH_FM 0x0 + +#define ATV_TOP_STD__A 0xC1001A +#define ATV_TOP_STD__W 2 +#define ATV_TOP_STD__M 0x3 +#define ATV_TOP_STD__PRE 0x0 + +#define ATV_TOP_STD_MODE__B 0 +#define ATV_TOP_STD_MODE__W 1 +#define ATV_TOP_STD_MODE__M 0x1 +#define ATV_TOP_STD_MODE__PRE 0x0 +#define ATV_TOP_STD_MODE_MN 0x0 +#define ATV_TOP_STD_MODE_FM 0x1 + +#define ATV_TOP_STD_VID_POL__B 1 +#define ATV_TOP_STD_VID_POL__W 1 +#define ATV_TOP_STD_VID_POL__M 0x2 +#define ATV_TOP_STD_VID_POL__PRE 0x0 +#define ATV_TOP_STD_VID_POL_NEG 0x0 +#define ATV_TOP_STD_VID_POL_POS 0x2 + +#define ATV_TOP_VID_AMP__A 0xC1001B +#define ATV_TOP_VID_AMP__W 12 +#define ATV_TOP_VID_AMP__M 0xFFF +#define ATV_TOP_VID_AMP__PRE 0x380 +#define ATV_TOP_VID_AMP_MN 0x380 +#define ATV_TOP_VID_AMP_FM 0x0 + +#define ATV_TOP_VID_PEAK__A 0xC1001C +#define ATV_TOP_VID_PEAK__W 5 +#define ATV_TOP_VID_PEAK__M 0x1F +#define ATV_TOP_VID_PEAK__PRE 0x1 + +#define ATV_TOP_FAGC_TH__A 0xC1001D +#define ATV_TOP_FAGC_TH__W 11 +#define ATV_TOP_FAGC_TH__M 0x7FF +#define ATV_TOP_FAGC_TH__PRE 0x2B2 +#define ATV_TOP_FAGC_TH_MN 0x2B2 + +#define ATV_TOP_SYNC_SLICE__A 0xC1001E +#define ATV_TOP_SYNC_SLICE__W 11 +#define ATV_TOP_SYNC_SLICE__M 0x7FF +#define ATV_TOP_SYNC_SLICE__PRE 0x243 +#define ATV_TOP_SYNC_SLICE_MN 0x243 + +#define ATV_TOP_SIF_GAIN__A 0xC1001F +#define ATV_TOP_SIF_GAIN__W 11 +#define ATV_TOP_SIF_GAIN__M 0x7FF +#define ATV_TOP_SIF_GAIN__PRE 0x0 + +#define ATV_TOP_SIF_TP__A 0xC10020 +#define ATV_TOP_SIF_TP__W 6 +#define ATV_TOP_SIF_TP__M 0x3F +#define ATV_TOP_SIF_TP__PRE 0x0 + +#define ATV_TOP_MOD_ACCU__A 0xC10021 +#define ATV_TOP_MOD_ACCU__W 10 +#define ATV_TOP_MOD_ACCU__M 0x3FF +#define ATV_TOP_MOD_ACCU__PRE 0x0 + +#define ATV_TOP_CR_FREQ__A 0xC10022 +#define ATV_TOP_CR_FREQ__W 8 +#define ATV_TOP_CR_FREQ__M 0xFF +#define ATV_TOP_CR_FREQ__PRE 0x0 + +#define ATV_TOP_CR_PHAD__A 0xC10023 +#define ATV_TOP_CR_PHAD__W 12 +#define ATV_TOP_CR_PHAD__M 0xFFF +#define ATV_TOP_CR_PHAD__PRE 0x0 + +#define ATV_TOP_AF_SIF_ATT__A 0xC10024 +#define ATV_TOP_AF_SIF_ATT__W 2 +#define ATV_TOP_AF_SIF_ATT__M 0x3 +#define ATV_TOP_AF_SIF_ATT__PRE 0x0 +#define ATV_TOP_AF_SIF_ATT_0DB 0x0 +#define ATV_TOP_AF_SIF_ATT_M3DB 0x1 +#define ATV_TOP_AF_SIF_ATT_M6DB 0x2 +#define ATV_TOP_AF_SIF_ATT_M9DB 0x3 + +#define ATV_TOP_STDBY__A 0xC10025 +#define ATV_TOP_STDBY__W 2 +#define ATV_TOP_STDBY__M 0x3 +#define ATV_TOP_STDBY__PRE 0x1 + +#define ATV_TOP_STDBY_SIF_STDBY__B 0 +#define ATV_TOP_STDBY_SIF_STDBY__W 1 +#define ATV_TOP_STDBY_SIF_STDBY__M 0x1 +#define ATV_TOP_STDBY_SIF_STDBY__PRE 0x1 +#define ATV_TOP_STDBY_SIF_STDBY_ACTIVE 0x0 +#define ATV_TOP_STDBY_SIF_STDBY_STANDBY 0x1 + +#define ATV_TOP_STDBY_CVBS_STDBY__B 1 +#define ATV_TOP_STDBY_CVBS_STDBY__W 1 +#define ATV_TOP_STDBY_CVBS_STDBY__M 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY__PRE 0x0 +#define ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE 0x0 +#define ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2 +#define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0x0 + +#define ATV_TOP_OVERRIDE_SFR__A 0xC10026 +#define ATV_TOP_OVERRIDE_SFR__W 1 +#define ATV_TOP_OVERRIDE_SFR__M 0x1 +#define ATV_TOP_OVERRIDE_SFR__PRE 0x0 +#define ATV_TOP_OVERRIDE_SFR_ACTIVE 0x0 +#define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0x1 + +#define ATV_TOP_SFR_VID_GAIN__A 0xC10027 +#define ATV_TOP_SFR_VID_GAIN__W 16 +#define ATV_TOP_SFR_VID_GAIN__M 0xFFFF +#define ATV_TOP_SFR_VID_GAIN__PRE 0x0 + +#define ATV_TOP_SFR_AGC_RES__A 0xC10028 +#define ATV_TOP_SFR_AGC_RES__W 5 +#define ATV_TOP_SFR_AGC_RES__M 0x1F +#define ATV_TOP_SFR_AGC_RES__PRE 0x0 + +#define ATV_TOP_OVM_COMP__A 0xC10029 +#define ATV_TOP_OVM_COMP__W 12 +#define ATV_TOP_OVM_COMP__M 0xFFF +#define ATV_TOP_OVM_COMP__PRE 0x0 +#define ATV_TOP_OUT_CONF__A 0xC1002A +#define ATV_TOP_OUT_CONF__W 5 +#define ATV_TOP_OUT_CONF__M 0x1F +#define ATV_TOP_OUT_CONF__PRE 0x0 + +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B 0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W 1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M 0x1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED 0x1 + +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M 0x2 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED 0x2 + +#define ATV_TOP_OUT_CONF_SIF20_SIGN__B 2 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__W 1 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__M 0x4 +#define ATV_TOP_OUT_CONF_SIF20_SIGN__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED 0x0 +#define ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED 0x4 + +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__B 3 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__W 1 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__M 0x8 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL 0x0 +#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED 0x8 + +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__B 4 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__W 1 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__M 0x10 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0x0 +#define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0x10 + +#define ATV_AFT_COMM_EXEC__A 0xFF0000 +#define ATV_AFT_COMM_EXEC__W 2 +#define ATV_AFT_COMM_EXEC__M 0x3 +#define ATV_AFT_COMM_EXEC__PRE 0x0 +#define ATV_AFT_COMM_EXEC_STOP 0x0 +#define ATV_AFT_COMM_EXEC_ACTIVE 0x1 +#define ATV_AFT_COMM_EXEC_HOLD 0x2 + +#define ATV_AFT_TST__A 0xFF0010 +#define ATV_AFT_TST__W 4 +#define ATV_AFT_TST__M 0xF +#define ATV_AFT_TST__PRE 0x0 + +#define AUD_COMM_EXEC__A 0x1000000 +#define AUD_COMM_EXEC__W 2 +#define AUD_COMM_EXEC__M 0x3 +#define AUD_COMM_EXEC__PRE 0x0 +#define AUD_COMM_EXEC_STOP 0x0 +#define AUD_COMM_EXEC_ACTIVE 0x1 + +#define AUD_COMM_MB__A 0x1000002 +#define AUD_COMM_MB__W 16 +#define AUD_COMM_MB__M 0xFFFF +#define AUD_COMM_MB__PRE 0x0 + +#define AUD_TOP_COMM_EXEC__A 0x1010000 +#define AUD_TOP_COMM_EXEC__W 2 +#define AUD_TOP_COMM_EXEC__M 0x3 +#define AUD_TOP_COMM_EXEC__PRE 0x0 +#define AUD_TOP_COMM_EXEC_STOP 0x0 +#define AUD_TOP_COMM_EXEC_ACTIVE 0x1 + +#define AUD_TOP_COMM_MB__A 0x1010002 +#define AUD_TOP_COMM_MB__W 16 +#define AUD_TOP_COMM_MB__M 0xFFFF +#define AUD_TOP_COMM_MB__PRE 0x0 + +#define AUD_TOP_COMM_MB_CTL__B 0 +#define AUD_TOP_COMM_MB_CTL__W 1 +#define AUD_TOP_COMM_MB_CTL__M 0x1 +#define AUD_TOP_COMM_MB_CTL__PRE 0x0 +#define AUD_TOP_COMM_MB_CTL_CTR_OFF 0x0 +#define AUD_TOP_COMM_MB_CTL_CTR_ON 0x1 + +#define AUD_TOP_COMM_MB_OBS__B 1 +#define AUD_TOP_COMM_MB_OBS__W 1 +#define AUD_TOP_COMM_MB_OBS__M 0x2 +#define AUD_TOP_COMM_MB_OBS__PRE 0x0 +#define AUD_TOP_COMM_MB_OBS_OBS_OFF 0x0 +#define AUD_TOP_COMM_MB_OBS_OBS_ON 0x2 + +#define AUD_TOP_COMM_MB_MUX_CTRL__B 2 +#define AUD_TOP_COMM_MB_MUX_CTRL__W 4 +#define AUD_TOP_COMM_MB_MUX_CTRL__M 0x3C +#define AUD_TOP_COMM_MB_MUX_CTRL__PRE 0x0 +#define AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO 0x0 +#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS 0x4 +#define AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC 0x8 +#define AUD_TOP_COMM_MB_MUX_CTRL_SAOUT 0xC +#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ 0x10 + +#define AUD_TOP_COMM_MB_MUX_OBS__B 6 +#define AUD_TOP_COMM_MB_MUX_OBS__W 4 +#define AUD_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define AUD_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO 0x0 +#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS 0x40 +#define AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC 0x80 +#define AUD_TOP_COMM_MB_MUX_OBS_SAOUT 0xC0 +#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ 0x100 + +#define AUD_TOP_TR_MDE__A 0x1010010 +#define AUD_TOP_TR_MDE__W 5 +#define AUD_TOP_TR_MDE__M 0x1F +#define AUD_TOP_TR_MDE__PRE 0x18 + +#define AUD_TOP_TR_MDE_FIFO_SIZE__B 0 +#define AUD_TOP_TR_MDE_FIFO_SIZE__W 4 +#define AUD_TOP_TR_MDE_FIFO_SIZE__M 0xF +#define AUD_TOP_TR_MDE_FIFO_SIZE__PRE 0x8 + +#define AUD_TOP_TR_MDE_RD_LOCK__B 4 +#define AUD_TOP_TR_MDE_RD_LOCK__W 1 +#define AUD_TOP_TR_MDE_RD_LOCK__M 0x10 +#define AUD_TOP_TR_MDE_RD_LOCK__PRE 0x10 +#define AUD_TOP_TR_MDE_RD_LOCK_NORMAL 0x0 +#define AUD_TOP_TR_MDE_RD_LOCK_LOCK 0x10 + +#define AUD_TOP_TR_CTR__A 0x1010011 +#define AUD_TOP_TR_CTR__W 4 +#define AUD_TOP_TR_CTR__M 0xF +#define AUD_TOP_TR_CTR__PRE 0x0 + +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__B 0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__W 1 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__M 0x1 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY 0x0 +#define AUD_TOP_TR_CTR_FIFO_RD_RDY_READY 0x1 + +#define AUD_TOP_TR_CTR_FIFO_EMPTY__B 1 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__W 1 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__M 0x2 +#define AUD_TOP_TR_CTR_FIFO_EMPTY__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY 0x0 +#define AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY 0x2 + +#define AUD_TOP_TR_CTR_FIFO_LOCK__B 2 +#define AUD_TOP_TR_CTR_FIFO_LOCK__W 1 +#define AUD_TOP_TR_CTR_FIFO_LOCK__M 0x4 +#define AUD_TOP_TR_CTR_FIFO_LOCK__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED 0x0 +#define AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED 0x4 + +#define AUD_TOP_TR_CTR_FIFO_FULL__B 3 +#define AUD_TOP_TR_CTR_FIFO_FULL__W 1 +#define AUD_TOP_TR_CTR_FIFO_FULL__M 0x8 +#define AUD_TOP_TR_CTR_FIFO_FULL__PRE 0x0 +#define AUD_TOP_TR_CTR_FIFO_FULL_EMPTY 0x0 +#define AUD_TOP_TR_CTR_FIFO_FULL_FULL 0x8 + +#define AUD_TOP_TR_RD_REG__A 0x1010012 +#define AUD_TOP_TR_RD_REG__W 16 +#define AUD_TOP_TR_RD_REG__M 0xFFFF +#define AUD_TOP_TR_RD_REG__PRE 0x0 + +#define AUD_TOP_TR_RD_REG_RESULT__B 0 +#define AUD_TOP_TR_RD_REG_RESULT__W 16 +#define AUD_TOP_TR_RD_REG_RESULT__M 0xFFFF +#define AUD_TOP_TR_RD_REG_RESULT__PRE 0x0 + +#define AUD_TOP_TR_TIMER__A 0x1010013 +#define AUD_TOP_TR_TIMER__W 16 +#define AUD_TOP_TR_TIMER__M 0xFFFF +#define AUD_TOP_TR_TIMER__PRE 0x0 + +#define AUD_TOP_TR_TIMER_CYCLES__B 0 +#define AUD_TOP_TR_TIMER_CYCLES__W 16 +#define AUD_TOP_TR_TIMER_CYCLES__M 0xFFFF +#define AUD_TOP_TR_TIMER_CYCLES__PRE 0x0 + +#define AUD_TOP_DEMOD_TBO_SEL__A 0x1010014 +#define AUD_TOP_DEMOD_TBO_SEL__W 5 +#define AUD_TOP_DEMOD_TBO_SEL__M 0x1F +#define AUD_TOP_DEMOD_TBO_SEL__PRE 0x0 + +#define AUD_DEM_WR_MODUS__A 0x1030030 +#define AUD_DEM_WR_MODUS__W 16 +#define AUD_DEM_WR_MODUS__M 0xFFFF +#define AUD_DEM_WR_MODUS__PRE 0x0 + +#define AUD_DEM_WR_MODUS_MOD_ASS__B 0 +#define AUD_DEM_WR_MODUS_MOD_ASS__W 1 +#define AUD_DEM_WR_MODUS_MOD_ASS__M 0x1 +#define AUD_DEM_WR_MODUS_MOD_ASS__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_ASS_OFF 0x0 +#define AUD_DEM_WR_MODUS_MOD_ASS_ON 0x1 + +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__B 1 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__W 1 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__M 0x2 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE 0x0 +#define AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE 0x2 + +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B 2 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W 1 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M 0x4 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED 0x0 +#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED 0x4 + +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__B 8 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__W 1 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__M 0x100 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL 0x0 +#define AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION 0x100 + +#define AUD_DEM_WR_MODUS_MOD_CM_A__B 9 +#define AUD_DEM_WR_MODUS_MOD_CM_A__W 1 +#define AUD_DEM_WR_MODUS_MOD_CM_A__M 0x200 +#define AUD_DEM_WR_MODUS_MOD_CM_A__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_A_MUTE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_A_NOISE 0x200 + +#define AUD_DEM_WR_MODUS_MOD_CM_B__B 10 +#define AUD_DEM_WR_MODUS_MOD_CM_B__W 1 +#define AUD_DEM_WR_MODUS_MOD_CM_B__M 0x400 +#define AUD_DEM_WR_MODUS_MOD_CM_B__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_B_MUTE 0x0 +#define AUD_DEM_WR_MODUS_MOD_CM_B_NOISE 0x400 + +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__B 11 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__W 1 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__M 0x800 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U 0x0 +#define AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U 0x800 + +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__B 12 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__W 1 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__M 0x1000 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM 0x0 +#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K 0x1000 + +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__B 13 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__W 2 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__M 0x6000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA 0x0 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC 0x2000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ 0x4000 +#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA 0x6000 + +#define AUD_DEM_WR_MODUS_MOD_BTSC__B 15 +#define AUD_DEM_WR_MODUS_MOD_BTSC__W 1 +#define AUD_DEM_WR_MODUS_MOD_BTSC__M 0x8000 +#define AUD_DEM_WR_MODUS_MOD_BTSC__PRE 0x0 +#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO 0x0 +#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP 0x8000 + +#define AUD_DEM_WR_STANDARD_SEL__A 0x1030020 +#define AUD_DEM_WR_STANDARD_SEL__W 16 +#define AUD_DEM_WR_STANDARD_SEL__M 0xFFFF +#define AUD_DEM_WR_STANDARD_SEL__PRE 0x0 + +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__B 0 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__W 12 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__M 0xFFF +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE 0x0 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO 0x1 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA 0x2 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM 0x3 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1 0x4 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2 0x5 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3 0x7 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM 0x8 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM 0x9 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM 0xA +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM 0xB +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO 0x20 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP 0x21 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0x30 +#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0x40 + +#define AUD_DEM_RD_STANDARD_RES__A 0x102007E +#define AUD_DEM_RD_STANDARD_RES__W 16 +#define AUD_DEM_RD_STANDARD_RES__M 0xFFFF +#define AUD_DEM_RD_STANDARD_RES__PRE 0x0 + +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__B 0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__W 16 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__M 0xFFFF +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE 0x0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD 0x0 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM 0x2 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM 0x3 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM 0x4 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM 0x5 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM 0x7 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM 0x8 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM 0x9 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM 0xA +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM 0xB +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO 0x20 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP 0x21 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J 0x30 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO 0x40 +#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE 0x7FF + +#define AUD_DEM_RD_STATUS__A 0x1020200 +#define AUD_DEM_RD_STATUS__W 16 +#define AUD_DEM_RD_STATUS__M 0xFFFF +#define AUD_DEM_RD_STATUS__PRE 0x0 + +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__B 0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__W 1 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__M 0x1 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA 0x0 +#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA 0x1 + +#define AUD_DEM_RD_STATUS_STAT_CARR_A__B 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__W 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__M 0x2 +#define AUD_DEM_RD_STATUS_STAT_CARR_A__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED 0x2 + +#define AUD_DEM_RD_STATUS_STAT_CARR_B__B 2 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__W 1 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__M 0x4 +#define AUD_DEM_RD_STATUS_STAT_CARR_B__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED 0x0 +#define AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED 0x4 + +#define AUD_DEM_RD_STATUS_STAT_NICAM__B 5 +#define AUD_DEM_RD_STATUS_STAT_NICAM__W 1 +#define AUD_DEM_RD_STATUS_STAT_NICAM__M 0x20 +#define AUD_DEM_RD_STATUS_STAT_NICAM__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM 0x0 +#define AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED 0x20 + +#define AUD_DEM_RD_STATUS_STAT_STEREO__B 6 +#define AUD_DEM_RD_STATUS_STAT_STEREO__W 1 +#define AUD_DEM_RD_STATUS_STAT_STEREO__M 0x40 +#define AUD_DEM_RD_STATUS_STAT_STEREO__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO 0x0 +#define AUD_DEM_RD_STATUS_STAT_STEREO_STEREO 0x40 + +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B 7 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W 1 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M 0x80 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM 0x0 +#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM 0x80 + +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B 8 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W 1 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M 0x100 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE 0x0 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP 0x0 +#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP 0x100 + +#define AUD_DEM_RD_STATUS_BAD_NICAM__B 9 +#define AUD_DEM_RD_STATUS_BAD_NICAM__W 1 +#define AUD_DEM_RD_STATUS_BAD_NICAM__M 0x200 +#define AUD_DEM_RD_STATUS_BAD_NICAM__PRE 0x0 +#define AUD_DEM_RD_STATUS_BAD_NICAM_OK 0x0 +#define AUD_DEM_RD_STATUS_BAD_NICAM_BAD 0x200 + +#define AUD_DEM_RD_RDS_ARRAY_CNT__A 0x102020F +#define AUD_DEM_RD_RDS_ARRAY_CNT__W 12 +#define AUD_DEM_RD_RDS_ARRAY_CNT__M 0xFFF +#define AUD_DEM_RD_RDS_ARRAY_CNT__PRE 0x0 + +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B 0 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W 12 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M 0xFFF +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0x0 +#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0xFFF + +#define AUD_DEM_RD_RDS_DATA__A 0x1020210 +#define AUD_DEM_RD_RDS_DATA__W 12 +#define AUD_DEM_RD_RDS_DATA__M 0xFFF +#define AUD_DEM_RD_RDS_DATA__PRE 0x0 + +#define AUD_DSP_WR_FM_PRESC__A 0x105000E +#define AUD_DSP_WR_FM_PRESC__W 16 +#define AUD_DSP_WR_FM_PRESC__M 0xFFFF +#define AUD_DSP_WR_FM_PRESC__PRE 0x0 + +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B 8 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W 8 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M 0xFF00 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE 0x0 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION 0x7F00 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION 0x4800 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION 0x3000 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION 0x2400 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION 0x1800 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0x1300 +#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0x900 + +#define AUD_DSP_WR_NICAM_PRESC__A 0x1050010 +#define AUD_DSP_WR_NICAM_PRESC__W 16 +#define AUD_DSP_WR_NICAM_PRESC__M 0xFFFF +#define AUD_DSP_WR_NICAM_PRESC__PRE 0x0 +#define AUD_DSP_WR_VOLUME__A 0x1050000 +#define AUD_DSP_WR_VOLUME__W 16 +#define AUD_DSP_WR_VOLUME__M 0xFFFF +#define AUD_DSP_WR_VOLUME__PRE 0x0 + +#define AUD_DSP_WR_VOLUME_VOL_MAIN__B 8 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__W 8 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__M 0xFF00 +#define AUD_DSP_WR_VOLUME_VOL_MAIN__PRE 0x0 + +#define AUD_DSP_WR_SRC_I2S_MATR__A 0x1050038 +#define AUD_DSP_WR_SRC_I2S_MATR__W 16 +#define AUD_DSP_WR_SRC_I2S_MATR__M 0xFFFF +#define AUD_DSP_WR_SRC_I2S_MATR__PRE 0x0 + +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B 8 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W 8 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M 0xFF00 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB 0x100 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A 0x300 +#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B 0x400 + +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B 0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W 8 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M 0xFF +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A 0x0 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B 0x10 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO 0x20 +#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO 0x30 + +#define AUD_DSP_WR_AVC__A 0x1050029 +#define AUD_DSP_WR_AVC__W 16 +#define AUD_DSP_WR_AVC__M 0xFFFF +#define AUD_DSP_WR_AVC__PRE 0x0 + +#define AUD_DSP_WR_AVC_AVC_ON__B 14 +#define AUD_DSP_WR_AVC_AVC_ON__W 2 +#define AUD_DSP_WR_AVC_AVC_ON__M 0xC000 +#define AUD_DSP_WR_AVC_AVC_ON__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_ON_OFF 0x0 +#define AUD_DSP_WR_AVC_AVC_ON_ON 0xC000 + +#define AUD_DSP_WR_AVC_AVC_DECAY__B 8 +#define AUD_DSP_WR_AVC_AVC_DECAY__W 4 +#define AUD_DSP_WR_AVC_AVC_DECAY__M 0xF00 +#define AUD_DSP_WR_AVC_AVC_DECAY__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_DECAY_8_SEC 0x800 +#define AUD_DSP_WR_AVC_AVC_DECAY_4_SEC 0x400 +#define AUD_DSP_WR_AVC_AVC_DECAY_2_SEC 0x200 +#define AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC 0x100 + +#define AUD_DSP_WR_AVC_AVC_REF_LEV__B 4 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__W 4 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__M 0xF0 +#define AUD_DSP_WR_AVC_AVC_REF_LEV__PRE 0x0 + +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__B 2 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__W 2 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__M 0xC +#define AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB 0x4 +#define AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB 0x8 + +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__B 0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__W 2 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__M 0x3 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB 0x0 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB 0x1 +#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB 0x3 + +#define AUD_DSP_WR_QPEAK__A 0x105000C +#define AUD_DSP_WR_QPEAK__W 16 +#define AUD_DSP_WR_QPEAK__M 0xFFFF +#define AUD_DSP_WR_QPEAK__PRE 0x0 + +#define AUD_DSP_WR_QPEAK_SRC_QP__B 8 +#define AUD_DSP_WR_QPEAK_SRC_QP__W 8 +#define AUD_DSP_WR_QPEAK_SRC_QP__M 0xFF00 +#define AUD_DSP_WR_QPEAK_SRC_QP__PRE 0x0 +#define AUD_DSP_WR_QPEAK_SRC_QP_MONO 0x0 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB 0x100 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A 0x300 +#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B 0x400 + +#define AUD_DSP_WR_QPEAK_MAT_QP__B 0 +#define AUD_DSP_WR_QPEAK_MAT_QP__W 8 +#define AUD_DSP_WR_QPEAK_MAT_QP__M 0xFF +#define AUD_DSP_WR_QPEAK_MAT_QP__PRE 0x0 +#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A 0x0 +#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B 0x10 +#define AUD_DSP_WR_QPEAK_MAT_QP_STEREO 0x20 +#define AUD_DSP_WR_QPEAK_MAT_QP_MONO 0x30 + +#define AUD_DSP_RD_QPEAK_L__A 0x1040019 +#define AUD_DSP_RD_QPEAK_L__W 16 +#define AUD_DSP_RD_QPEAK_L__M 0xFFFF +#define AUD_DSP_RD_QPEAK_L__PRE 0x0 + +#define AUD_DSP_RD_QPEAK_R__A 0x104001A +#define AUD_DSP_RD_QPEAK_R__W 16 +#define AUD_DSP_RD_QPEAK_R__M 0xFFFF +#define AUD_DSP_RD_QPEAK_R__PRE 0x0 + +#define AUD_DSP_WR_BEEPER__A 0x1050014 +#define AUD_DSP_WR_BEEPER__W 16 +#define AUD_DSP_WR_BEEPER__M 0xFFFF +#define AUD_DSP_WR_BEEPER__PRE 0x0 + +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__B 8 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__W 7 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__M 0x7F00 +#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE 0x0 + +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B 0 +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W 7 +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M 0x7F +#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE 0x0 + +#define AUD_DEM_WR_I2S_CONFIG2__A 0x1030050 +#define AUD_DEM_WR_I2S_CONFIG2__W 16 +#define AUD_DEM_WR_I2S_CONFIG2__M 0xFFFF +#define AUD_DEM_WR_I2S_CONFIG2__PRE 0x0 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B 6 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M 0x40 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED 0x40 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B 4 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M 0x10 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE 0x10 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B 3 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M 0x8 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE 0x8 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B 2 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M 0x4 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH 0x4 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M 0x2 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY 0x2 + +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B 0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W 1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M 0x1 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32 0x0 +#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16 0x1 + +#define AUD_DSP_WR_I2S_OUT_FS__A 0x105002A +#define AUD_DSP_WR_I2S_OUT_FS__W 16 +#define AUD_DSP_WR_I2S_OUT_FS__M 0xFFFF +#define AUD_DSP_WR_I2S_OUT_FS__PRE 0x0 + +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B 0 +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W 16 +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M 0xFFFF +#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE 0x0 + +#define AUD_DSP_WR_AV_SYNC__A 0x105002B +#define AUD_DSP_WR_AV_SYNC__W 16 +#define AUD_DSP_WR_AV_SYNC__M 0xFFFF +#define AUD_DSP_WR_AV_SYNC__PRE 0x0 + +#define AUD_DSP_WR_AV_SYNC_AV_ON__B 15 +#define AUD_DSP_WR_AV_SYNC_AV_ON__W 1 +#define AUD_DSP_WR_AV_SYNC_AV_ON__M 0x8000 +#define AUD_DSP_WR_AV_SYNC_AV_ON__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE 0x8000 + +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B 14 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W 1 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M 0x4000 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC 0x4000 + +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B 0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W 2 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M 0x3 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO 0x0 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM 0x1 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0x2 +#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME 0x3 + +#define AUD_DSP_RD_STATUS2__A 0x104007B +#define AUD_DSP_RD_STATUS2__W 16 +#define AUD_DSP_RD_STATUS2__M 0xFFFF +#define AUD_DSP_RD_STATUS2__PRE 0x0 + +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__B 15 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__W 1 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__M 0x8000 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE 0x0 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC 0x0 +#define AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE 0x8000 + +#define AUD_DSP_RD_XDFP_FW__A 0x104001D +#define AUD_DSP_RD_XDFP_FW__W 16 +#define AUD_DSP_RD_XDFP_FW__M 0xFFFF +#define AUD_DSP_RD_XDFP_FW__PRE 0x344 + +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B 0 +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W 16 +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M 0xFFFF +#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE 0x344 + +#define AUD_DSP_RD_XFP_FW__A 0x10404B8 +#define AUD_DSP_RD_XFP_FW__W 16 +#define AUD_DSP_RD_XFP_FW__M 0xFFFF +#define AUD_DSP_RD_XFP_FW__PRE 0x42 + +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__B 0 +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__W 16 +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__M 0xFFFF +#define AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE 0x42 + +#define AUD_DEM_WR_DCO_B_HI__A 0x103009B +#define AUD_DEM_WR_DCO_B_HI__W 16 +#define AUD_DEM_WR_DCO_B_HI__M 0xFFFF +#define AUD_DEM_WR_DCO_B_HI__PRE 0x0 + +#define AUD_DEM_WR_DCO_B_LO__A 0x1030093 +#define AUD_DEM_WR_DCO_B_LO__W 16 +#define AUD_DEM_WR_DCO_B_LO__M 0xFFFF +#define AUD_DEM_WR_DCO_B_LO__PRE 0x0 + +#define AUD_DEM_WR_DCO_A_HI__A 0x10300AB +#define AUD_DEM_WR_DCO_A_HI__W 16 +#define AUD_DEM_WR_DCO_A_HI__M 0xFFFF +#define AUD_DEM_WR_DCO_A_HI__PRE 0x0 + +#define AUD_DEM_WR_DCO_A_LO__A 0x10300A3 +#define AUD_DEM_WR_DCO_A_LO__W 16 +#define AUD_DEM_WR_DCO_A_LO__M 0xFFFF +#define AUD_DEM_WR_DCO_A_LO__PRE 0x0 +#define AUD_DEM_WR_NICAM_THRSHLD__A 0x1030021 +#define AUD_DEM_WR_NICAM_THRSHLD__W 16 +#define AUD_DEM_WR_NICAM_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_NICAM_THRSHLD__PRE 0x2BC + +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B 0 +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W 12 +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M 0xFFF +#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE 0x2BC + +#define AUD_DEM_WR_A2_THRSHLD__A 0x1030022 +#define AUD_DEM_WR_A2_THRSHLD__W 16 +#define AUD_DEM_WR_A2_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_A2_THRSHLD__PRE 0x190 + +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__B 0 +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__W 12 +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__M 0xFFF +#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE 0x190 + +#define AUD_DEM_WR_BTSC_THRSHLD__A 0x1030023 +#define AUD_DEM_WR_BTSC_THRSHLD__W 16 +#define AUD_DEM_WR_BTSC_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_BTSC_THRSHLD__PRE 0xC + +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B 0 +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W 12 +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M 0xFFF +#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE 0xC + +#define AUD_DEM_WR_CM_A_THRSHLD__A 0x1030024 +#define AUD_DEM_WR_CM_A_THRSHLD__W 16 +#define AUD_DEM_WR_CM_A_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_CM_A_THRSHLD__PRE 0x2A + +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B 0 +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W 12 +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M 0xFFF +#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE 0x2A + +#define AUD_DEM_WR_CM_B_THRSHLD__A 0x1030025 +#define AUD_DEM_WR_CM_B_THRSHLD__W 16 +#define AUD_DEM_WR_CM_B_THRSHLD__M 0xFFFF +#define AUD_DEM_WR_CM_B_THRSHLD__PRE 0x2A + +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B 0 +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W 12 +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M 0xFFF +#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE 0x2A + +#define AUD_DEM_RD_NIC_C_AD_BITS__A 0x1020023 +#define AUD_DEM_RD_NIC_C_AD_BITS__W 16 +#define AUD_DEM_RD_NIC_C_AD_BITS__M 0xFFFF +#define AUD_DEM_RD_NIC_C_AD_BITS__PRE 0x0 + +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B 0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W 1 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M 0x1 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE 0x0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED 0x0 +#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED 0x1 + +#define AUD_DEM_RD_NIC_C_AD_BITS_C__B 1 +#define AUD_DEM_RD_NIC_C_AD_BITS_C__W 4 +#define AUD_DEM_RD_NIC_C_AD_BITS_C__M 0x1E +#define AUD_DEM_RD_NIC_C_AD_BITS_C__PRE 0x0 + +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B 5 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W 3 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M 0xE0 +#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE 0x0 + +#define AUD_DEM_RD_NIC_ADD_BITS_HI__A 0x1020038 +#define AUD_DEM_RD_NIC_ADD_BITS_HI__W 16 +#define AUD_DEM_RD_NIC_ADD_BITS_HI__M 0xFFFF +#define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE 0x0 + +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B 0 +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W 8 +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M 0xFF +#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB__A 0x1020038 +#define AUD_DEM_RD_NIC_CIB__W 16 +#define AUD_DEM_RD_NIC_CIB__M 0xFFFF +#define AUD_DEM_RD_NIC_CIB__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB_CIB2__B 0 +#define AUD_DEM_RD_NIC_CIB_CIB2__W 1 +#define AUD_DEM_RD_NIC_CIB_CIB2__M 0x1 +#define AUD_DEM_RD_NIC_CIB_CIB2__PRE 0x0 + +#define AUD_DEM_RD_NIC_CIB_CIB1__B 1 +#define AUD_DEM_RD_NIC_CIB_CIB1__W 1 +#define AUD_DEM_RD_NIC_CIB_CIB1__M 0x2 +#define AUD_DEM_RD_NIC_CIB_CIB1__PRE 0x0 + +#define AUD_DEM_RD_NIC_ERROR_RATE__A 0x1020057 +#define AUD_DEM_RD_NIC_ERROR_RATE__W 16 +#define AUD_DEM_RD_NIC_ERROR_RATE__M 0xFFFF +#define AUD_DEM_RD_NIC_ERROR_RATE__PRE 0x0 + +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B 0 +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W 12 +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M 0xFFF +#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE 0x0 + +#define AUD_DEM_WR_FM_DEEMPH__A 0x103000F +#define AUD_DEM_WR_FM_DEEMPH__W 16 +#define AUD_DEM_WR_FM_DEEMPH__M 0xFFFF +#define AUD_DEM_WR_FM_DEEMPH__PRE 0x0 +#define AUD_DEM_WR_FM_DEEMPH_50US 0x0 +#define AUD_DEM_WR_FM_DEEMPH_75US 0x1 +#define AUD_DEM_WR_FM_DEEMPH_OFF 0x3F + +#define AUD_DEM_WR_FM_MATRIX__A 0x103006F +#define AUD_DEM_WR_FM_MATRIX__W 16 +#define AUD_DEM_WR_FM_MATRIX__M 0xFFFF +#define AUD_DEM_WR_FM_MATRIX__PRE 0x0 +#define AUD_DEM_WR_FM_MATRIX_NO_MATRIX 0x0 +#define AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX 0x1 +#define AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX 0x2 +#define AUD_DEM_WR_FM_MATRIX_SOUND_A 0x3 +#define AUD_DEM_WR_FM_MATRIX_SOUND_B 0x4 + +#define AUD_DSP_RD_FM_IDENT_VALUE__A 0x1040018 +#define AUD_DSP_RD_FM_IDENT_VALUE__W 16 +#define AUD_DSP_RD_FM_IDENT_VALUE__M 0xFFFF +#define AUD_DSP_RD_FM_IDENT_VALUE__PRE 0x0 + +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B 8 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W 8 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M 0xFF00 +#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_A__A 0x104001B +#define AUD_DSP_RD_FM_DC_LEVEL_A__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_A__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_A__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B 0 +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_B__A 0x104001C +#define AUD_DSP_RD_FM_DC_LEVEL_B__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_B__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_B__PRE 0x0 + +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B 0 +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W 16 +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M 0xFFFF +#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE 0x0 + +#define AUD_DEM_WR_FM_DC_NOTCH_SW__A 0x1030017 +#define AUD_DEM_WR_FM_DC_NOTCH_SW__W 16 +#define AUD_DEM_WR_FM_DC_NOTCH_SW__M 0xFFFF +#define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE 0x0 + +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B 0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W 16 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M 0xFFFF +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE 0x0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON 0x0 +#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF 0x3F + +#define AUD_DSP_WR_SYNC_OUT__A 0x1050026 +#define AUD_DSP_WR_SYNC_OUT__W 16 +#define AUD_DSP_WR_SYNC_OUT__M 0xFFFF +#define AUD_DSP_WR_SYNC_OUT__PRE 0x0 +#define AUD_DSP_WR_SYNC_OUT_OFF 0x0 +#define AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS 0x1 + +#define AUD_XFP_DRAM_1K__A 0x1060000 +#define AUD_XFP_DRAM_1K__W 16 +#define AUD_XFP_DRAM_1K__M 0xFFFF +#define AUD_XFP_DRAM_1K__PRE 0x0 +#define AUD_XFP_DRAM_1K_D__B 0 +#define AUD_XFP_DRAM_1K_D__W 16 +#define AUD_XFP_DRAM_1K_D__M 0xFFFF +#define AUD_XFP_DRAM_1K_D__PRE 0x0 + +#define AUD_XFP_PRAM_4K__A 0x1070000 +#define AUD_XFP_PRAM_4K__W 16 +#define AUD_XFP_PRAM_4K__M 0xFFFF +#define AUD_XFP_PRAM_4K__PRE 0x0 +#define AUD_XFP_PRAM_4K_D__B 0 +#define AUD_XFP_PRAM_4K_D__W 16 +#define AUD_XFP_PRAM_4K_D__M 0xFFFF +#define AUD_XFP_PRAM_4K_D__PRE 0x0 + +#define AUD_XDFP_DRAM_1K__A 0x1080000 +#define AUD_XDFP_DRAM_1K__W 16 +#define AUD_XDFP_DRAM_1K__M 0xFFFF +#define AUD_XDFP_DRAM_1K__PRE 0x0 +#define AUD_XDFP_DRAM_1K_D__B 0 +#define AUD_XDFP_DRAM_1K_D__W 16 +#define AUD_XDFP_DRAM_1K_D__M 0xFFFF +#define AUD_XDFP_DRAM_1K_D__PRE 0x0 + +#define AUD_XDFP_PRAM_4K__A 0x1090000 +#define AUD_XDFP_PRAM_4K__W 16 +#define AUD_XDFP_PRAM_4K__M 0xFFFF +#define AUD_XDFP_PRAM_4K__PRE 0x0 +#define AUD_XDFP_PRAM_4K_D__B 0 +#define AUD_XDFP_PRAM_4K_D__W 16 +#define AUD_XDFP_PRAM_4K_D__M 0xFFFF +#define AUD_XDFP_PRAM_4K_D__PRE 0x0 + +#define FEC_COMM_EXEC__A 0x2400000 +#define FEC_COMM_EXEC__W 2 +#define FEC_COMM_EXEC__M 0x3 +#define FEC_COMM_EXEC__PRE 0x0 +#define FEC_COMM_EXEC_STOP 0x0 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_HOLD 0x2 + +#define FEC_COMM_MB__A 0x2400002 +#define FEC_COMM_MB__W 16 +#define FEC_COMM_MB__M 0xFFFF +#define FEC_COMM_MB__PRE 0x0 +#define FEC_COMM_INT_REQ__A 0x2400003 +#define FEC_COMM_INT_REQ__W 16 +#define FEC_COMM_INT_REQ__M 0xFFFF +#define FEC_COMM_INT_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_OC_REQ__B 0 +#define FEC_COMM_INT_REQ_OC_REQ__W 1 +#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 +#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_RS_REQ__B 1 +#define FEC_COMM_INT_REQ_RS_REQ__W 1 +#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 +#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_DI_REQ__B 2 +#define FEC_COMM_INT_REQ_DI_REQ__W 1 +#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 +#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 + +#define FEC_COMM_INT_STA__A 0x2400005 +#define FEC_COMM_INT_STA__W 16 +#define FEC_COMM_INT_STA__M 0xFFFF +#define FEC_COMM_INT_STA__PRE 0x0 +#define FEC_COMM_INT_MSK__A 0x2400006 +#define FEC_COMM_INT_MSK__W 16 +#define FEC_COMM_INT_MSK__M 0xFFFF +#define FEC_COMM_INT_MSK__PRE 0x0 +#define FEC_COMM_INT_STM__A 0x2400007 +#define FEC_COMM_INT_STM__W 16 +#define FEC_COMM_INT_STM__M 0xFFFF +#define FEC_COMM_INT_STM__PRE 0x0 + +#define FEC_TOP_COMM_EXEC__A 0x2410000 +#define FEC_TOP_COMM_EXEC__W 2 +#define FEC_TOP_COMM_EXEC__M 0x3 +#define FEC_TOP_COMM_EXEC__PRE 0x0 +#define FEC_TOP_COMM_EXEC_STOP 0x0 +#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 +#define FEC_TOP_COMM_EXEC_HOLD 0x2 + +#define FEC_TOP_ANNEX__A 0x2410010 +#define FEC_TOP_ANNEX__W 2 +#define FEC_TOP_ANNEX__M 0x3 +#define FEC_TOP_ANNEX__PRE 0x0 +#define FEC_TOP_ANNEX_A 0x0 +#define FEC_TOP_ANNEX_B 0x1 +#define FEC_TOP_ANNEX_C 0x2 +#define FEC_TOP_ANNEX_D 0x3 + +#define FEC_DI_COMM_EXEC__A 0x2420000 +#define FEC_DI_COMM_EXEC__W 2 +#define FEC_DI_COMM_EXEC__M 0x3 +#define FEC_DI_COMM_EXEC__PRE 0x0 +#define FEC_DI_COMM_EXEC_STOP 0x0 +#define FEC_DI_COMM_EXEC_ACTIVE 0x1 +#define FEC_DI_COMM_EXEC_HOLD 0x2 + +#define FEC_DI_COMM_MB__A 0x2420002 +#define FEC_DI_COMM_MB__W 2 +#define FEC_DI_COMM_MB__M 0x3 +#define FEC_DI_COMM_MB__PRE 0x0 +#define FEC_DI_COMM_MB_CTL__B 0 +#define FEC_DI_COMM_MB_CTL__W 1 +#define FEC_DI_COMM_MB_CTL__M 0x1 +#define FEC_DI_COMM_MB_CTL__PRE 0x0 +#define FEC_DI_COMM_MB_CTL_OFF 0x0 +#define FEC_DI_COMM_MB_CTL_ON 0x1 +#define FEC_DI_COMM_MB_OBS__B 1 +#define FEC_DI_COMM_MB_OBS__W 1 +#define FEC_DI_COMM_MB_OBS__M 0x2 +#define FEC_DI_COMM_MB_OBS__PRE 0x0 +#define FEC_DI_COMM_MB_OBS_OFF 0x0 +#define FEC_DI_COMM_MB_OBS_ON 0x2 + +#define FEC_DI_COMM_INT_REQ__A 0x2420003 +#define FEC_DI_COMM_INT_REQ__W 1 +#define FEC_DI_COMM_INT_REQ__M 0x1 +#define FEC_DI_COMM_INT_REQ__PRE 0x0 +#define FEC_DI_COMM_INT_STA__A 0x2420005 +#define FEC_DI_COMM_INT_STA__W 2 +#define FEC_DI_COMM_INT_STA__M 0x3 +#define FEC_DI_COMM_INT_STA__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_MSK__A 0x2420006 +#define FEC_DI_COMM_INT_MSK__W 2 +#define FEC_DI_COMM_INT_MSK__M 0x3 +#define FEC_DI_COMM_INT_MSK__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STM__A 0x2420007 +#define FEC_DI_COMM_INT_STM__W 2 +#define FEC_DI_COMM_INT_STM__M 0x3 +#define FEC_DI_COMM_INT_STM__PRE 0x0 +#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_STATUS__A 0x2420010 +#define FEC_DI_STATUS__W 1 +#define FEC_DI_STATUS__M 0x1 +#define FEC_DI_STATUS__PRE 0x0 +#define FEC_DI_MODE__A 0x2420011 +#define FEC_DI_MODE__W 3 +#define FEC_DI_MODE__M 0x7 +#define FEC_DI_MODE__PRE 0x0 + +#define FEC_DI_MODE_NO_SYNC__B 0 +#define FEC_DI_MODE_NO_SYNC__W 1 +#define FEC_DI_MODE_NO_SYNC__M 0x1 +#define FEC_DI_MODE_NO_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 +#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 +#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 +#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 + +#define FEC_DI_CONTROL_WORD__A 0x2420012 +#define FEC_DI_CONTROL_WORD__W 4 +#define FEC_DI_CONTROL_WORD__M 0xF +#define FEC_DI_CONTROL_WORD__PRE 0x0 + +#define FEC_DI_RESTART__A 0x2420013 +#define FEC_DI_RESTART__W 1 +#define FEC_DI_RESTART__M 0x1 +#define FEC_DI_RESTART__PRE 0x0 + +#define FEC_DI_TIMEOUT_LO__A 0x2420014 +#define FEC_DI_TIMEOUT_LO__W 16 +#define FEC_DI_TIMEOUT_LO__M 0xFFFF +#define FEC_DI_TIMEOUT_LO__PRE 0x0 + +#define FEC_DI_TIMEOUT_HI__A 0x2420015 +#define FEC_DI_TIMEOUT_HI__W 8 +#define FEC_DI_TIMEOUT_HI__M 0xFF +#define FEC_DI_TIMEOUT_HI__PRE 0xA + +#define FEC_RS_COMM_EXEC__A 0x2430000 +#define FEC_RS_COMM_EXEC__W 2 +#define FEC_RS_COMM_EXEC__M 0x3 +#define FEC_RS_COMM_EXEC__PRE 0x0 +#define FEC_RS_COMM_EXEC_STOP 0x0 +#define FEC_RS_COMM_EXEC_ACTIVE 0x1 +#define FEC_RS_COMM_EXEC_HOLD 0x2 + +#define FEC_RS_COMM_MB__A 0x2430002 +#define FEC_RS_COMM_MB__W 2 +#define FEC_RS_COMM_MB__M 0x3 +#define FEC_RS_COMM_MB__PRE 0x0 +#define FEC_RS_COMM_MB_CTL__B 0 +#define FEC_RS_COMM_MB_CTL__W 1 +#define FEC_RS_COMM_MB_CTL__M 0x1 +#define FEC_RS_COMM_MB_CTL__PRE 0x0 +#define FEC_RS_COMM_MB_CTL_OFF 0x0 +#define FEC_RS_COMM_MB_CTL_ON 0x1 +#define FEC_RS_COMM_MB_OBS__B 1 +#define FEC_RS_COMM_MB_OBS__W 1 +#define FEC_RS_COMM_MB_OBS__M 0x2 +#define FEC_RS_COMM_MB_OBS__PRE 0x0 +#define FEC_RS_COMM_MB_OBS_OFF 0x0 +#define FEC_RS_COMM_MB_OBS_ON 0x2 + +#define FEC_RS_COMM_INT_REQ__A 0x2430003 +#define FEC_RS_COMM_INT_REQ__W 1 +#define FEC_RS_COMM_INT_REQ__M 0x1 +#define FEC_RS_COMM_INT_REQ__PRE 0x0 +#define FEC_RS_COMM_INT_STA__A 0x2430005 +#define FEC_RS_COMM_INT_STA__W 2 +#define FEC_RS_COMM_INT_STA__M 0x3 +#define FEC_RS_COMM_INT_STA__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_MSK__A 0x2430006 +#define FEC_RS_COMM_INT_MSK__W 2 +#define FEC_RS_COMM_INT_MSK__M 0x3 +#define FEC_RS_COMM_INT_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_COMM_INT_STM__A 0x2430007 +#define FEC_RS_COMM_INT_STM__W 2 +#define FEC_RS_COMM_INT_STM__M 0x3 +#define FEC_RS_COMM_INT_STM__PRE 0x0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_STATUS__A 0x2430010 +#define FEC_RS_STATUS__W 1 +#define FEC_RS_STATUS__M 0x1 +#define FEC_RS_STATUS__PRE 0x0 +#define FEC_RS_MODE__A 0x2430011 +#define FEC_RS_MODE__W 1 +#define FEC_RS_MODE__M 0x1 +#define FEC_RS_MODE__PRE 0x0 + +#define FEC_RS_MODE_BYPASS__B 0 +#define FEC_RS_MODE_BYPASS__W 1 +#define FEC_RS_MODE_BYPASS__M 0x1 +#define FEC_RS_MODE_BYPASS__PRE 0x0 + +#define FEC_RS_MEASUREMENT_PERIOD__A 0x2430012 +#define FEC_RS_MEASUREMENT_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x1171 + +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x2430013 +#define FEC_RS_MEASUREMENT_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 + +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 + +#define FEC_RS_NR_BIT_ERRORS__A 0x2430014 +#define FEC_RS_NR_BIT_ERRORS__W 16 +#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF +#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 +#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 +#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_SYMBOL_ERRORS__A 0x2430015 +#define FEC_RS_NR_SYMBOL_ERRORS__W 16 +#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF +#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_PACKET_ERRORS__A 0x2430016 +#define FEC_RS_NR_PACKET_ERRORS__W 16 +#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF +#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 +#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 +#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_FAILURES__A 0x2430017 +#define FEC_RS_NR_FAILURES__W 16 +#define FEC_RS_NR_FAILURES__M 0xFFFF +#define FEC_RS_NR_FAILURES__PRE 0x0 + +#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 +#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 +#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 + +#define FEC_RS_NR_FAILURES_EXP__B 12 +#define FEC_RS_NR_FAILURES_EXP__W 4 +#define FEC_RS_NR_FAILURES_EXP__M 0xF000 +#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 + +#define FEC_OC_COMM_EXEC__A 0x2440000 +#define FEC_OC_COMM_EXEC__W 2 +#define FEC_OC_COMM_EXEC__M 0x3 +#define FEC_OC_COMM_EXEC__PRE 0x0 +#define FEC_OC_COMM_EXEC_STOP 0x0 +#define FEC_OC_COMM_EXEC_ACTIVE 0x1 +#define FEC_OC_COMM_EXEC_HOLD 0x2 + +#define FEC_OC_COMM_MB__A 0x2440002 +#define FEC_OC_COMM_MB__W 2 +#define FEC_OC_COMM_MB__M 0x3 +#define FEC_OC_COMM_MB__PRE 0x0 +#define FEC_OC_COMM_MB_CTL__B 0 +#define FEC_OC_COMM_MB_CTL__W 1 +#define FEC_OC_COMM_MB_CTL__M 0x1 +#define FEC_OC_COMM_MB_CTL__PRE 0x0 +#define FEC_OC_COMM_MB_CTL_OFF 0x0 +#define FEC_OC_COMM_MB_CTL_ON 0x1 +#define FEC_OC_COMM_MB_OBS__B 1 +#define FEC_OC_COMM_MB_OBS__W 1 +#define FEC_OC_COMM_MB_OBS__M 0x2 +#define FEC_OC_COMM_MB_OBS__PRE 0x0 +#define FEC_OC_COMM_MB_OBS_OFF 0x0 +#define FEC_OC_COMM_MB_OBS_ON 0x2 + +#define FEC_OC_COMM_INT_REQ__A 0x2440003 +#define FEC_OC_COMM_INT_REQ__W 1 +#define FEC_OC_COMM_INT_REQ__M 0x1 +#define FEC_OC_COMM_INT_REQ__PRE 0x0 +#define FEC_OC_COMM_INT_STA__A 0x2440005 +#define FEC_OC_COMM_INT_STA__W 8 +#define FEC_OC_COMM_INT_STA__M 0xFF +#define FEC_OC_COMM_INT_STA__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_MSK__A 0x2440006 +#define FEC_OC_COMM_INT_MSK__W 8 +#define FEC_OC_COMM_INT_MSK__M 0xFF +#define FEC_OC_COMM_INT_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_COMM_INT_STM__A 0x2440007 +#define FEC_OC_COMM_INT_STM__W 8 +#define FEC_OC_COMM_INT_STM__M 0xFF +#define FEC_OC_COMM_INT_STM__PRE 0x0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_STATUS__A 0x2440010 +#define FEC_OC_STATUS__W 5 +#define FEC_OC_STATUS__M 0x1F +#define FEC_OC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_DPR_STATUS__B 0 +#define FEC_OC_STATUS_DPR_STATUS__W 1 +#define FEC_OC_STATUS_DPR_STATUS__M 0x1 +#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_SNC_STATUS__B 1 +#define FEC_OC_STATUS_SNC_STATUS__W 2 +#define FEC_OC_STATUS_SNC_STATUS__M 0x6 +#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_FULL__B 3 +#define FEC_OC_STATUS_FIFO_FULL__W 1 +#define FEC_OC_STATUS_FIFO_FULL__M 0x8 +#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_EMPTY__B 4 +#define FEC_OC_STATUS_FIFO_EMPTY__W 1 +#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 +#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 + +#define FEC_OC_MODE__A 0x2440011 +#define FEC_OC_MODE__W 4 +#define FEC_OC_MODE__M 0xF +#define FEC_OC_MODE__PRE 0x0 + +#define FEC_OC_MODE_PARITY__B 0 +#define FEC_OC_MODE_PARITY__W 1 +#define FEC_OC_MODE_PARITY__M 0x1 +#define FEC_OC_MODE_PARITY__PRE 0x0 + +#define FEC_OC_MODE_TRANSPARENT__B 1 +#define FEC_OC_MODE_TRANSPARENT__W 1 +#define FEC_OC_MODE_TRANSPARENT__M 0x2 +#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 + +#define FEC_OC_MODE_CLEAR__B 2 +#define FEC_OC_MODE_CLEAR__W 1 +#define FEC_OC_MODE_CLEAR__M 0x4 +#define FEC_OC_MODE_CLEAR__PRE 0x0 + +#define FEC_OC_MODE_RETAIN_FRAMING__B 3 +#define FEC_OC_MODE_RETAIN_FRAMING__W 1 +#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 +#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 + +#define FEC_OC_DPR_MODE__A 0x2440012 +#define FEC_OC_DPR_MODE__W 2 +#define FEC_OC_DPR_MODE__M 0x3 +#define FEC_OC_DPR_MODE__PRE 0x0 + +#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 +#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 + +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 + +#define FEC_OC_DPR_UNLOCK__A 0x2440013 +#define FEC_OC_DPR_UNLOCK__W 1 +#define FEC_OC_DPR_UNLOCK__M 0x1 +#define FEC_OC_DPR_UNLOCK__PRE 0x0 +#define FEC_OC_DTO_MODE__A 0x2440014 +#define FEC_OC_DTO_MODE__W 3 +#define FEC_OC_DTO_MODE__M 0x7 +#define FEC_OC_DTO_MODE__PRE 0x0 + +#define FEC_OC_DTO_MODE_DYNAMIC__B 0 +#define FEC_OC_DTO_MODE_DYNAMIC__W 1 +#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 + +#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 + +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 + +#define FEC_OC_DTO_PERIOD__A 0x2440015 +#define FEC_OC_DTO_PERIOD__W 8 +#define FEC_OC_DTO_PERIOD__M 0xFF +#define FEC_OC_DTO_PERIOD__PRE 0x0 +#define FEC_OC_DTO_RATE_LO__A 0x2440016 +#define FEC_OC_DTO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 +#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_HI__A 0x2440017 +#define FEC_OC_DTO_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 +#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_BURST_LEN__A 0x2440018 +#define FEC_OC_DTO_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN__PRE 0xBC + +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC + +#define FEC_OC_FCT_MODE__A 0x244001A +#define FEC_OC_FCT_MODE__W 2 +#define FEC_OC_FCT_MODE__M 0x3 +#define FEC_OC_FCT_MODE__PRE 0x0 + +#define FEC_OC_FCT_MODE_RAT_ENA__B 0 +#define FEC_OC_FCT_MODE_RAT_ENA__W 1 +#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 + +#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 + +#define FEC_OC_FCT_USAGE__A 0x244001B +#define FEC_OC_FCT_USAGE__W 3 +#define FEC_OC_FCT_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE__PRE 0x2 + +#define FEC_OC_FCT_USAGE_USAGE__B 0 +#define FEC_OC_FCT_USAGE_USAGE__W 3 +#define FEC_OC_FCT_USAGE_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE_USAGE__PRE 0x2 + +#define FEC_OC_FCT_OCCUPATION__A 0x244001C +#define FEC_OC_FCT_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION__PRE 0x0 + +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 + +#define FEC_OC_TMD_MODE__A 0x244001E +#define FEC_OC_TMD_MODE__W 3 +#define FEC_OC_TMD_MODE__M 0x7 +#define FEC_OC_TMD_MODE__PRE 0x4 + +#define FEC_OC_TMD_MODE_MODE__B 0 +#define FEC_OC_TMD_MODE_MODE__W 3 +#define FEC_OC_TMD_MODE_MODE__M 0x7 +#define FEC_OC_TMD_MODE_MODE__PRE 0x4 + +#define FEC_OC_TMD_COUNT__A 0x244001F +#define FEC_OC_TMD_COUNT__W 10 +#define FEC_OC_TMD_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_COUNT_COUNT__B 0 +#define FEC_OC_TMD_COUNT_COUNT__W 10 +#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_HI_MARGIN__A 0x2440020 +#define FEC_OC_TMD_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN__PRE 0x200 + +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x200 + +#define FEC_OC_TMD_LO_MARGIN__A 0x2440021 +#define FEC_OC_TMD_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN__PRE 0x100 + +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x100 + +#define FEC_OC_TMD_CTL_UPD_RATE__A 0x2440022 +#define FEC_OC_TMD_CTL_UPD_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 + +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 + +#define FEC_OC_TMD_INT_UPD_RATE__A 0x2440023 +#define FEC_OC_TMD_INT_UPD_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 + +#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 + +#define FEC_OC_AVR_PARM_A__A 0x2440026 +#define FEC_OC_AVR_PARM_A__W 4 +#define FEC_OC_AVR_PARM_A__M 0xF +#define FEC_OC_AVR_PARM_A__PRE 0x6 + +#define FEC_OC_AVR_PARM_A_PARM__B 0 +#define FEC_OC_AVR_PARM_A_PARM__W 4 +#define FEC_OC_AVR_PARM_A_PARM__M 0xF +#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 + +#define FEC_OC_AVR_PARM_B__A 0x2440027 +#define FEC_OC_AVR_PARM_B__W 4 +#define FEC_OC_AVR_PARM_B__M 0xF +#define FEC_OC_AVR_PARM_B__PRE 0x4 + +#define FEC_OC_AVR_PARM_B_PARM__B 0 +#define FEC_OC_AVR_PARM_B_PARM__W 4 +#define FEC_OC_AVR_PARM_B_PARM__M 0xF +#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 + +#define FEC_OC_AVR_AVG_LO__A 0x2440028 +#define FEC_OC_AVR_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 +#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI__A 0x2440029 +#define FEC_OC_AVR_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 +#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 + +#define FEC_OC_RCN_MODE__A 0x244002C +#define FEC_OC_RCN_MODE__W 5 +#define FEC_OC_RCN_MODE__M 0x1F +#define FEC_OC_RCN_MODE__PRE 0x1F + +#define FEC_OC_RCN_MODE_MODE__B 0 +#define FEC_OC_RCN_MODE_MODE__W 5 +#define FEC_OC_RCN_MODE_MODE__M 0x1F +#define FEC_OC_RCN_MODE_MODE__PRE 0x1F + +#define FEC_OC_RCN_OCC_SETTLE__A 0x244002D +#define FEC_OC_RCN_OCC_SETTLE__W 11 +#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE__PRE 0x180 + +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x180 + +#define FEC_OC_RCN_GAIN__A 0x244002E +#define FEC_OC_RCN_GAIN__W 4 +#define FEC_OC_RCN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN__PRE 0xC + +#define FEC_OC_RCN_GAIN_GAIN__B 0 +#define FEC_OC_RCN_GAIN_GAIN__W 4 +#define FEC_OC_RCN_GAIN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC + +#define FEC_OC_RCN_CTL_RATE_LO__A 0x2440030 +#define FEC_OC_RCN_CTL_RATE_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_HI__A 0x2440031 +#define FEC_OC_RCN_CTL_RATE_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_STEP_LO__A 0x2440032 +#define FEC_OC_RCN_CTL_STEP_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_HI__A 0x2440033 +#define FEC_OC_RCN_CTL_STEP_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 + +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 + +#define FEC_OC_RCN_DTO_OFS_LO__A 0x2440034 +#define FEC_OC_RCN_DTO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI__A 0x2440035 +#define FEC_OC_RCN_DTO_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO__A 0x2440036 +#define FEC_OC_RCN_DTO_RATE_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI__A 0x2440037 +#define FEC_OC_RCN_DTO_RATE_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO__A 0x2440038 +#define FEC_OC_RCN_RATE_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_HI__A 0x2440039 +#define FEC_OC_RCN_RATE_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_DYN_RATE_LO__A 0x244003A +#define FEC_OC_RCN_DYN_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI__A 0x244003B +#define FEC_OC_RCN_DYN_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 + +#define FEC_OC_SNC_MODE__A 0x2440040 +#define FEC_OC_SNC_MODE__W 4 +#define FEC_OC_SNC_MODE__M 0xF +#define FEC_OC_SNC_MODE__PRE 0x0 + +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 +#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 +#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 +#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 + +#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 +#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 +#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 +#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 + +#define FEC_OC_SNC_LWM__A 0x2440041 +#define FEC_OC_SNC_LWM__W 4 +#define FEC_OC_SNC_LWM__M 0xF +#define FEC_OC_SNC_LWM__PRE 0x3 + +#define FEC_OC_SNC_LWM_MARK__B 0 +#define FEC_OC_SNC_LWM_MARK__W 4 +#define FEC_OC_SNC_LWM_MARK__M 0xF +#define FEC_OC_SNC_LWM_MARK__PRE 0x3 + +#define FEC_OC_SNC_HWM__A 0x2440042 +#define FEC_OC_SNC_HWM__W 4 +#define FEC_OC_SNC_HWM__M 0xF +#define FEC_OC_SNC_HWM__PRE 0x5 + +#define FEC_OC_SNC_HWM_MARK__B 0 +#define FEC_OC_SNC_HWM_MARK__W 4 +#define FEC_OC_SNC_HWM_MARK__M 0xF +#define FEC_OC_SNC_HWM_MARK__PRE 0x5 + +#define FEC_OC_SNC_UNLOCK__A 0x2440043 +#define FEC_OC_SNC_UNLOCK__W 1 +#define FEC_OC_SNC_UNLOCK__M 0x1 +#define FEC_OC_SNC_UNLOCK__PRE 0x0 + +#define FEC_OC_SNC_UNLOCK_RESTART__B 0 +#define FEC_OC_SNC_UNLOCK_RESTART__W 1 +#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 +#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT__A 0x2440044 +#define FEC_OC_SNC_LOCK_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT__A 0x2440045 +#define FEC_OC_SNC_FAIL_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_PERIOD__A 0x2440046 +#define FEC_OC_SNC_FAIL_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 + +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_OC_EMS_MODE__A 0x2440047 +#define FEC_OC_EMS_MODE__W 2 +#define FEC_OC_EMS_MODE__M 0x3 +#define FEC_OC_EMS_MODE__PRE 0x0 + +#define FEC_OC_EMS_MODE_MODE__B 0 +#define FEC_OC_EMS_MODE_MODE__W 2 +#define FEC_OC_EMS_MODE_MODE__M 0x3 +#define FEC_OC_EMS_MODE_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE__A 0x2440048 +#define FEC_OC_IPR_MODE__W 12 +#define FEC_OC_IPR_MODE__M 0xFFF +#define FEC_OC_IPR_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE_SERIAL__B 0 +#define FEC_OC_IPR_MODE_SERIAL__W 1 +#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 + +#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT__A 0x2440049 +#define FEC_OC_IPR_INVERT__W 12 +#define FEC_OC_IPR_INVERT__M 0xFFF +#define FEC_OC_IPR_INVERT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD0__B 0 +#define FEC_OC_IPR_INVERT_MD0__W 1 +#define FEC_OC_IPR_INVERT_MD0__M 0x1 +#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD1__B 1 +#define FEC_OC_IPR_INVERT_MD1__W 1 +#define FEC_OC_IPR_INVERT_MD1__M 0x2 +#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD2__B 2 +#define FEC_OC_IPR_INVERT_MD2__W 1 +#define FEC_OC_IPR_INVERT_MD2__M 0x4 +#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD3__B 3 +#define FEC_OC_IPR_INVERT_MD3__W 1 +#define FEC_OC_IPR_INVERT_MD3__M 0x8 +#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD4__B 4 +#define FEC_OC_IPR_INVERT_MD4__W 1 +#define FEC_OC_IPR_INVERT_MD4__M 0x10 +#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD5__B 5 +#define FEC_OC_IPR_INVERT_MD5__W 1 +#define FEC_OC_IPR_INVERT_MD5__M 0x20 +#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD6__B 6 +#define FEC_OC_IPR_INVERT_MD6__W 1 +#define FEC_OC_IPR_INVERT_MD6__M 0x40 +#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD7__B 7 +#define FEC_OC_IPR_INVERT_MD7__W 1 +#define FEC_OC_IPR_INVERT_MD7__M 0x80 +#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MERR__B 8 +#define FEC_OC_IPR_INVERT_MERR__W 1 +#define FEC_OC_IPR_INVERT_MERR__M 0x100 +#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MSTRT__B 9 +#define FEC_OC_IPR_INVERT_MSTRT__W 1 +#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MVAL__B 10 +#define FEC_OC_IPR_INVERT_MVAL__W 1 +#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MCLK__B 11 +#define FEC_OC_IPR_INVERT_MCLK__W 1 +#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 + +#define FEC_OC_OCR_MODE__A 0x2440050 +#define FEC_OC_OCR_MODE__W 4 +#define FEC_OC_OCR_MODE__M 0xF +#define FEC_OC_OCR_MODE__PRE 0x0 + +#define FEC_OC_OCR_MODE_MB_SELECT__B 0 +#define FEC_OC_OCR_MODE_MB_SELECT__W 1 +#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 +#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 +#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 +#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 +#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 + +#define FEC_OC_OCR_RATE__A 0x2440051 +#define FEC_OC_OCR_RATE__W 4 +#define FEC_OC_OCR_RATE__M 0xF +#define FEC_OC_OCR_RATE__PRE 0x0 + +#define FEC_OC_OCR_RATE_RATE__B 0 +#define FEC_OC_OCR_RATE_RATE__W 4 +#define FEC_OC_OCR_RATE_RATE__M 0xF +#define FEC_OC_OCR_RATE_RATE__PRE 0x0 + +#define FEC_OC_OCR_INVERT__A 0x2440052 +#define FEC_OC_OCR_INVERT__W 12 +#define FEC_OC_OCR_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT__PRE 0x800 + +#define FEC_OC_OCR_INVERT_INVERT__B 0 +#define FEC_OC_OCR_INVERT_INVERT__W 12 +#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 + +#define FEC_OC_OCR_GRAB_COUNT__A 0x2440053 +#define FEC_OC_OCR_GRAB_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC__A 0x2440054 +#define FEC_OC_OCR_GRAB_SYNC__W 8 +#define FEC_OC_OCR_GRAB_SYNC__M 0xFF +#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0__A 0x2440055 +#define FEC_OC_OCR_GRAB_RD0__W 10 +#define FEC_OC_OCR_GRAB_RD0__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1__A 0x2440056 +#define FEC_OC_OCR_GRAB_RD1__W 10 +#define FEC_OC_OCR_GRAB_RD1__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2__A 0x2440057 +#define FEC_OC_OCR_GRAB_RD2__W 10 +#define FEC_OC_OCR_GRAB_RD2__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3__A 0x2440058 +#define FEC_OC_OCR_GRAB_RD3__W 10 +#define FEC_OC_OCR_GRAB_RD3__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4__A 0x2440059 +#define FEC_OC_OCR_GRAB_RD4__W 10 +#define FEC_OC_OCR_GRAB_RD4__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5__A 0x244005A +#define FEC_OC_OCR_GRAB_RD5__W 10 +#define FEC_OC_OCR_GRAB_RD5__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 + +#define FEC_DI_RAM__A 0x2450000 + +#define FEC_RS_RAM__A 0x2460000 + +#define FEC_OC_RAM__A 0x2470000 + +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__W 2 +#define IQM_COMM_EXEC__M 0x3 +#define IQM_COMM_EXEC__PRE 0x0 +#define IQM_COMM_EXEC_STOP 0x0 +#define IQM_COMM_EXEC_ACTIVE 0x1 +#define IQM_COMM_EXEC_HOLD 0x2 + +#define IQM_COMM_MB__A 0x1800002 +#define IQM_COMM_MB__W 16 +#define IQM_COMM_MB__M 0xFFFF +#define IQM_COMM_MB__PRE 0x0 +#define IQM_COMM_INT_REQ__A 0x1800003 +#define IQM_COMM_INT_REQ__W 2 +#define IQM_COMM_INT_REQ__M 0x3 +#define IQM_COMM_INT_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_AF_REQ__B 0 +#define IQM_COMM_INT_REQ_AF_REQ__W 1 +#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 +#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CF_REQ__B 1 +#define IQM_COMM_INT_REQ_CF_REQ__W 1 +#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 +#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 + +#define IQM_COMM_INT_STA__A 0x1800005 +#define IQM_COMM_INT_STA__W 16 +#define IQM_COMM_INT_STA__M 0xFFFF +#define IQM_COMM_INT_STA__PRE 0x0 +#define IQM_COMM_INT_MSK__A 0x1800006 +#define IQM_COMM_INT_MSK__W 16 +#define IQM_COMM_INT_MSK__M 0xFFFF +#define IQM_COMM_INT_MSK__PRE 0x0 +#define IQM_COMM_INT_STM__A 0x1800007 +#define IQM_COMM_INT_STM__W 16 +#define IQM_COMM_INT_STM__M 0xFFFF +#define IQM_COMM_INT_STM__PRE 0x0 + +#define IQM_FS_COMM_EXEC__A 0x1820000 +#define IQM_FS_COMM_EXEC__W 2 +#define IQM_FS_COMM_EXEC__M 0x3 +#define IQM_FS_COMM_EXEC__PRE 0x0 +#define IQM_FS_COMM_EXEC_STOP 0x0 +#define IQM_FS_COMM_EXEC_ACTIVE 0x1 +#define IQM_FS_COMM_EXEC_HOLD 0x2 + +#define IQM_FS_COMM_MB__A 0x1820002 +#define IQM_FS_COMM_MB__W 2 +#define IQM_FS_COMM_MB__M 0x3 +#define IQM_FS_COMM_MB__PRE 0x0 +#define IQM_FS_COMM_MB_CTL__B 0 +#define IQM_FS_COMM_MB_CTL__W 1 +#define IQM_FS_COMM_MB_CTL__M 0x1 +#define IQM_FS_COMM_MB_CTL__PRE 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FS_COMM_MB_OBS__B 1 +#define IQM_FS_COMM_MB_OBS__W 1 +#define IQM_FS_COMM_MB_OBS__M 0x2 +#define IQM_FS_COMM_MB_OBS__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_FS_RATE_OFS_LO__A 0x1820010 +#define IQM_FS_RATE_OFS_LO__W 16 +#define IQM_FS_RATE_OFS_LO__M 0xFFFF +#define IQM_FS_RATE_OFS_LO__PRE 0x0 +#define IQM_FS_RATE_OFS_HI__A 0x1820011 +#define IQM_FS_RATE_OFS_HI__W 12 +#define IQM_FS_RATE_OFS_HI__M 0xFFF +#define IQM_FS_RATE_OFS_HI__PRE 0x0 +#define IQM_FS_RATE_LO__A 0x1820012 +#define IQM_FS_RATE_LO__W 16 +#define IQM_FS_RATE_LO__M 0xFFFF +#define IQM_FS_RATE_LO__PRE 0x0 +#define IQM_FS_RATE_HI__A 0x1820013 +#define IQM_FS_RATE_HI__W 12 +#define IQM_FS_RATE_HI__M 0xFFF +#define IQM_FS_RATE_HI__PRE 0x0 + +#define IQM_FS_ADJ_SEL__A 0x1820014 +#define IQM_FS_ADJ_SEL__W 2 +#define IQM_FS_ADJ_SEL__M 0x3 +#define IQM_FS_ADJ_SEL__PRE 0x0 +#define IQM_FS_ADJ_SEL_OFF 0x0 +#define IQM_FS_ADJ_SEL_QAM 0x1 +#define IQM_FS_ADJ_SEL_VSB 0x2 + +#define IQM_FD_COMM_EXEC__A 0x1830000 +#define IQM_FD_COMM_EXEC__W 2 +#define IQM_FD_COMM_EXEC__M 0x3 +#define IQM_FD_COMM_EXEC__PRE 0x0 +#define IQM_FD_COMM_EXEC_STOP 0x0 +#define IQM_FD_COMM_EXEC_ACTIVE 0x1 +#define IQM_FD_COMM_EXEC_HOLD 0x2 + +#define IQM_FD_COMM_MB__A 0x1830002 +#define IQM_FD_COMM_MB__W 2 +#define IQM_FD_COMM_MB__M 0x3 +#define IQM_FD_COMM_MB__PRE 0x0 +#define IQM_FD_COMM_MB_CTL__B 0 +#define IQM_FD_COMM_MB_CTL__W 1 +#define IQM_FD_COMM_MB_CTL__M 0x1 +#define IQM_FD_COMM_MB_CTL__PRE 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FD_COMM_MB_OBS__B 1 +#define IQM_FD_COMM_MB_OBS__W 1 +#define IQM_FD_COMM_MB_OBS__M 0x2 +#define IQM_FD_COMM_MB_OBS__PRE 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RC_COMM_EXEC__A 0x1840000 +#define IQM_RC_COMM_EXEC__W 2 +#define IQM_RC_COMM_EXEC__M 0x3 +#define IQM_RC_COMM_EXEC__PRE 0x0 +#define IQM_RC_COMM_EXEC_STOP 0x0 +#define IQM_RC_COMM_EXEC_ACTIVE 0x1 +#define IQM_RC_COMM_EXEC_HOLD 0x2 + +#define IQM_RC_COMM_MB__A 0x1840002 +#define IQM_RC_COMM_MB__W 2 +#define IQM_RC_COMM_MB__M 0x3 +#define IQM_RC_COMM_MB__PRE 0x0 +#define IQM_RC_COMM_MB_CTL__B 0 +#define IQM_RC_COMM_MB_CTL__W 1 +#define IQM_RC_COMM_MB_CTL__M 0x1 +#define IQM_RC_COMM_MB_CTL__PRE 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RC_COMM_MB_OBS__B 1 +#define IQM_RC_COMM_MB_OBS__W 1 +#define IQM_RC_COMM_MB_OBS__M 0x2 +#define IQM_RC_COMM_MB_OBS__PRE 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__W 16 +#define IQM_RC_RATE_OFS_LO__M 0xFFFF +#define IQM_RC_RATE_OFS_LO__PRE 0x0 +#define IQM_RC_RATE_OFS_HI__A 0x1840011 +#define IQM_RC_RATE_OFS_HI__W 8 +#define IQM_RC_RATE_OFS_HI__M 0xFF +#define IQM_RC_RATE_OFS_HI__PRE 0x0 +#define IQM_RC_RATE_LO__A 0x1840012 +#define IQM_RC_RATE_LO__W 16 +#define IQM_RC_RATE_LO__M 0xFFFF +#define IQM_RC_RATE_LO__PRE 0x0 +#define IQM_RC_RATE_HI__A 0x1840013 +#define IQM_RC_RATE_HI__W 8 +#define IQM_RC_RATE_HI__M 0xFF +#define IQM_RC_RATE_HI__PRE 0x0 + +#define IQM_RC_ADJ_SEL__A 0x1840014 +#define IQM_RC_ADJ_SEL__W 2 +#define IQM_RC_ADJ_SEL__M 0x3 +#define IQM_RC_ADJ_SEL__PRE 0x0 +#define IQM_RC_ADJ_SEL_OFF 0x0 +#define IQM_RC_ADJ_SEL_QAM 0x1 +#define IQM_RC_ADJ_SEL_VSB 0x2 + +#define IQM_RC_CROUT_ENA__A 0x1840015 +#define IQM_RC_CROUT_ENA__W 1 +#define IQM_RC_CROUT_ENA__M 0x1 +#define IQM_RC_CROUT_ENA__PRE 0x0 + +#define IQM_RC_CROUT_ENA_ENA__B 0 +#define IQM_RC_CROUT_ENA_ENA__W 1 +#define IQM_RC_CROUT_ENA_ENA__M 0x1 +#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 + +#define IQM_RC_STRETCH__A 0x1840016 +#define IQM_RC_STRETCH__W 5 +#define IQM_RC_STRETCH__M 0x1F +#define IQM_RC_STRETCH__PRE 0x0 +#define IQM_RC_STRETCH_QAM_B_64 0x1E +#define IQM_RC_STRETCH_QAM_B_256 0x1C +#define IQM_RC_STRETCH_ATV 0xF + +#define IQM_RT_COMM_EXEC__A 0x1850000 +#define IQM_RT_COMM_EXEC__W 2 +#define IQM_RT_COMM_EXEC__M 0x3 +#define IQM_RT_COMM_EXEC__PRE 0x0 +#define IQM_RT_COMM_EXEC_STOP 0x0 +#define IQM_RT_COMM_EXEC_ACTIVE 0x1 +#define IQM_RT_COMM_EXEC_HOLD 0x2 + +#define IQM_RT_COMM_MB__A 0x1850002 +#define IQM_RT_COMM_MB__W 2 +#define IQM_RT_COMM_MB__M 0x3 +#define IQM_RT_COMM_MB__PRE 0x0 +#define IQM_RT_COMM_MB_CTL__B 0 +#define IQM_RT_COMM_MB_CTL__W 1 +#define IQM_RT_COMM_MB_CTL__M 0x1 +#define IQM_RT_COMM_MB_CTL__PRE 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RT_COMM_MB_OBS__B 1 +#define IQM_RT_COMM_MB_OBS__W 1 +#define IQM_RT_COMM_MB_OBS__M 0x2 +#define IQM_RT_COMM_MB_OBS__PRE 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RT_ACTIVE__A 0x1850010 +#define IQM_RT_ACTIVE__W 2 +#define IQM_RT_ACTIVE__M 0x3 +#define IQM_RT_ACTIVE__PRE 0x0 + +#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 +#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 +#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 +#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 + +#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 +#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 + +#define IQM_RT_LO_INCR__A 0x1850011 +#define IQM_RT_LO_INCR__W 12 +#define IQM_RT_LO_INCR__M 0xFFF +#define IQM_RT_LO_INCR__PRE 0x588 +#define IQM_RT_LO_INCR_FM 0x0 +#define IQM_RT_LO_INCR_MN 0x588 + +#define IQM_RT_ROT_BP__A 0x1850012 +#define IQM_RT_ROT_BP__W 2 +#define IQM_RT_ROT_BP__M 0x3 +#define IQM_RT_ROT_BP__PRE 0x0 + +#define IQM_RT_ROT_BP_ROT_OFF__B 0 +#define IQM_RT_ROT_BP_ROT_OFF__W 1 +#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 +#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 + +#define IQM_RT_ROT_BP_ROT_BPF__B 1 +#define IQM_RT_ROT_BP_ROT_BPF__W 1 +#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 +#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 + +#define IQM_RT_LP_BP__A 0x1850013 +#define IQM_RT_LP_BP__W 1 +#define IQM_RT_LP_BP__M 0x1 +#define IQM_RT_LP_BP__PRE 0x0 + +#define IQM_RT_DELAY__A 0x1850014 +#define IQM_RT_DELAY__W 7 +#define IQM_RT_DELAY__M 0x7F +#define IQM_RT_DELAY__PRE 0x45 + +#define IQM_CF_COMM_EXEC__A 0x1860000 +#define IQM_CF_COMM_EXEC__W 2 +#define IQM_CF_COMM_EXEC__M 0x3 +#define IQM_CF_COMM_EXEC__PRE 0x0 +#define IQM_CF_COMM_EXEC_STOP 0x0 +#define IQM_CF_COMM_EXEC_ACTIVE 0x1 +#define IQM_CF_COMM_EXEC_HOLD 0x2 + +#define IQM_CF_COMM_MB__A 0x1860002 +#define IQM_CF_COMM_MB__W 2 +#define IQM_CF_COMM_MB__M 0x3 +#define IQM_CF_COMM_MB__PRE 0x0 +#define IQM_CF_COMM_MB_CTL__B 0 +#define IQM_CF_COMM_MB_CTL__W 1 +#define IQM_CF_COMM_MB_CTL__M 0x1 +#define IQM_CF_COMM_MB_CTL__PRE 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_CF_COMM_MB_OBS__B 1 +#define IQM_CF_COMM_MB_OBS__W 1 +#define IQM_CF_COMM_MB_OBS__M 0x2 +#define IQM_CF_COMM_MB_OBS__PRE 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_CF_COMM_INT_REQ__A 0x1860003 +#define IQM_CF_COMM_INT_REQ__W 1 +#define IQM_CF_COMM_INT_REQ__M 0x1 +#define IQM_CF_COMM_INT_REQ__PRE 0x0 +#define IQM_CF_COMM_INT_STA__A 0x1860005 +#define IQM_CF_COMM_INT_STA__W 1 +#define IQM_CF_COMM_INT_STA__M 0x1 +#define IQM_CF_COMM_INT_STA__PRE 0x0 +#define IQM_CF_COMM_INT_STA_PM__B 0 +#define IQM_CF_COMM_INT_STA_PM__W 1 +#define IQM_CF_COMM_INT_STA_PM__M 0x1 +#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 + +#define IQM_CF_COMM_INT_MSK__A 0x1860006 +#define IQM_CF_COMM_INT_MSK__W 1 +#define IQM_CF_COMM_INT_MSK__M 0x1 +#define IQM_CF_COMM_INT_MSK__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_PM__B 0 +#define IQM_CF_COMM_INT_MSK_PM__W 1 +#define IQM_CF_COMM_INT_MSK_PM__M 0x1 +#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 + +#define IQM_CF_COMM_INT_STM__A 0x1860007 +#define IQM_CF_COMM_INT_STM__W 1 +#define IQM_CF_COMM_INT_STM__M 0x1 +#define IQM_CF_COMM_INT_STM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_PM__B 0 +#define IQM_CF_COMM_INT_STM_PM__W 1 +#define IQM_CF_COMM_INT_STM_PM__M 0x1 +#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 + +#define IQM_CF_SYMMETRIC__A 0x1860010 +#define IQM_CF_SYMMETRIC__W 2 +#define IQM_CF_SYMMETRIC__M 0x3 +#define IQM_CF_SYMMETRIC__PRE 0x0 + +#define IQM_CF_SYMMETRIC_RE__B 0 +#define IQM_CF_SYMMETRIC_RE__W 1 +#define IQM_CF_SYMMETRIC_RE__M 0x1 +#define IQM_CF_SYMMETRIC_RE__PRE 0x0 + +#define IQM_CF_SYMMETRIC_IM__B 1 +#define IQM_CF_SYMMETRIC_IM__W 1 +#define IQM_CF_SYMMETRIC_IM__M 0x2 +#define IQM_CF_SYMMETRIC_IM__PRE 0x0 + +#define IQM_CF_MIDTAP__A 0x1860011 +#define IQM_CF_MIDTAP__W 2 +#define IQM_CF_MIDTAP__M 0x3 +#define IQM_CF_MIDTAP__PRE 0x3 + +#define IQM_CF_MIDTAP_RE__B 0 +#define IQM_CF_MIDTAP_RE__W 1 +#define IQM_CF_MIDTAP_RE__M 0x1 +#define IQM_CF_MIDTAP_RE__PRE 0x1 + +#define IQM_CF_MIDTAP_IM__B 1 +#define IQM_CF_MIDTAP_IM__W 1 +#define IQM_CF_MIDTAP_IM__M 0x2 +#define IQM_CF_MIDTAP_IM__PRE 0x2 + +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_OUT_ENA__W 3 +#define IQM_CF_OUT_ENA__M 0x7 +#define IQM_CF_OUT_ENA__PRE 0x0 + +#define IQM_CF_OUT_ENA_ATV__B 0 +#define IQM_CF_OUT_ENA_ATV__W 1 +#define IQM_CF_OUT_ENA_ATV__M 0x1 +#define IQM_CF_OUT_ENA_ATV__PRE 0x0 + +#define IQM_CF_OUT_ENA_QAM__B 1 +#define IQM_CF_OUT_ENA_QAM__W 1 +#define IQM_CF_OUT_ENA_QAM__M 0x2 +#define IQM_CF_OUT_ENA_QAM__PRE 0x0 + +#define IQM_CF_OUT_ENA_VSB__B 2 +#define IQM_CF_OUT_ENA_VSB__W 1 +#define IQM_CF_OUT_ENA_VSB__M 0x4 +#define IQM_CF_OUT_ENA_VSB__PRE 0x0 + +#define IQM_CF_ADJ_SEL__A 0x1860013 +#define IQM_CF_ADJ_SEL__W 2 +#define IQM_CF_ADJ_SEL__M 0x3 +#define IQM_CF_ADJ_SEL__PRE 0x0 +#define IQM_CF_SCALE__A 0x1860014 +#define IQM_CF_SCALE__W 14 +#define IQM_CF_SCALE__M 0x3FFF +#define IQM_CF_SCALE__PRE 0x400 + +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__W 2 +#define IQM_CF_SCALE_SH__M 0x3 +#define IQM_CF_SCALE_SH__PRE 0x0 + +#define IQM_CF_AMP__A 0x1860016 +#define IQM_CF_AMP__W 14 +#define IQM_CF_AMP__M 0x3FFF +#define IQM_CF_AMP__PRE 0x0 + +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_POW_MEAS_LEN__W 3 +#define IQM_CF_POW_MEAS_LEN__M 0x7 +#define IQM_CF_POW_MEAS_LEN__PRE 0x2 +#define IQM_CF_POW_MEAS_LEN_QAM_B_64 0x1 +#define IQM_CF_POW_MEAS_LEN_QAM_B_256 0x1 + +#define IQM_CF_POW__A 0x1860018 +#define IQM_CF_POW__W 16 +#define IQM_CF_POW__M 0xFFFF +#define IQM_CF_POW__PRE 0x2 +#define IQM_CF_TAP_RE0__A 0x1860020 +#define IQM_CF_TAP_RE0__W 7 +#define IQM_CF_TAP_RE0__M 0x7F +#define IQM_CF_TAP_RE0__PRE 0x2 +#define IQM_CF_TAP_RE1__A 0x1860021 +#define IQM_CF_TAP_RE1__W 7 +#define IQM_CF_TAP_RE1__M 0x7F +#define IQM_CF_TAP_RE1__PRE 0x2 +#define IQM_CF_TAP_RE2__A 0x1860022 +#define IQM_CF_TAP_RE2__W 7 +#define IQM_CF_TAP_RE2__M 0x7F +#define IQM_CF_TAP_RE2__PRE 0x2 +#define IQM_CF_TAP_RE3__A 0x1860023 +#define IQM_CF_TAP_RE3__W 7 +#define IQM_CF_TAP_RE3__M 0x7F +#define IQM_CF_TAP_RE3__PRE 0x2 +#define IQM_CF_TAP_RE4__A 0x1860024 +#define IQM_CF_TAP_RE4__W 7 +#define IQM_CF_TAP_RE4__M 0x7F +#define IQM_CF_TAP_RE4__PRE 0x2 +#define IQM_CF_TAP_RE5__A 0x1860025 +#define IQM_CF_TAP_RE5__W 7 +#define IQM_CF_TAP_RE5__M 0x7F +#define IQM_CF_TAP_RE5__PRE 0x2 +#define IQM_CF_TAP_RE6__A 0x1860026 +#define IQM_CF_TAP_RE6__W 7 +#define IQM_CF_TAP_RE6__M 0x7F +#define IQM_CF_TAP_RE6__PRE 0x2 +#define IQM_CF_TAP_RE7__A 0x1860027 +#define IQM_CF_TAP_RE7__W 9 +#define IQM_CF_TAP_RE7__M 0x1FF +#define IQM_CF_TAP_RE7__PRE 0x2 +#define IQM_CF_TAP_RE8__A 0x1860028 +#define IQM_CF_TAP_RE8__W 9 +#define IQM_CF_TAP_RE8__M 0x1FF +#define IQM_CF_TAP_RE8__PRE 0x2 +#define IQM_CF_TAP_RE9__A 0x1860029 +#define IQM_CF_TAP_RE9__W 9 +#define IQM_CF_TAP_RE9__M 0x1FF +#define IQM_CF_TAP_RE9__PRE 0x2 +#define IQM_CF_TAP_RE10__A 0x186002A +#define IQM_CF_TAP_RE10__W 9 +#define IQM_CF_TAP_RE10__M 0x1FF +#define IQM_CF_TAP_RE10__PRE 0x2 +#define IQM_CF_TAP_RE11__A 0x186002B +#define IQM_CF_TAP_RE11__W 9 +#define IQM_CF_TAP_RE11__M 0x1FF +#define IQM_CF_TAP_RE11__PRE 0x2 +#define IQM_CF_TAP_RE12__A 0x186002C +#define IQM_CF_TAP_RE12__W 9 +#define IQM_CF_TAP_RE12__M 0x1FF +#define IQM_CF_TAP_RE12__PRE 0x2 +#define IQM_CF_TAP_RE13__A 0x186002D +#define IQM_CF_TAP_RE13__W 9 +#define IQM_CF_TAP_RE13__M 0x1FF +#define IQM_CF_TAP_RE13__PRE 0x2 +#define IQM_CF_TAP_RE14__A 0x186002E +#define IQM_CF_TAP_RE14__W 9 +#define IQM_CF_TAP_RE14__M 0x1FF +#define IQM_CF_TAP_RE14__PRE 0x2 +#define IQM_CF_TAP_RE15__A 0x186002F +#define IQM_CF_TAP_RE15__W 9 +#define IQM_CF_TAP_RE15__M 0x1FF +#define IQM_CF_TAP_RE15__PRE 0x2 +#define IQM_CF_TAP_RE16__A 0x1860030 +#define IQM_CF_TAP_RE16__W 9 +#define IQM_CF_TAP_RE16__M 0x1FF +#define IQM_CF_TAP_RE16__PRE 0x2 +#define IQM_CF_TAP_RE17__A 0x1860031 +#define IQM_CF_TAP_RE17__W 9 +#define IQM_CF_TAP_RE17__M 0x1FF +#define IQM_CF_TAP_RE17__PRE 0x2 +#define IQM_CF_TAP_RE18__A 0x1860032 +#define IQM_CF_TAP_RE18__W 9 +#define IQM_CF_TAP_RE18__M 0x1FF +#define IQM_CF_TAP_RE18__PRE 0x2 +#define IQM_CF_TAP_RE19__A 0x1860033 +#define IQM_CF_TAP_RE19__W 9 +#define IQM_CF_TAP_RE19__M 0x1FF +#define IQM_CF_TAP_RE19__PRE 0x2 +#define IQM_CF_TAP_RE20__A 0x1860034 +#define IQM_CF_TAP_RE20__W 9 +#define IQM_CF_TAP_RE20__M 0x1FF +#define IQM_CF_TAP_RE20__PRE 0x2 +#define IQM_CF_TAP_RE21__A 0x1860035 +#define IQM_CF_TAP_RE21__W 11 +#define IQM_CF_TAP_RE21__M 0x7FF +#define IQM_CF_TAP_RE21__PRE 0x2 +#define IQM_CF_TAP_RE22__A 0x1860036 +#define IQM_CF_TAP_RE22__W 11 +#define IQM_CF_TAP_RE22__M 0x7FF +#define IQM_CF_TAP_RE22__PRE 0x2 +#define IQM_CF_TAP_RE23__A 0x1860037 +#define IQM_CF_TAP_RE23__W 11 +#define IQM_CF_TAP_RE23__M 0x7FF +#define IQM_CF_TAP_RE23__PRE 0x2 +#define IQM_CF_TAP_RE24__A 0x1860038 +#define IQM_CF_TAP_RE24__W 11 +#define IQM_CF_TAP_RE24__M 0x7FF +#define IQM_CF_TAP_RE24__PRE 0x2 +#define IQM_CF_TAP_RE25__A 0x1860039 +#define IQM_CF_TAP_RE25__W 11 +#define IQM_CF_TAP_RE25__M 0x7FF +#define IQM_CF_TAP_RE25__PRE 0x2 +#define IQM_CF_TAP_RE26__A 0x186003A +#define IQM_CF_TAP_RE26__W 11 +#define IQM_CF_TAP_RE26__M 0x7FF +#define IQM_CF_TAP_RE26__PRE 0x2 +#define IQM_CF_TAP_RE27__A 0x186003B +#define IQM_CF_TAP_RE27__W 11 +#define IQM_CF_TAP_RE27__M 0x7FF +#define IQM_CF_TAP_RE27__PRE 0x2 +#define IQM_CF_TAP_IM0__A 0x1860040 +#define IQM_CF_TAP_IM0__W 7 +#define IQM_CF_TAP_IM0__M 0x7F +#define IQM_CF_TAP_IM0__PRE 0x2 +#define IQM_CF_TAP_IM1__A 0x1860041 +#define IQM_CF_TAP_IM1__W 7 +#define IQM_CF_TAP_IM1__M 0x7F +#define IQM_CF_TAP_IM1__PRE 0x2 +#define IQM_CF_TAP_IM2__A 0x1860042 +#define IQM_CF_TAP_IM2__W 7 +#define IQM_CF_TAP_IM2__M 0x7F +#define IQM_CF_TAP_IM2__PRE 0x2 +#define IQM_CF_TAP_IM3__A 0x1860043 +#define IQM_CF_TAP_IM3__W 7 +#define IQM_CF_TAP_IM3__M 0x7F +#define IQM_CF_TAP_IM3__PRE 0x2 +#define IQM_CF_TAP_IM4__A 0x1860044 +#define IQM_CF_TAP_IM4__W 7 +#define IQM_CF_TAP_IM4__M 0x7F +#define IQM_CF_TAP_IM4__PRE 0x2 +#define IQM_CF_TAP_IM5__A 0x1860045 +#define IQM_CF_TAP_IM5__W 7 +#define IQM_CF_TAP_IM5__M 0x7F +#define IQM_CF_TAP_IM5__PRE 0x2 +#define IQM_CF_TAP_IM6__A 0x1860046 +#define IQM_CF_TAP_IM6__W 7 +#define IQM_CF_TAP_IM6__M 0x7F +#define IQM_CF_TAP_IM6__PRE 0x2 +#define IQM_CF_TAP_IM7__A 0x1860047 +#define IQM_CF_TAP_IM7__W 9 +#define IQM_CF_TAP_IM7__M 0x1FF +#define IQM_CF_TAP_IM7__PRE 0x2 +#define IQM_CF_TAP_IM8__A 0x1860048 +#define IQM_CF_TAP_IM8__W 9 +#define IQM_CF_TAP_IM8__M 0x1FF +#define IQM_CF_TAP_IM8__PRE 0x2 +#define IQM_CF_TAP_IM9__A 0x1860049 +#define IQM_CF_TAP_IM9__W 9 +#define IQM_CF_TAP_IM9__M 0x1FF +#define IQM_CF_TAP_IM9__PRE 0x2 +#define IQM_CF_TAP_IM10__A 0x186004A +#define IQM_CF_TAP_IM10__W 9 +#define IQM_CF_TAP_IM10__M 0x1FF +#define IQM_CF_TAP_IM10__PRE 0x2 +#define IQM_CF_TAP_IM11__A 0x186004B +#define IQM_CF_TAP_IM11__W 9 +#define IQM_CF_TAP_IM11__M 0x1FF +#define IQM_CF_TAP_IM11__PRE 0x2 +#define IQM_CF_TAP_IM12__A 0x186004C +#define IQM_CF_TAP_IM12__W 9 +#define IQM_CF_TAP_IM12__M 0x1FF +#define IQM_CF_TAP_IM12__PRE 0x2 +#define IQM_CF_TAP_IM13__A 0x186004D +#define IQM_CF_TAP_IM13__W 9 +#define IQM_CF_TAP_IM13__M 0x1FF +#define IQM_CF_TAP_IM13__PRE 0x2 +#define IQM_CF_TAP_IM14__A 0x186004E +#define IQM_CF_TAP_IM14__W 9 +#define IQM_CF_TAP_IM14__M 0x1FF +#define IQM_CF_TAP_IM14__PRE 0x2 +#define IQM_CF_TAP_IM15__A 0x186004F +#define IQM_CF_TAP_IM15__W 9 +#define IQM_CF_TAP_IM15__M 0x1FF +#define IQM_CF_TAP_IM15__PRE 0x2 +#define IQM_CF_TAP_IM16__A 0x1860050 +#define IQM_CF_TAP_IM16__W 9 +#define IQM_CF_TAP_IM16__M 0x1FF +#define IQM_CF_TAP_IM16__PRE 0x2 +#define IQM_CF_TAP_IM17__A 0x1860051 +#define IQM_CF_TAP_IM17__W 9 +#define IQM_CF_TAP_IM17__M 0x1FF +#define IQM_CF_TAP_IM17__PRE 0x2 +#define IQM_CF_TAP_IM18__A 0x1860052 +#define IQM_CF_TAP_IM18__W 9 +#define IQM_CF_TAP_IM18__M 0x1FF +#define IQM_CF_TAP_IM18__PRE 0x2 +#define IQM_CF_TAP_IM19__A 0x1860053 +#define IQM_CF_TAP_IM19__W 9 +#define IQM_CF_TAP_IM19__M 0x1FF +#define IQM_CF_TAP_IM19__PRE 0x2 +#define IQM_CF_TAP_IM20__A 0x1860054 +#define IQM_CF_TAP_IM20__W 9 +#define IQM_CF_TAP_IM20__M 0x1FF +#define IQM_CF_TAP_IM20__PRE 0x2 +#define IQM_CF_TAP_IM21__A 0x1860055 +#define IQM_CF_TAP_IM21__W 11 +#define IQM_CF_TAP_IM21__M 0x7FF +#define IQM_CF_TAP_IM21__PRE 0x2 +#define IQM_CF_TAP_IM22__A 0x1860056 +#define IQM_CF_TAP_IM22__W 11 +#define IQM_CF_TAP_IM22__M 0x7FF +#define IQM_CF_TAP_IM22__PRE 0x2 +#define IQM_CF_TAP_IM23__A 0x1860057 +#define IQM_CF_TAP_IM23__W 11 +#define IQM_CF_TAP_IM23__M 0x7FF +#define IQM_CF_TAP_IM23__PRE 0x2 +#define IQM_CF_TAP_IM24__A 0x1860058 +#define IQM_CF_TAP_IM24__W 11 +#define IQM_CF_TAP_IM24__M 0x7FF +#define IQM_CF_TAP_IM24__PRE 0x2 +#define IQM_CF_TAP_IM25__A 0x1860059 +#define IQM_CF_TAP_IM25__W 11 +#define IQM_CF_TAP_IM25__M 0x7FF +#define IQM_CF_TAP_IM25__PRE 0x2 +#define IQM_CF_TAP_IM26__A 0x186005A +#define IQM_CF_TAP_IM26__W 11 +#define IQM_CF_TAP_IM26__M 0x7FF +#define IQM_CF_TAP_IM26__PRE 0x2 +#define IQM_CF_TAP_IM27__A 0x186005B +#define IQM_CF_TAP_IM27__W 11 +#define IQM_CF_TAP_IM27__M 0x7FF +#define IQM_CF_TAP_IM27__PRE 0x2 + +#define IQM_AF_COMM_EXEC__A 0x1870000 +#define IQM_AF_COMM_EXEC__W 2 +#define IQM_AF_COMM_EXEC__M 0x3 +#define IQM_AF_COMM_EXEC__PRE 0x0 +#define IQM_AF_COMM_EXEC_STOP 0x0 +#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +#define IQM_AF_COMM_EXEC_HOLD 0x2 + +#define IQM_AF_COMM_MB__A 0x1870002 +#define IQM_AF_COMM_MB__W 8 +#define IQM_AF_COMM_MB__M 0xFF +#define IQM_AF_COMM_MB__PRE 0x0 +#define IQM_AF_COMM_MB_CTL__B 0 +#define IQM_AF_COMM_MB_CTL__W 1 +#define IQM_AF_COMM_MB_CTL__M 0x1 +#define IQM_AF_COMM_MB_CTL__PRE 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_AF_COMM_MB_OBS__B 1 +#define IQM_AF_COMM_MB_OBS__W 1 +#define IQM_AF_COMM_MB_OBS__M 0x2 +#define IQM_AF_COMM_MB_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_AF_COMM_MB_MUX_CTRL__B 2 +#define IQM_AF_COMM_MB_MUX_CTRL__W 3 +#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C +#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 +#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC +#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 +#define IQM_AF_COMM_MB_MUX_OBS__B 5 +#define IQM_AF_COMM_MB_MUX_OBS__W 3 +#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 +#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 +#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 +#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 + +#define IQM_AF_COMM_INT_REQ__A 0x1870003 +#define IQM_AF_COMM_INT_REQ__W 1 +#define IQM_AF_COMM_INT_REQ__M 0x1 +#define IQM_AF_COMM_INT_REQ__PRE 0x0 +#define IQM_AF_COMM_INT_STA__A 0x1870005 +#define IQM_AF_COMM_INT_STA__W 2 +#define IQM_AF_COMM_INT_STA__M 0x3 +#define IQM_AF_COMM_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 + +#define IQM_AF_COMM_INT_MSK__A 0x1870006 +#define IQM_AF_COMM_INT_MSK__W 2 +#define IQM_AF_COMM_INT_MSK__M 0x3 +#define IQM_AF_COMM_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 + +#define IQM_AF_COMM_INT_STM__A 0x1870007 +#define IQM_AF_COMM_INT_STM__W 2 +#define IQM_AF_COMM_INT_STM__M 0x3 +#define IQM_AF_COMM_INT_STM__PRE 0x0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 + +#define IQM_AF_FDB_SEL__A 0x1870010 +#define IQM_AF_FDB_SEL__W 1 +#define IQM_AF_FDB_SEL__M 0x1 +#define IQM_AF_FDB_SEL__PRE 0x0 + +#define IQM_AF_INVEXT__A 0x1870011 +#define IQM_AF_INVEXT__W 1 +#define IQM_AF_INVEXT__M 0x1 +#define IQM_AF_INVEXT__PRE 0x0 +#define IQM_AF_CLKNEG__A 0x1870012 +#define IQM_AF_CLKNEG__W 2 +#define IQM_AF_CLKNEG__M 0x3 +#define IQM_AF_CLKNEG__PRE 0x0 + +#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 +#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 + +#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 + +#define IQM_AF_MON_IN_MUX__A 0x1870013 +#define IQM_AF_MON_IN_MUX__W 2 +#define IQM_AF_MON_IN_MUX__M 0x3 +#define IQM_AF_MON_IN_MUX__PRE 0x0 + +#define IQM_AF_MON_IN5__A 0x1870014 +#define IQM_AF_MON_IN5__W 10 +#define IQM_AF_MON_IN5__M 0x3FF +#define IQM_AF_MON_IN5__PRE 0x0 + +#define IQM_AF_MON_IN4__A 0x1870015 +#define IQM_AF_MON_IN4__W 10 +#define IQM_AF_MON_IN4__M 0x3FF +#define IQM_AF_MON_IN4__PRE 0x0 + +#define IQM_AF_MON_IN3__A 0x1870016 +#define IQM_AF_MON_IN3__W 10 +#define IQM_AF_MON_IN3__M 0x3FF +#define IQM_AF_MON_IN3__PRE 0x0 + +#define IQM_AF_MON_IN2__A 0x1870017 +#define IQM_AF_MON_IN2__W 10 +#define IQM_AF_MON_IN2__M 0x3FF +#define IQM_AF_MON_IN2__PRE 0x0 + +#define IQM_AF_MON_IN1__A 0x1870018 +#define IQM_AF_MON_IN1__W 10 +#define IQM_AF_MON_IN1__M 0x3FF +#define IQM_AF_MON_IN1__PRE 0x0 + +#define IQM_AF_MON_IN0__A 0x1870019 +#define IQM_AF_MON_IN0__W 10 +#define IQM_AF_MON_IN0__M 0x3FF +#define IQM_AF_MON_IN0__PRE 0x0 + +#define IQM_AF_MON_IN_VAL__A 0x187001A +#define IQM_AF_MON_IN_VAL__W 1 +#define IQM_AF_MON_IN_VAL__M 0x1 +#define IQM_AF_MON_IN_VAL__PRE 0x0 + +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_START_LOCK__W 1 +#define IQM_AF_START_LOCK__M 0x1 +#define IQM_AF_START_LOCK__PRE 0x0 + +#define IQM_AF_PHASE0__A 0x187001C +#define IQM_AF_PHASE0__W 7 +#define IQM_AF_PHASE0__M 0x7F +#define IQM_AF_PHASE0__PRE 0x0 + +#define IQM_AF_PHASE1__A 0x187001D +#define IQM_AF_PHASE1__W 7 +#define IQM_AF_PHASE1__M 0x7F +#define IQM_AF_PHASE1__PRE 0x0 + +#define IQM_AF_PHASE2__A 0x187001E +#define IQM_AF_PHASE2__W 7 +#define IQM_AF_PHASE2__M 0x7F +#define IQM_AF_PHASE2__PRE 0x0 + +#define IQM_AF_SCU_PHASE__A 0x187001F +#define IQM_AF_SCU_PHASE__W 2 +#define IQM_AF_SCU_PHASE__M 0x3 +#define IQM_AF_SCU_PHASE__PRE 0x0 + +#define IQM_AF_SYNC_SEL__A 0x1870020 +#define IQM_AF_SYNC_SEL__W 2 +#define IQM_AF_SYNC_SEL__M 0x3 +#define IQM_AF_SYNC_SEL__PRE 0x0 +#define IQM_AF_ADC_CONF__A 0x1870021 +#define IQM_AF_ADC_CONF__W 4 +#define IQM_AF_ADC_CONF__M 0xF +#define IQM_AF_ADC_CONF__PRE 0x0 + +#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 +#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 +#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 +#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 + +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 + +#define IQM_AF_CLP_CLIP__A 0x1870022 +#define IQM_AF_CLP_CLIP__W 16 +#define IQM_AF_CLP_CLIP__M 0xFFFF +#define IQM_AF_CLP_CLIP__PRE 0x0 + +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_LEN__W 16 +#define IQM_AF_CLP_LEN__M 0xFFFF +#define IQM_AF_CLP_LEN__PRE 0x0 +#define IQM_AF_CLP_LEN_QAM_B_64 0x400 +#define IQM_AF_CLP_LEN_QAM_B_256 0x400 +#define IQM_AF_CLP_LEN_ATV 0x0 + +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_CLP_TH__W 9 +#define IQM_AF_CLP_TH__M 0x1FF +#define IQM_AF_CLP_TH__PRE 0x0 +#define IQM_AF_CLP_TH_QAM_B_64 0x80 +#define IQM_AF_CLP_TH_QAM_B_256 0x80 +#define IQM_AF_CLP_TH_ATV 0x1C0 + +#define IQM_AF_DCF_BYPASS__A 0x1870025 +#define IQM_AF_DCF_BYPASS__W 1 +#define IQM_AF_DCF_BYPASS__M 0x1 +#define IQM_AF_DCF_BYPASS__PRE 0x0 +#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 +#define IQM_AF_DCF_BYPASS_BYPASS 0x1 + +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_SNS_LEN__W 16 +#define IQM_AF_SNS_LEN__M 0xFFFF +#define IQM_AF_SNS_LEN__PRE 0x0 +#define IQM_AF_SNS_LEN_QAM_B_64 0x400 +#define IQM_AF_SNS_LEN_QAM_B_256 0x400 +#define IQM_AF_SNS_LEN_ATV 0x0 + +#define IQM_AF_SNS_SENSE__A 0x1870027 +#define IQM_AF_SNS_SENSE__W 16 +#define IQM_AF_SNS_SENSE__M 0xFFFF +#define IQM_AF_SNS_SENSE__PRE 0x0 + +#define IQM_AF_AGC_IF__A 0x1870028 +#define IQM_AF_AGC_IF__W 15 +#define IQM_AF_AGC_IF__M 0x7FFF +#define IQM_AF_AGC_IF__PRE 0x0 + +#define IQM_AF_AGC_RF__A 0x1870029 +#define IQM_AF_AGC_RF__W 15 +#define IQM_AF_AGC_RF__M 0x7FFF +#define IQM_AF_AGC_RF__PRE 0x0 + +#define IQM_AF_PGA_GAIN__A 0x187002A +#define IQM_AF_PGA_GAIN__W 4 +#define IQM_AF_PGA_GAIN__M 0xF +#define IQM_AF_PGA_GAIN__PRE 0x0 + +#define IQM_AF_PDREF__A 0x187002B +#define IQM_AF_PDREF__W 5 +#define IQM_AF_PDREF__M 0x1F +#define IQM_AF_PDREF__PRE 0x0 +#define IQM_AF_PDREF_QAM_B_64 0xF +#define IQM_AF_PDREF_QAM_B_256 0xF +#define IQM_AF_PDREF_ATV 0xF + +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__W 6 +#define IQM_AF_STDBY__M 0x3F +#define IQM_AF_STDBY__PRE 0x0 + +#define IQM_AF_STDBY_STDBY_BIAS__B 0 +#define IQM_AF_STDBY_STDBY_BIAS__W 1 +#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 +#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 + +#define IQM_AF_STDBY_STDBY_ADC__B 1 +#define IQM_AF_STDBY_STDBY_ADC__W 1 +#define IQM_AF_STDBY_STDBY_ADC__M 0x2 +#define IQM_AF_STDBY_STDBY_ADC__PRE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_A1_STANDBY 0x2 +#define IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE 0x2 +#define IQM_AF_STDBY_STDBY_ADC_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_AMP__B 2 +#define IQM_AF_STDBY_STDBY_AMP__W 1 +#define IQM_AF_STDBY_STDBY_AMP__M 0x4 +#define IQM_AF_STDBY_STDBY_AMP__PRE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_A1_STANDBY 0x4 +#define IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE 0x4 +#define IQM_AF_STDBY_STDBY_AMP_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_PD__B 3 +#define IQM_AF_STDBY_STDBY_PD__W 1 +#define IQM_AF_STDBY_STDBY_PD__M 0x8 +#define IQM_AF_STDBY_STDBY_PD__PRE 0x0 +#define IQM_AF_STDBY_STDBY_PD_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_PD_A1_STANDBY 0x8 +#define IQM_AF_STDBY_STDBY_PD_A2_ACTIVE 0x8 +#define IQM_AF_STDBY_STDBY_PD_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 +#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY 0x0 + +#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 +#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY 0x0 + +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_AMUX__W 2 +#define IQM_AF_AMUX__M 0x3 +#define IQM_AF_AMUX__PRE 0x0 + +#define IQM_AF_TST_AFEMAIN__A 0x187002E +#define IQM_AF_TST_AFEMAIN__W 8 +#define IQM_AF_TST_AFEMAIN__M 0xFF +#define IQM_AF_TST_AFEMAIN__PRE 0x0 + +#define IQM_RT_RAM__A 0x1880000 + +#define IQM_RT_RAM_DLY__B 0 +#define IQM_RT_RAM_DLY__W 13 +#define IQM_RT_RAM_DLY__M 0x1FFF +#define IQM_RT_RAM_DLY__PRE 0x0 + +#define ORX_COMM_EXEC__A 0x2000000 +#define ORX_COMM_EXEC__W 2 +#define ORX_COMM_EXEC__M 0x3 +#define ORX_COMM_EXEC__PRE 0x0 +#define ORX_COMM_EXEC_STOP 0x0 +#define ORX_COMM_EXEC_ACTIVE 0x1 +#define ORX_COMM_EXEC_HOLD 0x2 + +#define ORX_COMM_STATE__A 0x2000001 +#define ORX_COMM_STATE__W 16 +#define ORX_COMM_STATE__M 0xFFFF +#define ORX_COMM_STATE__PRE 0x0 +#define ORX_COMM_MB__A 0x2000002 +#define ORX_COMM_MB__W 16 +#define ORX_COMM_MB__M 0xFFFF +#define ORX_COMM_MB__PRE 0x0 +#define ORX_COMM_INT_REQ__A 0x2000003 +#define ORX_COMM_INT_REQ__W 16 +#define ORX_COMM_INT_REQ__M 0xFFFF +#define ORX_COMM_INT_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_EQU_REQ__B 0 +#define ORX_COMM_INT_REQ_EQU_REQ__W 1 +#define ORX_COMM_INT_REQ_EQU_REQ__M 0x1 +#define ORX_COMM_INT_REQ_EQU_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_DDC_REQ__B 1 +#define ORX_COMM_INT_REQ_DDC_REQ__W 1 +#define ORX_COMM_INT_REQ_DDC_REQ__M 0x2 +#define ORX_COMM_INT_REQ_DDC_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_FWP_REQ__B 2 +#define ORX_COMM_INT_REQ_FWP_REQ__W 1 +#define ORX_COMM_INT_REQ_FWP_REQ__M 0x4 +#define ORX_COMM_INT_REQ_FWP_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_CON_REQ__B 3 +#define ORX_COMM_INT_REQ_CON_REQ__W 1 +#define ORX_COMM_INT_REQ_CON_REQ__M 0x8 +#define ORX_COMM_INT_REQ_CON_REQ__PRE 0x0 +#define ORX_COMM_INT_REQ_NSU_REQ__B 4 +#define ORX_COMM_INT_REQ_NSU_REQ__W 1 +#define ORX_COMM_INT_REQ_NSU_REQ__M 0x10 +#define ORX_COMM_INT_REQ_NSU_REQ__PRE 0x0 + +#define ORX_COMM_INT_STA__A 0x2000005 +#define ORX_COMM_INT_STA__W 16 +#define ORX_COMM_INT_STA__M 0xFFFF +#define ORX_COMM_INT_STA__PRE 0x0 +#define ORX_COMM_INT_MSK__A 0x2000006 +#define ORX_COMM_INT_MSK__W 16 +#define ORX_COMM_INT_MSK__M 0xFFFF +#define ORX_COMM_INT_MSK__PRE 0x0 +#define ORX_COMM_INT_STM__A 0x2000007 +#define ORX_COMM_INT_STM__W 16 +#define ORX_COMM_INT_STM__M 0xFFFF +#define ORX_COMM_INT_STM__PRE 0x0 + +#define ORX_TOP_COMM_EXEC__A 0x2010000 +#define ORX_TOP_COMM_EXEC__W 2 +#define ORX_TOP_COMM_EXEC__M 0x3 +#define ORX_TOP_COMM_EXEC__PRE 0x0 +#define ORX_TOP_COMM_EXEC_STOP 0x0 +#define ORX_TOP_COMM_EXEC_ACTIVE 0x1 +#define ORX_TOP_COMM_EXEC_HOLD 0x2 + +#define ORX_TOP_COMM_KEY__A 0x201000F +#define ORX_TOP_COMM_KEY__W 16 +#define ORX_TOP_COMM_KEY__M 0xFFFF +#define ORX_TOP_COMM_KEY__PRE 0x0 +#define ORX_TOP_COMM_KEY_KEY 0xFABA + +#define ORX_TOP_MDE_W__A 0x2010010 +#define ORX_TOP_MDE_W__W 2 +#define ORX_TOP_MDE_W__M 0x3 +#define ORX_TOP_MDE_W__PRE 0x2 +#define ORX_TOP_MDE_W_RATE_1544KBPS 0x0 +#define ORX_TOP_MDE_W_RATE_3088KBPS 0x1 +#define ORX_TOP_MDE_W_RATE_2048KBPS_SQRT 0x2 +#define ORX_TOP_MDE_W_RATE_2048KBPS_RO 0x3 + +#define ORX_TOP_AIF_CTRL_W__A 0x2010011 +#define ORX_TOP_AIF_CTRL_W__W 3 +#define ORX_TOP_AIF_CTRL_W__M 0x7 +#define ORX_TOP_AIF_CTRL_W__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B 0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W 1 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M 0x1 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE 0x0 +#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE 0x1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B 1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W 1 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M 0x2 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC 0x0 +#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC 0x2 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__B 2 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__W 1 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__M 0x4 +#define ORX_TOP_AIF_CTRL_W_INV_MSB__PRE 0x0 +#define ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC 0x0 +#define ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC 0x4 + +#define ORX_FWP_COMM_EXEC__A 0x2020000 +#define ORX_FWP_COMM_EXEC__W 2 +#define ORX_FWP_COMM_EXEC__M 0x3 +#define ORX_FWP_COMM_EXEC__PRE 0x0 +#define ORX_FWP_COMM_EXEC_STOP 0x0 +#define ORX_FWP_COMM_EXEC_ACTIVE 0x1 +#define ORX_FWP_COMM_EXEC_HOLD 0x2 + +#define ORX_FWP_COMM_MB__A 0x2020002 +#define ORX_FWP_COMM_MB__W 8 +#define ORX_FWP_COMM_MB__M 0xFF +#define ORX_FWP_COMM_MB__PRE 0x0 +#define ORX_FWP_COMM_MB_CTL__B 0 +#define ORX_FWP_COMM_MB_CTL__W 1 +#define ORX_FWP_COMM_MB_CTL__M 0x1 +#define ORX_FWP_COMM_MB_CTL__PRE 0x0 +#define ORX_FWP_COMM_MB_CTL_OFF 0x0 +#define ORX_FWP_COMM_MB_CTL_ON 0x1 +#define ORX_FWP_COMM_MB_OBS__B 1 +#define ORX_FWP_COMM_MB_OBS__W 1 +#define ORX_FWP_COMM_MB_OBS__M 0x2 +#define ORX_FWP_COMM_MB_OBS__PRE 0x0 +#define ORX_FWP_COMM_MB_OBS_OFF 0x0 +#define ORX_FWP_COMM_MB_OBS_ON 0x2 + +#define ORX_FWP_COMM_MB_CTL_MUX__B 2 +#define ORX_FWP_COMM_MB_CTL_MUX__W 3 +#define ORX_FWP_COMM_MB_CTL_MUX__M 0x1C +#define ORX_FWP_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_FWP_COMM_MB_OBS_MUX__B 5 +#define ORX_FWP_COMM_MB_OBS_MUX__W 3 +#define ORX_FWP_COMM_MB_OBS_MUX__M 0xE0 +#define ORX_FWP_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_FWP_AAG_LEN_W__A 0x2020010 +#define ORX_FWP_AAG_LEN_W__W 16 +#define ORX_FWP_AAG_LEN_W__M 0xFFFF +#define ORX_FWP_AAG_LEN_W__PRE 0x800 + +#define ORX_FWP_AAG_THR_W__A 0x2020011 +#define ORX_FWP_AAG_THR_W__W 8 +#define ORX_FWP_AAG_THR_W__M 0xFF +#define ORX_FWP_AAG_THR_W__PRE 0x50 + +#define ORX_FWP_AAG_THR_CNT_R__A 0x2020012 +#define ORX_FWP_AAG_THR_CNT_R__W 16 +#define ORX_FWP_AAG_THR_CNT_R__M 0xFFFF +#define ORX_FWP_AAG_THR_CNT_R__PRE 0x0 + +#define ORX_FWP_AAG_SNS_CNT_R__A 0x2020013 +#define ORX_FWP_AAG_SNS_CNT_R__W 16 +#define ORX_FWP_AAG_SNS_CNT_R__M 0xFFFF +#define ORX_FWP_AAG_SNS_CNT_R__PRE 0x0 + +#define ORX_FWP_PFI_A_W__A 0x2020014 +#define ORX_FWP_PFI_A_W__W 8 +#define ORX_FWP_PFI_A_W__M 0xFF +#define ORX_FWP_PFI_A_W__PRE 0xB0 +#define ORX_FWP_PFI_A_W_RATE_2048KBPS 0xB0 +#define ORX_FWP_PFI_A_W_RATE_1544KBPS 0xA4 +#define ORX_FWP_PFI_A_W_RATE_3088KBPS 0xC0 + +#define ORX_FWP_PFI_B_W__A 0x2020015 +#define ORX_FWP_PFI_B_W__W 8 +#define ORX_FWP_PFI_B_W__M 0xFF +#define ORX_FWP_PFI_B_W__PRE 0x9E +#define ORX_FWP_PFI_B_W_RATE_2048KBPS 0x9E +#define ORX_FWP_PFI_B_W_RATE_1544KBPS 0x94 +#define ORX_FWP_PFI_B_W_RATE_3088KBPS 0xB0 + +#define ORX_FWP_PFI_C_W__A 0x2020016 +#define ORX_FWP_PFI_C_W__W 8 +#define ORX_FWP_PFI_C_W__M 0xFF +#define ORX_FWP_PFI_C_W__PRE 0x5C +#define ORX_FWP_PFI_C_W_RATE_2048KBPS 0x5C +#define ORX_FWP_PFI_C_W_RATE_1544KBPS 0x64 +#define ORX_FWP_PFI_C_W_RATE_3088KBPS 0x50 + +#define ORX_FWP_KR1_AMP_R__A 0x2020017 +#define ORX_FWP_KR1_AMP_R__W 9 +#define ORX_FWP_KR1_AMP_R__M 0x1FF +#define ORX_FWP_KR1_AMP_R__PRE 0x0 + +#define ORX_FWP_KR1_LDT_W__A 0x2020018 +#define ORX_FWP_KR1_LDT_W__W 3 +#define ORX_FWP_KR1_LDT_W__M 0x7 +#define ORX_FWP_KR1_LDT_W__PRE 0x2 +#define ORX_FWP_SRC_DGN_W__A 0x2020019 +#define ORX_FWP_SRC_DGN_W__W 16 +#define ORX_FWP_SRC_DGN_W__M 0xFFFF +#define ORX_FWP_SRC_DGN_W__PRE 0x1FF + +#define ORX_FWP_SRC_DGN_W_MANT__B 0 +#define ORX_FWP_SRC_DGN_W_MANT__W 9 +#define ORX_FWP_SRC_DGN_W_MANT__M 0x1FF +#define ORX_FWP_SRC_DGN_W_MANT__PRE 0x1FF + +#define ORX_FWP_SRC_DGN_W_EXP__B 12 +#define ORX_FWP_SRC_DGN_W_EXP__W 4 +#define ORX_FWP_SRC_DGN_W_EXP__M 0xF000 +#define ORX_FWP_SRC_DGN_W_EXP__PRE 0x0 + +#define ORX_FWP_NYQ_ADR_W__A 0x202001A +#define ORX_FWP_NYQ_ADR_W__W 5 +#define ORX_FWP_NYQ_ADR_W__M 0x1F +#define ORX_FWP_NYQ_ADR_W__PRE 0x1F + +#define ORX_FWP_NYQ_COF_RW__A 0x202001B +#define ORX_FWP_NYQ_COF_RW__W 10 +#define ORX_FWP_NYQ_COF_RW__M 0x3FF +#define ORX_FWP_NYQ_COF_RW__PRE 0x0 + +#define ORX_FWP_IQM_FRQ_W__A 0x202001C +#define ORX_FWP_IQM_FRQ_W__W 16 +#define ORX_FWP_IQM_FRQ_W__M 0xFFFF +#define ORX_FWP_IQM_FRQ_W__PRE 0x4301 + +#define ORX_EQU_COMM_EXEC__A 0x2030000 +#define ORX_EQU_COMM_EXEC__W 2 +#define ORX_EQU_COMM_EXEC__M 0x3 +#define ORX_EQU_COMM_EXEC__PRE 0x0 +#define ORX_EQU_COMM_EXEC_STOP 0x0 +#define ORX_EQU_COMM_EXEC_ACTIVE 0x1 +#define ORX_EQU_COMM_EXEC_HOLD 0x2 + +#define ORX_EQU_COMM_MB__A 0x2030002 +#define ORX_EQU_COMM_MB__W 8 +#define ORX_EQU_COMM_MB__M 0xFF +#define ORX_EQU_COMM_MB__PRE 0x0 +#define ORX_EQU_COMM_MB_CTL__B 0 +#define ORX_EQU_COMM_MB_CTL__W 1 +#define ORX_EQU_COMM_MB_CTL__M 0x1 +#define ORX_EQU_COMM_MB_CTL__PRE 0x0 +#define ORX_EQU_COMM_MB_CTL_OFF 0x0 +#define ORX_EQU_COMM_MB_CTL_ON 0x1 +#define ORX_EQU_COMM_MB_OBS__B 1 +#define ORX_EQU_COMM_MB_OBS__W 1 +#define ORX_EQU_COMM_MB_OBS__M 0x2 +#define ORX_EQU_COMM_MB_OBS__PRE 0x0 +#define ORX_EQU_COMM_MB_OBS_OFF 0x0 +#define ORX_EQU_COMM_MB_OBS_ON 0x2 + +#define ORX_EQU_COMM_MB_CTL_MUX__B 2 +#define ORX_EQU_COMM_MB_CTL_MUX__W 3 +#define ORX_EQU_COMM_MB_CTL_MUX__M 0x1C +#define ORX_EQU_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_EQU_COMM_MB_OBS_MUX__B 5 +#define ORX_EQU_COMM_MB_OBS_MUX__W 3 +#define ORX_EQU_COMM_MB_OBS_MUX__M 0xE0 +#define ORX_EQU_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_EQU_COMM_INT_REQ__A 0x2030003 +#define ORX_EQU_COMM_INT_REQ__W 1 +#define ORX_EQU_COMM_INT_REQ__M 0x1 +#define ORX_EQU_COMM_INT_REQ__PRE 0x0 +#define ORX_EQU_COMM_INT_STA__A 0x2030005 +#define ORX_EQU_COMM_INT_STA__W 2 +#define ORX_EQU_COMM_INT_STA__M 0x3 +#define ORX_EQU_COMM_INT_STA__PRE 0x0 + +#define ORX_EQU_COMM_INT_STA_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_STA_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_STA_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_STA_FFF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_STA_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_STA_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_STA_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_STA_FBF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_MSK__A 0x2030006 +#define ORX_EQU_COMM_INT_MSK__W 2 +#define ORX_EQU_COMM_INT_MSK__M 0x3 +#define ORX_EQU_COMM_INT_MSK__PRE 0x0 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_MSK_FFF_READ__PRE 0x0 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_MSK_FBF_READ__PRE 0x0 + +#define ORX_EQU_COMM_INT_STM__A 0x2030007 +#define ORX_EQU_COMM_INT_STM__W 2 +#define ORX_EQU_COMM_INT_STM__M 0x3 +#define ORX_EQU_COMM_INT_STM__PRE 0x0 +#define ORX_EQU_COMM_INT_STM_FFF_READ__B 0 +#define ORX_EQU_COMM_INT_STM_FFF_READ__W 1 +#define ORX_EQU_COMM_INT_STM_FFF_READ__M 0x1 +#define ORX_EQU_COMM_INT_STM_FFF_READ__PRE 0x0 +#define ORX_EQU_COMM_INT_STM_FBF_READ__B 1 +#define ORX_EQU_COMM_INT_STM_FBF_READ__W 1 +#define ORX_EQU_COMM_INT_STM_FBF_READ__M 0x2 +#define ORX_EQU_COMM_INT_STM_FBF_READ__PRE 0x0 + +#define ORX_EQU_FFF_SCL_W__A 0x2030010 +#define ORX_EQU_FFF_SCL_W__W 1 +#define ORX_EQU_FFF_SCL_W__M 0x1 +#define ORX_EQU_FFF_SCL_W__PRE 0x0 +#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_1 0x0 +#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_2 0x1 + +#define ORX_EQU_FFF_UPD_W__A 0x2030011 +#define ORX_EQU_FFF_UPD_W__W 1 +#define ORX_EQU_FFF_UPD_W__M 0x1 +#define ORX_EQU_FFF_UPD_W__PRE 0x0 +#define ORX_EQU_FFF_UPD_W_NO_UPDATE 0x0 +#define ORX_EQU_FFF_UPD_W_LMS_UPDATE 0x1 + +#define ORX_EQU_FFF_STP_W__A 0x2030012 +#define ORX_EQU_FFF_STP_W__W 3 +#define ORX_EQU_FFF_STP_W__M 0x7 +#define ORX_EQU_FFF_STP_W__PRE 0x2 + +#define ORX_EQU_FFF_LEA_W__A 0x2030013 +#define ORX_EQU_FFF_LEA_W__W 4 +#define ORX_EQU_FFF_LEA_W__M 0xF +#define ORX_EQU_FFF_LEA_W__PRE 0x4 + +#define ORX_EQU_FFF_RWT_W__A 0x2030014 +#define ORX_EQU_FFF_RWT_W__W 2 +#define ORX_EQU_FFF_RWT_W__M 0x3 +#define ORX_EQU_FFF_RWT_W__PRE 0x0 + +#define ORX_EQU_FFF_C0RE_RW__A 0x2030015 +#define ORX_EQU_FFF_C0RE_RW__W 12 +#define ORX_EQU_FFF_C0RE_RW__M 0xFFF +#define ORX_EQU_FFF_C0RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C0IM_RW__A 0x2030016 +#define ORX_EQU_FFF_C0IM_RW__W 12 +#define ORX_EQU_FFF_C0IM_RW__M 0xFFF +#define ORX_EQU_FFF_C0IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C1RE_RW__A 0x2030017 +#define ORX_EQU_FFF_C1RE_RW__W 12 +#define ORX_EQU_FFF_C1RE_RW__M 0xFFF +#define ORX_EQU_FFF_C1RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C1IM_RW__A 0x2030018 +#define ORX_EQU_FFF_C1IM_RW__W 12 +#define ORX_EQU_FFF_C1IM_RW__M 0xFFF +#define ORX_EQU_FFF_C1IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C2RE_RW__A 0x2030019 +#define ORX_EQU_FFF_C2RE_RW__W 12 +#define ORX_EQU_FFF_C2RE_RW__M 0xFFF +#define ORX_EQU_FFF_C2RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C2IM_RW__A 0x203001A +#define ORX_EQU_FFF_C2IM_RW__W 12 +#define ORX_EQU_FFF_C2IM_RW__M 0xFFF +#define ORX_EQU_FFF_C2IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C3RE_RW__A 0x203001B +#define ORX_EQU_FFF_C3RE_RW__W 12 +#define ORX_EQU_FFF_C3RE_RW__M 0xFFF +#define ORX_EQU_FFF_C3RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C3IM_RW__A 0x203001C +#define ORX_EQU_FFF_C3IM_RW__W 12 +#define ORX_EQU_FFF_C3IM_RW__M 0xFFF +#define ORX_EQU_FFF_C3IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C4RE_RW__A 0x203001D +#define ORX_EQU_FFF_C4RE_RW__W 12 +#define ORX_EQU_FFF_C4RE_RW__M 0xFFF +#define ORX_EQU_FFF_C4RE_RW__PRE 0x400 + +#define ORX_EQU_FFF_C4IM_RW__A 0x203001E +#define ORX_EQU_FFF_C4IM_RW__W 12 +#define ORX_EQU_FFF_C4IM_RW__M 0xFFF +#define ORX_EQU_FFF_C4IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C5RE_RW__A 0x203001F +#define ORX_EQU_FFF_C5RE_RW__W 12 +#define ORX_EQU_FFF_C5RE_RW__M 0xFFF +#define ORX_EQU_FFF_C5RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C5IM_RW__A 0x2030020 +#define ORX_EQU_FFF_C5IM_RW__W 12 +#define ORX_EQU_FFF_C5IM_RW__M 0xFFF +#define ORX_EQU_FFF_C5IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C6RE_RW__A 0x2030021 +#define ORX_EQU_FFF_C6RE_RW__W 12 +#define ORX_EQU_FFF_C6RE_RW__M 0xFFF +#define ORX_EQU_FFF_C6RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C6IM_RW__A 0x2030022 +#define ORX_EQU_FFF_C6IM_RW__W 12 +#define ORX_EQU_FFF_C6IM_RW__M 0xFFF +#define ORX_EQU_FFF_C6IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C7RE_RW__A 0x2030023 +#define ORX_EQU_FFF_C7RE_RW__W 12 +#define ORX_EQU_FFF_C7RE_RW__M 0xFFF +#define ORX_EQU_FFF_C7RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C7IM_RW__A 0x2030024 +#define ORX_EQU_FFF_C7IM_RW__W 12 +#define ORX_EQU_FFF_C7IM_RW__M 0xFFF +#define ORX_EQU_FFF_C7IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C8RE_RW__A 0x2030025 +#define ORX_EQU_FFF_C8RE_RW__W 12 +#define ORX_EQU_FFF_C8RE_RW__M 0xFFF +#define ORX_EQU_FFF_C8RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C8IM_RW__A 0x2030026 +#define ORX_EQU_FFF_C8IM_RW__W 12 +#define ORX_EQU_FFF_C8IM_RW__M 0xFFF +#define ORX_EQU_FFF_C8IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C9RE_RW__A 0x2030027 +#define ORX_EQU_FFF_C9RE_RW__W 12 +#define ORX_EQU_FFF_C9RE_RW__M 0xFFF +#define ORX_EQU_FFF_C9RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C9IM_RW__A 0x2030028 +#define ORX_EQU_FFF_C9IM_RW__W 12 +#define ORX_EQU_FFF_C9IM_RW__M 0xFFF +#define ORX_EQU_FFF_C9IM_RW__PRE 0x0 + +#define ORX_EQU_FFF_C10RE_RW__A 0x2030029 +#define ORX_EQU_FFF_C10RE_RW__W 12 +#define ORX_EQU_FFF_C10RE_RW__M 0xFFF +#define ORX_EQU_FFF_C10RE_RW__PRE 0x0 + +#define ORX_EQU_FFF_C10IM_RW__A 0x203002A +#define ORX_EQU_FFF_C10IM_RW__W 12 +#define ORX_EQU_FFF_C10IM_RW__M 0xFFF +#define ORX_EQU_FFF_C10IM_RW__PRE 0x0 + +#define ORX_EQU_MXB_SEL_W__A 0x203002B +#define ORX_EQU_MXB_SEL_W__W 1 +#define ORX_EQU_MXB_SEL_W__M 0x1 +#define ORX_EQU_MXB_SEL_W__PRE 0x0 +#define ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS 0x0 +#define ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS 0x1 + +#define ORX_EQU_FBF_UPD_W__A 0x203002C +#define ORX_EQU_FBF_UPD_W__W 1 +#define ORX_EQU_FBF_UPD_W__M 0x1 +#define ORX_EQU_FBF_UPD_W__PRE 0x0 +#define ORX_EQU_FBF_UPD_W_NO_UPDATE 0x0 +#define ORX_EQU_FBF_UPD_W_LMS_UPDATE 0x1 + +#define ORX_EQU_FBF_STP_W__A 0x203002D +#define ORX_EQU_FBF_STP_W__W 3 +#define ORX_EQU_FBF_STP_W__M 0x7 +#define ORX_EQU_FBF_STP_W__PRE 0x2 + +#define ORX_EQU_FBF_LEA_W__A 0x203002E +#define ORX_EQU_FBF_LEA_W__W 4 +#define ORX_EQU_FBF_LEA_W__M 0xF +#define ORX_EQU_FBF_LEA_W__PRE 0x4 + +#define ORX_EQU_FBF_RWT_W__A 0x203002F +#define ORX_EQU_FBF_RWT_W__W 2 +#define ORX_EQU_FBF_RWT_W__M 0x3 +#define ORX_EQU_FBF_RWT_W__PRE 0x0 + +#define ORX_EQU_FBF_C0RE_RW__A 0x2030030 +#define ORX_EQU_FBF_C0RE_RW__W 12 +#define ORX_EQU_FBF_C0RE_RW__M 0xFFF +#define ORX_EQU_FBF_C0RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C0IM_RW__A 0x2030031 +#define ORX_EQU_FBF_C0IM_RW__W 12 +#define ORX_EQU_FBF_C0IM_RW__M 0xFFF +#define ORX_EQU_FBF_C0IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C1RE_RW__A 0x2030032 +#define ORX_EQU_FBF_C1RE_RW__W 12 +#define ORX_EQU_FBF_C1RE_RW__M 0xFFF +#define ORX_EQU_FBF_C1RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C1IM_RW__A 0x2030033 +#define ORX_EQU_FBF_C1IM_RW__W 12 +#define ORX_EQU_FBF_C1IM_RW__M 0xFFF +#define ORX_EQU_FBF_C1IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C2RE_RW__A 0x2030034 +#define ORX_EQU_FBF_C2RE_RW__W 12 +#define ORX_EQU_FBF_C2RE_RW__M 0xFFF +#define ORX_EQU_FBF_C2RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C2IM_RW__A 0x2030035 +#define ORX_EQU_FBF_C2IM_RW__W 12 +#define ORX_EQU_FBF_C2IM_RW__M 0xFFF +#define ORX_EQU_FBF_C2IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C3RE_RW__A 0x2030036 +#define ORX_EQU_FBF_C3RE_RW__W 12 +#define ORX_EQU_FBF_C3RE_RW__M 0xFFF +#define ORX_EQU_FBF_C3RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C3IM_RW__A 0x2030037 +#define ORX_EQU_FBF_C3IM_RW__W 12 +#define ORX_EQU_FBF_C3IM_RW__M 0xFFF +#define ORX_EQU_FBF_C3IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C4RE_RW__A 0x2030038 +#define ORX_EQU_FBF_C4RE_RW__W 12 +#define ORX_EQU_FBF_C4RE_RW__M 0xFFF +#define ORX_EQU_FBF_C4RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C4IM_RW__A 0x2030039 +#define ORX_EQU_FBF_C4IM_RW__W 12 +#define ORX_EQU_FBF_C4IM_RW__M 0xFFF +#define ORX_EQU_FBF_C4IM_RW__PRE 0x0 + +#define ORX_EQU_FBF_C5RE_RW__A 0x203003A +#define ORX_EQU_FBF_C5RE_RW__W 12 +#define ORX_EQU_FBF_C5RE_RW__M 0xFFF +#define ORX_EQU_FBF_C5RE_RW__PRE 0x0 + +#define ORX_EQU_FBF_C5IM_RW__A 0x203003B +#define ORX_EQU_FBF_C5IM_RW__W 12 +#define ORX_EQU_FBF_C5IM_RW__M 0xFFF +#define ORX_EQU_FBF_C5IM_RW__PRE 0x0 + +#define ORX_EQU_ERR_SEL_W__A 0x203003C +#define ORX_EQU_ERR_SEL_W__W 1 +#define ORX_EQU_ERR_SEL_W__M 0x1 +#define ORX_EQU_ERR_SEL_W__PRE 0x0 +#define ORX_EQU_ERR_SEL_W_CMA_ERROR 0x0 +#define ORX_EQU_ERR_SEL_W_DDA_ERROR 0x1 + +#define ORX_EQU_ERR_TIS_W__A 0x203003D +#define ORX_EQU_ERR_TIS_W__W 1 +#define ORX_EQU_ERR_TIS_W__M 0x1 +#define ORX_EQU_ERR_TIS_W__PRE 0x0 +#define ORX_EQU_ERR_TIS_W_CMA_SIGNALS 0x0 +#define ORX_EQU_ERR_TIS_W_DDA_SIGNALS 0x1 + +#define ORX_EQU_ERR_EDI_R__A 0x203003E +#define ORX_EQU_ERR_EDI_R__W 5 +#define ORX_EQU_ERR_EDI_R__M 0x1F +#define ORX_EQU_ERR_EDI_R__PRE 0xF + +#define ORX_EQU_ERR_EDQ_R__A 0x203003F +#define ORX_EQU_ERR_EDQ_R__W 5 +#define ORX_EQU_ERR_EDQ_R__M 0x1F +#define ORX_EQU_ERR_EDQ_R__PRE 0xF + +#define ORX_EQU_ERR_ECI_R__A 0x2030040 +#define ORX_EQU_ERR_ECI_R__W 5 +#define ORX_EQU_ERR_ECI_R__M 0x1F +#define ORX_EQU_ERR_ECI_R__PRE 0xF + +#define ORX_EQU_ERR_ECQ_R__A 0x2030041 +#define ORX_EQU_ERR_ECQ_R__W 5 +#define ORX_EQU_ERR_ECQ_R__M 0x1F +#define ORX_EQU_ERR_ECQ_R__PRE 0xF + +#define ORX_EQU_MER_MER_R__A 0x2030042 +#define ORX_EQU_MER_MER_R__W 6 +#define ORX_EQU_MER_MER_R__M 0x3F +#define ORX_EQU_MER_MER_R__PRE 0x3F + +#define ORX_EQU_MER_LDT_W__A 0x2030043 +#define ORX_EQU_MER_LDT_W__W 3 +#define ORX_EQU_MER_LDT_W__M 0x7 +#define ORX_EQU_MER_LDT_W__PRE 0x4 + +#define ORX_EQU_SYN_LEN_W__A 0x2030044 +#define ORX_EQU_SYN_LEN_W__W 16 +#define ORX_EQU_SYN_LEN_W__M 0xFFFF +#define ORX_EQU_SYN_LEN_W__PRE 0x0 + +#define ORX_DDC_COMM_EXEC__A 0x2040000 +#define ORX_DDC_COMM_EXEC__W 2 +#define ORX_DDC_COMM_EXEC__M 0x3 +#define ORX_DDC_COMM_EXEC__PRE 0x0 +#define ORX_DDC_COMM_EXEC_STOP 0x0 +#define ORX_DDC_COMM_EXEC_ACTIVE 0x1 +#define ORX_DDC_COMM_EXEC_HOLD 0x2 + +#define ORX_DDC_COMM_MB__A 0x2040002 +#define ORX_DDC_COMM_MB__W 6 +#define ORX_DDC_COMM_MB__M 0x3F +#define ORX_DDC_COMM_MB__PRE 0x0 +#define ORX_DDC_COMM_MB_CTL__B 0 +#define ORX_DDC_COMM_MB_CTL__W 1 +#define ORX_DDC_COMM_MB_CTL__M 0x1 +#define ORX_DDC_COMM_MB_CTL__PRE 0x0 +#define ORX_DDC_COMM_MB_CTL_OFF 0x0 +#define ORX_DDC_COMM_MB_CTL_ON 0x1 +#define ORX_DDC_COMM_MB_OBS__B 1 +#define ORX_DDC_COMM_MB_OBS__W 1 +#define ORX_DDC_COMM_MB_OBS__M 0x2 +#define ORX_DDC_COMM_MB_OBS__PRE 0x0 +#define ORX_DDC_COMM_MB_OBS_OFF 0x0 +#define ORX_DDC_COMM_MB_OBS_ON 0x2 + +#define ORX_DDC_COMM_MB_CTL_MUX__B 2 +#define ORX_DDC_COMM_MB_CTL_MUX__W 2 +#define ORX_DDC_COMM_MB_CTL_MUX__M 0xC +#define ORX_DDC_COMM_MB_CTL_MUX__PRE 0x0 + +#define ORX_DDC_COMM_MB_OBS_MUX__B 4 +#define ORX_DDC_COMM_MB_OBS_MUX__W 2 +#define ORX_DDC_COMM_MB_OBS_MUX__M 0x30 +#define ORX_DDC_COMM_MB_OBS_MUX__PRE 0x0 + +#define ORX_DDC_COMM_INT_REQ__A 0x2040003 +#define ORX_DDC_COMM_INT_REQ__W 1 +#define ORX_DDC_COMM_INT_REQ__M 0x1 +#define ORX_DDC_COMM_INT_REQ__PRE 0x0 +#define ORX_DDC_COMM_INT_STA__A 0x2040005 +#define ORX_DDC_COMM_INT_STA__W 1 +#define ORX_DDC_COMM_INT_STA__M 0x1 +#define ORX_DDC_COMM_INT_STA__PRE 0x0 +#define ORX_DDC_COMM_INT_MSK__A 0x2040006 +#define ORX_DDC_COMM_INT_MSK__W 1 +#define ORX_DDC_COMM_INT_MSK__M 0x1 +#define ORX_DDC_COMM_INT_MSK__PRE 0x0 +#define ORX_DDC_COMM_INT_STM__A 0x2040007 +#define ORX_DDC_COMM_INT_STM__W 1 +#define ORX_DDC_COMM_INT_STM__M 0x1 +#define ORX_DDC_COMM_INT_STM__PRE 0x0 +#define ORX_DDC_DEC_MAP_W__A 0x2040010 +#define ORX_DDC_DEC_MAP_W__W 9 +#define ORX_DDC_DEC_MAP_W__M 0x1FF +#define ORX_DDC_DEC_MAP_W__PRE 0x178 + +#define ORX_DDC_DEC_MAP_W_QUADR0__B 0 +#define ORX_DDC_DEC_MAP_W_QUADR0__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR0__M 0x3 +#define ORX_DDC_DEC_MAP_W_QUADR0__PRE 0x0 +#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_DEFAULT 0x0 +#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE 0x0 + +#define ORX_DDC_DEC_MAP_W_QUADR1__B 2 +#define ORX_DDC_DEC_MAP_W_QUADR1__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR1__M 0xC +#define ORX_DDC_DEC_MAP_W_QUADR1__PRE 0x8 +#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT 0x8 +#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE 0x4 + +#define ORX_DDC_DEC_MAP_W_QUADR2__B 4 +#define ORX_DDC_DEC_MAP_W_QUADR2__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR2__M 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2__PRE 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT 0x30 +#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE 0x30 + +#define ORX_DDC_DEC_MAP_W_QUADR3__B 6 +#define ORX_DDC_DEC_MAP_W_QUADR3__W 2 +#define ORX_DDC_DEC_MAP_W_QUADR3__M 0xC0 +#define ORX_DDC_DEC_MAP_W_QUADR3__PRE 0x40 +#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT 0x40 +#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE 0x80 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__B 8 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__W 1 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__M 0x100 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__PRE 0x100 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING 0x0 +#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING 0x100 + +#define ORX_DDC_OFO_SET_W__A 0x2040011 +#define ORX_DDC_OFO_SET_W__W 16 +#define ORX_DDC_OFO_SET_W__M 0xFFFF +#define ORX_DDC_OFO_SET_W__PRE 0x1402 + +#define ORX_DDC_OFO_SET_W_PHASE__B 0 +#define ORX_DDC_OFO_SET_W_PHASE__W 7 +#define ORX_DDC_OFO_SET_W_PHASE__M 0x7F +#define ORX_DDC_OFO_SET_W_PHASE__PRE 0x2 + +#define ORX_DDC_OFO_SET_W_CRXHITIME__B 7 +#define ORX_DDC_OFO_SET_W_CRXHITIME__W 7 +#define ORX_DDC_OFO_SET_W_CRXHITIME__M 0x3F80 +#define ORX_DDC_OFO_SET_W_CRXHITIME__PRE 0x1400 + +#define ORX_DDC_OFO_SET_W_CRXINV__B 14 +#define ORX_DDC_OFO_SET_W_CRXINV__W 1 +#define ORX_DDC_OFO_SET_W_CRXINV__M 0x4000 +#define ORX_DDC_OFO_SET_W_CRXINV__PRE 0x0 + +#define ORX_DDC_OFO_SET_W_DISABLE__B 15 +#define ORX_DDC_OFO_SET_W_DISABLE__W 1 +#define ORX_DDC_OFO_SET_W_DISABLE__M 0x8000 +#define ORX_DDC_OFO_SET_W_DISABLE__PRE 0x0 + +#define ORX_CON_COMM_EXEC__A 0x2050000 +#define ORX_CON_COMM_EXEC__W 2 +#define ORX_CON_COMM_EXEC__M 0x3 +#define ORX_CON_COMM_EXEC__PRE 0x0 +#define ORX_CON_COMM_EXEC_STOP 0x0 +#define ORX_CON_COMM_EXEC_ACTIVE 0x1 +#define ORX_CON_COMM_EXEC_HOLD 0x2 + +#define ORX_CON_LDT_W__A 0x2050010 +#define ORX_CON_LDT_W__W 3 +#define ORX_CON_LDT_W__M 0x7 +#define ORX_CON_LDT_W__PRE 0x3 + +#define ORX_CON_LDT_W_CON_LDT_W__B 0 +#define ORX_CON_LDT_W_CON_LDT_W__W 3 +#define ORX_CON_LDT_W_CON_LDT_W__M 0x7 +#define ORX_CON_LDT_W_CON_LDT_W__PRE 0x3 + +#define ORX_CON_RST_W__A 0x2050011 +#define ORX_CON_RST_W__W 4 +#define ORX_CON_RST_W__M 0xF +#define ORX_CON_RST_W__PRE 0x0 + +#define ORX_CON_RST_W_CPH__B 0 +#define ORX_CON_RST_W_CPH__W 1 +#define ORX_CON_RST_W_CPH__M 0x1 +#define ORX_CON_RST_W_CPH__PRE 0x0 + +#define ORX_CON_RST_W_CTI__B 1 +#define ORX_CON_RST_W_CTI__W 1 +#define ORX_CON_RST_W_CTI__M 0x2 +#define ORX_CON_RST_W_CTI__PRE 0x0 + +#define ORX_CON_RST_W_KRN__B 2 +#define ORX_CON_RST_W_KRN__W 1 +#define ORX_CON_RST_W_KRN__M 0x4 +#define ORX_CON_RST_W_KRN__PRE 0x0 + +#define ORX_CON_RST_W_KRP__B 3 +#define ORX_CON_RST_W_KRP__W 1 +#define ORX_CON_RST_W_KRP__M 0x8 +#define ORX_CON_RST_W_KRP__PRE 0x0 + +#define ORX_CON_CPH_PHI_R__A 0x2050012 +#define ORX_CON_CPH_PHI_R__W 16 +#define ORX_CON_CPH_PHI_R__M 0xFFFF +#define ORX_CON_CPH_PHI_R__PRE 0x0 + +#define ORX_CON_CPH_FRQ_R__A 0x2050013 +#define ORX_CON_CPH_FRQ_R__W 16 +#define ORX_CON_CPH_FRQ_R__M 0xFFFF +#define ORX_CON_CPH_FRQ_R__PRE 0x0 + +#define ORX_CON_CPH_AMP_R__A 0x2050014 +#define ORX_CON_CPH_AMP_R__W 16 +#define ORX_CON_CPH_AMP_R__M 0xFFFF +#define ORX_CON_CPH_AMP_R__PRE 0x0 + +#define ORX_CON_CPH_KDF_W__A 0x2050015 +#define ORX_CON_CPH_KDF_W__W 4 +#define ORX_CON_CPH_KDF_W__M 0xF +#define ORX_CON_CPH_KDF_W__PRE 0x0 + +#define ORX_CON_CPH_KPF_W__A 0x2050016 +#define ORX_CON_CPH_KPF_W__W 4 +#define ORX_CON_CPH_KPF_W__M 0xF +#define ORX_CON_CPH_KPF_W__PRE 0x0 + +#define ORX_CON_CPH_KIF_W__A 0x2050017 +#define ORX_CON_CPH_KIF_W__W 4 +#define ORX_CON_CPH_KIF_W__M 0xF +#define ORX_CON_CPH_KIF_W__PRE 0x0 +#define ORX_CON_CPH_APT_W__A 0x2050018 +#define ORX_CON_CPH_APT_W__W 16 +#define ORX_CON_CPH_APT_W__M 0xFFFF +#define ORX_CON_CPH_APT_W__PRE 0x804 + +#define ORX_CON_CPH_APT_W_PTH__B 0 +#define ORX_CON_CPH_APT_W_PTH__W 8 +#define ORX_CON_CPH_APT_W_PTH__M 0xFF +#define ORX_CON_CPH_APT_W_PTH__PRE 0x4 + +#define ORX_CON_CPH_APT_W_ATH__B 8 +#define ORX_CON_CPH_APT_W_ATH__W 8 +#define ORX_CON_CPH_APT_W_ATH__M 0xFF00 +#define ORX_CON_CPH_APT_W_ATH__PRE 0x800 + +#define ORX_CON_CPH_WLC_W__A 0x2050019 +#define ORX_CON_CPH_WLC_W__W 8 +#define ORX_CON_CPH_WLC_W__M 0xFF +#define ORX_CON_CPH_WLC_W__PRE 0x81 + +#define ORX_CON_CPH_WLC_W_LATC__B 0 +#define ORX_CON_CPH_WLC_W_LATC__W 4 +#define ORX_CON_CPH_WLC_W_LATC__M 0xF +#define ORX_CON_CPH_WLC_W_LATC__PRE 0x1 + +#define ORX_CON_CPH_WLC_W_WLIM__B 4 +#define ORX_CON_CPH_WLC_W_WLIM__W 4 +#define ORX_CON_CPH_WLC_W_WLIM__M 0xF0 +#define ORX_CON_CPH_WLC_W_WLIM__PRE 0x80 + +#define ORX_CON_CPH_DLY_W__A 0x205001A +#define ORX_CON_CPH_DLY_W__W 3 +#define ORX_CON_CPH_DLY_W__M 0x7 +#define ORX_CON_CPH_DLY_W__PRE 0x4 + +#define ORX_CON_CPH_TCL_W__A 0x205001B +#define ORX_CON_CPH_TCL_W__W 3 +#define ORX_CON_CPH_TCL_W__M 0x7 +#define ORX_CON_CPH_TCL_W__PRE 0x3 + +#define ORX_CON_KRP_AMP_R__A 0x205001C +#define ORX_CON_KRP_AMP_R__W 9 +#define ORX_CON_KRP_AMP_R__M 0x1FF +#define ORX_CON_KRP_AMP_R__PRE 0x0 + +#define ORX_CON_KRN_AMP_R__A 0x205001D +#define ORX_CON_KRN_AMP_R__W 9 +#define ORX_CON_KRN_AMP_R__M 0x1FF +#define ORX_CON_KRN_AMP_R__PRE 0x0 + +#define ORX_CON_CTI_DTI_R__A 0x205001E +#define ORX_CON_CTI_DTI_R__W 16 +#define ORX_CON_CTI_DTI_R__M 0xFFFF +#define ORX_CON_CTI_DTI_R__PRE 0x0 + +#define ORX_CON_CTI_KDT_W__A 0x205001F +#define ORX_CON_CTI_KDT_W__W 4 +#define ORX_CON_CTI_KDT_W__M 0xF +#define ORX_CON_CTI_KDT_W__PRE 0x4 + +#define ORX_CON_CTI_KPT_W__A 0x2050020 +#define ORX_CON_CTI_KPT_W__W 4 +#define ORX_CON_CTI_KPT_W__M 0xF +#define ORX_CON_CTI_KPT_W__PRE 0x3 + +#define ORX_CON_CTI_KIT_W__A 0x2050021 +#define ORX_CON_CTI_KIT_W__W 4 +#define ORX_CON_CTI_KIT_W__M 0xF +#define ORX_CON_CTI_KIT_W__PRE 0xB + +#define ORX_CON_CTI_TAT_W__A 0x2050022 +#define ORX_CON_CTI_TAT_W__W 4 +#define ORX_CON_CTI_TAT_W__M 0xF +#define ORX_CON_CTI_TAT_W__PRE 0x3 + +#define ORX_NSU_COMM_EXEC__A 0x2060000 +#define ORX_NSU_COMM_EXEC__W 2 +#define ORX_NSU_COMM_EXEC__M 0x3 +#define ORX_NSU_COMM_EXEC__PRE 0x0 +#define ORX_NSU_COMM_EXEC_STOP 0x0 +#define ORX_NSU_COMM_EXEC_ACTIVE 0x1 +#define ORX_NSU_COMM_EXEC_HOLD 0x2 + +#define ORX_NSU_AOX_STDBY_W__A 0x2060010 +#define ORX_NSU_AOX_STDBY_W__W 8 +#define ORX_NSU_AOX_STDBY_W__M 0xFF +#define ORX_NSU_AOX_STDBY_W__PRE 0x0 + +#define ORX_NSU_AOX_STDBY_W_STDBYADC__B 0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__M 0x1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF 0x1 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON 0x1 + +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__B 1 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__M 0x2 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF 0x2 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON 0x2 + +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__B 2 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__M 0x4 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF 0x4 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON 0x4 + +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__B 3 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__M 0x8 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF 0x8 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON 0x8 + +#define ORX_NSU_AOX_STDBY_W_STDBYPD__B 4 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__M 0x10 +#define ORX_NSU_AOX_STDBY_W_STDBYPD__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF 0x10 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON 0x10 + +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B 5 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M 0x20 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF 0x20 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON 0x20 + +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B 6 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M 0x40 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF 0x40 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON 0x40 + +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__B 7 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__W 1 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__M 0x80 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF 0x80 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF 0x0 +#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON 0x80 + +#define ORX_NSU_AOX_LOFRQ_W__A 0x2060011 +#define ORX_NSU_AOX_LOFRQ_W__W 16 +#define ORX_NSU_AOX_LOFRQ_W__M 0xFFFF +#define ORX_NSU_AOX_LOFRQ_W__PRE 0x0 +#define ORX_NSU_AOX_LOMDE_W__A 0x2060012 +#define ORX_NSU_AOX_LOMDE_W__W 16 +#define ORX_NSU_AOX_LOMDE_W__M 0xFFFF +#define ORX_NSU_AOX_LOMDE_W__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B 0 +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W 8 +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M 0xFF +#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__B 13 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__W 1 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__M 0x2000 +#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE 0x0 + +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__B 14 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__W 2 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__M 0xC000 +#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE 0x0 + +#define ORX_NSU_AOX_LOPOW_W__A 0x2060013 +#define ORX_NSU_AOX_LOPOW_W__W 2 +#define ORX_NSU_AOX_LOPOW_W__M 0x3 +#define ORX_NSU_AOX_LOPOW_W__PRE 0x0 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB 0x0 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB 0x1 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB 0x2 +#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB 0x3 + +#define ORX_NSU_AOX_STHR_W__A 0x2060014 +#define ORX_NSU_AOX_STHR_W__W 5 +#define ORX_NSU_AOX_STHR_W__M 0x1F +#define ORX_NSU_AOX_STHR_W__PRE 0x0 + +#define ORX_NSU_TUN_RFGAIN_W__A 0x2060015 +#define ORX_NSU_TUN_RFGAIN_W__W 15 +#define ORX_NSU_TUN_RFGAIN_W__M 0x7FFF +#define ORX_NSU_TUN_RFGAIN_W__PRE 0x0 + +#define ORX_NSU_TUN_IFGAIN_W__A 0x2060016 +#define ORX_NSU_TUN_IFGAIN_W__W 15 +#define ORX_NSU_TUN_IFGAIN_W__M 0x7FFF +#define ORX_NSU_TUN_IFGAIN_W__PRE 0x0 + +#define ORX_NSU_TUN_BPF_W__A 0x2060017 +#define ORX_NSU_TUN_BPF_W__W 15 +#define ORX_NSU_TUN_BPF_W__M 0x7FFF +#define ORX_NSU_TUN_BPF_W__PRE 0x1F9 +#define ORX_NSU_NSS_BITSWAP_W__A 0x2060018 +#define ORX_NSU_NSS_BITSWAP_W__W 3 +#define ORX_NSU_NSS_BITSWAP_W__M 0x7 +#define ORX_NSU_NSS_BITSWAP_W__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B 0 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M 0x1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M 0x2 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE 0x0 + +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B 2 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W 1 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M 0x4 +#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE 0x0 + +#define ORX_TST_COMM_EXEC__A 0x23F0000 +#define ORX_TST_COMM_EXEC__W 2 +#define ORX_TST_COMM_EXEC__M 0x3 +#define ORX_TST_COMM_EXEC__PRE 0x0 +#define ORX_TST_COMM_EXEC_STOP 0x0 +#define ORX_TST_COMM_EXEC_ACTIVE 0x1 +#define ORX_TST_COMM_EXEC_HOLD 0x2 + +#define ORX_TST_AOX_TST_W__A 0x23F0010 +#define ORX_TST_AOX_TST_W__W 8 +#define ORX_TST_AOX_TST_W__M 0xFF +#define ORX_TST_AOX_TST_W__PRE 0x0 + +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__W 2 +#define QAM_COMM_EXEC__M 0x3 +#define QAM_COMM_EXEC__PRE 0x0 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC_ACTIVE 0x1 +#define QAM_COMM_EXEC_HOLD 0x2 + +#define QAM_COMM_MB__A 0x1400002 +#define QAM_COMM_MB__W 16 +#define QAM_COMM_MB__M 0xFFFF +#define QAM_COMM_MB__PRE 0x0 +#define QAM_COMM_INT_REQ__A 0x1400003 +#define QAM_COMM_INT_REQ__W 16 +#define QAM_COMM_INT_REQ__M 0xFFFF +#define QAM_COMM_INT_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SL_REQ__B 0 +#define QAM_COMM_INT_REQ_SL_REQ__W 1 +#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 +#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_LC_REQ__B 1 +#define QAM_COMM_INT_REQ_LC_REQ__W 1 +#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 +#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_VD_REQ__B 2 +#define QAM_COMM_INT_REQ_VD_REQ__W 1 +#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 +#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SY_REQ__B 3 +#define QAM_COMM_INT_REQ_SY_REQ__W 1 +#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 +#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define QAM_COMM_INT_STA__A 0x1400005 +#define QAM_COMM_INT_STA__W 16 +#define QAM_COMM_INT_STA__M 0xFFFF +#define QAM_COMM_INT_STA__PRE 0x0 +#define QAM_COMM_INT_MSK__A 0x1400006 +#define QAM_COMM_INT_MSK__W 16 +#define QAM_COMM_INT_MSK__M 0xFFFF +#define QAM_COMM_INT_MSK__PRE 0x0 +#define QAM_COMM_INT_STM__A 0x1400007 +#define QAM_COMM_INT_STM__W 16 +#define QAM_COMM_INT_STM__M 0xFFFF +#define QAM_COMM_INT_STM__PRE 0x0 + +#define QAM_TOP_COMM_EXEC__A 0x1410000 +#define QAM_TOP_COMM_EXEC__W 2 +#define QAM_TOP_COMM_EXEC__M 0x3 +#define QAM_TOP_COMM_EXEC__PRE 0x0 +#define QAM_TOP_COMM_EXEC_STOP 0x0 +#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 +#define QAM_TOP_COMM_EXEC_HOLD 0x2 + +#define QAM_TOP_ANNEX__A 0x1410010 +#define QAM_TOP_ANNEX__W 2 +#define QAM_TOP_ANNEX__M 0x3 +#define QAM_TOP_ANNEX__PRE 0x1 +#define QAM_TOP_ANNEX_A 0x0 +#define QAM_TOP_ANNEX_B 0x1 +#define QAM_TOP_ANNEX_C 0x2 +#define QAM_TOP_ANNEX_D 0x3 + +#define QAM_TOP_CONSTELLATION__A 0x1410011 +#define QAM_TOP_CONSTELLATION__W 3 +#define QAM_TOP_CONSTELLATION__M 0x7 +#define QAM_TOP_CONSTELLATION__PRE 0x5 +#define QAM_TOP_CONSTELLATION_NONE 0x0 +#define QAM_TOP_CONSTELLATION_QPSK 0x1 +#define QAM_TOP_CONSTELLATION_QAM8 0x2 +#define QAM_TOP_CONSTELLATION_QAM16 0x3 +#define QAM_TOP_CONSTELLATION_QAM32 0x4 +#define QAM_TOP_CONSTELLATION_QAM64 0x5 +#define QAM_TOP_CONSTELLATION_QAM128 0x6 +#define QAM_TOP_CONSTELLATION_QAM256 0x7 + +#define QAM_FQ_COMM_EXEC__A 0x1420000 +#define QAM_FQ_COMM_EXEC__W 2 +#define QAM_FQ_COMM_EXEC__M 0x3 +#define QAM_FQ_COMM_EXEC__PRE 0x0 +#define QAM_FQ_COMM_EXEC_STOP 0x0 +#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_FQ_COMM_EXEC_HOLD 0x2 + +#define QAM_FQ_MODE__A 0x1420010 +#define QAM_FQ_MODE__W 3 +#define QAM_FQ_MODE__M 0x7 +#define QAM_FQ_MODE__PRE 0x0 + +#define QAM_FQ_MODE_TAPRESET__B 0 +#define QAM_FQ_MODE_TAPRESET__W 1 +#define QAM_FQ_MODE_TAPRESET__M 0x1 +#define QAM_FQ_MODE_TAPRESET__PRE 0x0 +#define QAM_FQ_MODE_TAPRESET_RST 0x1 + +#define QAM_FQ_MODE_TAPLMS__B 1 +#define QAM_FQ_MODE_TAPLMS__W 1 +#define QAM_FQ_MODE_TAPLMS__M 0x2 +#define QAM_FQ_MODE_TAPLMS__PRE 0x0 +#define QAM_FQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_FQ_MODE_TAPDRAIN__B 2 +#define QAM_FQ_MODE_TAPDRAIN__W 1 +#define QAM_FQ_MODE_TAPDRAIN__M 0x4 +#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 + +#define QAM_FQ_MU_FACTOR__A 0x1420011 +#define QAM_FQ_MU_FACTOR__W 3 +#define QAM_FQ_MU_FACTOR__M 0x7 +#define QAM_FQ_MU_FACTOR__PRE 0x0 + +#define QAM_FQ_LA_FACTOR__A 0x1420012 +#define QAM_FQ_LA_FACTOR__W 4 +#define QAM_FQ_LA_FACTOR__M 0xF +#define QAM_FQ_LA_FACTOR__PRE 0xC +#define QAM_FQ_CENTTAP_IDX__A 0x1420016 +#define QAM_FQ_CENTTAP_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_IDX_IDX__B 0 +#define QAM_FQ_CENTTAP_IDX_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 +#define QAM_FQ_CENTTAP_VALUE__W 12 +#define QAM_FQ_CENTTAP_VALUE__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 + +#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 +#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 +#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL0__A 0x1420020 +#define QAM_FQ_TAP_RE_EL0__W 12 +#define QAM_FQ_TAP_RE_EL0__M 0xFFF +#define QAM_FQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL0_TAP__B 0 +#define QAM_FQ_TAP_RE_EL0_TAP__W 12 +#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0__A 0x1420021 +#define QAM_FQ_TAP_IM_EL0__W 12 +#define QAM_FQ_TAP_IM_EL0__M 0xFFF +#define QAM_FQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0_TAP__B 0 +#define QAM_FQ_TAP_IM_EL0_TAP__W 12 +#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1__A 0x1420022 +#define QAM_FQ_TAP_RE_EL1__W 12 +#define QAM_FQ_TAP_RE_EL1__M 0xFFF +#define QAM_FQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1_TAP__B 0 +#define QAM_FQ_TAP_RE_EL1_TAP__W 12 +#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1__A 0x1420023 +#define QAM_FQ_TAP_IM_EL1__W 12 +#define QAM_FQ_TAP_IM_EL1__M 0xFFF +#define QAM_FQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1_TAP__B 0 +#define QAM_FQ_TAP_IM_EL1_TAP__W 12 +#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2__A 0x1420024 +#define QAM_FQ_TAP_RE_EL2__W 12 +#define QAM_FQ_TAP_RE_EL2__M 0xFFF +#define QAM_FQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2_TAP__B 0 +#define QAM_FQ_TAP_RE_EL2_TAP__W 12 +#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2__A 0x1420025 +#define QAM_FQ_TAP_IM_EL2__W 12 +#define QAM_FQ_TAP_IM_EL2__M 0xFFF +#define QAM_FQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2_TAP__B 0 +#define QAM_FQ_TAP_IM_EL2_TAP__W 12 +#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3__A 0x1420026 +#define QAM_FQ_TAP_RE_EL3__W 12 +#define QAM_FQ_TAP_RE_EL3__M 0xFFF +#define QAM_FQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3_TAP__B 0 +#define QAM_FQ_TAP_RE_EL3_TAP__W 12 +#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3__A 0x1420027 +#define QAM_FQ_TAP_IM_EL3__W 12 +#define QAM_FQ_TAP_IM_EL3__M 0xFFF +#define QAM_FQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3_TAP__B 0 +#define QAM_FQ_TAP_IM_EL3_TAP__W 12 +#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4__A 0x1420028 +#define QAM_FQ_TAP_RE_EL4__W 12 +#define QAM_FQ_TAP_RE_EL4__M 0xFFF +#define QAM_FQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4_TAP__B 0 +#define QAM_FQ_TAP_RE_EL4_TAP__W 12 +#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4__A 0x1420029 +#define QAM_FQ_TAP_IM_EL4__W 12 +#define QAM_FQ_TAP_IM_EL4__M 0xFFF +#define QAM_FQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4_TAP__B 0 +#define QAM_FQ_TAP_IM_EL4_TAP__W 12 +#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5__A 0x142002A +#define QAM_FQ_TAP_RE_EL5__W 12 +#define QAM_FQ_TAP_RE_EL5__M 0xFFF +#define QAM_FQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5_TAP__B 0 +#define QAM_FQ_TAP_RE_EL5_TAP__W 12 +#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5__A 0x142002B +#define QAM_FQ_TAP_IM_EL5__W 12 +#define QAM_FQ_TAP_IM_EL5__M 0xFFF +#define QAM_FQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5_TAP__B 0 +#define QAM_FQ_TAP_IM_EL5_TAP__W 12 +#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6__A 0x142002C +#define QAM_FQ_TAP_RE_EL6__W 12 +#define QAM_FQ_TAP_RE_EL6__M 0xFFF +#define QAM_FQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6_TAP__B 0 +#define QAM_FQ_TAP_RE_EL6_TAP__W 12 +#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6__A 0x142002D +#define QAM_FQ_TAP_IM_EL6__W 12 +#define QAM_FQ_TAP_IM_EL6__M 0xFFF +#define QAM_FQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6_TAP__B 0 +#define QAM_FQ_TAP_IM_EL6_TAP__W 12 +#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7__A 0x142002E +#define QAM_FQ_TAP_RE_EL7__W 12 +#define QAM_FQ_TAP_RE_EL7__M 0xFFF +#define QAM_FQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7_TAP__B 0 +#define QAM_FQ_TAP_RE_EL7_TAP__W 12 +#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7__A 0x142002F +#define QAM_FQ_TAP_IM_EL7__W 12 +#define QAM_FQ_TAP_IM_EL7__M 0xFFF +#define QAM_FQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7_TAP__B 0 +#define QAM_FQ_TAP_IM_EL7_TAP__W 12 +#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8__A 0x1420030 +#define QAM_FQ_TAP_RE_EL8__W 12 +#define QAM_FQ_TAP_RE_EL8__M 0xFFF +#define QAM_FQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8_TAP__B 0 +#define QAM_FQ_TAP_RE_EL8_TAP__W 12 +#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8__A 0x1420031 +#define QAM_FQ_TAP_IM_EL8__W 12 +#define QAM_FQ_TAP_IM_EL8__M 0xFFF +#define QAM_FQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8_TAP__B 0 +#define QAM_FQ_TAP_IM_EL8_TAP__W 12 +#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9__A 0x1420032 +#define QAM_FQ_TAP_RE_EL9__W 12 +#define QAM_FQ_TAP_RE_EL9__M 0xFFF +#define QAM_FQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9_TAP__B 0 +#define QAM_FQ_TAP_RE_EL9_TAP__W 12 +#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9__A 0x1420033 +#define QAM_FQ_TAP_IM_EL9__W 12 +#define QAM_FQ_TAP_IM_EL9__M 0xFFF +#define QAM_FQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9_TAP__B 0 +#define QAM_FQ_TAP_IM_EL9_TAP__W 12 +#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10__A 0x1420034 +#define QAM_FQ_TAP_RE_EL10__W 12 +#define QAM_FQ_TAP_RE_EL10__M 0xFFF +#define QAM_FQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10_TAP__B 0 +#define QAM_FQ_TAP_RE_EL10_TAP__W 12 +#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10__A 0x1420035 +#define QAM_FQ_TAP_IM_EL10__W 12 +#define QAM_FQ_TAP_IM_EL10__M 0xFFF +#define QAM_FQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10_TAP__B 0 +#define QAM_FQ_TAP_IM_EL10_TAP__W 12 +#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11__A 0x1420036 +#define QAM_FQ_TAP_RE_EL11__W 12 +#define QAM_FQ_TAP_RE_EL11__M 0xFFF +#define QAM_FQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11_TAP__B 0 +#define QAM_FQ_TAP_RE_EL11_TAP__W 12 +#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11__A 0x1420037 +#define QAM_FQ_TAP_IM_EL11__W 12 +#define QAM_FQ_TAP_IM_EL11__M 0xFFF +#define QAM_FQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11_TAP__B 0 +#define QAM_FQ_TAP_IM_EL11_TAP__W 12 +#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12__A 0x1420038 +#define QAM_FQ_TAP_RE_EL12__W 12 +#define QAM_FQ_TAP_RE_EL12__M 0xFFF +#define QAM_FQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12_TAP__B 0 +#define QAM_FQ_TAP_RE_EL12_TAP__W 12 +#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12__A 0x1420039 +#define QAM_FQ_TAP_IM_EL12__W 12 +#define QAM_FQ_TAP_IM_EL12__M 0xFFF +#define QAM_FQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12_TAP__B 0 +#define QAM_FQ_TAP_IM_EL12_TAP__W 12 +#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13__A 0x142003A +#define QAM_FQ_TAP_RE_EL13__W 12 +#define QAM_FQ_TAP_RE_EL13__M 0xFFF +#define QAM_FQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13_TAP__B 0 +#define QAM_FQ_TAP_RE_EL13_TAP__W 12 +#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13__A 0x142003B +#define QAM_FQ_TAP_IM_EL13__W 12 +#define QAM_FQ_TAP_IM_EL13__M 0xFFF +#define QAM_FQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13_TAP__B 0 +#define QAM_FQ_TAP_IM_EL13_TAP__W 12 +#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14__A 0x142003C +#define QAM_FQ_TAP_RE_EL14__W 12 +#define QAM_FQ_TAP_RE_EL14__M 0xFFF +#define QAM_FQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14_TAP__B 0 +#define QAM_FQ_TAP_RE_EL14_TAP__W 12 +#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14__A 0x142003D +#define QAM_FQ_TAP_IM_EL14__W 12 +#define QAM_FQ_TAP_IM_EL14__M 0xFFF +#define QAM_FQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14_TAP__B 0 +#define QAM_FQ_TAP_IM_EL14_TAP__W 12 +#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15__A 0x142003E +#define QAM_FQ_TAP_RE_EL15__W 12 +#define QAM_FQ_TAP_RE_EL15__M 0xFFF +#define QAM_FQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15_TAP__B 0 +#define QAM_FQ_TAP_RE_EL15_TAP__W 12 +#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15__A 0x142003F +#define QAM_FQ_TAP_IM_EL15__W 12 +#define QAM_FQ_TAP_IM_EL15__M 0xFFF +#define QAM_FQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15_TAP__B 0 +#define QAM_FQ_TAP_IM_EL15_TAP__W 12 +#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16__A 0x1420040 +#define QAM_FQ_TAP_RE_EL16__W 12 +#define QAM_FQ_TAP_RE_EL16__M 0xFFF +#define QAM_FQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16_TAP__B 0 +#define QAM_FQ_TAP_RE_EL16_TAP__W 12 +#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16__A 0x1420041 +#define QAM_FQ_TAP_IM_EL16__W 12 +#define QAM_FQ_TAP_IM_EL16__M 0xFFF +#define QAM_FQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16_TAP__B 0 +#define QAM_FQ_TAP_IM_EL16_TAP__W 12 +#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17__A 0x1420042 +#define QAM_FQ_TAP_RE_EL17__W 12 +#define QAM_FQ_TAP_RE_EL17__M 0xFFF +#define QAM_FQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17_TAP__B 0 +#define QAM_FQ_TAP_RE_EL17_TAP__W 12 +#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17__A 0x1420043 +#define QAM_FQ_TAP_IM_EL17__W 12 +#define QAM_FQ_TAP_IM_EL17__M 0xFFF +#define QAM_FQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17_TAP__B 0 +#define QAM_FQ_TAP_IM_EL17_TAP__W 12 +#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18__A 0x1420044 +#define QAM_FQ_TAP_RE_EL18__W 12 +#define QAM_FQ_TAP_RE_EL18__M 0xFFF +#define QAM_FQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18_TAP__B 0 +#define QAM_FQ_TAP_RE_EL18_TAP__W 12 +#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18__A 0x1420045 +#define QAM_FQ_TAP_IM_EL18__W 12 +#define QAM_FQ_TAP_IM_EL18__M 0xFFF +#define QAM_FQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18_TAP__B 0 +#define QAM_FQ_TAP_IM_EL18_TAP__W 12 +#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL19__A 0x1420046 +#define QAM_FQ_TAP_RE_EL19__W 12 +#define QAM_FQ_TAP_RE_EL19__M 0xFFF +#define QAM_FQ_TAP_RE_EL19__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL19_TAP__B 0 +#define QAM_FQ_TAP_RE_EL19_TAP__W 12 +#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 + +#define QAM_FQ_TAP_IM_EL19__A 0x1420047 +#define QAM_FQ_TAP_IM_EL19__W 12 +#define QAM_FQ_TAP_IM_EL19__M 0xFFF +#define QAM_FQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL19_TAP__B 0 +#define QAM_FQ_TAP_IM_EL19_TAP__W 12 +#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20__A 0x1420048 +#define QAM_FQ_TAP_RE_EL20__W 12 +#define QAM_FQ_TAP_RE_EL20__M 0xFFF +#define QAM_FQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20_TAP__B 0 +#define QAM_FQ_TAP_RE_EL20_TAP__W 12 +#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20__A 0x1420049 +#define QAM_FQ_TAP_IM_EL20__W 12 +#define QAM_FQ_TAP_IM_EL20__M 0xFFF +#define QAM_FQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20_TAP__B 0 +#define QAM_FQ_TAP_IM_EL20_TAP__W 12 +#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21__A 0x142004A +#define QAM_FQ_TAP_RE_EL21__W 12 +#define QAM_FQ_TAP_RE_EL21__M 0xFFF +#define QAM_FQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21_TAP__B 0 +#define QAM_FQ_TAP_RE_EL21_TAP__W 12 +#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21__A 0x142004B +#define QAM_FQ_TAP_IM_EL21__W 12 +#define QAM_FQ_TAP_IM_EL21__M 0xFFF +#define QAM_FQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21_TAP__B 0 +#define QAM_FQ_TAP_IM_EL21_TAP__W 12 +#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22__A 0x142004C +#define QAM_FQ_TAP_RE_EL22__W 12 +#define QAM_FQ_TAP_RE_EL22__M 0xFFF +#define QAM_FQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22_TAP__B 0 +#define QAM_FQ_TAP_RE_EL22_TAP__W 12 +#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22__A 0x142004D +#define QAM_FQ_TAP_IM_EL22__W 12 +#define QAM_FQ_TAP_IM_EL22__M 0xFFF +#define QAM_FQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22_TAP__B 0 +#define QAM_FQ_TAP_IM_EL22_TAP__W 12 +#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23__A 0x142004E +#define QAM_FQ_TAP_RE_EL23__W 12 +#define QAM_FQ_TAP_RE_EL23__M 0xFFF +#define QAM_FQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23_TAP__B 0 +#define QAM_FQ_TAP_RE_EL23_TAP__W 12 +#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23__A 0x142004F +#define QAM_FQ_TAP_IM_EL23__W 12 +#define QAM_FQ_TAP_IM_EL23__M 0xFFF +#define QAM_FQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23_TAP__B 0 +#define QAM_FQ_TAP_IM_EL23_TAP__W 12 +#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 + +#define QAM_SL_COMM_EXEC__A 0x1430000 +#define QAM_SL_COMM_EXEC__W 2 +#define QAM_SL_COMM_EXEC__M 0x3 +#define QAM_SL_COMM_EXEC__PRE 0x0 +#define QAM_SL_COMM_EXEC_STOP 0x0 +#define QAM_SL_COMM_EXEC_ACTIVE 0x1 +#define QAM_SL_COMM_EXEC_HOLD 0x2 + +#define QAM_SL_COMM_MB__A 0x1430002 +#define QAM_SL_COMM_MB__W 4 +#define QAM_SL_COMM_MB__M 0xF +#define QAM_SL_COMM_MB__PRE 0x0 +#define QAM_SL_COMM_MB_CTL__B 0 +#define QAM_SL_COMM_MB_CTL__W 1 +#define QAM_SL_COMM_MB_CTL__M 0x1 +#define QAM_SL_COMM_MB_CTL__PRE 0x0 +#define QAM_SL_COMM_MB_CTL_OFF 0x0 +#define QAM_SL_COMM_MB_CTL_ON 0x1 +#define QAM_SL_COMM_MB_OBS__B 1 +#define QAM_SL_COMM_MB_OBS__W 1 +#define QAM_SL_COMM_MB_OBS__M 0x2 +#define QAM_SL_COMM_MB_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_OBS_OFF 0x0 +#define QAM_SL_COMM_MB_OBS_ON 0x2 +#define QAM_SL_COMM_MB_MUX_OBS__B 2 +#define QAM_SL_COMM_MB_MUX_OBS__W 2 +#define QAM_SL_COMM_MB_MUX_OBS__M 0xC +#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 +#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC + +#define QAM_SL_COMM_INT_REQ__A 0x1430003 +#define QAM_SL_COMM_INT_REQ__W 1 +#define QAM_SL_COMM_INT_REQ__M 0x1 +#define QAM_SL_COMM_INT_REQ__PRE 0x0 +#define QAM_SL_COMM_INT_STA__A 0x1430005 +#define QAM_SL_COMM_INT_STA__W 2 +#define QAM_SL_COMM_INT_STA__M 0x3 +#define QAM_SL_COMM_INT_STA__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MER_INT__B 1 +#define QAM_SL_COMM_INT_STA_MER_INT__W 1 +#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 +#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_MSK__A 0x1430006 +#define QAM_SL_COMM_INT_MSK__W 2 +#define QAM_SL_COMM_INT_MSK__M 0x3 +#define QAM_SL_COMM_INT_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 +#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 + +#define QAM_SL_COMM_INT_STM__A 0x1430007 +#define QAM_SL_COMM_INT_STM__W 2 +#define QAM_SL_COMM_INT_STM__M 0x3 +#define QAM_SL_COMM_INT_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MER_STM__B 1 +#define QAM_SL_COMM_INT_STM_MER_STM__W 1 +#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 +#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 + +#define QAM_SL_MODE__A 0x1430010 +#define QAM_SL_MODE__W 11 +#define QAM_SL_MODE__M 0x7FF +#define QAM_SL_MODE__PRE 0x0 + +#define QAM_SL_MODE_SLICER4LC__B 0 +#define QAM_SL_MODE_SLICER4LC__W 2 +#define QAM_SL_MODE_SLICER4LC__M 0x3 +#define QAM_SL_MODE_SLICER4LC__PRE 0x0 +#define QAM_SL_MODE_SLICER4LC_RECT 0x0 +#define QAM_SL_MODE_SLICER4LC_ONET 0x1 +#define QAM_SL_MODE_SLICER4LC_RAD 0x2 + +#define QAM_SL_MODE_SLICER4DQ__B 2 +#define QAM_SL_MODE_SLICER4DQ__W 2 +#define QAM_SL_MODE_SLICER4DQ__M 0xC +#define QAM_SL_MODE_SLICER4DQ__PRE 0x0 +#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 +#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 +#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 + +#define QAM_SL_MODE_SLICER4VD__B 4 +#define QAM_SL_MODE_SLICER4VD__W 2 +#define QAM_SL_MODE_SLICER4VD__M 0x30 +#define QAM_SL_MODE_SLICER4VD__PRE 0x0 +#define QAM_SL_MODE_SLICER4VD_RECT 0x0 +#define QAM_SL_MODE_SLICER4VD_ONET 0x10 +#define QAM_SL_MODE_SLICER4VD_RAD 0x20 + +#define QAM_SL_MODE_ROT_DIS__B 6 +#define QAM_SL_MODE_ROT_DIS__W 1 +#define QAM_SL_MODE_ROT_DIS__M 0x40 +#define QAM_SL_MODE_ROT_DIS__PRE 0x0 + +#define QAM_SL_MODE_DQROT_DIS__B 7 +#define QAM_SL_MODE_DQROT_DIS__W 1 +#define QAM_SL_MODE_DQROT_DIS__M 0x80 +#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 + +#define QAM_SL_MODE_DFE_DIS__B 8 +#define QAM_SL_MODE_DFE_DIS__W 1 +#define QAM_SL_MODE_DFE_DIS__M 0x100 +#define QAM_SL_MODE_DFE_DIS__PRE 0x0 + +#define QAM_SL_MODE_RADIUS_MIX__B 9 +#define QAM_SL_MODE_RADIUS_MIX__W 1 +#define QAM_SL_MODE_RADIUS_MIX__M 0x200 +#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 + +#define QAM_SL_MODE_TILT_COMP__B 10 +#define QAM_SL_MODE_TILT_COMP__W 1 +#define QAM_SL_MODE_TILT_COMP__M 0x400 +#define QAM_SL_MODE_TILT_COMP__PRE 0x0 + +#define QAM_SL_K_FACTOR__A 0x1430011 +#define QAM_SL_K_FACTOR__W 4 +#define QAM_SL_K_FACTOR__M 0xF +#define QAM_SL_K_FACTOR__PRE 0x0 +#define QAM_SL_MEDIAN__A 0x1430012 +#define QAM_SL_MEDIAN__W 14 +#define QAM_SL_MEDIAN__M 0x3FFF +#define QAM_SL_MEDIAN__PRE 0x0 + +#define QAM_SL_MEDIAN_LENGTH__B 0 +#define QAM_SL_MEDIAN_LENGTH__W 2 +#define QAM_SL_MEDIAN_LENGTH__M 0x3 +#define QAM_SL_MEDIAN_LENGTH__PRE 0x0 + +#define QAM_SL_MEDIAN_CORRECT__B 2 +#define QAM_SL_MEDIAN_CORRECT__W 4 +#define QAM_SL_MEDIAN_CORRECT__M 0x3C +#define QAM_SL_MEDIAN_CORRECT__PRE 0x0 + +#define QAM_SL_MEDIAN_TOLERANCE__B 6 +#define QAM_SL_MEDIAN_TOLERANCE__W 7 +#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 +#define QAM_SL_MEDIAN_TOLERANCE__PRE 0x0 + +#define QAM_SL_MEDIAN_FAST__B 13 +#define QAM_SL_MEDIAN_FAST__W 1 +#define QAM_SL_MEDIAN_FAST__M 0x2000 +#define QAM_SL_MEDIAN_FAST__PRE 0x0 + +#define QAM_SL_ALPHA__A 0x1430013 +#define QAM_SL_ALPHA__W 3 +#define QAM_SL_ALPHA__M 0x7 +#define QAM_SL_ALPHA__PRE 0x0 + +#define QAM_SL_PHASELIMIT__A 0x1430014 +#define QAM_SL_PHASELIMIT__W 9 +#define QAM_SL_PHASELIMIT__M 0x1FF +#define QAM_SL_PHASELIMIT__PRE 0x0 +#define QAM_SL_MTA_LENGTH__A 0x1430015 +#define QAM_SL_MTA_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH__PRE 0x1 + +#define QAM_SL_MTA_LENGTH_LENGTH__B 0 +#define QAM_SL_MTA_LENGTH_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 + +#define QAM_SL_MEDIAN_ERROR__A 0x1430016 +#define QAM_SL_MEDIAN_ERROR__W 10 +#define QAM_SL_MEDIAN_ERROR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR__PRE 0x0 + +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 + +#define QAM_SL_ERR_POWER__A 0x1430017 +#define QAM_SL_ERR_POWER__W 16 +#define QAM_SL_ERR_POWER__M 0xFFFF +#define QAM_SL_ERR_POWER__PRE 0x0 + +#define QAM_DQ_COMM_EXEC__A 0x1440000 +#define QAM_DQ_COMM_EXEC__W 2 +#define QAM_DQ_COMM_EXEC__M 0x3 +#define QAM_DQ_COMM_EXEC__PRE 0x0 +#define QAM_DQ_COMM_EXEC_STOP 0x0 +#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_DQ_COMM_EXEC_HOLD 0x2 + +#define QAM_DQ_MODE__A 0x1440010 +#define QAM_DQ_MODE__W 5 +#define QAM_DQ_MODE__M 0x1F +#define QAM_DQ_MODE__PRE 0x0 + +#define QAM_DQ_MODE_TAPRESET__B 0 +#define QAM_DQ_MODE_TAPRESET__W 1 +#define QAM_DQ_MODE_TAPRESET__M 0x1 +#define QAM_DQ_MODE_TAPRESET__PRE 0x0 +#define QAM_DQ_MODE_TAPRESET_RST 0x1 + +#define QAM_DQ_MODE_TAPLMS__B 1 +#define QAM_DQ_MODE_TAPLMS__W 1 +#define QAM_DQ_MODE_TAPLMS__M 0x2 +#define QAM_DQ_MODE_TAPLMS__PRE 0x0 +#define QAM_DQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_DQ_MODE_TAPDRAIN__B 2 +#define QAM_DQ_MODE_TAPDRAIN__W 1 +#define QAM_DQ_MODE_TAPDRAIN__M 0x4 +#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 + +#define QAM_DQ_MODE_FB__B 3 +#define QAM_DQ_MODE_FB__W 2 +#define QAM_DQ_MODE_FB__M 0x18 +#define QAM_DQ_MODE_FB__PRE 0x0 +#define QAM_DQ_MODE_FB_CMA 0x0 +#define QAM_DQ_MODE_FB_RADIUS 0x8 +#define QAM_DQ_MODE_FB_DFB 0x10 +#define QAM_DQ_MODE_FB_TRELLIS 0x18 + +#define QAM_DQ_MU_FACTOR__A 0x1440011 +#define QAM_DQ_MU_FACTOR__W 3 +#define QAM_DQ_MU_FACTOR__M 0x7 +#define QAM_DQ_MU_FACTOR__PRE 0x0 + +#define QAM_DQ_LA_FACTOR__A 0x1440012 +#define QAM_DQ_LA_FACTOR__W 4 +#define QAM_DQ_LA_FACTOR__M 0xF +#define QAM_DQ_LA_FACTOR__PRE 0xC + +#define QAM_DQ_CMA_RATIO__A 0x1440013 +#define QAM_DQ_CMA_RATIO__W 14 +#define QAM_DQ_CMA_RATIO__M 0x3FFF +#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 +#define QAM_DQ_CMA_RATIO_QPSK 0x2000 +#define QAM_DQ_CMA_RATIO_QAM16 0x34CD +#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 +#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D +#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 + +#define QAM_DQ_QUAL_RADSEL__A 0x1440014 +#define QAM_DQ_QUAL_RADSEL__W 3 +#define QAM_DQ_QUAL_RADSEL__M 0x7 +#define QAM_DQ_QUAL_RADSEL__PRE 0x0 + +#define QAM_DQ_QUAL_RADSEL_BIT__B 0 +#define QAM_DQ_QUAL_RADSEL_BIT__W 3 +#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 +#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 + +#define QAM_DQ_QUAL_ENA__A 0x1440015 +#define QAM_DQ_QUAL_ENA__W 1 +#define QAM_DQ_QUAL_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA__PRE 0x0 + +#define QAM_DQ_QUAL_ENA_ENA__B 0 +#define QAM_DQ_QUAL_ENA_ENA__W 1 +#define QAM_DQ_QUAL_ENA_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 +#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 + +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__PRE 0x4 + +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__PRE 0x6 + +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 + +#define QAM_DQ_RAW_LIM__A 0x144001E +#define QAM_DQ_RAW_LIM__W 5 +#define QAM_DQ_RAW_LIM__M 0x1F +#define QAM_DQ_RAW_LIM__PRE 0x1F + +#define QAM_DQ_RAW_LIM_BIT__B 0 +#define QAM_DQ_RAW_LIM_BIT__W 5 +#define QAM_DQ_RAW_LIM_BIT__M 0x1F +#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F + +#define QAM_DQ_TAP_RE_EL0__A 0x1440020 +#define QAM_DQ_TAP_RE_EL0__W 12 +#define QAM_DQ_TAP_RE_EL0__M 0xFFF +#define QAM_DQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL0_TAP__B 0 +#define QAM_DQ_TAP_RE_EL0_TAP__W 12 +#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0__A 0x1440021 +#define QAM_DQ_TAP_IM_EL0__W 12 +#define QAM_DQ_TAP_IM_EL0__M 0xFFF +#define QAM_DQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0_TAP__B 0 +#define QAM_DQ_TAP_IM_EL0_TAP__W 12 +#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1__A 0x1440022 +#define QAM_DQ_TAP_RE_EL1__W 12 +#define QAM_DQ_TAP_RE_EL1__M 0xFFF +#define QAM_DQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1_TAP__B 0 +#define QAM_DQ_TAP_RE_EL1_TAP__W 12 +#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1__A 0x1440023 +#define QAM_DQ_TAP_IM_EL1__W 12 +#define QAM_DQ_TAP_IM_EL1__M 0xFFF +#define QAM_DQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1_TAP__B 0 +#define QAM_DQ_TAP_IM_EL1_TAP__W 12 +#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2__A 0x1440024 +#define QAM_DQ_TAP_RE_EL2__W 12 +#define QAM_DQ_TAP_RE_EL2__M 0xFFF +#define QAM_DQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2_TAP__B 0 +#define QAM_DQ_TAP_RE_EL2_TAP__W 12 +#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2__A 0x1440025 +#define QAM_DQ_TAP_IM_EL2__W 12 +#define QAM_DQ_TAP_IM_EL2__M 0xFFF +#define QAM_DQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2_TAP__B 0 +#define QAM_DQ_TAP_IM_EL2_TAP__W 12 +#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3__A 0x1440026 +#define QAM_DQ_TAP_RE_EL3__W 12 +#define QAM_DQ_TAP_RE_EL3__M 0xFFF +#define QAM_DQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3_TAP__B 0 +#define QAM_DQ_TAP_RE_EL3_TAP__W 12 +#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3__A 0x1440027 +#define QAM_DQ_TAP_IM_EL3__W 12 +#define QAM_DQ_TAP_IM_EL3__M 0xFFF +#define QAM_DQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3_TAP__B 0 +#define QAM_DQ_TAP_IM_EL3_TAP__W 12 +#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4__A 0x1440028 +#define QAM_DQ_TAP_RE_EL4__W 12 +#define QAM_DQ_TAP_RE_EL4__M 0xFFF +#define QAM_DQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4_TAP__B 0 +#define QAM_DQ_TAP_RE_EL4_TAP__W 12 +#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4__A 0x1440029 +#define QAM_DQ_TAP_IM_EL4__W 12 +#define QAM_DQ_TAP_IM_EL4__M 0xFFF +#define QAM_DQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4_TAP__B 0 +#define QAM_DQ_TAP_IM_EL4_TAP__W 12 +#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5__A 0x144002A +#define QAM_DQ_TAP_RE_EL5__W 12 +#define QAM_DQ_TAP_RE_EL5__M 0xFFF +#define QAM_DQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5_TAP__B 0 +#define QAM_DQ_TAP_RE_EL5_TAP__W 12 +#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5__A 0x144002B +#define QAM_DQ_TAP_IM_EL5__W 12 +#define QAM_DQ_TAP_IM_EL5__M 0xFFF +#define QAM_DQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5_TAP__B 0 +#define QAM_DQ_TAP_IM_EL5_TAP__W 12 +#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6__A 0x144002C +#define QAM_DQ_TAP_RE_EL6__W 12 +#define QAM_DQ_TAP_RE_EL6__M 0xFFF +#define QAM_DQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6_TAP__B 0 +#define QAM_DQ_TAP_RE_EL6_TAP__W 12 +#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6__A 0x144002D +#define QAM_DQ_TAP_IM_EL6__W 12 +#define QAM_DQ_TAP_IM_EL6__M 0xFFF +#define QAM_DQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6_TAP__B 0 +#define QAM_DQ_TAP_IM_EL6_TAP__W 12 +#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7__A 0x144002E +#define QAM_DQ_TAP_RE_EL7__W 12 +#define QAM_DQ_TAP_RE_EL7__M 0xFFF +#define QAM_DQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7_TAP__B 0 +#define QAM_DQ_TAP_RE_EL7_TAP__W 12 +#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7__A 0x144002F +#define QAM_DQ_TAP_IM_EL7__W 12 +#define QAM_DQ_TAP_IM_EL7__M 0xFFF +#define QAM_DQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7_TAP__B 0 +#define QAM_DQ_TAP_IM_EL7_TAP__W 12 +#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8__A 0x1440030 +#define QAM_DQ_TAP_RE_EL8__W 12 +#define QAM_DQ_TAP_RE_EL8__M 0xFFF +#define QAM_DQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8_TAP__B 0 +#define QAM_DQ_TAP_RE_EL8_TAP__W 12 +#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8__A 0x1440031 +#define QAM_DQ_TAP_IM_EL8__W 12 +#define QAM_DQ_TAP_IM_EL8__M 0xFFF +#define QAM_DQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8_TAP__B 0 +#define QAM_DQ_TAP_IM_EL8_TAP__W 12 +#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9__A 0x1440032 +#define QAM_DQ_TAP_RE_EL9__W 12 +#define QAM_DQ_TAP_RE_EL9__M 0xFFF +#define QAM_DQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9_TAP__B 0 +#define QAM_DQ_TAP_RE_EL9_TAP__W 12 +#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9__A 0x1440033 +#define QAM_DQ_TAP_IM_EL9__W 12 +#define QAM_DQ_TAP_IM_EL9__M 0xFFF +#define QAM_DQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9_TAP__B 0 +#define QAM_DQ_TAP_IM_EL9_TAP__W 12 +#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10__A 0x1440034 +#define QAM_DQ_TAP_RE_EL10__W 12 +#define QAM_DQ_TAP_RE_EL10__M 0xFFF +#define QAM_DQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10_TAP__B 0 +#define QAM_DQ_TAP_RE_EL10_TAP__W 12 +#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10__A 0x1440035 +#define QAM_DQ_TAP_IM_EL10__W 12 +#define QAM_DQ_TAP_IM_EL10__M 0xFFF +#define QAM_DQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10_TAP__B 0 +#define QAM_DQ_TAP_IM_EL10_TAP__W 12 +#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11__A 0x1440036 +#define QAM_DQ_TAP_RE_EL11__W 12 +#define QAM_DQ_TAP_RE_EL11__M 0xFFF +#define QAM_DQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11_TAP__B 0 +#define QAM_DQ_TAP_RE_EL11_TAP__W 12 +#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11__A 0x1440037 +#define QAM_DQ_TAP_IM_EL11__W 12 +#define QAM_DQ_TAP_IM_EL11__M 0xFFF +#define QAM_DQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11_TAP__B 0 +#define QAM_DQ_TAP_IM_EL11_TAP__W 12 +#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12__A 0x1440038 +#define QAM_DQ_TAP_RE_EL12__W 12 +#define QAM_DQ_TAP_RE_EL12__M 0xFFF +#define QAM_DQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12_TAP__B 0 +#define QAM_DQ_TAP_RE_EL12_TAP__W 12 +#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12__A 0x1440039 +#define QAM_DQ_TAP_IM_EL12__W 12 +#define QAM_DQ_TAP_IM_EL12__M 0xFFF +#define QAM_DQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12_TAP__B 0 +#define QAM_DQ_TAP_IM_EL12_TAP__W 12 +#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13__A 0x144003A +#define QAM_DQ_TAP_RE_EL13__W 12 +#define QAM_DQ_TAP_RE_EL13__M 0xFFF +#define QAM_DQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13_TAP__B 0 +#define QAM_DQ_TAP_RE_EL13_TAP__W 12 +#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13__A 0x144003B +#define QAM_DQ_TAP_IM_EL13__W 12 +#define QAM_DQ_TAP_IM_EL13__M 0xFFF +#define QAM_DQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13_TAP__B 0 +#define QAM_DQ_TAP_IM_EL13_TAP__W 12 +#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14__A 0x144003C +#define QAM_DQ_TAP_RE_EL14__W 12 +#define QAM_DQ_TAP_RE_EL14__M 0xFFF +#define QAM_DQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14_TAP__B 0 +#define QAM_DQ_TAP_RE_EL14_TAP__W 12 +#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14__A 0x144003D +#define QAM_DQ_TAP_IM_EL14__W 12 +#define QAM_DQ_TAP_IM_EL14__M 0xFFF +#define QAM_DQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14_TAP__B 0 +#define QAM_DQ_TAP_IM_EL14_TAP__W 12 +#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15__A 0x144003E +#define QAM_DQ_TAP_RE_EL15__W 12 +#define QAM_DQ_TAP_RE_EL15__M 0xFFF +#define QAM_DQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15_TAP__B 0 +#define QAM_DQ_TAP_RE_EL15_TAP__W 12 +#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15__A 0x144003F +#define QAM_DQ_TAP_IM_EL15__W 12 +#define QAM_DQ_TAP_IM_EL15__M 0xFFF +#define QAM_DQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15_TAP__B 0 +#define QAM_DQ_TAP_IM_EL15_TAP__W 12 +#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16__A 0x1440040 +#define QAM_DQ_TAP_RE_EL16__W 12 +#define QAM_DQ_TAP_RE_EL16__M 0xFFF +#define QAM_DQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16_TAP__B 0 +#define QAM_DQ_TAP_RE_EL16_TAP__W 12 +#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16__A 0x1440041 +#define QAM_DQ_TAP_IM_EL16__W 12 +#define QAM_DQ_TAP_IM_EL16__M 0xFFF +#define QAM_DQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16_TAP__B 0 +#define QAM_DQ_TAP_IM_EL16_TAP__W 12 +#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17__A 0x1440042 +#define QAM_DQ_TAP_RE_EL17__W 12 +#define QAM_DQ_TAP_RE_EL17__M 0xFFF +#define QAM_DQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17_TAP__B 0 +#define QAM_DQ_TAP_RE_EL17_TAP__W 12 +#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17__A 0x1440043 +#define QAM_DQ_TAP_IM_EL17__W 12 +#define QAM_DQ_TAP_IM_EL17__M 0xFFF +#define QAM_DQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17_TAP__B 0 +#define QAM_DQ_TAP_IM_EL17_TAP__W 12 +#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18__A 0x1440044 +#define QAM_DQ_TAP_RE_EL18__W 12 +#define QAM_DQ_TAP_RE_EL18__M 0xFFF +#define QAM_DQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18_TAP__B 0 +#define QAM_DQ_TAP_RE_EL18_TAP__W 12 +#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18__A 0x1440045 +#define QAM_DQ_TAP_IM_EL18__W 12 +#define QAM_DQ_TAP_IM_EL18__M 0xFFF +#define QAM_DQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18_TAP__B 0 +#define QAM_DQ_TAP_IM_EL18_TAP__W 12 +#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19__A 0x1440046 +#define QAM_DQ_TAP_RE_EL19__W 12 +#define QAM_DQ_TAP_RE_EL19__M 0xFFF +#define QAM_DQ_TAP_RE_EL19__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19_TAP__B 0 +#define QAM_DQ_TAP_RE_EL19_TAP__W 12 +#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19__A 0x1440047 +#define QAM_DQ_TAP_IM_EL19__W 12 +#define QAM_DQ_TAP_IM_EL19__M 0xFFF +#define QAM_DQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19_TAP__B 0 +#define QAM_DQ_TAP_IM_EL19_TAP__W 12 +#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20__A 0x1440048 +#define QAM_DQ_TAP_RE_EL20__W 12 +#define QAM_DQ_TAP_RE_EL20__M 0xFFF +#define QAM_DQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20_TAP__B 0 +#define QAM_DQ_TAP_RE_EL20_TAP__W 12 +#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20__A 0x1440049 +#define QAM_DQ_TAP_IM_EL20__W 12 +#define QAM_DQ_TAP_IM_EL20__M 0xFFF +#define QAM_DQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20_TAP__B 0 +#define QAM_DQ_TAP_IM_EL20_TAP__W 12 +#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21__A 0x144004A +#define QAM_DQ_TAP_RE_EL21__W 12 +#define QAM_DQ_TAP_RE_EL21__M 0xFFF +#define QAM_DQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21_TAP__B 0 +#define QAM_DQ_TAP_RE_EL21_TAP__W 12 +#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21__A 0x144004B +#define QAM_DQ_TAP_IM_EL21__W 12 +#define QAM_DQ_TAP_IM_EL21__M 0xFFF +#define QAM_DQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21_TAP__B 0 +#define QAM_DQ_TAP_IM_EL21_TAP__W 12 +#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22__A 0x144004C +#define QAM_DQ_TAP_RE_EL22__W 12 +#define QAM_DQ_TAP_RE_EL22__M 0xFFF +#define QAM_DQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22_TAP__B 0 +#define QAM_DQ_TAP_RE_EL22_TAP__W 12 +#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22__A 0x144004D +#define QAM_DQ_TAP_IM_EL22__W 12 +#define QAM_DQ_TAP_IM_EL22__M 0xFFF +#define QAM_DQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22_TAP__B 0 +#define QAM_DQ_TAP_IM_EL22_TAP__W 12 +#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23__A 0x144004E +#define QAM_DQ_TAP_RE_EL23__W 12 +#define QAM_DQ_TAP_RE_EL23__M 0xFFF +#define QAM_DQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23_TAP__B 0 +#define QAM_DQ_TAP_RE_EL23_TAP__W 12 +#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23__A 0x144004F +#define QAM_DQ_TAP_IM_EL23__W 12 +#define QAM_DQ_TAP_IM_EL23__M 0xFFF +#define QAM_DQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23_TAP__B 0 +#define QAM_DQ_TAP_IM_EL23_TAP__W 12 +#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24__A 0x1440050 +#define QAM_DQ_TAP_RE_EL24__W 12 +#define QAM_DQ_TAP_RE_EL24__M 0xFFF +#define QAM_DQ_TAP_RE_EL24__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24_TAP__B 0 +#define QAM_DQ_TAP_RE_EL24_TAP__W 12 +#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24__A 0x1440051 +#define QAM_DQ_TAP_IM_EL24__W 12 +#define QAM_DQ_TAP_IM_EL24__M 0xFFF +#define QAM_DQ_TAP_IM_EL24__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24_TAP__B 0 +#define QAM_DQ_TAP_IM_EL24_TAP__W 12 +#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25__A 0x1440052 +#define QAM_DQ_TAP_RE_EL25__W 12 +#define QAM_DQ_TAP_RE_EL25__M 0xFFF +#define QAM_DQ_TAP_RE_EL25__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25_TAP__B 0 +#define QAM_DQ_TAP_RE_EL25_TAP__W 12 +#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25__A 0x1440053 +#define QAM_DQ_TAP_IM_EL25__W 12 +#define QAM_DQ_TAP_IM_EL25__M 0xFFF +#define QAM_DQ_TAP_IM_EL25__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25_TAP__B 0 +#define QAM_DQ_TAP_IM_EL25_TAP__W 12 +#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26__A 0x1440054 +#define QAM_DQ_TAP_RE_EL26__W 12 +#define QAM_DQ_TAP_RE_EL26__M 0xFFF +#define QAM_DQ_TAP_RE_EL26__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26_TAP__B 0 +#define QAM_DQ_TAP_RE_EL26_TAP__W 12 +#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26__A 0x1440055 +#define QAM_DQ_TAP_IM_EL26__W 12 +#define QAM_DQ_TAP_IM_EL26__M 0xFFF +#define QAM_DQ_TAP_IM_EL26__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26_TAP__B 0 +#define QAM_DQ_TAP_IM_EL26_TAP__W 12 +#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27__A 0x1440056 +#define QAM_DQ_TAP_RE_EL27__W 12 +#define QAM_DQ_TAP_RE_EL27__M 0xFFF +#define QAM_DQ_TAP_RE_EL27__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27_TAP__B 0 +#define QAM_DQ_TAP_RE_EL27_TAP__W 12 +#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27__A 0x1440057 +#define QAM_DQ_TAP_IM_EL27__W 12 +#define QAM_DQ_TAP_IM_EL27__M 0xFFF +#define QAM_DQ_TAP_IM_EL27__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27_TAP__B 0 +#define QAM_DQ_TAP_IM_EL27_TAP__W 12 +#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 + +#define QAM_LC_COMM_EXEC__A 0x1450000 +#define QAM_LC_COMM_EXEC__W 2 +#define QAM_LC_COMM_EXEC__M 0x3 +#define QAM_LC_COMM_EXEC__PRE 0x0 +#define QAM_LC_COMM_EXEC_STOP 0x0 +#define QAM_LC_COMM_EXEC_ACTIVE 0x1 +#define QAM_LC_COMM_EXEC_HOLD 0x2 + +#define QAM_LC_COMM_MB__A 0x1450002 +#define QAM_LC_COMM_MB__W 2 +#define QAM_LC_COMM_MB__M 0x3 +#define QAM_LC_COMM_MB__PRE 0x0 +#define QAM_LC_COMM_MB_CTL__B 0 +#define QAM_LC_COMM_MB_CTL__W 1 +#define QAM_LC_COMM_MB_CTL__M 0x1 +#define QAM_LC_COMM_MB_CTL__PRE 0x0 +#define QAM_LC_COMM_MB_CTL_OFF 0x0 +#define QAM_LC_COMM_MB_CTL_ON 0x1 +#define QAM_LC_COMM_MB_OBS__B 1 +#define QAM_LC_COMM_MB_OBS__W 1 +#define QAM_LC_COMM_MB_OBS__M 0x2 +#define QAM_LC_COMM_MB_OBS__PRE 0x0 +#define QAM_LC_COMM_MB_OBS_OFF 0x0 +#define QAM_LC_COMM_MB_OBS_ON 0x2 + +#define QAM_LC_COMM_INT_REQ__A 0x1450003 +#define QAM_LC_COMM_INT_REQ__W 1 +#define QAM_LC_COMM_INT_REQ__M 0x1 +#define QAM_LC_COMM_INT_REQ__PRE 0x0 +#define QAM_LC_COMM_INT_STA__A 0x1450005 +#define QAM_LC_COMM_INT_STA__W 3 +#define QAM_LC_COMM_INT_STA__M 0x7 +#define QAM_LC_COMM_INT_STA__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_READY__B 0 +#define QAM_LC_COMM_INT_STA_READY__W 1 +#define QAM_LC_COMM_INT_STA_READY__M 0x1 +#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_MSK__A 0x1450006 +#define QAM_LC_COMM_INT_MSK__W 3 +#define QAM_LC_COMM_INT_MSK__M 0x7 +#define QAM_LC_COMM_INT_MSK__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_READY__B 0 +#define QAM_LC_COMM_INT_MSK_READY__W 1 +#define QAM_LC_COMM_INT_MSK_READY__M 0x1 +#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_STM__A 0x1450007 +#define QAM_LC_COMM_INT_STM__W 3 +#define QAM_LC_COMM_INT_STM__M 0x7 +#define QAM_LC_COMM_INT_STM__PRE 0x0 +#define QAM_LC_COMM_INT_STM_READY__B 0 +#define QAM_LC_COMM_INT_STM_READY__W 1 +#define QAM_LC_COMM_INT_STM_READY__M 0x1 +#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 +#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_MODE__A 0x1450010 +#define QAM_LC_MODE__W 3 +#define QAM_LC_MODE__M 0x7 +#define QAM_LC_MODE__PRE 0x7 + +#define QAM_LC_MODE_ENABLE_A__B 0 +#define QAM_LC_MODE_ENABLE_A__W 1 +#define QAM_LC_MODE_ENABLE_A__M 0x1 +#define QAM_LC_MODE_ENABLE_A__PRE 0x1 + +#define QAM_LC_MODE_ENABLE_F__B 1 +#define QAM_LC_MODE_ENABLE_F__W 1 +#define QAM_LC_MODE_ENABLE_F__M 0x2 +#define QAM_LC_MODE_ENABLE_F__PRE 0x2 + +#define QAM_LC_MODE_ENABLE_R__B 2 +#define QAM_LC_MODE_ENABLE_R__W 1 +#define QAM_LC_MODE_ENABLE_R__M 0x4 +#define QAM_LC_MODE_ENABLE_R__PRE 0x4 + +#define QAM_LC_CA__A 0x1450011 +#define QAM_LC_CA__W 6 +#define QAM_LC_CA__M 0x3F +#define QAM_LC_CA__PRE 0x28 + +#define QAM_LC_CA_COEF__B 0 +#define QAM_LC_CA_COEF__W 6 +#define QAM_LC_CA_COEF__M 0x3F +#define QAM_LC_CA_COEF__PRE 0x28 + +#define QAM_LC_CF__A 0x1450012 +#define QAM_LC_CF__W 8 +#define QAM_LC_CF__M 0xFF +#define QAM_LC_CF__PRE 0x8C + +#define QAM_LC_CF_COEF__B 0 +#define QAM_LC_CF_COEF__W 8 +#define QAM_LC_CF_COEF__M 0xFF +#define QAM_LC_CF_COEF__PRE 0x8C + +#define QAM_LC_CF1__A 0x1450013 +#define QAM_LC_CF1__W 8 +#define QAM_LC_CF1__M 0xFF +#define QAM_LC_CF1__PRE 0x1E + +#define QAM_LC_CF1_COEF__B 0 +#define QAM_LC_CF1_COEF__W 8 +#define QAM_LC_CF1_COEF__M 0xFF +#define QAM_LC_CF1_COEF__PRE 0x1E + +#define QAM_LC_CP__A 0x1450014 +#define QAM_LC_CP__W 8 +#define QAM_LC_CP__M 0xFF +#define QAM_LC_CP__PRE 0x78 + +#define QAM_LC_CP_COEF__B 0 +#define QAM_LC_CP_COEF__W 8 +#define QAM_LC_CP_COEF__M 0xFF +#define QAM_LC_CP_COEF__PRE 0x78 + +#define QAM_LC_CI__A 0x1450015 +#define QAM_LC_CI__W 8 +#define QAM_LC_CI__M 0xFF +#define QAM_LC_CI__PRE 0x46 + +#define QAM_LC_CI_COEF__B 0 +#define QAM_LC_CI_COEF__W 8 +#define QAM_LC_CI_COEF__M 0xFF +#define QAM_LC_CI_COEF__PRE 0x46 + +#define QAM_LC_EP__A 0x1450016 +#define QAM_LC_EP__W 6 +#define QAM_LC_EP__M 0x3F +#define QAM_LC_EP__PRE 0x0 + +#define QAM_LC_EP_COEF__B 0 +#define QAM_LC_EP_COEF__W 6 +#define QAM_LC_EP_COEF__M 0x3F +#define QAM_LC_EP_COEF__PRE 0x0 + +#define QAM_LC_EI__A 0x1450017 +#define QAM_LC_EI__W 6 +#define QAM_LC_EI__M 0x3F +#define QAM_LC_EI__PRE 0x0 + +#define QAM_LC_EI_COEF__B 0 +#define QAM_LC_EI_COEF__W 6 +#define QAM_LC_EI_COEF__M 0x3F +#define QAM_LC_EI_COEF__PRE 0x0 + +#define QAM_LC_QUAL_TAB0__A 0x1450018 +#define QAM_LC_QUAL_TAB0__W 5 +#define QAM_LC_QUAL_TAB0__M 0x1F +#define QAM_LC_QUAL_TAB0__PRE 0x1 + +#define QAM_LC_QUAL_TAB0_VALUE__B 0 +#define QAM_LC_QUAL_TAB0_VALUE__W 5 +#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB1__A 0x1450019 +#define QAM_LC_QUAL_TAB1__W 5 +#define QAM_LC_QUAL_TAB1__M 0x1F +#define QAM_LC_QUAL_TAB1__PRE 0x1 + +#define QAM_LC_QUAL_TAB1_VALUE__B 0 +#define QAM_LC_QUAL_TAB1_VALUE__W 5 +#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB2__A 0x145001A +#define QAM_LC_QUAL_TAB2__W 5 +#define QAM_LC_QUAL_TAB2__M 0x1F +#define QAM_LC_QUAL_TAB2__PRE 0x1 + +#define QAM_LC_QUAL_TAB2_VALUE__B 0 +#define QAM_LC_QUAL_TAB2_VALUE__W 5 +#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB3__A 0x145001B +#define QAM_LC_QUAL_TAB3__W 5 +#define QAM_LC_QUAL_TAB3__M 0x1F +#define QAM_LC_QUAL_TAB3__PRE 0x1 + +#define QAM_LC_QUAL_TAB3_VALUE__B 0 +#define QAM_LC_QUAL_TAB3_VALUE__W 5 +#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB4__A 0x145001C +#define QAM_LC_QUAL_TAB4__W 5 +#define QAM_LC_QUAL_TAB4__M 0x1F +#define QAM_LC_QUAL_TAB4__PRE 0x1 + +#define QAM_LC_QUAL_TAB4_VALUE__B 0 +#define QAM_LC_QUAL_TAB4_VALUE__W 5 +#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB5__A 0x145001D +#define QAM_LC_QUAL_TAB5__W 5 +#define QAM_LC_QUAL_TAB5__M 0x1F +#define QAM_LC_QUAL_TAB5__PRE 0x1 + +#define QAM_LC_QUAL_TAB5_VALUE__B 0 +#define QAM_LC_QUAL_TAB5_VALUE__W 5 +#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB6__A 0x145001E +#define QAM_LC_QUAL_TAB6__W 5 +#define QAM_LC_QUAL_TAB6__M 0x1F +#define QAM_LC_QUAL_TAB6__PRE 0x1 + +#define QAM_LC_QUAL_TAB6_VALUE__B 0 +#define QAM_LC_QUAL_TAB6_VALUE__W 5 +#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB8__A 0x145001F +#define QAM_LC_QUAL_TAB8__W 5 +#define QAM_LC_QUAL_TAB8__M 0x1F +#define QAM_LC_QUAL_TAB8__PRE 0x1 + +#define QAM_LC_QUAL_TAB8_VALUE__B 0 +#define QAM_LC_QUAL_TAB8_VALUE__W 5 +#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB9__A 0x1450020 +#define QAM_LC_QUAL_TAB9__W 5 +#define QAM_LC_QUAL_TAB9__M 0x1F +#define QAM_LC_QUAL_TAB9__PRE 0x1 + +#define QAM_LC_QUAL_TAB9_VALUE__B 0 +#define QAM_LC_QUAL_TAB9_VALUE__W 5 +#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB10__A 0x1450021 +#define QAM_LC_QUAL_TAB10__W 5 +#define QAM_LC_QUAL_TAB10__M 0x1F +#define QAM_LC_QUAL_TAB10__PRE 0x1 + +#define QAM_LC_QUAL_TAB10_VALUE__B 0 +#define QAM_LC_QUAL_TAB10_VALUE__W 5 +#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB10_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB12__A 0x1450022 +#define QAM_LC_QUAL_TAB12__W 5 +#define QAM_LC_QUAL_TAB12__M 0x1F +#define QAM_LC_QUAL_TAB12__PRE 0x1 + +#define QAM_LC_QUAL_TAB12_VALUE__B 0 +#define QAM_LC_QUAL_TAB12_VALUE__W 5 +#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB12_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB15__A 0x1450023 +#define QAM_LC_QUAL_TAB15__W 5 +#define QAM_LC_QUAL_TAB15__M 0x1F +#define QAM_LC_QUAL_TAB15__PRE 0x1 + +#define QAM_LC_QUAL_TAB15_VALUE__B 0 +#define QAM_LC_QUAL_TAB15_VALUE__W 5 +#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB15_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB16__A 0x1450024 +#define QAM_LC_QUAL_TAB16__W 5 +#define QAM_LC_QUAL_TAB16__M 0x1F +#define QAM_LC_QUAL_TAB16__PRE 0x1 + +#define QAM_LC_QUAL_TAB16_VALUE__B 0 +#define QAM_LC_QUAL_TAB16_VALUE__W 5 +#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB20__A 0x1450025 +#define QAM_LC_QUAL_TAB20__W 5 +#define QAM_LC_QUAL_TAB20__M 0x1F +#define QAM_LC_QUAL_TAB20__PRE 0x1 + +#define QAM_LC_QUAL_TAB20_VALUE__B 0 +#define QAM_LC_QUAL_TAB20_VALUE__W 5 +#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB25__A 0x1450026 +#define QAM_LC_QUAL_TAB25__W 5 +#define QAM_LC_QUAL_TAB25__M 0x1F +#define QAM_LC_QUAL_TAB25__PRE 0x1 + +#define QAM_LC_QUAL_TAB25_VALUE__B 0 +#define QAM_LC_QUAL_TAB25_VALUE__W 5 +#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x1 + +#define QAM_LC_EQ_TIMING__A 0x1450027 +#define QAM_LC_EQ_TIMING__W 10 +#define QAM_LC_EQ_TIMING__M 0x3FF +#define QAM_LC_EQ_TIMING__PRE 0x0 + +#define QAM_LC_EQ_TIMING_OFFS__B 0 +#define QAM_LC_EQ_TIMING_OFFS__W 10 +#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF +#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 + +#define QAM_LC_LPF_FACTORP__A 0x1450028 +#define QAM_LC_LPF_FACTORP__W 3 +#define QAM_LC_LPF_FACTORP__M 0x7 +#define QAM_LC_LPF_FACTORP__PRE 0x3 + +#define QAM_LC_LPF_FACTORP_FACTOR__B 0 +#define QAM_LC_LPF_FACTORP_FACTOR__W 3 +#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 + +#define QAM_LC_LPF_FACTORI__A 0x1450029 +#define QAM_LC_LPF_FACTORI__W 3 +#define QAM_LC_LPF_FACTORI__M 0x7 +#define QAM_LC_LPF_FACTORI__PRE 0x3 + +#define QAM_LC_LPF_FACTORI_FACTOR__B 0 +#define QAM_LC_LPF_FACTORI_FACTOR__W 3 +#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 + +#define QAM_LC_RATE_LIMIT__A 0x145002A +#define QAM_LC_RATE_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT__PRE 0x3 + +#define QAM_LC_RATE_LIMIT_LIMIT__B 0 +#define QAM_LC_RATE_LIMIT_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 + +#define QAM_LC_SYMBOL_FREQ__A 0x145002B +#define QAM_LC_SYMBOL_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ__PRE 0x199 + +#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 +#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x199 +#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_64 0x197 +#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256 0x1B2 + +#define QAM_LC_MTA_LENGTH__A 0x145002C +#define QAM_LC_MTA_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH__PRE 0x2 + +#define QAM_LC_MTA_LENGTH_LENGTH__B 0 +#define QAM_LC_MTA_LENGTH_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 + +#define QAM_LC_AMP_ACCU__A 0x145002D +#define QAM_LC_AMP_ACCU__W 14 +#define QAM_LC_AMP_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU__PRE 0x600 + +#define QAM_LC_AMP_ACCU_ACCU__B 0 +#define QAM_LC_AMP_ACCU_ACCU__W 14 +#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 + +#define QAM_LC_FREQ_ACCU__A 0x145002E +#define QAM_LC_FREQ_ACCU__W 10 +#define QAM_LC_FREQ_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU__PRE 0x0 + +#define QAM_LC_FREQ_ACCU_ACCU__B 0 +#define QAM_LC_FREQ_ACCU_ACCU__W 10 +#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU__A 0x145002F +#define QAM_LC_RATE_ACCU__W 10 +#define QAM_LC_RATE_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU_ACCU__B 0 +#define QAM_LC_RATE_ACCU_ACCU__W 10 +#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_AMPLITUDE__A 0x1450030 +#define QAM_LC_AMPLITUDE__W 10 +#define QAM_LC_AMPLITUDE__M 0x3FF +#define QAM_LC_AMPLITUDE__PRE 0x0 + +#define QAM_LC_AMPLITUDE_SIZE__B 0 +#define QAM_LC_AMPLITUDE_SIZE__W 10 +#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF +#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 + +#define QAM_LC_RAD_ERROR__A 0x1450031 +#define QAM_LC_RAD_ERROR__W 10 +#define QAM_LC_RAD_ERROR__M 0x3FF +#define QAM_LC_RAD_ERROR__PRE 0x0 + +#define QAM_LC_RAD_ERROR_SIZE__B 0 +#define QAM_LC_RAD_ERROR_SIZE__W 10 +#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF +#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 + +#define QAM_LC_FREQ_OFFS__A 0x1450032 +#define QAM_LC_FREQ_OFFS__W 10 +#define QAM_LC_FREQ_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS__PRE 0x0 + +#define QAM_LC_FREQ_OFFS_OFFS__B 0 +#define QAM_LC_FREQ_OFFS_OFFS__W 10 +#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 + +#define QAM_LC_PHASE_ERROR__A 0x1450033 +#define QAM_LC_PHASE_ERROR__W 10 +#define QAM_LC_PHASE_ERROR__M 0x3FF +#define QAM_LC_PHASE_ERROR__PRE 0x0 + +#define QAM_LC_PHASE_ERROR_SIZE__B 0 +#define QAM_LC_PHASE_ERROR_SIZE__W 10 +#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF +#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 + +#define QAM_VD_COMM_EXEC__A 0x1460000 +#define QAM_VD_COMM_EXEC__W 2 +#define QAM_VD_COMM_EXEC__M 0x3 +#define QAM_VD_COMM_EXEC__PRE 0x0 +#define QAM_VD_COMM_EXEC_STOP 0x0 +#define QAM_VD_COMM_EXEC_ACTIVE 0x1 +#define QAM_VD_COMM_EXEC_HOLD 0x2 + +#define QAM_VD_COMM_MB__A 0x1460002 +#define QAM_VD_COMM_MB__W 2 +#define QAM_VD_COMM_MB__M 0x3 +#define QAM_VD_COMM_MB__PRE 0x0 +#define QAM_VD_COMM_MB_CTL__B 0 +#define QAM_VD_COMM_MB_CTL__W 1 +#define QAM_VD_COMM_MB_CTL__M 0x1 +#define QAM_VD_COMM_MB_CTL__PRE 0x0 +#define QAM_VD_COMM_MB_CTL_OFF 0x0 +#define QAM_VD_COMM_MB_CTL_ON 0x1 +#define QAM_VD_COMM_MB_OBS__B 1 +#define QAM_VD_COMM_MB_OBS__W 1 +#define QAM_VD_COMM_MB_OBS__M 0x2 +#define QAM_VD_COMM_MB_OBS__PRE 0x0 +#define QAM_VD_COMM_MB_OBS_OFF 0x0 +#define QAM_VD_COMM_MB_OBS_ON 0x2 + +#define QAM_VD_COMM_INT_REQ__A 0x1460003 +#define QAM_VD_COMM_INT_REQ__W 1 +#define QAM_VD_COMM_INT_REQ__M 0x1 +#define QAM_VD_COMM_INT_REQ__PRE 0x0 +#define QAM_VD_COMM_INT_STA__A 0x1460005 +#define QAM_VD_COMM_INT_STA__W 2 +#define QAM_VD_COMM_INT_STA__M 0x3 +#define QAM_VD_COMM_INT_STA__PRE 0x0 + +#define QAM_VD_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_STA_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_STA_PERIOD_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_MSK__A 0x1460006 +#define QAM_VD_COMM_INT_MSK__W 2 +#define QAM_VD_COMM_INT_MSK__M 0x3 +#define QAM_VD_COMM_INT_MSK__PRE 0x0 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_MSK_LOCK_INT__PRE 0x0 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_MSK_PERIOD_INT__PRE 0x0 + +#define QAM_VD_COMM_INT_STM__A 0x1460007 +#define QAM_VD_COMM_INT_STM__W 2 +#define QAM_VD_COMM_INT_STM__M 0x3 +#define QAM_VD_COMM_INT_STM__PRE 0x0 +#define QAM_VD_COMM_INT_STM_LOCK_INT__B 0 +#define QAM_VD_COMM_INT_STM_LOCK_INT__W 1 +#define QAM_VD_COMM_INT_STM_LOCK_INT__M 0x1 +#define QAM_VD_COMM_INT_STM_LOCK_INT__PRE 0x0 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__B 1 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__W 1 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__M 0x2 +#define QAM_VD_COMM_INT_STM_PERIOD_INT__PRE 0x0 + +#define QAM_VD_STATUS__A 0x1460010 +#define QAM_VD_STATUS__W 1 +#define QAM_VD_STATUS__M 0x1 +#define QAM_VD_STATUS__PRE 0x0 + +#define QAM_VD_STATUS_LOCK__B 0 +#define QAM_VD_STATUS_LOCK__W 1 +#define QAM_VD_STATUS_LOCK__M 0x1 +#define QAM_VD_STATUS_LOCK__PRE 0x0 + +#define QAM_VD_UNLOCK_CONTROL__A 0x1460011 +#define QAM_VD_UNLOCK_CONTROL__W 1 +#define QAM_VD_UNLOCK_CONTROL__M 0x1 +#define QAM_VD_UNLOCK_CONTROL__PRE 0x0 + +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__B 0 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__W 1 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__M 0x1 +#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__PRE 0x0 + +#define QAM_VD_MIN_VOTING_ROUNDS__A 0x1460012 +#define QAM_VD_MIN_VOTING_ROUNDS__W 6 +#define QAM_VD_MIN_VOTING_ROUNDS__M 0x3F +#define QAM_VD_MIN_VOTING_ROUNDS__PRE 0x10 + +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__B 0 +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__W 6 +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__M 0x3F +#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__PRE 0x10 + +#define QAM_VD_MAX_VOTING_ROUNDS__A 0x1460013 +#define QAM_VD_MAX_VOTING_ROUNDS__W 6 +#define QAM_VD_MAX_VOTING_ROUNDS__M 0x3F +#define QAM_VD_MAX_VOTING_ROUNDS__PRE 0x10 + +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__B 0 +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__W 6 +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__M 0x3F +#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__PRE 0x10 + +#define QAM_VD_TRACEBACK_DEPTH__A 0x1460014 +#define QAM_VD_TRACEBACK_DEPTH__W 5 +#define QAM_VD_TRACEBACK_DEPTH__M 0x1F +#define QAM_VD_TRACEBACK_DEPTH__PRE 0x10 + +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__B 0 +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__W 5 +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__M 0x1F +#define QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE 0x10 + +#define QAM_VD_UNLOCK__A 0x1460015 +#define QAM_VD_UNLOCK__W 1 +#define QAM_VD_UNLOCK__M 0x1 +#define QAM_VD_UNLOCK__PRE 0x0 +#define QAM_VD_MEASUREMENT_PERIOD__A 0x1460016 +#define QAM_VD_MEASUREMENT_PERIOD__W 16 +#define QAM_VD_MEASUREMENT_PERIOD__M 0xFFFF +#define QAM_VD_MEASUREMENT_PERIOD__PRE 0x8236 + +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__B 0 +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__W 16 +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__PRE 0x8236 + +#define QAM_VD_MEASUREMENT_PRESCALE__A 0x1460017 +#define QAM_VD_MEASUREMENT_PRESCALE__W 16 +#define QAM_VD_MEASUREMENT_PRESCALE__M 0xFFFF +#define QAM_VD_MEASUREMENT_PRESCALE__PRE 0x4 + +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x4 + +#define QAM_VD_DELTA_PATH_METRIC__A 0x1460018 +#define QAM_VD_DELTA_PATH_METRIC__W 16 +#define QAM_VD_DELTA_PATH_METRIC__M 0xFFFF +#define QAM_VD_DELTA_PATH_METRIC__PRE 0xFFFF + +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__B 0 +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__W 12 +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__M 0xFFF +#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_DELTA_PATH_METRIC_EXP__B 12 +#define QAM_VD_DELTA_PATH_METRIC_EXP__W 4 +#define QAM_VD_DELTA_PATH_METRIC_EXP__M 0xF000 +#define QAM_VD_DELTA_PATH_METRIC_EXP__PRE 0xF000 + +#define QAM_VD_NR_QSYM_ERRORS__A 0x1460019 +#define QAM_VD_NR_QSYM_ERRORS__W 16 +#define QAM_VD_NR_QSYM_ERRORS__M 0xFFFF +#define QAM_VD_NR_QSYM_ERRORS__PRE 0xFFFF + +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__B 0 +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__W 12 +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__M 0xFFF +#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_NR_QSYM_ERRORS_EXP__B 12 +#define QAM_VD_NR_QSYM_ERRORS_EXP__W 4 +#define QAM_VD_NR_QSYM_ERRORS_EXP__M 0xF000 +#define QAM_VD_NR_QSYM_ERRORS_EXP__PRE 0xF000 + +#define QAM_VD_NR_SYMBOL_ERRORS__A 0x146001A +#define QAM_VD_NR_SYMBOL_ERRORS__W 16 +#define QAM_VD_NR_SYMBOL_ERRORS__M 0xFFFF +#define QAM_VD_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__B 12 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__W 4 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define QAM_VD_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define QAM_VD_RELOCK_COUNT__A 0x146001B +#define QAM_VD_RELOCK_COUNT__W 16 +#define QAM_VD_RELOCK_COUNT__M 0xFFFF +#define QAM_VD_RELOCK_COUNT__PRE 0x0 + +#define QAM_VD_RELOCK_COUNT_COUNT__B 0 +#define QAM_VD_RELOCK_COUNT_COUNT__W 8 +#define QAM_VD_RELOCK_COUNT_COUNT__M 0xFF +#define QAM_VD_RELOCK_COUNT_COUNT__PRE 0x0 + +#define QAM_SY_COMM_EXEC__A 0x1470000 +#define QAM_SY_COMM_EXEC__W 2 +#define QAM_SY_COMM_EXEC__M 0x3 +#define QAM_SY_COMM_EXEC__PRE 0x0 +#define QAM_SY_COMM_EXEC_STOP 0x0 +#define QAM_SY_COMM_EXEC_ACTIVE 0x1 +#define QAM_SY_COMM_EXEC_HOLD 0x2 + +#define QAM_SY_COMM_MB__A 0x1470002 +#define QAM_SY_COMM_MB__W 2 +#define QAM_SY_COMM_MB__M 0x3 +#define QAM_SY_COMM_MB__PRE 0x0 +#define QAM_SY_COMM_MB_CTL__B 0 +#define QAM_SY_COMM_MB_CTL__W 1 +#define QAM_SY_COMM_MB_CTL__M 0x1 +#define QAM_SY_COMM_MB_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_CTL_OFF 0x0 +#define QAM_SY_COMM_MB_CTL_ON 0x1 +#define QAM_SY_COMM_MB_OBS__B 1 +#define QAM_SY_COMM_MB_OBS__W 1 +#define QAM_SY_COMM_MB_OBS__M 0x2 +#define QAM_SY_COMM_MB_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_OBS_OFF 0x0 +#define QAM_SY_COMM_MB_OBS_ON 0x2 + +#define QAM_SY_COMM_INT_REQ__A 0x1470003 +#define QAM_SY_COMM_INT_REQ__W 1 +#define QAM_SY_COMM_INT_REQ__M 0x1 +#define QAM_SY_COMM_INT_REQ__PRE 0x0 +#define QAM_SY_COMM_INT_STA__A 0x1470005 +#define QAM_SY_COMM_INT_STA__W 4 +#define QAM_SY_COMM_INT_STA__M 0xF +#define QAM_SY_COMM_INT_STA__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_MSK__A 0x1470006 +#define QAM_SY_COMM_INT_MSK__W 4 +#define QAM_SY_COMM_INT_MSK__M 0xF +#define QAM_SY_COMM_INT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_COMM_INT_STM__A 0x1470007 +#define QAM_SY_COMM_INT_STM__W 4 +#define QAM_SY_COMM_INT_STM__M 0xF +#define QAM_SY_COMM_INT_STM__PRE 0x0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_STATUS__A 0x1470010 +#define QAM_SY_STATUS__W 2 +#define QAM_SY_STATUS__M 0x3 +#define QAM_SY_STATUS__PRE 0x0 + +#define QAM_SY_STATUS_SYNC_STATE__B 0 +#define QAM_SY_STATUS_SYNC_STATE__W 2 +#define QAM_SY_STATUS_SYNC_STATE__M 0x3 +#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 + +#define QAM_SY_TIMEOUT__A 0x1470011 +#define QAM_SY_TIMEOUT__W 16 +#define QAM_SY_TIMEOUT__M 0xFFFF +#define QAM_SY_TIMEOUT__PRE 0x3A98 + +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__W 4 +#define QAM_SY_SYNC_LWM__M 0xF +#define QAM_SY_SYNC_LWM__PRE 0x2 + +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__W 4 +#define QAM_SY_SYNC_AWM__M 0xF +#define QAM_SY_SYNC_AWM__PRE 0x3 + +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__W 4 +#define QAM_SY_SYNC_HWM__M 0xF +#define QAM_SY_SYNC_HWM__PRE 0x5 + +#define QAM_SY_UNLOCK__A 0x1470015 +#define QAM_SY_UNLOCK__W 1 +#define QAM_SY_UNLOCK__M 0x1 +#define QAM_SY_UNLOCK__PRE 0x0 +#define QAM_SY_CONTROL_WORD__A 0x1470016 +#define QAM_SY_CONTROL_WORD__W 4 +#define QAM_SY_CONTROL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD__PRE 0x0 + +#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 + +#define QAM_VD_ISS_RAM__A 0x1480000 + +#define QAM_VD_QSS_RAM__A 0x1490000 + +#define QAM_VD_SYM_RAM__A 0x14A0000 + +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__W 2 +#define SCU_COMM_EXEC__M 0x3 +#define SCU_COMM_EXEC__PRE 0x0 +#define SCU_COMM_EXEC_STOP 0x0 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_HOLD 0x2 + +#define SCU_COMM_STATE__A 0x800001 +#define SCU_COMM_STATE__W 16 +#define SCU_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE__PRE 0x0 + +#define SCU_COMM_STATE_COMM_STATE__B 0 +#define SCU_COMM_STATE_COMM_STATE__W 16 +#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 + +#define SCU_TOP_COMM_EXEC__A 0x810000 +#define SCU_TOP_COMM_EXEC__W 2 +#define SCU_TOP_COMM_EXEC__M 0x3 +#define SCU_TOP_COMM_EXEC__PRE 0x0 +#define SCU_TOP_COMM_EXEC_STOP 0x0 +#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 +#define SCU_TOP_COMM_EXEC_HOLD 0x2 + +#define SCU_TOP_COMM_STATE__A 0x810001 +#define SCU_TOP_COMM_STATE__W 16 +#define SCU_TOP_COMM_STATE__M 0xFFFF +#define SCU_TOP_COMM_STATE__PRE 0x0 +#define SCU_TOP_MWAIT_CTR__A 0x810010 +#define SCU_TOP_MWAIT_CTR__W 2 +#define SCU_TOP_MWAIT_CTR__M 0x3 +#define SCU_TOP_MWAIT_CTR__PRE 0x0 + +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 + +#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 +#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 + +#define SCU_LOW_RAM__A 0x820000 + +#define SCU_LOW_RAM_LOW__B 0 +#define SCU_LOW_RAM_LOW__W 16 +#define SCU_LOW_RAM_LOW__M 0xFFFF +#define SCU_LOW_RAM_LOW__PRE 0x0 + +#define SCU_HIGH_RAM__A 0x830000 + +#define SCU_HIGH_RAM_HIGH__B 0 +#define SCU_HIGH_RAM_HIGH__W 16 +#define SCU_HIGH_RAM_HIGH__M 0xFFFF +#define SCU_HIGH_RAM_HIGH__PRE 0x0 + +#define SCU_RAM_AGC_RF_MAX__A 0x831E96 +#define SCU_RAM_AGC_RF_MAX__W 15 +#define SCU_RAM_AGC_RF_MAX__M 0x7FFF +#define SCU_RAM_AGC_RF_MAX__PRE 0x0 + +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831E97 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCCNT__A 0x831E98 +#define SCU_RAM_AGC_KI_CYCCNT__W 16 +#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCLEN__A 0x831E99 +#define SCU_RAM_AGC_KI_CYCLEN__W 16 +#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831E9A +#define SCU_RAM_AGC_SNS_CYCLEN__W 16 +#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831E9B +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x0 + +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831E9C +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0x0 +#define SCU_RAM_AGC_KI__A 0x831E9D +#define SCU_RAM_AGC_KI__W 15 +#define SCU_RAM_AGC_KI__M 0x7FFF +#define SCU_RAM_AGC_KI__PRE 0x0 + +#define SCU_RAM_AGC_KI_DGAIN__B 0 +#define SCU_RAM_AGC_KI_DGAIN__W 4 +#define SCU_RAM_AGC_KI_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_RF__B 4 +#define SCU_RAM_AGC_KI_RF__W 4 +#define SCU_RAM_AGC_KI_RF__M 0xF0 +#define SCU_RAM_AGC_KI_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_IF__B 8 +#define SCU_RAM_AGC_KI_IF__W 4 +#define SCU_RAM_AGC_KI_IF__M 0xF00 +#define SCU_RAM_AGC_KI_IF__PRE 0x0 + +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__B 12 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__W 1 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__M 0x1000 +#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__PRE 0x0 + +#define SCU_RAM_AGC_KI_INV_IF_POL__B 13 +#define SCU_RAM_AGC_KI_INV_IF_POL__W 1 +#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 +#define SCU_RAM_AGC_KI_INV_IF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI_INV_RF_POL__B 14 +#define SCU_RAM_AGC_KI_INV_RF_POL__W 1 +#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 +#define SCU_RAM_AGC_KI_INV_RF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED__A 0x831E9E +#define SCU_RAM_AGC_KI_RED__W 6 +#define SCU_RAM_AGC_KI_RED__M 0x3F +#define SCU_RAM_AGC_KI_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 +#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 +#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 +#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831E9F +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MINGAIN__A 0x831EA0 +#define SCU_RAM_AGC_KI_MINGAIN__W 16 +#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831EA1 +#define SCU_RAM_AGC_KI_MAXGAIN__W 16 +#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831EA2 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 +#define SCU_RAM_AGC_KI_MIN__A 0x831EA3 +#define SCU_RAM_AGC_KI_MIN__W 12 +#define SCU_RAM_AGC_KI_MIN__M 0xFFF +#define SCU_RAM_AGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_RF__B 4 +#define SCU_RAM_AGC_KI_MIN_RF__W 4 +#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_IF__B 8 +#define SCU_RAM_AGC_KI_MIN_IF__W 4 +#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX__A 0x831EA4 +#define SCU_RAM_AGC_KI_MAX__W 12 +#define SCU_RAM_AGC_KI_MAX__M 0xFFF +#define SCU_RAM_AGC_KI_MAX__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_RF__B 4 +#define SCU_RAM_AGC_KI_MAX_RF__W 4 +#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MAX_RF__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_IF__B 8 +#define SCU_RAM_AGC_KI_MAX_IF__W 4 +#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MAX_IF__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM__A 0x831EA5 +#define SCU_RAM_AGC_CLP_SUM__W 16 +#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831EA6 +#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 +#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831EA7 +#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 +#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831EA8 +#define SCU_RAM_AGC_CLP_CYCLEN__W 16 +#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831EA9 +#define SCU_RAM_AGC_CLP_CYCCNT__W 16 +#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831EAA +#define SCU_RAM_AGC_CLP_DIR_TO__W 8 +#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831EAB +#define SCU_RAM_AGC_CLP_DIR_WD__W 8 +#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831EAC +#define SCU_RAM_AGC_CLP_DIR_STP__W 16 +#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM__A 0x831EAD +#define SCU_RAM_AGC_SNS_SUM__W 16 +#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831EAE +#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 +#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831EAF +#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 +#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x0 + +#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831EB0 +#define SCU_RAM_AGC_SNS_CYCCNT__W 16 +#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831EB1 +#define SCU_RAM_AGC_SNS_DIR_TO__W 8 +#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831EB2 +#define SCU_RAM_AGC_SNS_DIR_WD__W 8 +#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831EB3 +#define SCU_RAM_AGC_SNS_DIR_STP__W 16 +#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN__A 0x831EB4 +#define SCU_RAM_AGC_INGAIN__W 16 +#define SCU_RAM_AGC_INGAIN__M 0xFFFF +#define SCU_RAM_AGC_INGAIN__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT__A 0x831EB5 +#define SCU_RAM_AGC_INGAIN_TGT__W 15 +#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831EB6 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831EB7 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831EB8 +#define SCU_RAM_AGC_IF_IACCU_HI__W 16 +#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831EB9 +#define SCU_RAM_AGC_IF_IACCU_LO__W 8 +#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831EBA +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831EBB +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831EBC +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831EBD +#define SCU_RAM_AGC_RF_IACCU_HI__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831EBE +#define SCU_RAM_AGC_RF_IACCU_LO__W 8 +#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831EBF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 + +#define SCU_RAM_SP__A 0x831EC0 +#define SCU_RAM_SP__W 16 +#define SCU_RAM_SP__M 0xFFFF +#define SCU_RAM_SP__PRE 0x0 + +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831EC1 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x0 + +#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC2 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC3 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_MEAS_COUNT__A 0x831EC4 +#define SCU_RAM_FEC_MEAS_COUNT__W 16 +#define SCU_RAM_FEC_MEAS_COUNT__M 0xFFFF +#define SCU_RAM_FEC_MEAS_COUNT__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A 0x831EC5 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__W 16 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__A 0x831EC6 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__W 16 +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__PRE 0x0 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__W 1 +#define SCU_RAM_GPIO__M 0x1 +#define SCU_RAM_GPIO__PRE 0x0 + +#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 +#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 +#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 +#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF +#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_false 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_true 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 + +#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA +#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 + +#define SCU_RAM_INHIBIT_1__A 0x831ECC +#define SCU_RAM_INHIBIT_1__W 16 +#define SCU_RAM_INHIBIT_1__M 0xFFFF +#define SCU_RAM_INHIBIT_1__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_0__A 0x831ECD +#define SCU_RAM_HTOL_BUF_0__W 16 +#define SCU_RAM_HTOL_BUF_0__M 0xFFFF +#define SCU_RAM_HTOL_BUF_0__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_1__A 0x831ECE +#define SCU_RAM_HTOL_BUF_1__W 16 +#define SCU_RAM_HTOL_BUF_1__M 0xFFFF +#define SCU_RAM_HTOL_BUF_1__PRE 0x0 + +#define SCU_RAM_INHIBIT_2__A 0x831ECF +#define SCU_RAM_INHIBIT_2__W 16 +#define SCU_RAM_INHIBIT_2__M 0xFFFF +#define SCU_RAM_INHIBIT_2__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 +#define SCU_RAM_TR_SHORT_BUF_0__W 16 +#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 +#define SCU_RAM_TR_SHORT_BUF_1__W 16 +#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 +#define SCU_RAM_TR_LONG_BUF_0__W 16 +#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 +#define SCU_RAM_TR_LONG_BUF_1__W 16 +#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 +#define SCU_RAM_TR_LONG_BUF_2__W 16 +#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 +#define SCU_RAM_TR_LONG_BUF_3__W 16 +#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 +#define SCU_RAM_TR_LONG_BUF_4__W 16 +#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 +#define SCU_RAM_TR_LONG_BUF_5__W 16 +#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 +#define SCU_RAM_TR_LONG_BUF_6__W 16 +#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 +#define SCU_RAM_TR_LONG_BUF_7__W 16 +#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA +#define SCU_RAM_TR_LONG_BUF_8__W 16 +#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB +#define SCU_RAM_TR_LONG_BUF_9__W 16 +#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC +#define SCU_RAM_TR_LONG_BUF_10__W 16 +#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD +#define SCU_RAM_TR_LONG_BUF_11__W 16 +#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE +#define SCU_RAM_TR_LONG_BUF_12__W 16 +#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF +#define SCU_RAM_TR_LONG_BUF_13__W 16 +#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 +#define SCU_RAM_TR_LONG_BUF_14__W 16 +#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 +#define SCU_RAM_TR_LONG_BUF_15__W 16 +#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 +#define SCU_RAM_TR_LONG_BUF_16__W 16 +#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 +#define SCU_RAM_TR_LONG_BUF_17__W 16 +#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 +#define SCU_RAM_TR_LONG_BUF_18__W 16 +#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 +#define SCU_RAM_TR_LONG_BUF_19__W 16 +#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 +#define SCU_RAM_TR_LONG_BUF_20__W 16 +#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 +#define SCU_RAM_TR_LONG_BUF_21__W 16 +#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 +#define SCU_RAM_TR_LONG_BUF_22__W 16 +#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 +#define SCU_RAM_TR_LONG_BUF_23__W 16 +#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA +#define SCU_RAM_TR_LONG_BUF_24__W 16 +#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB +#define SCU_RAM_TR_LONG_BUF_25__W 16 +#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC +#define SCU_RAM_TR_LONG_BUF_26__W 16 +#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED +#define SCU_RAM_TR_LONG_BUF_27__W 16 +#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE +#define SCU_RAM_TR_LONG_BUF_28__W 16 +#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF +#define SCU_RAM_TR_LONG_BUF_29__W 16 +#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 +#define SCU_RAM_TR_LONG_BUF_30__W 16 +#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 +#define SCU_RAM_TR_LONG_BUF_31__W 16 +#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 +#define SCU_RAM_ATV_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 +#define SCU_RAM_ATV_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 +#define SCU_RAM_ATV_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 +#define SCU_RAM_ATV_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 + +#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 +#define SCU_RAM_ATV_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 +#define SCU_RAM_ATV_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 +#define SCU_RAM_ATV_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 +#define SCU_RAM_ATV_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF__A 0x831EFA +#define SCU_RAM_ATV_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 +#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB +#define SCU_RAM_ATV_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC +#define SCU_RAM_ATV_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT__A 0x831EFD +#define SCU_RAM_ATV_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE +#define SCU_RAM_ATV_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF +#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 +#define SCU_RAM_ATV_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A 0x831F01 +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W 16 +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M 0xFFFF +#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__PRE 0x0 + +#define SCU_RAM_ORX_RF_RX_DATA_RATE__A 0x831F02 +#define SCU_RAM_ORX_RF_RX_DATA_RATE__W 8 +#define SCU_RAM_ORX_RF_RX_DATA_RATE__M 0xFF +#define SCU_RAM_ORX_RF_RX_DATA_RATE__PRE 0x0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC 0x0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC 0x1 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT 0x40 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT 0x41 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC 0x80 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC 0x81 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC 0xC0 +#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC 0xC1 + +#define SCU_RAM_ORX_SCU_STATE__A 0x831F03 +#define SCU_RAM_ORX_SCU_STATE__W 8 +#define SCU_RAM_ORX_SCU_STATE__M 0xFF +#define SCU_RAM_ORX_SCU_STATE__PRE 0x0 +#define SCU_RAM_ORX_SCU_STATE_RESET 0x0 +#define SCU_RAM_ORX_SCU_STATE_AGN_HUNT 0x1 +#define SCU_RAM_ORX_SCU_STATE_DGN_HUNT 0x2 +#define SCU_RAM_ORX_SCU_STATE_AGC_HUNT 0x3 +#define SCU_RAM_ORX_SCU_STATE_FRQ_HUNT 0x4 +#define SCU_RAM_ORX_SCU_STATE_PHA_HUNT 0x8 +#define SCU_RAM_ORX_SCU_STATE_TIM_HUNT 0x10 +#define SCU_RAM_ORX_SCU_STATE_EQU_HUNT 0x20 +#define SCU_RAM_ORX_SCU_STATE_EQT_HUNT 0x30 +#define SCU_RAM_ORX_SCU_STATE_SYNC 0x40 + +#define SCU_RAM_ORX_SCU_LOCK__A 0x831F04 +#define SCU_RAM_ORX_SCU_LOCK__W 16 +#define SCU_RAM_ORX_SCU_LOCK__M 0xFFFF +#define SCU_RAM_ORX_SCU_LOCK__PRE 0x0 + +#define SCU_RAM_ORX_TARGET_MODE__A 0x831F05 +#define SCU_RAM_ORX_TARGET_MODE__W 2 +#define SCU_RAM_ORX_TARGET_MODE__M 0x3 +#define SCU_RAM_ORX_TARGET_MODE__PRE 0x0 +#define SCU_RAM_ORX_TARGET_MODE_1544KBPS 0x0 +#define SCU_RAM_ORX_TARGET_MODE_3088KBPS 0x1 +#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT 0x2 +#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO 0x3 + +#define SCU_RAM_ORX_MER_MIN_DB__A 0x831F06 +#define SCU_RAM_ORX_MER_MIN_DB__W 8 +#define SCU_RAM_ORX_MER_MIN_DB__M 0xFF +#define SCU_RAM_ORX_MER_MIN_DB__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN__A 0x831F07 +#define SCU_RAM_ORX_RF_GAIN__W 16 +#define SCU_RAM_ORX_RF_GAIN__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN_MIN__A 0x831F08 +#define SCU_RAM_ORX_RF_GAIN_MIN__W 16 +#define SCU_RAM_ORX_RF_GAIN_MIN__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_RF_GAIN_MAX__A 0x831F09 +#define SCU_RAM_ORX_RF_GAIN_MAX__W 16 +#define SCU_RAM_ORX_RF_GAIN_MAX__M 0xFFFF +#define SCU_RAM_ORX_RF_GAIN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN__A 0x831F0A +#define SCU_RAM_ORX_IF_GAIN__W 16 +#define SCU_RAM_ORX_IF_GAIN__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN_MIN__A 0x831F0B +#define SCU_RAM_ORX_IF_GAIN_MIN__W 16 +#define SCU_RAM_ORX_IF_GAIN_MIN__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_IF_GAIN_MAX__A 0x831F0C +#define SCU_RAM_ORX_IF_GAIN_MAX__W 16 +#define SCU_RAM_ORX_IF_GAIN_MAX__M 0xFFFF +#define SCU_RAM_ORX_IF_GAIN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_AGN_HEADR__A 0x831F0D +#define SCU_RAM_ORX_AGN_HEADR__W 16 +#define SCU_RAM_ORX_AGN_HEADR__M 0xFFFF +#define SCU_RAM_ORX_AGN_HEADR__PRE 0x0 + +#define SCU_RAM_ORX_AGN_HEADR_STP__A 0x831F0E +#define SCU_RAM_ORX_AGN_HEADR_STP__W 8 +#define SCU_RAM_ORX_AGN_HEADR_STP__M 0xFF +#define SCU_RAM_ORX_AGN_HEADR_STP__PRE 0x0 + +#define SCU_RAM_ORX_AGN_KI__A 0x831F0F +#define SCU_RAM_ORX_AGN_KI__W 8 +#define SCU_RAM_ORX_AGN_KI__M 0xFF +#define SCU_RAM_ORX_AGN_KI__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_TH__A 0x831F10 +#define SCU_RAM_ORX_AGN_LOCK_TH__W 16 +#define SCU_RAM_ORX_AGN_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_WD__A 0x831F11 +#define SCU_RAM_ORX_AGN_LOCK_WD__W 16 +#define SCU_RAM_ORX_AGN_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__A 0x831F12 +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__A 0x831F13 +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_TOTH__A 0x831F14 +#define SCU_RAM_ORX_AGN_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_AGN_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_AGN_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_AGN_LOCK_MASK__A 0x831F15 +#define SCU_RAM_ORX_AGN_LOCK_MASK__W 8 +#define SCU_RAM_ORX_AGN_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_AGN_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_DGN__A 0x831F16 +#define SCU_RAM_ORX_DGN__W 16 +#define SCU_RAM_ORX_DGN__M 0xFFFF +#define SCU_RAM_ORX_DGN__PRE 0x0 + +#define SCU_RAM_ORX_DGN_MIN__A 0x831F17 +#define SCU_RAM_ORX_DGN_MIN__W 16 +#define SCU_RAM_ORX_DGN_MIN__M 0xFFFF +#define SCU_RAM_ORX_DGN_MIN__PRE 0x0 + +#define SCU_RAM_ORX_DGN_MAX__A 0x831F18 +#define SCU_RAM_ORX_DGN_MAX__W 16 +#define SCU_RAM_ORX_DGN_MAX__M 0xFFFF +#define SCU_RAM_ORX_DGN_MAX__PRE 0x0 + +#define SCU_RAM_ORX_DGN_AMP__A 0x831F19 +#define SCU_RAM_ORX_DGN_AMP__W 16 +#define SCU_RAM_ORX_DGN_AMP__M 0xFFFF +#define SCU_RAM_ORX_DGN_AMP__PRE 0x0 + +#define SCU_RAM_ORX_DGN_AMPTARGET__A 0x831F1A +#define SCU_RAM_ORX_DGN_AMPTARGET__W 16 +#define SCU_RAM_ORX_DGN_AMPTARGET__M 0xFFFF +#define SCU_RAM_ORX_DGN_AMPTARGET__PRE 0x0 + +#define SCU_RAM_ORX_DGN_KI__A 0x831F1B +#define SCU_RAM_ORX_DGN_KI__W 8 +#define SCU_RAM_ORX_DGN_KI__M 0xFF +#define SCU_RAM_ORX_DGN_KI__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_TH__A 0x831F1C +#define SCU_RAM_ORX_DGN_LOCK_TH__W 16 +#define SCU_RAM_ORX_DGN_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_WD__A 0x831F1D +#define SCU_RAM_ORX_DGN_LOCK_WD__W 16 +#define SCU_RAM_ORX_DGN_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__A 0x831F1E +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__A 0x831F1F +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_TOTH__A 0x831F20 +#define SCU_RAM_ORX_DGN_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_DGN_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_DGN_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_DGN_LOCK_MASK__A 0x831F21 +#define SCU_RAM_ORX_DGN_LOCK_MASK__W 8 +#define SCU_RAM_ORX_DGN_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_DGN_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_FREQ_GAIN_CORR__A 0x831F22 +#define SCU_RAM_ORX_FREQ_GAIN_CORR__W 8 +#define SCU_RAM_ORX_FREQ_GAIN_CORR__M 0xFF +#define SCU_RAM_ORX_FREQ_GAIN_CORR__PRE 0x0 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_1544KBPS 0x60 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS 0x80 +#define SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS 0xC0 + +#define SCU_RAM_ORX_FRQ_OFFSET__A 0x831F23 +#define SCU_RAM_ORX_FRQ_OFFSET__W 16 +#define SCU_RAM_ORX_FRQ_OFFSET__M 0xFFFF +#define SCU_RAM_ORX_FRQ_OFFSET__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__A 0x831F24 +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__W 15 +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__M 0x7FFF +#define SCU_RAM_ORX_FRQ_OFFSET_MAX__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_KI__A 0x831F25 +#define SCU_RAM_ORX_FRQ_KI__W 8 +#define SCU_RAM_ORX_FRQ_KI__M 0xFF +#define SCU_RAM_ORX_FRQ_KI__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_DIFF__A 0x831F26 +#define SCU_RAM_ORX_FRQ_DIFF__W 16 +#define SCU_RAM_ORX_FRQ_DIFF__M 0xFFFF +#define SCU_RAM_ORX_FRQ_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_TH__A 0x831F27 +#define SCU_RAM_ORX_FRQ_LOCK_TH__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_WD__A 0x831F28 +#define SCU_RAM_ORX_FRQ_LOCK_WD__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__A 0x831F29 +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__A 0x831F2A +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__A 0x831F2B +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_FRQ_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_FRQ_LOCK_MASK__A 0x831F2C +#define SCU_RAM_ORX_FRQ_LOCK_MASK__W 8 +#define SCU_RAM_ORX_FRQ_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_FRQ_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_PHA_DIFF__A 0x831F2D +#define SCU_RAM_ORX_PHA_DIFF__W 16 +#define SCU_RAM_ORX_PHA_DIFF__M 0xFFFF +#define SCU_RAM_ORX_PHA_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_TH__A 0x831F2E +#define SCU_RAM_ORX_PHA_LOCK_TH__W 16 +#define SCU_RAM_ORX_PHA_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_WD__A 0x831F2F +#define SCU_RAM_ORX_PHA_LOCK_WD__W 16 +#define SCU_RAM_ORX_PHA_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__A 0x831F30 +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__A 0x831F31 +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_TOTH__A 0x831F32 +#define SCU_RAM_ORX_PHA_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_PHA_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_PHA_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_PHA_LOCK_MASK__A 0x831F33 +#define SCU_RAM_ORX_PHA_LOCK_MASK__W 8 +#define SCU_RAM_ORX_PHA_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_PHA_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_TIM_OFFSET__A 0x831F34 +#define SCU_RAM_ORX_TIM_OFFSET__W 16 +#define SCU_RAM_ORX_TIM_OFFSET__M 0xFFFF +#define SCU_RAM_ORX_TIM_OFFSET__PRE 0x0 + +#define SCU_RAM_ORX_TIM_DIFF__A 0x831F35 +#define SCU_RAM_ORX_TIM_DIFF__W 16 +#define SCU_RAM_ORX_TIM_DIFF__M 0xFFFF +#define SCU_RAM_ORX_TIM_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_TH__A 0x831F36 +#define SCU_RAM_ORX_TIM_LOCK_TH__W 16 +#define SCU_RAM_ORX_TIM_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_WD__A 0x831F37 +#define SCU_RAM_ORX_TIM_LOCK_WD__W 16 +#define SCU_RAM_ORX_TIM_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__A 0x831F38 +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__A 0x831F39 +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_TOTH__A 0x831F3A +#define SCU_RAM_ORX_TIM_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_TIM_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_TIM_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_TIM_LOCK_MASK__A 0x831F3B +#define SCU_RAM_ORX_TIM_LOCK_MASK__W 8 +#define SCU_RAM_ORX_TIM_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_TIM_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_EQU_DIFF__A 0x831F3C +#define SCU_RAM_ORX_EQU_DIFF__W 16 +#define SCU_RAM_ORX_EQU_DIFF__M 0xFFFF +#define SCU_RAM_ORX_EQU_DIFF__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_TH__A 0x831F3D +#define SCU_RAM_ORX_EQU_LOCK_TH__W 16 +#define SCU_RAM_ORX_EQU_LOCK_TH__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_TH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_WD__A 0x831F3E +#define SCU_RAM_ORX_EQU_LOCK_WD__W 16 +#define SCU_RAM_ORX_EQU_LOCK_WD__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_WD__PRE 0x0 + +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__A 0x831F3F +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__W 16 +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_ONLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__A 0x831F40 +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__W 16 +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_UNLOCK_TTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_TOTH__A 0x831F41 +#define SCU_RAM_ORX_EQU_LOCK_TOTH__W 16 +#define SCU_RAM_ORX_EQU_LOCK_TOTH__M 0xFFFF +#define SCU_RAM_ORX_EQU_LOCK_TOTH__PRE 0x0 + +#define SCU_RAM_ORX_EQU_LOCK_MASK__A 0x831F42 +#define SCU_RAM_ORX_EQU_LOCK_MASK__W 8 +#define SCU_RAM_ORX_EQU_LOCK_MASK__M 0xFF +#define SCU_RAM_ORX_EQU_LOCK_MASK__PRE 0x0 + +#define SCU_RAM_ORX_FLT_FRQ__A 0x831F43 +#define SCU_RAM_ORX_FLT_FRQ__W 16 +#define SCU_RAM_ORX_FLT_FRQ__M 0xFFFF +#define SCU_RAM_ORX_FLT_FRQ__PRE 0x0 +#define SCU_RAM_ORX_RST_CPH__A 0x831F44 +#define SCU_RAM_ORX_RST_CPH__W 4 +#define SCU_RAM_ORX_RST_CPH__M 0xF +#define SCU_RAM_ORX_RST_CPH__PRE 0x0 + +#define SCU_RAM_ORX_RST_CPH_RST_CPH__B 0 +#define SCU_RAM_ORX_RST_CPH_RST_CPH__W 4 +#define SCU_RAM_ORX_RST_CPH_RST_CPH__M 0xF +#define SCU_RAM_ORX_RST_CPH_RST_CPH__PRE 0x0 + +#define SCU_RAM_ORX_RST_CTI__A 0x831F45 +#define SCU_RAM_ORX_RST_CTI__W 4 +#define SCU_RAM_ORX_RST_CTI__M 0xF +#define SCU_RAM_ORX_RST_CTI__PRE 0x0 + +#define SCU_RAM_ORX_RST_CTI_RST_CTI__B 0 +#define SCU_RAM_ORX_RST_CTI_RST_CTI__W 4 +#define SCU_RAM_ORX_RST_CTI_RST_CTI__M 0xF +#define SCU_RAM_ORX_RST_CTI_RST_CTI__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRN__A 0x831F46 +#define SCU_RAM_ORX_RST_KRN__W 4 +#define SCU_RAM_ORX_RST_KRN__M 0xF +#define SCU_RAM_ORX_RST_KRN__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRN_RST_KRN__B 0 +#define SCU_RAM_ORX_RST_KRN_RST_KRN__W 4 +#define SCU_RAM_ORX_RST_KRN_RST_KRN__M 0xF +#define SCU_RAM_ORX_RST_KRN_RST_KRN__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRP__A 0x831F47 +#define SCU_RAM_ORX_RST_KRP__W 4 +#define SCU_RAM_ORX_RST_KRP__M 0xF +#define SCU_RAM_ORX_RST_KRP__PRE 0x0 + +#define SCU_RAM_ORX_RST_KRP_RST_KRP__B 0 +#define SCU_RAM_ORX_RST_KRP_RST_KRP__W 4 +#define SCU_RAM_ORX_RST_KRP_RST_KRP__M 0xF +#define SCU_RAM_ORX_RST_KRP_RST_KRP__PRE 0x0 + +#define SCU_RAM_ATV_STANDARD__A 0x831F48 +#define SCU_RAM_ATV_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD__PRE 0x0 + +#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 +#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x0 +#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 +#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 +#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 +#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 +#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 +#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA +#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 + +#define SCU_RAM_ATV_DETECT__A 0x831F49 +#define SCU_RAM_ATV_DETECT__W 1 +#define SCU_RAM_ATV_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_DETECT__B 0 +#define SCU_RAM_ATV_DETECT_DETECT__W 1 +#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_false 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_true 0x1 + +#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A +#define SCU_RAM_ATV_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x0 + +#define SCU_RAM_ATV_LOCK__A 0x831F4B +#define SCU_RAM_ATV_LOCK__W 2 +#define SCU_RAM_ATV_LOCK__M 0x3 +#define SCU_RAM_ATV_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 + +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 + +#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C +#define SCU_RAM_ATV_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D +#define SCU_RAM_ATV_AGC_MODE__W 8 +#define SCU_RAM_ATV_AGC_MODE__M 0xFF +#define SCU_RAM_ATV_AGC_MODE__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 + +#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 + +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 + +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 + +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 + +#define SCU_RAM_ATV_RSV_01__A 0x831F4E +#define SCU_RAM_ATV_RSV_01__W 16 +#define SCU_RAM_ATV_RSV_01__M 0xFFFF +#define SCU_RAM_ATV_RSV_01__PRE 0x0 + +#define SCU_RAM_ATV_RSV_02__A 0x831F4F +#define SCU_RAM_ATV_RSV_02__W 16 +#define SCU_RAM_ATV_RSV_02__M 0xFFFF +#define SCU_RAM_ATV_RSV_02__PRE 0x0 + +#define SCU_RAM_ATV_RSV_03__A 0x831F50 +#define SCU_RAM_ATV_RSV_03__W 16 +#define SCU_RAM_ATV_RSV_03__M 0xFFFF +#define SCU_RAM_ATV_RSV_03__PRE 0x0 + +#define SCU_RAM_ATV_RSV_04__A 0x831F51 +#define SCU_RAM_ATV_RSV_04__W 16 +#define SCU_RAM_ATV_RSV_04__M 0xFFFF +#define SCU_RAM_ATV_RSV_04__PRE 0x0 +#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 +#define SCU_RAM_ATV_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0x0 + +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 +#define SCU_RAM_ATV_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A + +#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 +#define SCU_RAM_ATV_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 +#define SCU_RAM_ATV_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_RSV_05__A 0x831F56 +#define SCU_RAM_ATV_RSV_05__W 16 +#define SCU_RAM_ATV_RSV_05__M 0xFFFF +#define SCU_RAM_ATV_RSV_05__PRE 0x0 + +#define SCU_RAM_ATV_RSV_06__A 0x831F57 +#define SCU_RAM_ATV_RSV_06__W 16 +#define SCU_RAM_ATV_RSV_06__M 0xFFFF +#define SCU_RAM_ATV_RSV_06__PRE 0x0 + +#define SCU_RAM_ATV_RSV_07__A 0x831F58 +#define SCU_RAM_ATV_RSV_07__W 16 +#define SCU_RAM_ATV_RSV_07__M 0xFFFF +#define SCU_RAM_ATV_RSV_07__PRE 0x0 + +#define SCU_RAM_ATV_RSV_08__A 0x831F59 +#define SCU_RAM_ATV_RSV_08__W 16 +#define SCU_RAM_ATV_RSV_08__M 0xFFFF +#define SCU_RAM_ATV_RSV_08__PRE 0x0 + +#define SCU_RAM_ATV_RSV_09__A 0x831F5A +#define SCU_RAM_ATV_RSV_09__W 16 +#define SCU_RAM_ATV_RSV_09__M 0xFFFF +#define SCU_RAM_ATV_RSV_09__PRE 0x0 + +#define SCU_RAM_ATV_RSV_10__A 0x831F5B +#define SCU_RAM_ATV_RSV_10__W 16 +#define SCU_RAM_ATV_RSV_10__M 0xFFFF +#define SCU_RAM_ATV_RSV_10__PRE 0x0 + +#define SCU_RAM_ATV_RSV_11__A 0x831F5C +#define SCU_RAM_ATV_RSV_11__W 16 +#define SCU_RAM_ATV_RSV_11__M 0xFFFF +#define SCU_RAM_ATV_RSV_11__PRE 0x0 + +#define SCU_RAM_ATV_RSV_12__A 0x831F5D +#define SCU_RAM_ATV_RSV_12__W 16 +#define SCU_RAM_ATV_RSV_12__M 0xFFFF +#define SCU_RAM_ATV_RSV_12__PRE 0x0 +#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E +#define SCU_RAM_ATV_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F +#define SCU_RAM_ATV_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 + +#define SCU_RAM_ATV_RSV_13__A 0x831F60 +#define SCU_RAM_ATV_RSV_13__W 16 +#define SCU_RAM_ATV_RSV_13__M 0xFFFF +#define SCU_RAM_ATV_RSV_13__PRE 0x0 + +#define SCU_RAM_ATV_RSV_14__A 0x831F61 +#define SCU_RAM_ATV_RSV_14__W 16 +#define SCU_RAM_ATV_RSV_14__M 0xFFFF +#define SCU_RAM_ATV_RSV_14__PRE 0x0 + +#define SCU_RAM_ATV_RSV_15__A 0x831F62 +#define SCU_RAM_ATV_RSV_15__W 16 +#define SCU_RAM_ATV_RSV_15__M 0xFFFF +#define SCU_RAM_ATV_RSV_15__PRE 0x0 + +#define SCU_RAM_ATV_RSV_16__A 0x831F63 +#define SCU_RAM_ATV_RSV_16__W 16 +#define SCU_RAM_ATV_RSV_16__M 0xFFFF +#define SCU_RAM_ATV_RSV_16__PRE 0x0 +#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 +#define SCU_RAM_ATV_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x0 + +#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 +#define SCU_RAM_ATV_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN__PRE 0x0 + +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x0 + +#define SCU_RAM_ATV_RSV_17__A 0x831F66 +#define SCU_RAM_ATV_RSV_17__W 16 +#define SCU_RAM_ATV_RSV_17__M 0xFFFF +#define SCU_RAM_ATV_RSV_17__PRE 0x0 + +#define SCU_RAM_ATV_RSV_18__A 0x831F67 +#define SCU_RAM_ATV_RSV_18__W 16 +#define SCU_RAM_ATV_RSV_18__M 0xFFFF +#define SCU_RAM_ATV_RSV_18__PRE 0x0 + +#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 +#define SCU_RAM_ATV_RATE_OFS__W 12 +#define SCU_RAM_ATV_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_LO_INCR__A 0x831F69 +#define SCU_RAM_ATV_LO_INCR__W 12 +#define SCU_RAM_ATV_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A +#define SCU_RAM_ATV_IIR_CRIT__W 12 +#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF +#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 + +#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B +#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 +#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C +#define SCU_RAM_ATV_DEF_LO_INCR__W 12 +#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D +#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 + +#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E +#define SCU_RAM_ATV_MOD_CONTROL__W 12 +#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F +#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x0 + +#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 +#define SCU_RAM_ATV_BPC_KI_MAX__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x0 + +#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 +#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x0 +#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 +#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x0 + +#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 +#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x0 + +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 + +#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 +#define SCU_RAM_QAM_PARAM_ANNEX__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 +#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 +#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF +#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A +#define SCU_RAM_QAM_WR_RSV_0__W 16 +#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D +#define SCU_RAM_QAM_WR_RSV_5__W 16 +#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E +#define SCU_RAM_QAM_WR_RSV_6__W 16 +#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F +#define SCU_RAM_QAM_WR_RSV_7__W 16 +#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 +#define SCU_RAM_QAM_WR_RSV_8__W 16 +#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 +#define SCU_RAM_QAM_WR_RSV_9__W 16 +#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 +#define SCU_RAM_QAM_WR_RSV_10__W 16 +#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 +#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B +#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D +#define SCU_RAM_QAM_FSM_ATH__W 16 +#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 +#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 +#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__W 16 +#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D + +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__W 16 +#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 + +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__W 16 +#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 + +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__W 16 +#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 + +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__W 16 +#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C + +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__W 16 +#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 + +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 + +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x0 + +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 + +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__W 16 +#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 +#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__W 16 +#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__W 16 +#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__W 16 +#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__W 16 +#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__W 16 +#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__W 16 +#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__W 16 +#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__W 16 +#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__W 16 +#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x0 + +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0x0 + +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE + +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 + +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF + +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 + +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D + +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 + +#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 +#define SCU_RAM_QAM_CTL_ENA__W 16 +#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF +#define SCU_RAM_QAM_CTL_ENA__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 +#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 +#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 +#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 +#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 +#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 +#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 +#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 +#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 +#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_LC__B 4 +#define SCU_RAM_QAM_CTL_ENA_LC__W 1 +#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 +#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 +#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 +#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 +#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 +#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 +#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 +#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 +#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 +#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 +#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x0 + +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 +#define SCU_RAM_QAM_WR_RSV_1__W 16 +#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 +#define SCU_RAM_QAM_WR_RSV_2__W 16 +#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 +#define SCU_RAM_QAM_WR_RSV_3__W 16 +#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE + +#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 +#define SCU_RAM_QAM_RD_RSV_4__W 16 +#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED__A 0x831FBA +#define SCU_RAM_QAM_LOCKED__W 16 +#define SCU_RAM_QAM_LOCKED__M 0xFFFF +#define SCU_RAM_QAM_LOCKED__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF +#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 + +#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 +#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 + +#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB +#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC +#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD +#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE +#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF +#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 +#define SCU_RAM_QAM_TASKLETS_RUN__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 +#define SCU_RAM_QAM_RD_RSV_5__W 16 +#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 +#define SCU_RAM_QAM_RD_RSV_6__W 16 +#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 +#define SCU_RAM_QAM_RD_RSV_7__W 16 +#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 +#define SCU_RAM_QAM_RD_RSV_8__W 16 +#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 +#define SCU_RAM_QAM_RD_RSV_9__W 16 +#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 +#define SCU_RAM_QAM_RD_RSV_10__W 16 +#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA +#define SCU_RAM_QAM_FSM_STATE__W 4 +#define SCU_RAM_QAM_FSM_STATE__M 0xF +#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB +#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD +#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF +#define SCU_RAM_QAM_ERR_STATE__W 4 +#define SCU_RAM_QAM_ERR_STATE__M 0xF +#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 +#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 +#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF +#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 +#define SCU_RAM_QAM_EQ_LOCK__W 1 +#define SCU_RAM_QAM_EQ_LOCK__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 +#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 +#define SCU_RAM_QAM_EQ_STATE__W 16 +#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 +#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 +#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 +#define SCU_RAM_QAM_RD_RSV_0__W 16 +#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 +#define SCU_RAM_QAM_RD_RSV_1__W 16 +#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 +#define SCU_RAM_QAM_RD_RSV_2__W 16 +#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 +#define SCU_RAM_QAM_RD_RSV_3__W 16 +#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_VSB_CTL_MODE__A 0x831FD7 +#define SCU_RAM_VSB_CTL_MODE__W 2 +#define SCU_RAM_VSB_CTL_MODE__M 0x3 +#define SCU_RAM_VSB_CTL_MODE__PRE 0x0 + +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__B 0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__W 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__M 0x1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__PRE 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_OFF 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_ON 0x1 + +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__B 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__W 1 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__M 0x2 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__PRE 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF 0x0 +#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON 0x2 + +#define SCU_RAM_VSB_NOTCH_THRESHOLD__A 0x831FD8 +#define SCU_RAM_VSB_NOTCH_THRESHOLD__W 16 +#define SCU_RAM_VSB_NOTCH_THRESHOLD__M 0xFFFF +#define SCU_RAM_VSB_NOTCH_THRESHOLD__PRE 0x0 + +#define SCU_RAM_VSB_RSV_0__A 0x831FD9 +#define SCU_RAM_VSB_RSV_0__W 16 +#define SCU_RAM_VSB_RSV_0__M 0xFFFF +#define SCU_RAM_VSB_RSV_0__PRE 0x0 + +#define SCU_RAM_VSB_RSV_1__A 0x831FDA +#define SCU_RAM_VSB_RSV_1__W 16 +#define SCU_RAM_VSB_RSV_1__M 0xFFFF +#define SCU_RAM_VSB_RSV_1__PRE 0x0 + +#define SCU_RAM_VSB_RSV_2__A 0x831FDB +#define SCU_RAM_VSB_RSV_2__W 16 +#define SCU_RAM_VSB_RSV_2__M 0xFFFF +#define SCU_RAM_VSB_RSV_2__PRE 0x0 + +#define SCU_RAM_VSB_RSV_3__A 0x831FDC +#define SCU_RAM_VSB_RSV_3__W 16 +#define SCU_RAM_VSB_RSV_3__M 0xFFFF +#define SCU_RAM_VSB_RSV_3__PRE 0x0 + +#define SCU_RAM_VSB_RSV_4__A 0x831FDD +#define SCU_RAM_VSB_RSV_4__W 16 +#define SCU_RAM_VSB_RSV_4__M 0xFFFF +#define SCU_RAM_VSB_RSV_4__PRE 0x0 + +#define SCU_RAM_VSB_RSV_5__A 0x831FDE +#define SCU_RAM_VSB_RSV_5__W 16 +#define SCU_RAM_VSB_RSV_5__M 0xFFFF +#define SCU_RAM_VSB_RSV_5__PRE 0x0 + +#define SCU_RAM_VSB_RSV_6__A 0x831FDF +#define SCU_RAM_VSB_RSV_6__W 16 +#define SCU_RAM_VSB_RSV_6__M 0xFFFF +#define SCU_RAM_VSB_RSV_6__PRE 0x0 + +#define SCU_RAM_VSB_RSV_7__A 0x831FE0 +#define SCU_RAM_VSB_RSV_7__W 16 +#define SCU_RAM_VSB_RSV_7__M 0xFFFF +#define SCU_RAM_VSB_RSV_7__PRE 0x0 + +#define SCU_RAM_VSB_RSV_8__A 0x831FE1 +#define SCU_RAM_VSB_RSV_8__W 16 +#define SCU_RAM_VSB_RSV_8__M 0xFFFF +#define SCU_RAM_VSB_RSV_8__PRE 0x0 + +#define SCU_RAM_VSB_RSV_9__A 0x831FE2 +#define SCU_RAM_VSB_RSV_9__W 16 +#define SCU_RAM_VSB_RSV_9__M 0xFFFF +#define SCU_RAM_VSB_RSV_9__PRE 0x0 + +#define SCU_RAM_VSB_RSV_10__A 0x831FE3 +#define SCU_RAM_VSB_RSV_10__W 16 +#define SCU_RAM_VSB_RSV_10__M 0xFFFF +#define SCU_RAM_VSB_RSV_10__PRE 0x0 + +#define SCU_RAM_VSB_RSV_11__A 0x831FE4 +#define SCU_RAM_VSB_RSV_11__W 16 +#define SCU_RAM_VSB_RSV_11__M 0xFFFF +#define SCU_RAM_VSB_RSV_11__PRE 0x0 + +#define SCU_RAM_VSB_RSV_12__A 0x831FE5 +#define SCU_RAM_VSB_RSV_12__W 16 +#define SCU_RAM_VSB_RSV_12__M 0xFFFF +#define SCU_RAM_VSB_RSV_12__PRE 0x0 + +#define SCU_RAM_VSB_RSV_13__A 0x831FE6 +#define SCU_RAM_VSB_RSV_13__W 16 +#define SCU_RAM_VSB_RSV_13__M 0xFFFF +#define SCU_RAM_VSB_RSV_13__PRE 0x0 + +#define SCU_RAM_VSB_AGC_POW_TGT__A 0x831FE7 +#define SCU_RAM_VSB_AGC_POW_TGT__W 15 +#define SCU_RAM_VSB_AGC_POW_TGT__M 0x7FFF +#define SCU_RAM_VSB_AGC_POW_TGT__PRE 0x0 + +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__A 0x831FE8 +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__W 8 +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__M 0xFF +#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__PRE 0x0 + +#define SCU_RAM_VSB_FIELD_NUMBER__A 0x831FE9 +#define SCU_RAM_VSB_FIELD_NUMBER__W 9 +#define SCU_RAM_VSB_FIELD_NUMBER__M 0x1FF +#define SCU_RAM_VSB_FIELD_NUMBER__PRE 0x0 + +#define SCU_RAM_VSB_SEGMENT_NUMBER__A 0x831FEA +#define SCU_RAM_VSB_SEGMENT_NUMBER__W 10 +#define SCU_RAM_VSB_SEGMENT_NUMBER__M 0x3FF +#define SCU_RAM_VSB_SEGMENT_NUMBER__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +#define SCU_RAM_DRIVER_VER_HI__W 16 +#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF +#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +#define SCU_RAM_DRIVER_VER_LO__W 16 +#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF +#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 + +#define SCU_RAM_PARAM_15__A 0x831FED +#define SCU_RAM_PARAM_15__W 16 +#define SCU_RAM_PARAM_15__M 0xFFFF +#define SCU_RAM_PARAM_15__PRE 0x0 + +#define SCU_RAM_PARAM_14__A 0x831FEE +#define SCU_RAM_PARAM_14__W 16 +#define SCU_RAM_PARAM_14__M 0xFFFF +#define SCU_RAM_PARAM_14__PRE 0x0 + +#define SCU_RAM_PARAM_13__A 0x831FEF +#define SCU_RAM_PARAM_13__W 16 +#define SCU_RAM_PARAM_13__M 0xFFFF +#define SCU_RAM_PARAM_13__PRE 0x0 + +#define SCU_RAM_PARAM_12__A 0x831FF0 +#define SCU_RAM_PARAM_12__W 16 +#define SCU_RAM_PARAM_12__M 0xFFFF +#define SCU_RAM_PARAM_12__PRE 0x0 + +#define SCU_RAM_PARAM_11__A 0x831FF1 +#define SCU_RAM_PARAM_11__W 16 +#define SCU_RAM_PARAM_11__M 0xFFFF +#define SCU_RAM_PARAM_11__PRE 0x0 + +#define SCU_RAM_PARAM_10__A 0x831FF2 +#define SCU_RAM_PARAM_10__W 16 +#define SCU_RAM_PARAM_10__M 0xFFFF +#define SCU_RAM_PARAM_10__PRE 0x0 + +#define SCU_RAM_PARAM_9__A 0x831FF3 +#define SCU_RAM_PARAM_9__W 16 +#define SCU_RAM_PARAM_9__M 0xFFFF +#define SCU_RAM_PARAM_9__PRE 0x0 + +#define SCU_RAM_PARAM_8__A 0x831FF4 +#define SCU_RAM_PARAM_8__W 16 +#define SCU_RAM_PARAM_8__M 0xFFFF +#define SCU_RAM_PARAM_8__PRE 0x0 + +#define SCU_RAM_PARAM_7__A 0x831FF5 +#define SCU_RAM_PARAM_7__W 16 +#define SCU_RAM_PARAM_7__M 0xFFFF +#define SCU_RAM_PARAM_7__PRE 0x0 + +#define SCU_RAM_PARAM_6__A 0x831FF6 +#define SCU_RAM_PARAM_6__W 16 +#define SCU_RAM_PARAM_6__M 0xFFFF +#define SCU_RAM_PARAM_6__PRE 0x0 + +#define SCU_RAM_PARAM_5__A 0x831FF7 +#define SCU_RAM_PARAM_5__W 16 +#define SCU_RAM_PARAM_5__M 0xFFFF +#define SCU_RAM_PARAM_5__PRE 0x0 + +#define SCU_RAM_PARAM_4__A 0x831FF8 +#define SCU_RAM_PARAM_4__W 16 +#define SCU_RAM_PARAM_4__M 0xFFFF +#define SCU_RAM_PARAM_4__PRE 0x0 + +#define SCU_RAM_PARAM_3__A 0x831FF9 +#define SCU_RAM_PARAM_3__W 16 +#define SCU_RAM_PARAM_3__M 0xFFFF +#define SCU_RAM_PARAM_3__PRE 0x0 + +#define SCU_RAM_PARAM_2__A 0x831FFA +#define SCU_RAM_PARAM_2__W 16 +#define SCU_RAM_PARAM_2__M 0xFFFF +#define SCU_RAM_PARAM_2__PRE 0x0 + +#define SCU_RAM_PARAM_1__A 0x831FFB +#define SCU_RAM_PARAM_1__W 16 +#define SCU_RAM_PARAM_1__M 0xFFFF +#define SCU_RAM_PARAM_1__PRE 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 + +#define SCU_RAM_PARAM_0__A 0x831FFC +#define SCU_RAM_PARAM_0__W 16 +#define SCU_RAM_PARAM_0__M 0xFFFF +#define SCU_RAM_PARAM_0__PRE 0x0 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC + +#define SCU_RAM_COMMAND__A 0x831FFD +#define SCU_RAM_COMMAND__W 16 +#define SCU_RAM_COMMAND__M 0xFFFF +#define SCU_RAM_COMMAND__PRE 0x0 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 +#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 +#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 +#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 +#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 +#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 +#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 +#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD +#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 + +#define SCU_RAM_COMMAND_STANDARD__B 8 +#define SCU_RAM_COMMAND_STANDARD__W 8 +#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 +#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 +#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 +#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 + +#define SCU_RAM_VERSION_HI__A 0x831FFE +#define SCU_RAM_VERSION_HI__W 16 +#define SCU_RAM_VERSION_HI__M 0xFFFF +#define SCU_RAM_VERSION_HI__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_LO__A 0x831FFF +#define SCU_RAM_VERSION_LO__W 16 +#define SCU_RAM_VERSION_LO__M 0xFFFF +#define SCU_RAM_VERSION_LO__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 + +#define SIO_COMM_EXEC__A 0x400000 +#define SIO_COMM_EXEC__W 2 +#define SIO_COMM_EXEC__M 0x3 +#define SIO_COMM_EXEC__PRE 0x0 +#define SIO_COMM_EXEC_STOP 0x0 +#define SIO_COMM_EXEC_ACTIVE 0x1 +#define SIO_COMM_EXEC_HOLD 0x2 + +#define SIO_COMM_STATE__A 0x400001 +#define SIO_COMM_STATE__W 16 +#define SIO_COMM_STATE__M 0xFFFF +#define SIO_COMM_STATE__PRE 0x0 +#define SIO_COMM_MB__A 0x400002 +#define SIO_COMM_MB__W 16 +#define SIO_COMM_MB__M 0xFFFF +#define SIO_COMM_MB__PRE 0x0 +#define SIO_COMM_INT_REQ__A 0x400003 +#define SIO_COMM_INT_REQ__W 16 +#define SIO_COMM_INT_REQ__M 0xFFFF +#define SIO_COMM_INT_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_HI_REQ__B 0 +#define SIO_COMM_INT_REQ_HI_REQ__W 1 +#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 +#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_SA_REQ__B 1 +#define SIO_COMM_INT_REQ_SA_REQ__W 1 +#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 +#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 + +#define SIO_COMM_INT_STA__A 0x400005 +#define SIO_COMM_INT_STA__W 16 +#define SIO_COMM_INT_STA__M 0xFFFF +#define SIO_COMM_INT_STA__PRE 0x0 +#define SIO_COMM_INT_MSK__A 0x400006 +#define SIO_COMM_INT_MSK__W 16 +#define SIO_COMM_INT_MSK__M 0xFFFF +#define SIO_COMM_INT_MSK__PRE 0x0 +#define SIO_COMM_INT_STM__A 0x400007 +#define SIO_COMM_INT_STM__W 16 +#define SIO_COMM_INT_STM__M 0xFFFF +#define SIO_COMM_INT_STM__PRE 0x0 + +#define SIO_TOP_COMM_EXEC__A 0x410000 +#define SIO_TOP_COMM_EXEC__W 2 +#define SIO_TOP_COMM_EXEC__M 0x3 +#define SIO_TOP_COMM_EXEC__PRE 0x0 +#define SIO_TOP_COMM_EXEC_STOP 0x0 +#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 +#define SIO_TOP_COMM_EXEC_HOLD 0x2 + +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__W 16 +#define SIO_TOP_COMM_KEY__M 0xFFFF +#define SIO_TOP_COMM_KEY__PRE 0x0 +#define SIO_TOP_COMM_KEY_KEY 0xFABA + +#define SIO_TOP_JTAGID_LO__A 0x410012 +#define SIO_TOP_JTAGID_LO__W 16 +#define SIO_TOP_JTAGID_LO__M 0xFFFF +#define SIO_TOP_JTAGID_LO__PRE 0x0 + +#define SIO_TOP_JTAGID_HI__A 0x410013 +#define SIO_TOP_JTAGID_HI__W 16 +#define SIO_TOP_JTAGID_HI__M 0xFFFF +#define SIO_TOP_JTAGID_HI__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 +#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 +#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 +#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 +#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 +#define SIO_HI_RA_RAM_S0_STATE__W 1 +#define SIO_HI_RA_RAM_S0_STATE__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 +#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 +#define SIO_HI_RA_RAM_S0_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 +#define SIO_HI_RA_RAM_S0_CRC__W 16 +#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 +#define SIO_HI_RA_RAM_S0_BUFFER__W 16 +#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 +#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A +#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B +#define SIO_HI_RA_RAM_S0_TEMP0__W 16 +#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C +#define SIO_HI_RA_RAM_S0_TEMP1__W 16 +#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D +#define SIO_HI_RA_RAM_S0_OFFSET__W 16 +#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 +#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 +#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 +#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 +#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 +#define SIO_HI_RA_RAM_S1_STATE__W 1 +#define SIO_HI_RA_RAM_S1_STATE__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 +#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 +#define SIO_HI_RA_RAM_S1_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 +#define SIO_HI_RA_RAM_S1_CRC__W 16 +#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 +#define SIO_HI_RA_RAM_S1_BUFFER__W 16 +#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 +#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A +#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B +#define SIO_HI_RA_RAM_S1_TEMP0__W 16 +#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C +#define SIO_HI_RA_RAM_S1_TEMP1__W 16 +#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D +#define SIO_HI_RA_RAM_S1_OFFSET__W 16 +#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA__A 0x420030 +#define SIO_HI_RA_RAM_SEMA__W 1 +#define SIO_HI_RA_RAM_SEMA__M 0x1 +#define SIO_HI_RA_RAM_SEMA__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA_FREE 0x0 +#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 + +#define SIO_HI_RA_RAM_RES__A 0x420031 +#define SIO_HI_RA_RAM_RES__W 3 +#define SIO_HI_RA_RAM_RES__M 0x7 +#define SIO_HI_RA_RAM_RES__PRE 0x0 +#define SIO_HI_RA_RAM_RES_OK 0x0 +#define SIO_HI_RA_RAM_RES_ERROR 0x1 +#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 +#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 +#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 +#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 + +#define SIO_HI_RA_RAM_CMD__A 0x420032 +#define SIO_HI_RA_RAM_CMD__W 4 +#define SIO_HI_RA_RAM_CMD__M 0xF +#define SIO_HI_RA_RAM_CMD__PRE 0x0 +#define SIO_HI_RA_RAM_CMD_NULL 0x0 +#define SIO_HI_RA_RAM_CMD_UIO 0x1 +#define SIO_HI_RA_RAM_CMD_RESET 0x2 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 +#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 +#define SIO_HI_RA_RAM_CMD_EXEC 0x6 +#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 + +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 + +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 + +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 + +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 + +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 + +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 + +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 + +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF + +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 + +#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E +#define SIO_HI_RA_RAM_AB_TEMP__W 16 +#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF +#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 + +#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F +#define SIO_HI_RA_RAM_I2C_CTL__W 16 +#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF +#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 +#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 +#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 +#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 +#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 +#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 +#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 +#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 +#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 +#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 +#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A +#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B +#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C +#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D +#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E +#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F +#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 + +#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 +#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 +#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 +#define SIO_HI_IF_RAM_TRP_STK_0__W 12 +#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 +#define SIO_HI_IF_RAM_TRP_STK_1__W 12 +#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 +#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 +#define SIO_HI_IF_RAM_FUN_BASE__W 12 +#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF +#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 + +#define SIO_HI_IF_COMM_EXEC__A 0x440000 +#define SIO_HI_IF_COMM_EXEC__W 2 +#define SIO_HI_IF_COMM_EXEC__M 0x3 +#define SIO_HI_IF_COMM_EXEC__PRE 0x0 +#define SIO_HI_IF_COMM_EXEC_STOP 0x0 +#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 +#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 +#define SIO_HI_IF_COMM_EXEC_STEP 0x3 + +#define SIO_HI_IF_COMM_STATE__A 0x440001 +#define SIO_HI_IF_COMM_STATE__W 10 +#define SIO_HI_IF_COMM_STATE__M 0x3FF +#define SIO_HI_IF_COMM_STATE__PRE 0x0 +#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 +#define SIO_HI_IF_COMM_INT_REQ__W 1 +#define SIO_HI_IF_COMM_INT_REQ__M 0x1 +#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA__A 0x440005 +#define SIO_HI_IF_COMM_INT_STA__W 1 +#define SIO_HI_IF_COMM_INT_STA__M 0x1 +#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 +#define SIO_HI_IF_COMM_INT_MSK__W 1 +#define SIO_HI_IF_COMM_INT_MSK__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_STM__A 0x440007 +#define SIO_HI_IF_COMM_INT_STM__W 1 +#define SIO_HI_IF_COMM_INT_STM__M 0x1 +#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 + +#define SIO_HI_IF_STK_0__A 0x440010 +#define SIO_HI_IF_STK_0__W 10 +#define SIO_HI_IF_STK_0__M 0x3FF +#define SIO_HI_IF_STK_0__PRE 0x2 + +#define SIO_HI_IF_STK_0_ADDR__B 0 +#define SIO_HI_IF_STK_0_ADDR__W 10 +#define SIO_HI_IF_STK_0_ADDR__M 0x3FF +#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_1__A 0x440011 +#define SIO_HI_IF_STK_1__W 10 +#define SIO_HI_IF_STK_1__M 0x3FF +#define SIO_HI_IF_STK_1__PRE 0x2 +#define SIO_HI_IF_STK_1_ADDR__B 0 +#define SIO_HI_IF_STK_1_ADDR__W 10 +#define SIO_HI_IF_STK_1_ADDR__M 0x3FF +#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_2__A 0x440012 +#define SIO_HI_IF_STK_2__W 10 +#define SIO_HI_IF_STK_2__M 0x3FF +#define SIO_HI_IF_STK_2__PRE 0x2 +#define SIO_HI_IF_STK_2_ADDR__B 0 +#define SIO_HI_IF_STK_2_ADDR__W 10 +#define SIO_HI_IF_STK_2_ADDR__M 0x3FF +#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_3__A 0x440013 +#define SIO_HI_IF_STK_3__W 10 +#define SIO_HI_IF_STK_3__M 0x3FF +#define SIO_HI_IF_STK_3__PRE 0x2 + +#define SIO_HI_IF_STK_3_ADDR__B 0 +#define SIO_HI_IF_STK_3_ADDR__W 10 +#define SIO_HI_IF_STK_3_ADDR__M 0x3FF +#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 + +#define SIO_HI_IF_BPT_IDX__A 0x44001F +#define SIO_HI_IF_BPT_IDX__W 1 +#define SIO_HI_IF_BPT_IDX__M 0x1 +#define SIO_HI_IF_BPT_IDX__PRE 0x0 + +#define SIO_HI_IF_BPT_IDX_ADDR__B 0 +#define SIO_HI_IF_BPT_IDX_ADDR__W 1 +#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 +#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 + +#define SIO_HI_IF_BPT__A 0x440020 +#define SIO_HI_IF_BPT__W 10 +#define SIO_HI_IF_BPT__M 0x3FF +#define SIO_HI_IF_BPT__PRE 0x2 + +#define SIO_HI_IF_BPT_ADDR__B 0 +#define SIO_HI_IF_BPT_ADDR__W 10 +#define SIO_HI_IF_BPT_ADDR__M 0x3FF +#define SIO_HI_IF_BPT_ADDR__PRE 0x2 + +#define SIO_CC_COMM_EXEC__A 0x450000 +#define SIO_CC_COMM_EXEC__W 2 +#define SIO_CC_COMM_EXEC__M 0x3 +#define SIO_CC_COMM_EXEC__PRE 0x0 +#define SIO_CC_COMM_EXEC_STOP 0x0 +#define SIO_CC_COMM_EXEC_ACTIVE 0x1 +#define SIO_CC_COMM_EXEC_HOLD 0x2 + +#define SIO_CC_PLL_MODE__A 0x450010 +#define SIO_CC_PLL_MODE__W 6 +#define SIO_CC_PLL_MODE__M 0x3F +#define SIO_CC_PLL_MODE__PRE 0x0 + +#define SIO_CC_PLL_MODE_FREF_SEL__B 0 +#define SIO_CC_PLL_MODE_FREF_SEL__W 2 +#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 +#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 +#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 +#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 + +#define SIO_CC_PLL_MODE_LOCKSEL__B 2 +#define SIO_CC_PLL_MODE_LOCKSEL__W 2 +#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC +#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 + +#define SIO_CC_PLL_MODE_BYPASS__B 4 +#define SIO_CC_PLL_MODE_BYPASS__W 2 +#define SIO_CC_PLL_MODE_BYPASS__M 0x30 +#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 +#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 + +#define SIO_CC_PLL_TEST__A 0x450011 +#define SIO_CC_PLL_TEST__W 8 +#define SIO_CC_PLL_TEST__M 0xFF +#define SIO_CC_PLL_TEST__PRE 0x0 + +#define SIO_CC_PLL_LOCK__A 0x450012 +#define SIO_CC_PLL_LOCK__W 1 +#define SIO_CC_PLL_LOCK__M 0x1 +#define SIO_CC_PLL_LOCK__PRE 0x0 +#define SIO_CC_CLK_MODE__A 0x450014 +#define SIO_CC_CLK_MODE__W 5 +#define SIO_CC_CLK_MODE__M 0x1F +#define SIO_CC_CLK_MODE__PRE 0x0 + +#define SIO_CC_CLK_MODE_DELAY__B 0 +#define SIO_CC_CLK_MODE_DELAY__W 4 +#define SIO_CC_CLK_MODE_DELAY__M 0xF +#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 + +#define SIO_CC_CLK_MODE_INVERT__B 4 +#define SIO_CC_CLK_MODE_INVERT__W 1 +#define SIO_CC_CLK_MODE_INVERT__M 0x10 +#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 + +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__W 3 +#define SIO_CC_PWD_MODE__M 0x7 +#define SIO_CC_PWD_MODE__PRE 0x0 + +#define SIO_CC_PWD_MODE_LEVEL__B 0 +#define SIO_CC_PWD_MODE_LEVEL__W 2 +#define SIO_CC_PWD_MODE_LEVEL__M 0x3 +#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x1 +#define SIO_CC_PWD_MODE_LEVEL_PLL 0x2 +#define SIO_CC_PWD_MODE_LEVEL_OSC 0x3 + +#define SIO_CC_PWD_MODE_USE_LOCK__B 2 +#define SIO_CC_PWD_MODE_USE_LOCK__W 1 +#define SIO_CC_PWD_MODE_USE_LOCK__M 0x4 +#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 + +#define SIO_CC_SOFT_RST__A 0x450016 +#define SIO_CC_SOFT_RST__W 2 +#define SIO_CC_SOFT_RST__M 0x3 +#define SIO_CC_SOFT_RST__PRE 0x0 + +#define SIO_CC_SOFT_RST_SYS__B 0 +#define SIO_CC_SOFT_RST_SYS__W 1 +#define SIO_CC_SOFT_RST_SYS__M 0x1 +#define SIO_CC_SOFT_RST_SYS__PRE 0x0 + +#define SIO_CC_SOFT_RST_OSC__B 1 +#define SIO_CC_SOFT_RST_OSC__W 1 +#define SIO_CC_SOFT_RST_OSC__M 0x2 +#define SIO_CC_SOFT_RST_OSC__PRE 0x0 + +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__W 16 +#define SIO_CC_UPDATE__M 0xFFFF +#define SIO_CC_UPDATE__PRE 0x0 +#define SIO_CC_UPDATE_KEY 0xFABA + +#define SIO_SA_COMM_EXEC__A 0x460000 +#define SIO_SA_COMM_EXEC__W 2 +#define SIO_SA_COMM_EXEC__M 0x3 +#define SIO_SA_COMM_EXEC__PRE 0x0 +#define SIO_SA_COMM_EXEC_STOP 0x0 +#define SIO_SA_COMM_EXEC_ACTIVE 0x1 +#define SIO_SA_COMM_EXEC_HOLD 0x2 + +#define SIO_SA_COMM_INT_REQ__A 0x460003 +#define SIO_SA_COMM_INT_REQ__W 1 +#define SIO_SA_COMM_INT_REQ__M 0x1 +#define SIO_SA_COMM_INT_REQ__PRE 0x0 +#define SIO_SA_COMM_INT_STA__A 0x460005 +#define SIO_SA_COMM_INT_STA__W 4 +#define SIO_SA_COMM_INT_STA__M 0xF +#define SIO_SA_COMM_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK__A 0x460006 +#define SIO_SA_COMM_INT_MSK__W 4 +#define SIO_SA_COMM_INT_MSK__M 0xF +#define SIO_SA_COMM_INT_MSK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM__A 0x460007 +#define SIO_SA_COMM_INT_STM__W 4 +#define SIO_SA_COMM_INT_STM__M 0xF +#define SIO_SA_COMM_INT_STM__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_PRESCALER__A 0x460010 +#define SIO_SA_PRESCALER__W 13 +#define SIO_SA_PRESCALER__M 0x1FFF +#define SIO_SA_PRESCALER__PRE 0x18B7 +#define SIO_SA_TX_DATA0__A 0x460011 +#define SIO_SA_TX_DATA0__W 16 +#define SIO_SA_TX_DATA0__M 0xFFFF +#define SIO_SA_TX_DATA0__PRE 0x0 +#define SIO_SA_TX_DATA1__A 0x460012 +#define SIO_SA_TX_DATA1__W 16 +#define SIO_SA_TX_DATA1__M 0xFFFF +#define SIO_SA_TX_DATA1__PRE 0x0 +#define SIO_SA_TX_DATA2__A 0x460013 +#define SIO_SA_TX_DATA2__W 16 +#define SIO_SA_TX_DATA2__M 0xFFFF +#define SIO_SA_TX_DATA2__PRE 0x0 +#define SIO_SA_TX_DATA3__A 0x460014 +#define SIO_SA_TX_DATA3__W 16 +#define SIO_SA_TX_DATA3__M 0xFFFF +#define SIO_SA_TX_DATA3__PRE 0x0 +#define SIO_SA_TX_LENGTH__A 0x460015 +#define SIO_SA_TX_LENGTH__W 6 +#define SIO_SA_TX_LENGTH__M 0x3F +#define SIO_SA_TX_LENGTH__PRE 0x0 +#define SIO_SA_TX_COMMAND__A 0x460016 +#define SIO_SA_TX_COMMAND__W 2 +#define SIO_SA_TX_COMMAND__M 0x3 +#define SIO_SA_TX_COMMAND__PRE 0x3 + +#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 +#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 +#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 +#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 + +#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 +#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 + +#define SIO_SA_TX_STATUS__A 0x460017 +#define SIO_SA_TX_STATUS__W 2 +#define SIO_SA_TX_STATUS__M 0x3 +#define SIO_SA_TX_STATUS__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUSY__B 0 +#define SIO_SA_TX_STATUS_BUSY__W 1 +#define SIO_SA_TX_STATUS_BUSY__M 0x1 +#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 + +#define SIO_SA_RX_DATA0__A 0x460018 +#define SIO_SA_RX_DATA0__W 16 +#define SIO_SA_RX_DATA0__M 0xFFFF +#define SIO_SA_RX_DATA0__PRE 0x0 +#define SIO_SA_RX_DATA1__A 0x460019 +#define SIO_SA_RX_DATA1__W 16 +#define SIO_SA_RX_DATA1__M 0xFFFF +#define SIO_SA_RX_DATA1__PRE 0x0 +#define SIO_SA_RX_LENGTH__A 0x46001A +#define SIO_SA_RX_LENGTH__W 6 +#define SIO_SA_RX_LENGTH__M 0x3F +#define SIO_SA_RX_LENGTH__PRE 0x0 +#define SIO_SA_RX_COMMAND__A 0x46001B +#define SIO_SA_RX_COMMAND__W 1 +#define SIO_SA_RX_COMMAND__M 0x1 +#define SIO_SA_RX_COMMAND__PRE 0x1 + +#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 +#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 +#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 +#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 + +#define SIO_SA_RX_STATUS__A 0x46001C +#define SIO_SA_RX_STATUS__W 2 +#define SIO_SA_RX_STATUS__M 0x3 +#define SIO_SA_RX_STATUS__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUSY__B 0 +#define SIO_SA_RX_STATUS_BUSY__W 1 +#define SIO_SA_RX_STATUS_BUSY__M 0x1 +#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 + +#define SIO_PDR_COMM_EXEC__A 0x7F0000 +#define SIO_PDR_COMM_EXEC__W 2 +#define SIO_PDR_COMM_EXEC__M 0x3 +#define SIO_PDR_COMM_EXEC__PRE 0x0 +#define SIO_PDR_COMM_EXEC_STOP 0x0 +#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 +#define SIO_PDR_COMM_EXEC_HOLD 0x2 + +#define SIO_PDR_MON_CFG__A 0x7F0010 +#define SIO_PDR_MON_CFG__W 2 +#define SIO_PDR_MON_CFG__M 0x3 +#define SIO_PDR_MON_CFG__PRE 0x0 + +#define SIO_PDR_MON_CFG_OSEL__B 0 +#define SIO_PDR_MON_CFG_OSEL__W 1 +#define SIO_PDR_MON_CFG_OSEL__M 0x1 +#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_IACT__B 1 +#define SIO_PDR_MON_CFG_IACT__W 1 +#define SIO_PDR_MON_CFG_IACT__M 0x2 +#define SIO_PDR_MON_CFG_IACT__PRE 0x0 + +#define SIO_PDR_FDB_CFG__A 0x7F0011 +#define SIO_PDR_FDB_CFG__W 2 +#define SIO_PDR_FDB_CFG__M 0x3 +#define SIO_PDR_FDB_CFG__PRE 0x0 +#define SIO_PDR_FDB_CFG_SEL__B 0 +#define SIO_PDR_FDB_CFG_SEL__W 2 +#define SIO_PDR_FDB_CFG_SEL__M 0x3 +#define SIO_PDR_FDB_CFG_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 +#define SIO_PDR_SMA_RX_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL__PRE 0x0 +#define SIO_PDR_SMA_RX_SEL_SEL__B 0 +#define SIO_PDR_SMA_RX_SEL_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_SILENT__A 0x7F0013 +#define SIO_PDR_SMA_TX_SILENT__W 1 +#define SIO_PDR_SMA_TX_SILENT__M 0x1 +#define SIO_PDR_SMA_TX_SILENT__PRE 0x0 +#define SIO_PDR_UIO_IN_LO__A 0x7F0014 +#define SIO_PDR_UIO_IN_LO__W 16 +#define SIO_PDR_UIO_IN_LO__M 0xFFFF +#define SIO_PDR_UIO_IN_LO__PRE 0x0 +#define SIO_PDR_UIO_IN_LO_DATA__B 0 +#define SIO_PDR_UIO_IN_LO_DATA__W 16 +#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +#define SIO_PDR_UIO_IN_HI__W 14 +#define SIO_PDR_UIO_IN_HI__M 0x3FFF +#define SIO_PDR_UIO_IN_HI__PRE 0x0 +#define SIO_PDR_UIO_IN_HI_DATA__B 0 +#define SIO_PDR_UIO_IN_HI_DATA__W 14 +#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +#define SIO_PDR_UIO_OUT_LO__W 16 +#define SIO_PDR_UIO_OUT_LO__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO__PRE 0x0 +#define SIO_PDR_UIO_OUT_LO_DATA__B 0 +#define SIO_PDR_UIO_OUT_LO_DATA__W 16 +#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 +#define SIO_PDR_UIO_OUT_HI__W 14 +#define SIO_PDR_UIO_OUT_HI__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI__PRE 0x0 +#define SIO_PDR_UIO_OUT_HI_DATA__B 0 +#define SIO_PDR_UIO_OUT_HI_DATA__W 14 +#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 + +#define SIO_PDR_PWM1_MODE__A 0x7F0018 +#define SIO_PDR_PWM1_MODE__W 2 +#define SIO_PDR_PWM1_MODE__M 0x3 +#define SIO_PDR_PWM1_MODE__PRE 0x0 +#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 +#define SIO_PDR_PWM1_PRESCALE__W 6 +#define SIO_PDR_PWM1_PRESCALE__M 0x3F +#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM1_VALUE__A 0x7F001A +#define SIO_PDR_PWM1_VALUE__W 11 +#define SIO_PDR_PWM1_VALUE__M 0x7FF +#define SIO_PDR_PWM1_VALUE__PRE 0x0 +#define SIO_PDR_PWM2_MODE__A 0x7F001C +#define SIO_PDR_PWM2_MODE__W 2 +#define SIO_PDR_PWM2_MODE__M 0x3 +#define SIO_PDR_PWM2_MODE__PRE 0x0 +#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D +#define SIO_PDR_PWM2_PRESCALE__W 6 +#define SIO_PDR_PWM2_PRESCALE__M 0x3F +#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM2_VALUE__A 0x7F001E +#define SIO_PDR_PWM2_VALUE__W 11 +#define SIO_PDR_PWM2_VALUE__M 0x7FF +#define SIO_PDR_PWM2_VALUE__PRE 0x0 +#define SIO_PDR_OHW_CFG__A 0x7F001F +#define SIO_PDR_OHW_CFG__W 7 +#define SIO_PDR_OHW_CFG__M 0x7F +#define SIO_PDR_OHW_CFG__PRE 0x0 + +#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 +#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 +#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_BYPASS__B 2 +#define SIO_PDR_OHW_CFG_BYPASS__W 1 +#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 +#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 + +#define SIO_PDR_OHW_CFG_ASEL__B 3 +#define SIO_PDR_OHW_CFG_ASEL__W 3 +#define SIO_PDR_OHW_CFG_ASEL__M 0x38 +#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_SPEED__B 6 +#define SIO_PDR_OHW_CFG_SPEED__W 1 +#define SIO_PDR_OHW_CFG_SPEED__M 0x40 +#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 + +#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 +#define SIO_PDR_I2S_WS_CFG__W 9 +#define SIO_PDR_I2S_WS_CFG__M 0x1FF +#define SIO_PDR_I2S_WS_CFG__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_MODE__B 0 +#define SIO_PDR_I2S_WS_CFG_MODE__W 3 +#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 +#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 +#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_UIO__B 8 +#define SIO_PDR_I2S_WS_CFG_UIO__W 1 +#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_CFG__A 0x7F0021 +#define SIO_PDR_GPIO_CFG__W 9 +#define SIO_PDR_GPIO_CFG__M 0x1FF +#define SIO_PDR_GPIO_CFG__PRE 0x10 +#define SIO_PDR_GPIO_CFG_MODE__B 0 +#define SIO_PDR_GPIO_CFG_MODE__W 3 +#define SIO_PDR_GPIO_CFG_MODE__M 0x7 +#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 +#define SIO_PDR_GPIO_CFG_DRIVE__B 3 +#define SIO_PDR_GPIO_CFG_DRIVE__W 3 +#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 +#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_GPIO_CFG_KEEP__B 6 +#define SIO_PDR_GPIO_CFG_KEEP__W 2 +#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 +#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 +#define SIO_PDR_GPIO_CFG_UIO__B 8 +#define SIO_PDR_GPIO_CFG_UIO__W 1 +#define SIO_PDR_GPIO_CFG_UIO__M 0x100 +#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 + +#define SIO_PDR_IRQN_CFG__A 0x7F0022 +#define SIO_PDR_IRQN_CFG__W 9 +#define SIO_PDR_IRQN_CFG__M 0x1FF +#define SIO_PDR_IRQN_CFG__PRE 0x10 +#define SIO_PDR_IRQN_CFG_MODE__B 0 +#define SIO_PDR_IRQN_CFG_MODE__W 3 +#define SIO_PDR_IRQN_CFG_MODE__M 0x7 +#define SIO_PDR_IRQN_CFG_MODE__PRE 0x0 +#define SIO_PDR_IRQN_CFG_DRIVE__B 3 +#define SIO_PDR_IRQN_CFG_DRIVE__W 3 +#define SIO_PDR_IRQN_CFG_DRIVE__M 0x38 +#define SIO_PDR_IRQN_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_IRQN_CFG_KEEP__B 6 +#define SIO_PDR_IRQN_CFG_KEEP__W 2 +#define SIO_PDR_IRQN_CFG_KEEP__M 0xC0 +#define SIO_PDR_IRQN_CFG_KEEP__PRE 0x0 +#define SIO_PDR_IRQN_CFG_UIO__B 8 +#define SIO_PDR_IRQN_CFG_UIO__W 1 +#define SIO_PDR_IRQN_CFG_UIO__M 0x100 +#define SIO_PDR_IRQN_CFG_UIO__PRE 0x0 + +#define SIO_PDR_OOB_CRX_CFG__A 0x7F0023 +#define SIO_PDR_OOB_CRX_CFG__W 9 +#define SIO_PDR_OOB_CRX_CFG__M 0x1FF +#define SIO_PDR_OOB_CRX_CFG__PRE 0x10 +#define SIO_PDR_OOB_CRX_CFG_MODE__B 0 +#define SIO_PDR_OOB_CRX_CFG_MODE__W 3 +#define SIO_PDR_OOB_CRX_CFG_MODE__M 0x7 +#define SIO_PDR_OOB_CRX_CFG_MODE__PRE 0x0 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__B 3 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__W 3 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__M 0x38 +#define SIO_PDR_OOB_CRX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_OOB_CRX_CFG_KEEP__B 6 +#define SIO_PDR_OOB_CRX_CFG_KEEP__W 2 +#define SIO_PDR_OOB_CRX_CFG_KEEP__M 0xC0 +#define SIO_PDR_OOB_CRX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_OOB_CRX_CFG_UIO__B 8 +#define SIO_PDR_OOB_CRX_CFG_UIO__W 1 +#define SIO_PDR_OOB_CRX_CFG_UIO__M 0x100 +#define SIO_PDR_OOB_CRX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_OOB_DRX_CFG__A 0x7F0024 +#define SIO_PDR_OOB_DRX_CFG__W 9 +#define SIO_PDR_OOB_DRX_CFG__M 0x1FF +#define SIO_PDR_OOB_DRX_CFG__PRE 0x10 +#define SIO_PDR_OOB_DRX_CFG_MODE__B 0 +#define SIO_PDR_OOB_DRX_CFG_MODE__W 3 +#define SIO_PDR_OOB_DRX_CFG_MODE__M 0x7 +#define SIO_PDR_OOB_DRX_CFG_MODE__PRE 0x0 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__B 3 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__W 3 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__M 0x38 +#define SIO_PDR_OOB_DRX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_OOB_DRX_CFG_KEEP__B 6 +#define SIO_PDR_OOB_DRX_CFG_KEEP__W 2 +#define SIO_PDR_OOB_DRX_CFG_KEEP__M 0xC0 +#define SIO_PDR_OOB_DRX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_OOB_DRX_CFG_UIO__B 8 +#define SIO_PDR_OOB_DRX_CFG_UIO__W 1 +#define SIO_PDR_OOB_DRX_CFG_UIO__M 0x100 +#define SIO_PDR_OOB_DRX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +#define SIO_PDR_MSTRT_CFG__W 9 +#define SIO_PDR_MSTRT_CFG__M 0x1FF +#define SIO_PDR_MSTRT_CFG__PRE 0x50 +#define SIO_PDR_MSTRT_CFG_MODE__B 0 +#define SIO_PDR_MSTRT_CFG_MODE__W 3 +#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 +#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 +#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 +#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MSTRT_CFG_KEEP__B 6 +#define SIO_PDR_MSTRT_CFG_KEEP__W 2 +#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 +#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MSTRT_CFG_UIO__B 8 +#define SIO_PDR_MSTRT_CFG_UIO__W 1 +#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 +#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MERR_CFG__A 0x7F0026 +#define SIO_PDR_MERR_CFG__W 9 +#define SIO_PDR_MERR_CFG__M 0x1FF +#define SIO_PDR_MERR_CFG__PRE 0x50 +#define SIO_PDR_MERR_CFG_MODE__B 0 +#define SIO_PDR_MERR_CFG_MODE__W 3 +#define SIO_PDR_MERR_CFG_MODE__M 0x7 +#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 +#define SIO_PDR_MERR_CFG_DRIVE__B 3 +#define SIO_PDR_MERR_CFG_DRIVE__W 3 +#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 +#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MERR_CFG_KEEP__B 6 +#define SIO_PDR_MERR_CFG_KEEP__W 2 +#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 +#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MERR_CFG_UIO__B 8 +#define SIO_PDR_MERR_CFG_UIO__W 1 +#define SIO_PDR_MERR_CFG_UIO__M 0x100 +#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MCLK_CFG__A 0x7F0028 +#define SIO_PDR_MCLK_CFG__W 9 +#define SIO_PDR_MCLK_CFG__M 0x1FF +#define SIO_PDR_MCLK_CFG__PRE 0x50 +#define SIO_PDR_MCLK_CFG_MODE__B 0 +#define SIO_PDR_MCLK_CFG_MODE__W 3 +#define SIO_PDR_MCLK_CFG_MODE__M 0x7 +#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 +#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +#define SIO_PDR_MCLK_CFG_DRIVE__W 3 +#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 +#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MCLK_CFG_KEEP__B 6 +#define SIO_PDR_MCLK_CFG_KEEP__W 2 +#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 +#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MCLK_CFG_UIO__B 8 +#define SIO_PDR_MCLK_CFG_UIO__W 1 +#define SIO_PDR_MCLK_CFG_UIO__M 0x100 +#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MVAL_CFG__A 0x7F0029 +#define SIO_PDR_MVAL_CFG__W 9 +#define SIO_PDR_MVAL_CFG__M 0x1FF +#define SIO_PDR_MVAL_CFG__PRE 0x50 +#define SIO_PDR_MVAL_CFG_MODE__B 0 +#define SIO_PDR_MVAL_CFG_MODE__W 3 +#define SIO_PDR_MVAL_CFG_MODE__M 0x7 +#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 +#define SIO_PDR_MVAL_CFG_DRIVE__B 3 +#define SIO_PDR_MVAL_CFG_DRIVE__W 3 +#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 +#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MVAL_CFG_KEEP__B 6 +#define SIO_PDR_MVAL_CFG_KEEP__W 2 +#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 +#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MVAL_CFG_UIO__B 8 +#define SIO_PDR_MVAL_CFG_UIO__W 1 +#define SIO_PDR_MVAL_CFG_UIO__M 0x100 +#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD0_CFG__A 0x7F002A +#define SIO_PDR_MD0_CFG__W 9 +#define SIO_PDR_MD0_CFG__M 0x1FF +#define SIO_PDR_MD0_CFG__PRE 0x50 +#define SIO_PDR_MD0_CFG_MODE__B 0 +#define SIO_PDR_MD0_CFG_MODE__W 3 +#define SIO_PDR_MD0_CFG_MODE__M 0x7 +#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD0_CFG_DRIVE__B 3 +#define SIO_PDR_MD0_CFG_DRIVE__W 3 +#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD0_CFG_KEEP__B 6 +#define SIO_PDR_MD0_CFG_KEEP__W 2 +#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD0_CFG_UIO__B 8 +#define SIO_PDR_MD0_CFG_UIO__W 1 +#define SIO_PDR_MD0_CFG_UIO__M 0x100 +#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD1_CFG__A 0x7F002B +#define SIO_PDR_MD1_CFG__W 9 +#define SIO_PDR_MD1_CFG__M 0x1FF +#define SIO_PDR_MD1_CFG__PRE 0x50 +#define SIO_PDR_MD1_CFG_MODE__B 0 +#define SIO_PDR_MD1_CFG_MODE__W 3 +#define SIO_PDR_MD1_CFG_MODE__M 0x7 +#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD1_CFG_DRIVE__B 3 +#define SIO_PDR_MD1_CFG_DRIVE__W 3 +#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD1_CFG_KEEP__B 6 +#define SIO_PDR_MD1_CFG_KEEP__W 2 +#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD1_CFG_UIO__B 8 +#define SIO_PDR_MD1_CFG_UIO__W 1 +#define SIO_PDR_MD1_CFG_UIO__M 0x100 +#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD2_CFG__A 0x7F002C +#define SIO_PDR_MD2_CFG__W 9 +#define SIO_PDR_MD2_CFG__M 0x1FF +#define SIO_PDR_MD2_CFG__PRE 0x50 +#define SIO_PDR_MD2_CFG_MODE__B 0 +#define SIO_PDR_MD2_CFG_MODE__W 3 +#define SIO_PDR_MD2_CFG_MODE__M 0x7 +#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD2_CFG_DRIVE__B 3 +#define SIO_PDR_MD2_CFG_DRIVE__W 3 +#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD2_CFG_KEEP__B 6 +#define SIO_PDR_MD2_CFG_KEEP__W 2 +#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD2_CFG_UIO__B 8 +#define SIO_PDR_MD2_CFG_UIO__W 1 +#define SIO_PDR_MD2_CFG_UIO__M 0x100 +#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD3_CFG__A 0x7F002D +#define SIO_PDR_MD3_CFG__W 9 +#define SIO_PDR_MD3_CFG__M 0x1FF +#define SIO_PDR_MD3_CFG__PRE 0x50 +#define SIO_PDR_MD3_CFG_MODE__B 0 +#define SIO_PDR_MD3_CFG_MODE__W 3 +#define SIO_PDR_MD3_CFG_MODE__M 0x7 +#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD3_CFG_DRIVE__B 3 +#define SIO_PDR_MD3_CFG_DRIVE__W 3 +#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD3_CFG_KEEP__B 6 +#define SIO_PDR_MD3_CFG_KEEP__W 2 +#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD3_CFG_UIO__B 8 +#define SIO_PDR_MD3_CFG_UIO__W 1 +#define SIO_PDR_MD3_CFG_UIO__M 0x100 +#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD4_CFG__A 0x7F002F +#define SIO_PDR_MD4_CFG__W 9 +#define SIO_PDR_MD4_CFG__M 0x1FF +#define SIO_PDR_MD4_CFG__PRE 0x50 +#define SIO_PDR_MD4_CFG_MODE__B 0 +#define SIO_PDR_MD4_CFG_MODE__W 3 +#define SIO_PDR_MD4_CFG_MODE__M 0x7 +#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD4_CFG_DRIVE__B 3 +#define SIO_PDR_MD4_CFG_DRIVE__W 3 +#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD4_CFG_KEEP__B 6 +#define SIO_PDR_MD4_CFG_KEEP__W 2 +#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD4_CFG_UIO__B 8 +#define SIO_PDR_MD4_CFG_UIO__W 1 +#define SIO_PDR_MD4_CFG_UIO__M 0x100 +#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD5_CFG__A 0x7F0030 +#define SIO_PDR_MD5_CFG__W 9 +#define SIO_PDR_MD5_CFG__M 0x1FF +#define SIO_PDR_MD5_CFG__PRE 0x50 +#define SIO_PDR_MD5_CFG_MODE__B 0 +#define SIO_PDR_MD5_CFG_MODE__W 3 +#define SIO_PDR_MD5_CFG_MODE__M 0x7 +#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD5_CFG_DRIVE__B 3 +#define SIO_PDR_MD5_CFG_DRIVE__W 3 +#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD5_CFG_KEEP__B 6 +#define SIO_PDR_MD5_CFG_KEEP__W 2 +#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD5_CFG_UIO__B 8 +#define SIO_PDR_MD5_CFG_UIO__W 1 +#define SIO_PDR_MD5_CFG_UIO__M 0x100 +#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD6_CFG__A 0x7F0031 +#define SIO_PDR_MD6_CFG__W 9 +#define SIO_PDR_MD6_CFG__M 0x1FF +#define SIO_PDR_MD6_CFG__PRE 0x50 +#define SIO_PDR_MD6_CFG_MODE__B 0 +#define SIO_PDR_MD6_CFG_MODE__W 3 +#define SIO_PDR_MD6_CFG_MODE__M 0x7 +#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD6_CFG_DRIVE__B 3 +#define SIO_PDR_MD6_CFG_DRIVE__W 3 +#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD6_CFG_KEEP__B 6 +#define SIO_PDR_MD6_CFG_KEEP__W 2 +#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD6_CFG_UIO__B 8 +#define SIO_PDR_MD6_CFG_UIO__W 1 +#define SIO_PDR_MD6_CFG_UIO__M 0x100 +#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD7_CFG__A 0x7F0032 +#define SIO_PDR_MD7_CFG__W 9 +#define SIO_PDR_MD7_CFG__M 0x1FF +#define SIO_PDR_MD7_CFG__PRE 0x50 +#define SIO_PDR_MD7_CFG_MODE__B 0 +#define SIO_PDR_MD7_CFG_MODE__W 3 +#define SIO_PDR_MD7_CFG_MODE__M 0x7 +#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD7_CFG_DRIVE__B 3 +#define SIO_PDR_MD7_CFG_DRIVE__W 3 +#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD7_CFG_KEEP__B 6 +#define SIO_PDR_MD7_CFG_KEEP__W 2 +#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD7_CFG_UIO__B 8 +#define SIO_PDR_MD7_CFG_UIO__W 1 +#define SIO_PDR_MD7_CFG_UIO__M 0x100 +#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 +#define SIO_PDR_I2C_SCL1_CFG__W 9 +#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 +#define SIO_PDR_I2C_SDA1_CFG__W 9 +#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_VSYNC_CFG__A 0x7F0036 +#define SIO_PDR_VSYNC_CFG__W 9 +#define SIO_PDR_VSYNC_CFG__M 0x1FF +#define SIO_PDR_VSYNC_CFG__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_MODE__B 0 +#define SIO_PDR_VSYNC_CFG_MODE__W 3 +#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 +#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 +#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_KEEP__B 6 +#define SIO_PDR_VSYNC_CFG_KEEP__W 2 +#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 +#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_UIO__B 8 +#define SIO_PDR_VSYNC_CFG_UIO__W 1 +#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 +#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 +#define SIO_PDR_SMA_RX_CFG__W 9 +#define SIO_PDR_SMA_RX_CFG__M 0x1FF +#define SIO_PDR_SMA_RX_CFG__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_MODE__B 0 +#define SIO_PDR_SMA_RX_CFG_MODE__W 3 +#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_UIO__B 8 +#define SIO_PDR_SMA_RX_CFG_UIO__W 1 +#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +#define SIO_PDR_SMA_TX_CFG__W 9 +#define SIO_PDR_SMA_TX_CFG__M 0x1FF +#define SIO_PDR_SMA_TX_CFG__PRE 0x90 +#define SIO_PDR_SMA_TX_CFG_MODE__B 0 +#define SIO_PDR_SMA_TX_CFG_MODE__W 3 +#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 +#define SIO_PDR_SMA_TX_CFG_UIO__B 8 +#define SIO_PDR_SMA_TX_CFG_UIO__W 1 +#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F +#define SIO_PDR_I2C_SDA2_CFG__W 9 +#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 +#define SIO_PDR_I2C_SCL2_CFG__W 9 +#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 +#define SIO_PDR_I2S_CL_CFG__W 9 +#define SIO_PDR_I2S_CL_CFG__M 0x1FF +#define SIO_PDR_I2S_CL_CFG__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_MODE__B 0 +#define SIO_PDR_I2S_CL_CFG_MODE__W 3 +#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 +#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 +#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_UIO__B 8 +#define SIO_PDR_I2S_CL_CFG_UIO__W 1 +#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 +#define SIO_PDR_I2S_DA_CFG__W 9 +#define SIO_PDR_I2S_DA_CFG__M 0x1FF +#define SIO_PDR_I2S_DA_CFG__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_MODE__B 0 +#define SIO_PDR_I2S_DA_CFG_MODE__W 3 +#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 +#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 +#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_UIO__B 8 +#define SIO_PDR_I2S_DA_CFG_UIO__W 1 +#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 +#define SIO_PDR_GPIO_GPIO_FNC__W 2 +#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_IRQN_GPIO_FNC__A 0x7F0051 +#define SIO_PDR_IRQN_GPIO_FNC__W 2 +#define SIO_PDR_IRQN_GPIO_FNC__M 0x3 +#define SIO_PDR_IRQN_GPIO_FNC__PRE 0x0 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__B 0 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__W 2 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_IRQN_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 +#define SIO_PDR_MSTRT_GPIO_FNC__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 +#define SIO_PDR_MERR_GPIO_FNC__W 2 +#define SIO_PDR_MERR_GPIO_FNC__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 +#define SIO_PDR_MCLK_GPIO_FNC__W 2 +#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 +#define SIO_PDR_MVAL_GPIO_FNC__W 2 +#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +#define SIO_PDR_MD0_GPIO_FNC__W 2 +#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +#define SIO_PDR_MD1_GPIO_FNC__W 2 +#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +#define SIO_PDR_MD2_GPIO_FNC__W 2 +#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +#define SIO_PDR_MD3_GPIO_FNC__W 2 +#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +#define SIO_PDR_MD4_GPIO_FNC__W 2 +#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +#define SIO_PDR_MD5_GPIO_FNC__W 2 +#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +#define SIO_PDR_MD6_GPIO_FNC__W 2 +#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +#define SIO_PDR_MD7_GPIO_FNC__W 2 +#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E +#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F +#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 + +#define VSB_COMM_EXEC__A 0x1C00000 +#define VSB_COMM_EXEC__W 2 +#define VSB_COMM_EXEC__M 0x3 +#define VSB_COMM_EXEC__PRE 0x0 +#define VSB_COMM_EXEC_STOP 0x0 +#define VSB_COMM_EXEC_ACTIVE 0x1 +#define VSB_COMM_EXEC_HOLD 0x2 + +#define VSB_COMM_MB__A 0x1C00002 +#define VSB_COMM_MB__W 16 +#define VSB_COMM_MB__M 0xFFFF +#define VSB_COMM_MB__PRE 0x0 +#define VSB_COMM_INT_REQ__A 0x1C00003 +#define VSB_COMM_INT_REQ__W 1 +#define VSB_COMM_INT_REQ__M 0x1 +#define VSB_COMM_INT_REQ__PRE 0x0 + +#define VSB_COMM_INT_REQ_TOP_INT_REQ__B 0 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__W 1 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__M 0x1 +#define VSB_COMM_INT_REQ_TOP_INT_REQ__PRE 0x0 + +#define VSB_COMM_INT_STA__A 0x1C00005 +#define VSB_COMM_INT_STA__W 16 +#define VSB_COMM_INT_STA__M 0xFFFF +#define VSB_COMM_INT_STA__PRE 0x0 + +#define VSB_COMM_INT_MSK__A 0x1C00006 +#define VSB_COMM_INT_MSK__W 16 +#define VSB_COMM_INT_MSK__M 0xFFFF +#define VSB_COMM_INT_MSK__PRE 0x0 + +#define VSB_COMM_INT_STM__A 0x1C00007 +#define VSB_COMM_INT_STM__W 16 +#define VSB_COMM_INT_STM__M 0xFFFF +#define VSB_COMM_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_EXEC__A 0x1C10000 +#define VSB_TOP_COMM_EXEC__W 2 +#define VSB_TOP_COMM_EXEC__M 0x3 +#define VSB_TOP_COMM_EXEC__PRE 0x0 +#define VSB_TOP_COMM_EXEC_STOP 0x0 +#define VSB_TOP_COMM_EXEC_ACTIVE 0x1 +#define VSB_TOP_COMM_EXEC_HOLD 0x2 + +#define VSB_TOP_COMM_MB__A 0x1C10002 +#define VSB_TOP_COMM_MB__W 10 +#define VSB_TOP_COMM_MB__M 0x3FF +#define VSB_TOP_COMM_MB__PRE 0x0 + +#define VSB_TOP_COMM_MB_CTL__B 0 +#define VSB_TOP_COMM_MB_CTL__W 1 +#define VSB_TOP_COMM_MB_CTL__M 0x1 +#define VSB_TOP_COMM_MB_CTL__PRE 0x0 +#define VSB_TOP_COMM_MB_CTL_CTL_OFF 0x0 +#define VSB_TOP_COMM_MB_CTL_CTL_ON 0x1 + +#define VSB_TOP_COMM_MB_OBS__B 1 +#define VSB_TOP_COMM_MB_OBS__W 1 +#define VSB_TOP_COMM_MB_OBS__M 0x2 +#define VSB_TOP_COMM_MB_OBS__PRE 0x0 +#define VSB_TOP_COMM_MB_OBS_OBS_OFF 0x0 +#define VSB_TOP_COMM_MB_OBS_OBS_ON 0x2 + +#define VSB_TOP_COMM_MB_MUX_CTL__B 2 +#define VSB_TOP_COMM_MB_MUX_CTL__W 4 +#define VSB_TOP_COMM_MB_MUX_CTL__M 0x3C +#define VSB_TOP_COMM_MB_MUX_CTL__PRE 0x0 + +#define VSB_TOP_COMM_MB_MUX_OBS__B 6 +#define VSB_TOP_COMM_MB_MUX_OBS__W 4 +#define VSB_TOP_COMM_MB_MUX_OBS__M 0x3C0 +#define VSB_TOP_COMM_MB_MUX_OBS__PRE 0x0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FEC 0x0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM 0x40 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM_AMPLITUDE 0x80 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_1 0xC0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2 0x100 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_1 0x140 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_2 0x180 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1 0x1C0 +#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2 0x200 + +#define VSB_TOP_COMM_INT_REQ__A 0x1C10003 +#define VSB_TOP_COMM_INT_REQ__W 1 +#define VSB_TOP_COMM_INT_REQ__M 0x1 +#define VSB_TOP_COMM_INT_REQ__PRE 0x0 +#define VSB_TOP_COMM_INT_STA__A 0x1C10005 +#define VSB_TOP_COMM_INT_STA__W 6 +#define VSB_TOP_COMM_INT_STA__M 0x3F +#define VSB_TOP_COMM_INT_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__B 0 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__W 1 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__M 0x1 +#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_LOCK_STA__B 1 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__W 1 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__M 0x2 +#define VSB_TOP_COMM_INT_STA_LOCK_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__B 2 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__W 1 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__M 0x4 +#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__B 3 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__W 1 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__M 0x8 +#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__B 4 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__W 1 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__M 0x10 +#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_STA_MERSER_STA__B 5 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__W 1 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__M 0x20 +#define VSB_TOP_COMM_INT_STA_MERSER_STA__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK__A 0x1C10006 +#define VSB_TOP_COMM_INT_MSK__W 6 +#define VSB_TOP_COMM_INT_MSK__M 0x3F +#define VSB_TOP_COMM_INT_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__B 0 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__M 0x1 +#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__B 1 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__M 0x2 +#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__B 2 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__M 0x4 +#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__B 3 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__M 0x8 +#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__B 4 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__M 0x10 +#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__B 5 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__W 1 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__M 0x20 +#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM__A 0x1C10007 +#define VSB_TOP_COMM_INT_STM__W 6 +#define VSB_TOP_COMM_INT_STM__M 0x3F +#define VSB_TOP_COMM_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__B 0 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__W 1 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__M 0x1 +#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_LOCK_STM__B 1 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__W 1 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__M 0x2 +#define VSB_TOP_COMM_INT_STM_LOCK_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__B 2 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__W 1 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__M 0x4 +#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__B 3 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__W 1 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__M 0x8 +#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__B 4 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__W 1 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__M 0x10 +#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__PRE 0x0 + +#define VSB_TOP_COMM_INT_STM_MERSER_STM__B 5 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__W 1 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__M 0x20 +#define VSB_TOP_COMM_INT_STM_MERSER_STM__PRE 0x0 + +#define VSB_TOP_CKGN1ACQ__A 0x1C10010 +#define VSB_TOP_CKGN1ACQ__W 8 +#define VSB_TOP_CKGN1ACQ__M 0xFF +#define VSB_TOP_CKGN1ACQ__PRE 0x4 + +#define VSB_TOP_CKGN1TRK__A 0x1C10011 +#define VSB_TOP_CKGN1TRK__W 8 +#define VSB_TOP_CKGN1TRK__M 0xFF +#define VSB_TOP_CKGN1TRK__PRE 0x0 + +#define VSB_TOP_CKGN2ACQ__A 0x1C10012 +#define VSB_TOP_CKGN2ACQ__W 8 +#define VSB_TOP_CKGN2ACQ__M 0xFF +#define VSB_TOP_CKGN2ACQ__PRE 0x2 + +#define VSB_TOP_CKGN2TRK__A 0x1C10013 +#define VSB_TOP_CKGN2TRK__W 8 +#define VSB_TOP_CKGN2TRK__M 0xFF +#define VSB_TOP_CKGN2TRK__PRE 0x1 + +#define VSB_TOP_CKGN3__A 0x1C10014 +#define VSB_TOP_CKGN3__W 8 +#define VSB_TOP_CKGN3__M 0xFF +#define VSB_TOP_CKGN3__PRE 0x5 + +#define VSB_TOP_CYGN1ACQ__A 0x1C10015 +#define VSB_TOP_CYGN1ACQ__W 8 +#define VSB_TOP_CYGN1ACQ__M 0xFF +#define VSB_TOP_CYGN1ACQ__PRE 0x3 + +#define VSB_TOP_CYGN1TRK__A 0x1C10016 +#define VSB_TOP_CYGN1TRK__W 8 +#define VSB_TOP_CYGN1TRK__M 0xFF +#define VSB_TOP_CYGN1TRK__PRE 0x0 + +#define VSB_TOP_CYGN2ACQ__A 0x1C10017 +#define VSB_TOP_CYGN2ACQ__W 8 +#define VSB_TOP_CYGN2ACQ__M 0xFF +#define VSB_TOP_CYGN2ACQ__PRE 0x3 + +#define VSB_TOP_CYGN2TRK__A 0x1C10018 +#define VSB_TOP_CYGN2TRK__W 8 +#define VSB_TOP_CYGN2TRK__M 0xFF +#define VSB_TOP_CYGN2TRK__PRE 0x2 + +#define VSB_TOP_CYGN3__A 0x1C10019 +#define VSB_TOP_CYGN3__W 8 +#define VSB_TOP_CYGN3__M 0xFF +#define VSB_TOP_CYGN3__PRE 0x6 +#define VSB_TOP_SYNCCTRLWORD__A 0x1C1001A +#define VSB_TOP_SYNCCTRLWORD__W 5 +#define VSB_TOP_SYNCCTRLWORD__M 0x1F +#define VSB_TOP_SYNCCTRLWORD__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_PRST__B 0 +#define VSB_TOP_SYNCCTRLWORD_PRST__W 1 +#define VSB_TOP_SYNCCTRLWORD_PRST__M 0x1 +#define VSB_TOP_SYNCCTRLWORD_PRST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__B 1 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__W 1 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__M 0x2 +#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_INVCNST__B 2 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__W 1 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__M 0x4 +#define VSB_TOP_SYNCCTRLWORD_INVCNST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__B 3 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__W 1 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__M 0x8 +#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__PRE 0x0 + +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__B 4 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__W 1 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M 0x10 +#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE 0x0 + +#define VSB_TOP_MAINSMUP__A 0x1C1001B +#define VSB_TOP_MAINSMUP__W 8 +#define VSB_TOP_MAINSMUP__M 0xFF +#define VSB_TOP_MAINSMUP__PRE 0xFF + +#define VSB_TOP_EQSMUP__A 0x1C1001C +#define VSB_TOP_EQSMUP__W 8 +#define VSB_TOP_EQSMUP__M 0xFF +#define VSB_TOP_EQSMUP__PRE 0xFF +#define VSB_TOP_SYSMUXCTRL__A 0x1C1001D +#define VSB_TOP_SYSMUXCTRL__W 13 +#define VSB_TOP_SYSMUXCTRL__M 0x1FFF +#define VSB_TOP_SYSMUXCTRL__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__B 0 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__M 0x1 +#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__B 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__M 0x2 +#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__B 2 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__M 0x4 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__B 3 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__M 0x8 +#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__B 4 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__M 0x10 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__B 5 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__M 0x20 +#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__B 6 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__M 0x40 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__B 7 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__M 0x80 +#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__B 8 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__W 4 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__M 0xF00 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__PRE 0x0 + +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__B 12 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__W 1 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__M 0x1000 +#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__PRE 0x0 + +#define VSB_TOP_SNRTH_RCA1__A 0x1C1001E +#define VSB_TOP_SNRTH_RCA1__W 8 +#define VSB_TOP_SNRTH_RCA1__M 0xFF +#define VSB_TOP_SNRTH_RCA1__PRE 0x53 + +#define VSB_TOP_SNRTH_RCA1_DN__B 0 +#define VSB_TOP_SNRTH_RCA1_DN__W 4 +#define VSB_TOP_SNRTH_RCA1_DN__M 0xF +#define VSB_TOP_SNRTH_RCA1_DN__PRE 0x3 + +#define VSB_TOP_SNRTH_RCA1_UP__B 4 +#define VSB_TOP_SNRTH_RCA1_UP__W 4 +#define VSB_TOP_SNRTH_RCA1_UP__M 0xF0 +#define VSB_TOP_SNRTH_RCA1_UP__PRE 0x50 + +#define VSB_TOP_SNRTH_RCA2__A 0x1C1001F +#define VSB_TOP_SNRTH_RCA2__W 8 +#define VSB_TOP_SNRTH_RCA2__M 0xFF +#define VSB_TOP_SNRTH_RCA2__PRE 0x75 + +#define VSB_TOP_SNRTH_RCA2_DN__B 0 +#define VSB_TOP_SNRTH_RCA2_DN__W 4 +#define VSB_TOP_SNRTH_RCA2_DN__M 0xF +#define VSB_TOP_SNRTH_RCA2_DN__PRE 0x5 + +#define VSB_TOP_SNRTH_RCA2_UP__B 4 +#define VSB_TOP_SNRTH_RCA2_UP__W 4 +#define VSB_TOP_SNRTH_RCA2_UP__M 0xF0 +#define VSB_TOP_SNRTH_RCA2_UP__PRE 0x70 + +#define VSB_TOP_SNRTH_DDM1__A 0x1C10020 +#define VSB_TOP_SNRTH_DDM1__W 8 +#define VSB_TOP_SNRTH_DDM1__M 0xFF +#define VSB_TOP_SNRTH_DDM1__PRE 0xCA + +#define VSB_TOP_SNRTH_DDM1_DN__B 0 +#define VSB_TOP_SNRTH_DDM1_DN__W 4 +#define VSB_TOP_SNRTH_DDM1_DN__M 0xF +#define VSB_TOP_SNRTH_DDM1_DN__PRE 0xA + +#define VSB_TOP_SNRTH_DDM1_UP__B 4 +#define VSB_TOP_SNRTH_DDM1_UP__W 4 +#define VSB_TOP_SNRTH_DDM1_UP__M 0xF0 +#define VSB_TOP_SNRTH_DDM1_UP__PRE 0xC0 + +#define VSB_TOP_SNRTH_DDM2__A 0x1C10021 +#define VSB_TOP_SNRTH_DDM2__W 8 +#define VSB_TOP_SNRTH_DDM2__M 0xFF +#define VSB_TOP_SNRTH_DDM2__PRE 0xCA + +#define VSB_TOP_SNRTH_DDM2_DN__B 0 +#define VSB_TOP_SNRTH_DDM2_DN__W 4 +#define VSB_TOP_SNRTH_DDM2_DN__M 0xF +#define VSB_TOP_SNRTH_DDM2_DN__PRE 0xA + +#define VSB_TOP_SNRTH_DDM2_UP__B 4 +#define VSB_TOP_SNRTH_DDM2_UP__W 4 +#define VSB_TOP_SNRTH_DDM2_UP__M 0xF0 +#define VSB_TOP_SNRTH_DDM2_UP__PRE 0xC0 + +#define VSB_TOP_SNRTH_PT__A 0x1C10022 +#define VSB_TOP_SNRTH_PT__W 8 +#define VSB_TOP_SNRTH_PT__M 0xFF +#define VSB_TOP_SNRTH_PT__PRE 0xD8 + +#define VSB_TOP_SNRTH_PT_DN__B 0 +#define VSB_TOP_SNRTH_PT_DN__W 4 +#define VSB_TOP_SNRTH_PT_DN__M 0xF +#define VSB_TOP_SNRTH_PT_DN__PRE 0x8 + +#define VSB_TOP_SNRTH_PT_UP__B 4 +#define VSB_TOP_SNRTH_PT_UP__W 4 +#define VSB_TOP_SNRTH_PT_UP__M 0xF0 +#define VSB_TOP_SNRTH_PT_UP__PRE 0xD0 + +#define VSB_TOP_CYSMSTATES__A 0x1C10023 +#define VSB_TOP_CYSMSTATES__W 8 +#define VSB_TOP_CYSMSTATES__M 0xFF +#define VSB_TOP_CYSMSTATES__PRE 0x0 + +#define VSB_TOP_CYSMSTATES_SYSST__B 0 +#define VSB_TOP_CYSMSTATES_SYSST__W 4 +#define VSB_TOP_CYSMSTATES_SYSST__M 0xF +#define VSB_TOP_CYSMSTATES_SYSST__PRE 0x0 + +#define VSB_TOP_CYSMSTATES_EQST__B 4 +#define VSB_TOP_CYSMSTATES_EQST__W 4 +#define VSB_TOP_CYSMSTATES_EQST__M 0xF0 +#define VSB_TOP_CYSMSTATES_EQST__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL__A 0x1C10024 +#define VSB_TOP_SMALL_NOTCH_CONTROL__W 8 +#define VSB_TOP_SMALL_NOTCH_CONTROL__M 0xFF +#define VSB_TOP_SMALL_NOTCH_CONTROL__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__B 0 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__M 0x1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__B 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M 0x2 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__B 2 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__M 0x4 +#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__B 3 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__W 4 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__M 0x78 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__PRE 0x0 + +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__B 7 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__W 1 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M 0x80 +#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE 0x0 + +#define VSB_TOP_TAPREADCYC__A 0x1C10025 +#define VSB_TOP_TAPREADCYC__W 9 +#define VSB_TOP_TAPREADCYC__M 0x1FF +#define VSB_TOP_TAPREADCYC__PRE 0x1 + +#define VSB_TOP_VALIDPKLVL__A 0x1C10026 +#define VSB_TOP_VALIDPKLVL__W 13 +#define VSB_TOP_VALIDPKLVL__M 0x1FFF +#define VSB_TOP_VALIDPKLVL__PRE 0x100 + +#define VSB_TOP_CENTROID_FINE_DELAY__A 0x1C10027 +#define VSB_TOP_CENTROID_FINE_DELAY__W 10 +#define VSB_TOP_CENTROID_FINE_DELAY__M 0x3FF +#define VSB_TOP_CENTROID_FINE_DELAY__PRE 0xFF + +#define VSB_TOP_CENTROID_SMACH_DELAY__A 0x1C10028 +#define VSB_TOP_CENTROID_SMACH_DELAY__W 10 +#define VSB_TOP_CENTROID_SMACH_DELAY__M 0x3FF +#define VSB_TOP_CENTROID_SMACH_DELAY__PRE 0x1FF + +#define VSB_TOP_SNR__A 0x1C10029 +#define VSB_TOP_SNR__W 14 +#define VSB_TOP_SNR__M 0x3FFF +#define VSB_TOP_SNR__PRE 0x0 +#define VSB_TOP_LOCKSTATUS__A 0x1C1002A +#define VSB_TOP_LOCKSTATUS__W 7 +#define VSB_TOP_LOCKSTATUS__M 0x7F +#define VSB_TOP_LOCKSTATUS__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_VSBMODE__B 0 +#define VSB_TOP_LOCKSTATUS_VSBMODE__W 4 +#define VSB_TOP_LOCKSTATUS_VSBMODE__M 0xF +#define VSB_TOP_LOCKSTATUS_VSBMODE__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_FRMLOCK__B 4 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__W 1 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__M 0x10 +#define VSB_TOP_LOCKSTATUS_FRMLOCK__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_CYLOCK__B 5 +#define VSB_TOP_LOCKSTATUS_CYLOCK__W 1 +#define VSB_TOP_LOCKSTATUS_CYLOCK__M 0x20 +#define VSB_TOP_LOCKSTATUS_CYLOCK__PRE 0x0 + +#define VSB_TOP_LOCKSTATUS_DDMON__B 6 +#define VSB_TOP_LOCKSTATUS_DDMON__W 1 +#define VSB_TOP_LOCKSTATUS_DDMON__M 0x40 +#define VSB_TOP_LOCKSTATUS_DDMON__PRE 0x0 + +#define VSB_TOP_CTST__A 0x1C1002B +#define VSB_TOP_CTST__W 4 +#define VSB_TOP_CTST__M 0xF +#define VSB_TOP_CTST__PRE 0x0 +#define VSB_TOP_EQSMRSTCTRL__A 0x1C1002C +#define VSB_TOP_EQSMRSTCTRL__W 7 +#define VSB_TOP_EQSMRSTCTRL__M 0x7F +#define VSB_TOP_EQSMRSTCTRL__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_RCAON__B 0 +#define VSB_TOP_EQSMRSTCTRL_RCAON__W 1 +#define VSB_TOP_EQSMRSTCTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRSTCTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DFEON__B 1 +#define VSB_TOP_EQSMRSTCTRL_DFEON__W 1 +#define VSB_TOP_EQSMRSTCTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRSTCTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRSTCTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRSTCTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL__A 0x1C1002D +#define VSB_TOP_EQSMTRNCTRL__W 7 +#define VSB_TOP_EQSMTRNCTRL__M 0x7F +#define VSB_TOP_EQSMTRNCTRL__PRE 0x40 + +#define VSB_TOP_EQSMTRNCTRL_RCAON__B 0 +#define VSB_TOP_EQSMTRNCTRL_RCAON__W 1 +#define VSB_TOP_EQSMTRNCTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMTRNCTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DFEON__B 1 +#define VSB_TOP_EQSMTRNCTRL_DFEON__W 1 +#define VSB_TOP_EQSMTRNCTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMTRNCTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMTRNCTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMTRNCTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__PRE 0x40 + +#define VSB_TOP_EQSMRCA1CTRL__A 0x1C1002E +#define VSB_TOP_EQSMRCA1CTRL__W 7 +#define VSB_TOP_EQSMRCA1CTRL__M 0x7F +#define VSB_TOP_EQSMRCA1CTRL__PRE 0x1 + +#define VSB_TOP_EQSMRCA1CTRL_RCAON__B 0 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRCA1CTRL_RCAON__PRE 0x1 + +#define VSB_TOP_EQSMRCA1CTRL_DFEON__B 1 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRCA1CTRL_DFEON__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL__A 0x1C1002F +#define VSB_TOP_EQSMRCA2CTRL__W 7 +#define VSB_TOP_EQSMRCA2CTRL__M 0x7F +#define VSB_TOP_EQSMRCA2CTRL__PRE 0x3 + +#define VSB_TOP_EQSMRCA2CTRL_RCAON__B 0 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMRCA2CTRL_RCAON__PRE 0x1 + +#define VSB_TOP_EQSMRCA2CTRL_DFEON__B 1 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMRCA2CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL__A 0x1C10030 +#define VSB_TOP_EQSMDDM1CTRL__W 7 +#define VSB_TOP_EQSMDDM1CTRL__M 0x7F +#define VSB_TOP_EQSMDDM1CTRL__PRE 0x6 + +#define VSB_TOP_EQSMDDM1CTRL_RCAON__B 0 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMDDM1CTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_DFEON__B 1 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMDDM1CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__PRE 0x4 + +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL__A 0x1C10031 +#define VSB_TOP_EQSMDDM2CTRL__W 7 +#define VSB_TOP_EQSMDDM2CTRL__M 0x7F +#define VSB_TOP_EQSMDDM2CTRL__PRE 0x1E + +#define VSB_TOP_EQSMDDM2CTRL_RCAON__B 0 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__M 0x1 +#define VSB_TOP_EQSMDDM2CTRL_RCAON__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL_DFEON__B 1 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__M 0x2 +#define VSB_TOP_EQSMDDM2CTRL_DFEON__PRE 0x2 + +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__B 2 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__M 0x4 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__PRE 0x4 + +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__B 3 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__M 0x8 +#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__PRE 0x8 + +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__B 4 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__W 1 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__M 0x10 +#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__PRE 0x10 + +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__B 5 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__W 1 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__M 0x20 +#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__PRE 0x0 + +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__B 6 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__W 1 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__M 0x40 +#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL__A 0x1C10032 +#define VSB_TOP_SYSSMRSTCTRL__W 11 +#define VSB_TOP_SYSSMRSTCTRL__M 0x7FF +#define VSB_TOP_SYSSMRSTCTRL__PRE 0x7F9 + +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__PRE 0x10 + +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__PRE 0x100 + +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__PRE 0x400 + +#define VSB_TOP_SYSSMCYCTRL__A 0x1C10033 +#define VSB_TOP_SYSSMCYCTRL__W 11 +#define VSB_TOP_SYSSMCYCTRL__M 0x7FF +#define VSB_TOP_SYSSMCYCTRL__PRE 0x4E9 + +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMCYCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMCYCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMCYCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMCYCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__PRE 0x400 + +#define VSB_TOP_SYSSMTRNCTRL__A 0x1C10034 +#define VSB_TOP_SYSSMTRNCTRL__W 11 +#define VSB_TOP_SYSSMTRNCTRL__M 0x7FF +#define VSB_TOP_SYSSMTRNCTRL__PRE 0x204 + +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__PRE 0x4 + +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL__A 0x1C10035 +#define VSB_TOP_SYSSMEQCTRL__W 11 +#define VSB_TOP_SYSSMEQCTRL__M 0x7FF +#define VSB_TOP_SYSSMEQCTRL__PRE 0x304 + +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMEQCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMEQCTRL_STARTTRN__PRE 0x4 + +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMEQCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMEQCTRL_CKBWSW__PRE 0x100 + +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__PRE 0x200 + +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL__A 0x1C10036 +#define VSB_TOP_SYSSMAGCCTRL__W 11 +#define VSB_TOP_SYSSMAGCCTRL__M 0x7FF +#define VSB_TOP_SYSSMAGCCTRL__PRE 0xF9 + +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__PRE 0x1 + +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__PRE 0x10 + +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__PRE 0x20 + +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__PRE 0x80 + +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL__A 0x1C10037 +#define VSB_TOP_SYSSMCTCTRL__W 11 +#define VSB_TOP_SYSSMCTCTRL__M 0x7FF +#define VSB_TOP_SYSSMCTCTRL__PRE 0x4A + +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__B 0 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__M 0x1 +#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__B 1 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__W 1 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__M 0x2 +#define VSB_TOP_SYSSMCTCTRL_CTCALEN__PRE 0x2 + +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__B 2 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__W 1 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__M 0x4 +#define VSB_TOP_SYSSMCTCTRL_STARTTRN__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__B 3 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__M 0x8 +#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__PRE 0x8 + +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__B 4 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__M 0x10 +#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__B 5 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__M 0x20 +#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__B 6 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__W 1 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__M 0x40 +#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__PRE 0x40 + +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__B 7 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__W 1 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__M 0x80 +#define VSB_TOP_SYSSMCTCTRL_CKFRZ__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__B 8 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__W 1 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__M 0x100 +#define VSB_TOP_SYSSMCTCTRL_CKBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__B 9 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__W 1 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__M 0x200 +#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__PRE 0x0 + +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__B 10 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__W 1 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__M 0x400 +#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__PRE 0x0 + +#define VSB_TOP_EQCTRL__A 0x1C10038 +#define VSB_TOP_EQCTRL__W 10 +#define VSB_TOP_EQCTRL__M 0x3FF +#define VSB_TOP_EQCTRL__PRE 0x6 + +#define VSB_TOP_EQCTRL_STASSIGNEN__B 0 +#define VSB_TOP_EQCTRL_STASSIGNEN__W 1 +#define VSB_TOP_EQCTRL_STASSIGNEN__M 0x1 +#define VSB_TOP_EQCTRL_STASSIGNEN__PRE 0x0 + +#define VSB_TOP_EQCTRL_ORCANCMAEN__B 1 +#define VSB_TOP_EQCTRL_ORCANCMAEN__W 1 +#define VSB_TOP_EQCTRL_ORCANCMAEN__M 0x2 +#define VSB_TOP_EQCTRL_ORCANCMAEN__PRE 0x2 + +#define VSB_TOP_EQCTRL_ODAGCGO__B 2 +#define VSB_TOP_EQCTRL_ODAGCGO__W 1 +#define VSB_TOP_EQCTRL_ODAGCGO__M 0x4 +#define VSB_TOP_EQCTRL_ODAGCGO__PRE 0x4 + +#define VSB_TOP_EQCTRL_OPTGAIN__B 3 +#define VSB_TOP_EQCTRL_OPTGAIN__W 3 +#define VSB_TOP_EQCTRL_OPTGAIN__M 0x38 +#define VSB_TOP_EQCTRL_OPTGAIN__PRE 0x0 + +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__B 6 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__W 1 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__M 0x40 +#define VSB_TOP_EQCTRL_TAPRAMWRTEN__PRE 0x0 + +#define VSB_TOP_EQCTRL_CMAGAIN__B 7 +#define VSB_TOP_EQCTRL_CMAGAIN__W 3 +#define VSB_TOP_EQCTRL_CMAGAIN__M 0x380 +#define VSB_TOP_EQCTRL_CMAGAIN__PRE 0x0 + +#define VSB_TOP_PREEQAGCCTRL__A 0x1C10039 +#define VSB_TOP_PREEQAGCCTRL__W 5 +#define VSB_TOP_PREEQAGCCTRL__M 0x1F +#define VSB_TOP_PREEQAGCCTRL__PRE 0x10 + +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__B 0 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__W 4 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__M 0xF +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__PRE 0x0 + +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__B 4 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__W 1 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M 0x10 +#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE 0x10 + +#define VSB_TOP_PREEQAGCPWRREFLVLHI__A 0x1C1003A +#define VSB_TOP_PREEQAGCPWRREFLVLHI__W 8 +#define VSB_TOP_PREEQAGCPWRREFLVLHI__M 0xFF +#define VSB_TOP_PREEQAGCPWRREFLVLHI__PRE 0x0 + +#define VSB_TOP_PREEQAGCPWRREFLVLLO__A 0x1C1003B +#define VSB_TOP_PREEQAGCPWRREFLVLLO__W 16 +#define VSB_TOP_PREEQAGCPWRREFLVLLO__M 0xFFFF +#define VSB_TOP_PREEQAGCPWRREFLVLLO__PRE 0x1D66 + +#define VSB_TOP_CORINGSEL__A 0x1C1003C +#define VSB_TOP_CORINGSEL__W 8 +#define VSB_TOP_CORINGSEL__M 0xFF +#define VSB_TOP_CORINGSEL__PRE 0x3 +#define VSB_TOP_BEDETCTRL__A 0x1C1003D +#define VSB_TOP_BEDETCTRL__W 9 +#define VSB_TOP_BEDETCTRL__M 0x1FF +#define VSB_TOP_BEDETCTRL__PRE 0x145 + +#define VSB_TOP_BEDETCTRL_MIXRATIO__B 0 +#define VSB_TOP_BEDETCTRL_MIXRATIO__W 3 +#define VSB_TOP_BEDETCTRL_MIXRATIO__M 0x7 +#define VSB_TOP_BEDETCTRL_MIXRATIO__PRE 0x5 + +#define VSB_TOP_BEDETCTRL_CYOFFSEL__B 3 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__W 1 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__M 0x8 +#define VSB_TOP_BEDETCTRL_CYOFFSEL__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__B 4 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__W 1 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__M 0x10 +#define VSB_TOP_BEDETCTRL_DATAOFFSEL__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__B 5 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__M 0x20 +#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__B 6 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__M 0x40 +#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__PRE 0x40 + +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__B 7 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__M 0x80 +#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__PRE 0x0 + +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__B 8 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__W 1 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__M 0x100 +#define VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE 0x100 + +#define VSB_TOP_LBAGCREFLVL__A 0x1C1003E +#define VSB_TOP_LBAGCREFLVL__W 12 +#define VSB_TOP_LBAGCREFLVL__M 0xFFF +#define VSB_TOP_LBAGCREFLVL__PRE 0x200 + +#define VSB_TOP_UBAGCREFLVL__A 0x1C1003F +#define VSB_TOP_UBAGCREFLVL__W 12 +#define VSB_TOP_UBAGCREFLVL__M 0xFFF +#define VSB_TOP_UBAGCREFLVL__PRE 0x400 + +#define VSB_TOP_NOTCH1_BIN_NUM__A 0x1C10040 +#define VSB_TOP_NOTCH1_BIN_NUM__W 11 +#define VSB_TOP_NOTCH1_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH1_BIN_NUM__PRE 0xB2 + +#define VSB_TOP_NOTCH2_BIN_NUM__A 0x1C10041 +#define VSB_TOP_NOTCH2_BIN_NUM__W 11 +#define VSB_TOP_NOTCH2_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH2_BIN_NUM__PRE 0x40B + +#define VSB_TOP_NOTCH_START_BIN_NUM__A 0x1C10042 +#define VSB_TOP_NOTCH_START_BIN_NUM__W 11 +#define VSB_TOP_NOTCH_START_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH_START_BIN_NUM__PRE 0x7C0 + +#define VSB_TOP_NOTCH_STOP_BIN_NUM__A 0x1C10043 +#define VSB_TOP_NOTCH_STOP_BIN_NUM__W 11 +#define VSB_TOP_NOTCH_STOP_BIN_NUM__M 0x7FF +#define VSB_TOP_NOTCH_STOP_BIN_NUM__PRE 0x43F + +#define VSB_TOP_NOTCH_TEST_DURATION__A 0x1C10044 +#define VSB_TOP_NOTCH_TEST_DURATION__W 11 +#define VSB_TOP_NOTCH_TEST_DURATION__M 0x7FF +#define VSB_TOP_NOTCH_TEST_DURATION__PRE 0x7FF + +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__A 0x1C10045 +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__W 11 +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__M 0x7FF +#define VSB_TOP_RESULT_LARGE_PEAK_BIN__PRE 0x0 + +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__A 0x1C10046 +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__W 16 +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__M 0xFFFF +#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__PRE 0x0 + +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__A 0x1C10047 +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__W 11 +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__M 0x7FF +#define VSB_TOP_RESULT_SMALL_PEAK_BIN__PRE 0x0 + +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__A 0x1C10048 +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__W 16 +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__M 0xFFFF +#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__PRE 0x0 + +#define VSB_TOP_NOTCH_SWEEP_RUNNING__A 0x1C10049 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__W 1 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__M 0x1 +#define VSB_TOP_NOTCH_SWEEP_RUNNING__PRE 0x0 + +#define VSB_TOP_PREEQDAGCRATIO__A 0x1C1004A +#define VSB_TOP_PREEQDAGCRATIO__W 13 +#define VSB_TOP_PREEQDAGCRATIO__M 0x1FFF +#define VSB_TOP_PREEQDAGCRATIO__PRE 0x0 +#define VSB_TOP_AGC_TRUNCCTRL__A 0x1C1004B +#define VSB_TOP_AGC_TRUNCCTRL__W 4 +#define VSB_TOP_AGC_TRUNCCTRL__M 0xF +#define VSB_TOP_AGC_TRUNCCTRL__PRE 0xF + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__B 0 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__W 2 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__M 0x3 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__PRE 0x3 + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__B 2 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__W 1 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__M 0x4 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__PRE 0x4 + +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__B 3 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__W 1 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M 0x8 +#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE 0x8 + +#define VSB_TOP_BEAGC_DEADZONEINIT__A 0x1C1004C +#define VSB_TOP_BEAGC_DEADZONEINIT__W 8 +#define VSB_TOP_BEAGC_DEADZONEINIT__M 0xFF +#define VSB_TOP_BEAGC_DEADZONEINIT__PRE 0x50 + +#define VSB_TOP_BEAGC_REFLEVEL__A 0x1C1004D +#define VSB_TOP_BEAGC_REFLEVEL__W 9 +#define VSB_TOP_BEAGC_REFLEVEL__M 0x1FF +#define VSB_TOP_BEAGC_REFLEVEL__PRE 0xAE + +#define VSB_TOP_BEAGC_GAINSHIFT__A 0x1C1004E +#define VSB_TOP_BEAGC_GAINSHIFT__W 3 +#define VSB_TOP_BEAGC_GAINSHIFT__M 0x7 +#define VSB_TOP_BEAGC_GAINSHIFT__PRE 0x3 + +#define VSB_TOP_BEAGC_REGINIT__A 0x1C1004F +#define VSB_TOP_BEAGC_REGINIT__W 15 +#define VSB_TOP_BEAGC_REGINIT__M 0x7FFF +#define VSB_TOP_BEAGC_REGINIT__PRE 0x40 + +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__B 14 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__W 1 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M 0x4000 +#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE 0x0 + +#define VSB_TOP_BEAGC_SCALE__A 0x1C10050 +#define VSB_TOP_BEAGC_SCALE__W 14 +#define VSB_TOP_BEAGC_SCALE__M 0x3FFF +#define VSB_TOP_BEAGC_SCALE__PRE 0x0 + +#define VSB_TOP_CFAGC_DEADZONEINIT__A 0x1C10051 +#define VSB_TOP_CFAGC_DEADZONEINIT__W 8 +#define VSB_TOP_CFAGC_DEADZONEINIT__M 0xFF +#define VSB_TOP_CFAGC_DEADZONEINIT__PRE 0x50 + +#define VSB_TOP_CFAGC_REFLEVEL__A 0x1C10052 +#define VSB_TOP_CFAGC_REFLEVEL__W 9 +#define VSB_TOP_CFAGC_REFLEVEL__M 0x1FF +#define VSB_TOP_CFAGC_REFLEVEL__PRE 0xAE + +#define VSB_TOP_CFAGC_GAINSHIFT__A 0x1C10053 +#define VSB_TOP_CFAGC_GAINSHIFT__W 3 +#define VSB_TOP_CFAGC_GAINSHIFT__M 0x7 +#define VSB_TOP_CFAGC_GAINSHIFT__PRE 0x3 + +#define VSB_TOP_CFAGC_REGINIT__A 0x1C10054 +#define VSB_TOP_CFAGC_REGINIT__W 15 +#define VSB_TOP_CFAGC_REGINIT__M 0x7FFF +#define VSB_TOP_CFAGC_REGINIT__PRE 0x80 + +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__B 14 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__W 1 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M 0x4000 +#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE 0x0 + +#define VSB_TOP_CFAGC_SCALE__A 0x1C10055 +#define VSB_TOP_CFAGC_SCALE__W 14 +#define VSB_TOP_CFAGC_SCALE__M 0x3FFF +#define VSB_TOP_CFAGC_SCALE__PRE 0x0 + +#define VSB_TOP_CKTRKONCTL__A 0x1C10056 +#define VSB_TOP_CKTRKONCTL__W 2 +#define VSB_TOP_CKTRKONCTL__M 0x3 +#define VSB_TOP_CKTRKONCTL__PRE 0x0 + +#define VSB_TOP_CYTRKONCTL__A 0x1C10057 +#define VSB_TOP_CYTRKONCTL__W 2 +#define VSB_TOP_CYTRKONCTL__M 0x3 +#define VSB_TOP_CYTRKONCTL__PRE 0x0 + +#define VSB_TOP_PTONCTL__A 0x1C10058 +#define VSB_TOP_PTONCTL__W 2 +#define VSB_TOP_PTONCTL__M 0x3 +#define VSB_TOP_PTONCTL__PRE 0x0 + +#define VSB_TOP_NOTCH_SCALE_1__A 0x1C10059 +#define VSB_TOP_NOTCH_SCALE_1__W 8 +#define VSB_TOP_NOTCH_SCALE_1__M 0xFF +#define VSB_TOP_NOTCH_SCALE_1__PRE 0xA + +#define VSB_TOP_NOTCH_SCALE_2__A 0x1C1005A +#define VSB_TOP_NOTCH_SCALE_2__W 8 +#define VSB_TOP_NOTCH_SCALE_2__M 0xFF +#define VSB_TOP_NOTCH_SCALE_2__PRE 0xA + +#define VSB_TOP_FIRSTLARGFFETAP__A 0x1C1005B +#define VSB_TOP_FIRSTLARGFFETAP__W 12 +#define VSB_TOP_FIRSTLARGFFETAP__M 0xFFF +#define VSB_TOP_FIRSTLARGFFETAP__PRE 0x0 + +#define VSB_TOP_FIRSTLARGFFETAPADDR__A 0x1C1005C +#define VSB_TOP_FIRSTLARGFFETAPADDR__W 11 +#define VSB_TOP_FIRSTLARGFFETAPADDR__M 0x7FF +#define VSB_TOP_FIRSTLARGFFETAPADDR__PRE 0x0 + +#define VSB_TOP_SECONDLARGFFETAP__A 0x1C1005D +#define VSB_TOP_SECONDLARGFFETAP__W 12 +#define VSB_TOP_SECONDLARGFFETAP__M 0xFFF +#define VSB_TOP_SECONDLARGFFETAP__PRE 0x0 + +#define VSB_TOP_SECONDLARGFFETAPADDR__A 0x1C1005E +#define VSB_TOP_SECONDLARGFFETAPADDR__W 11 +#define VSB_TOP_SECONDLARGFFETAPADDR__M 0x7FF +#define VSB_TOP_SECONDLARGFFETAPADDR__PRE 0x0 + +#define VSB_TOP_FIRSTLARGDFETAP__A 0x1C1005F +#define VSB_TOP_FIRSTLARGDFETAP__W 12 +#define VSB_TOP_FIRSTLARGDFETAP__M 0xFFF +#define VSB_TOP_FIRSTLARGDFETAP__PRE 0x0 + +#define VSB_TOP_FIRSTLARGDFETAPADDR__A 0x1C10060 +#define VSB_TOP_FIRSTLARGDFETAPADDR__W 11 +#define VSB_TOP_FIRSTLARGDFETAPADDR__M 0x7FF +#define VSB_TOP_FIRSTLARGDFETAPADDR__PRE 0x0 + +#define VSB_TOP_SECONDLARGDFETAP__A 0x1C10061 +#define VSB_TOP_SECONDLARGDFETAP__W 12 +#define VSB_TOP_SECONDLARGDFETAP__M 0xFFF +#define VSB_TOP_SECONDLARGDFETAP__PRE 0x0 + +#define VSB_TOP_SECONDLARGDFETAPADDR__A 0x1C10062 +#define VSB_TOP_SECONDLARGDFETAPADDR__W 11 +#define VSB_TOP_SECONDLARGDFETAPADDR__M 0x7FF +#define VSB_TOP_SECONDLARGDFETAPADDR__PRE 0x0 + +#define VSB_TOP_PARAOWDBUS__A 0x1C10063 +#define VSB_TOP_PARAOWDBUS__W 12 +#define VSB_TOP_PARAOWDBUS__M 0xFFF +#define VSB_TOP_PARAOWDBUS__PRE 0x0 +#define VSB_TOP_PARAOWCTRL__A 0x1C10064 +#define VSB_TOP_PARAOWCTRL__W 7 +#define VSB_TOP_PARAOWCTRL__M 0x7F +#define VSB_TOP_PARAOWCTRL__PRE 0x0 + +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__B 0 +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__W 6 +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__M 0x3F +#define VSB_TOP_PARAOWCTRL_PARAOWABUS__PRE 0x0 + +#define VSB_TOP_PARAOWCTRL_PARAOWEN__B 6 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__W 1 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__M 0x40 +#define VSB_TOP_PARAOWCTRL_PARAOWEN__PRE 0x0 + +#define VSB_TOP_CURRENTSEGLOCAT__A 0x1C10065 +#define VSB_TOP_CURRENTSEGLOCAT__W 10 +#define VSB_TOP_CURRENTSEGLOCAT__M 0x3FF +#define VSB_TOP_CURRENTSEGLOCAT__PRE 0x0 + +#define VSB_TOP_MEASUREMENT_PERIOD__A 0x1C10066 +#define VSB_TOP_MEASUREMENT_PERIOD__W 16 +#define VSB_TOP_MEASUREMENT_PERIOD__M 0xFFFF +#define VSB_TOP_MEASUREMENT_PERIOD__PRE 0x0 + +#define VSB_TOP_NR_SYM_ERRS__A 0x1C10067 +#define VSB_TOP_NR_SYM_ERRS__W 16 +#define VSB_TOP_NR_SYM_ERRS__M 0xFFFF +#define VSB_TOP_NR_SYM_ERRS__PRE 0xFFFF + +#define VSB_TOP_ERR_ENERGY_L__A 0x1C10068 +#define VSB_TOP_ERR_ENERGY_L__W 16 +#define VSB_TOP_ERR_ENERGY_L__M 0xFFFF +#define VSB_TOP_ERR_ENERGY_L__PRE 0xFFFF + +#define VSB_TOP_ERR_ENERGY_H__A 0x1C10069 +#define VSB_TOP_ERR_ENERGY_H__W 16 +#define VSB_TOP_ERR_ENERGY_H__M 0xFFFF +#define VSB_TOP_ERR_ENERGY_H__PRE 0xFFFF + +#define VSB_TOP_SLICER_SEL_8LEV__A 0x1C1006A +#define VSB_TOP_SLICER_SEL_8LEV__W 1 +#define VSB_TOP_SLICER_SEL_8LEV__M 0x1 +#define VSB_TOP_SLICER_SEL_8LEV__PRE 0x1 + +#define VSB_TOP_BNFIELD__A 0x1C1006B +#define VSB_TOP_BNFIELD__W 3 +#define VSB_TOP_BNFIELD__M 0x7 +#define VSB_TOP_BNFIELD__PRE 0x3 + +#define VSB_TOP_CLPLASTNUM__A 0x1C1006C +#define VSB_TOP_CLPLASTNUM__W 8 +#define VSB_TOP_CLPLASTNUM__M 0xFF +#define VSB_TOP_CLPLASTNUM__PRE 0x0 + +#define VSB_TOP_BNSQERR__A 0x1C1006D +#define VSB_TOP_BNSQERR__W 16 +#define VSB_TOP_BNSQERR__M 0xFFFF +#define VSB_TOP_BNSQERR__PRE 0x1AD + +#define VSB_TOP_BNTHRESH__A 0x1C1006E +#define VSB_TOP_BNTHRESH__W 9 +#define VSB_TOP_BNTHRESH__M 0x1FF +#define VSB_TOP_BNTHRESH__PRE 0x120 + +#define VSB_TOP_BNCLPNUM__A 0x1C1006F +#define VSB_TOP_BNCLPNUM__W 16 +#define VSB_TOP_BNCLPNUM__M 0xFFFF +#define VSB_TOP_BNCLPNUM__PRE 0x0 +#define VSB_TOP_PHASELOCKCTRL__A 0x1C10070 +#define VSB_TOP_PHASELOCKCTRL__W 7 +#define VSB_TOP_PHASELOCKCTRL__M 0x7F +#define VSB_TOP_PHASELOCKCTRL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__B 0 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__M 0x1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__B 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M 0x2 +#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__B 2 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__M 0x4 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__B 3 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__M 0x8 +#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__B 4 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__W 1 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__M 0x10 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__B 5 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__W 1 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__M 0x20 +#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__PRE 0x0 + +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__B 6 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__W 1 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__M 0x40 +#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE 0x0 + +#define VSB_TOP_DLOCKACCUM__A 0x1C10071 +#define VSB_TOP_DLOCKACCUM__W 16 +#define VSB_TOP_DLOCKACCUM__M 0xFFFF +#define VSB_TOP_DLOCKACCUM__PRE 0x0 + +#define VSB_TOP_PLOCKACCUM__A 0x1C10072 +#define VSB_TOP_PLOCKACCUM__W 16 +#define VSB_TOP_PLOCKACCUM__M 0xFFFF +#define VSB_TOP_PLOCKACCUM__PRE 0x0 + +#define VSB_TOP_CLOCKACCUM__A 0x1C10073 +#define VSB_TOP_CLOCKACCUM__W 16 +#define VSB_TOP_CLOCKACCUM__M 0xFFFF +#define VSB_TOP_CLOCKACCUM__PRE 0x0 + +#define VSB_TOP_DCRMVACUMI__A 0x1C10074 +#define VSB_TOP_DCRMVACUMI__W 10 +#define VSB_TOP_DCRMVACUMI__M 0x3FF +#define VSB_TOP_DCRMVACUMI__PRE 0x0 + +#define VSB_TOP_DCRMVACUMQ__A 0x1C10075 +#define VSB_TOP_DCRMVACUMQ__W 10 +#define VSB_TOP_DCRMVACUMQ__M 0x3FF +#define VSB_TOP_DCRMVACUMQ__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A 0x1C20000 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__A 0x1C20001 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__A 0x1C20002 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__A 0x1C20003 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__A 0x1C20004 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__A 0x1C20005 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__A 0x1C20006 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__A 0x1C20007 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__A 0x1C20008 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__A 0x1C20009 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__A 0x1C2000A +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__A 0x1C2000B +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__A 0x1C2000C +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__A 0x1C2000D +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__A 0x1C2000E +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__A 0x1C2000F +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__A 0x1C20010 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__A 0x1C20011 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__A 0x1C20012 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__A 0x1C20013 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__A 0x1C20014 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__A 0x1C20015 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__A 0x1C20016 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__A 0x1C20017 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__A 0x1C20018 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__A 0x1C20019 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__A 0x1C2001A +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__A 0x1C2001B +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__A 0x1C2001C +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__A 0x1C2001D +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__A 0x1C2001E +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__A 0x1C2001F +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__A 0x1C20020 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__A 0x1C20021 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__A 0x1C20022 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__A 0x1C20023 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__A 0x1C20024 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__A 0x1C20025 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__A 0x1C20026 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__A 0x1C20027 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__A 0x1C20028 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__A 0x1C20029 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__A 0x1C2002A +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__A 0x1C2002B +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__A 0x1C2002C +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__A 0x1C2002D +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__A 0x1C2002E +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__A 0x1C2002F +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__A 0x1C20030 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__A 0x1C20031 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__A 0x1C20032 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__A 0x1C20033 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__A 0x1C20034 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__A 0x1C20035 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__A 0x1C20036 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__A 0x1C20037 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__A 0x1C20038 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__A 0x1C20039 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__A 0x1C2003A +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__A 0x1C2003B +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__A 0x1C2003C +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__A 0x1C2003D +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__A 0x1C2003E +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__A 0x1C2003F +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__A 0x1C20040 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__A 0x1C20041 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__A 0x1C20042 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__A 0x1C20043 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__A 0x1C20044 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__A 0x1C20045 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__A 0x1C20046 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__A 0x1C20047 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__A 0x1C20048 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__A 0x1C20049 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__A 0x1C2004A +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__A 0x1C2004B +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__A 0x1C2004C +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__A 0x1C2004D +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__A 0x1C2004E +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__A 0x1C2004F +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__A 0x1C20050 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__A 0x1C20051 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__A 0x1C20052 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__A 0x1C20053 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__A 0x1C20054 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__A 0x1C20055 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__A 0x1C20056 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__A 0x1C20057 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__A 0x1C20058 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__A 0x1C20059 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__A 0x1C2005A +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__A 0x1C2005B +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__A 0x1C2005C +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__A 0x1C2005D +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__A 0x1C2005E +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__A 0x1C2005F +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__A 0x1C20060 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__A 0x1C20061 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__A 0x1C20062 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__A 0x1C20063 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__A 0x1C20064 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__A 0x1C20065 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__A 0x1C20066 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__A 0x1C20067 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__A 0x1C20068 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__A 0x1C20069 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__A 0x1C2006A +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__A 0x1C2006B +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__W 12 +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__M 0xFFF +#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__A 0x1C2006C +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__A 0x1C2006D +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__A 0x1C2006E +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__A 0x1C2006F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__A 0x1C20070 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__A 0x1C20071 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__A 0x1C20072 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__A 0x1C20073 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__A 0x1C20074 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__A 0x1C20075 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__A 0x1C20076 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__A 0x1C20077 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__PRE 0x0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__A 0x1C20078 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__A 0x1C20079 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__A 0x1C2007A +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__A 0x1C2007B +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__A 0x1C2007C +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__A 0x1C2007D +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__A 0x1C2007E +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__A 0x1C2007F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__W 15 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A 0x1C30000 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__A 0x1C30001 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__A 0x1C30002 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__A 0x1C30003 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__A 0x1C30004 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__A 0x1C30005 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__A 0x1C30006 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__A 0x1C30007 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__A 0x1C30008 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__A 0x1C30009 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__A 0x1C3000A +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__A 0x1C3000B +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__A 0x1C3000C +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__A 0x1C3000D +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__A 0x1C3000E +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__A 0x1C3000F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__A 0x1C30010 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__A 0x1C30011 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__A 0x1C30012 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__A 0x1C30013 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__A 0x1C30014 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__A 0x1C30015 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__A 0x1C30016 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__A 0x1C30017 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__A 0x1C30018 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__A 0x1C30019 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__A 0x1C3001A +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__A 0x1C3001B +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__A 0x1C3001C +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__A 0x1C3001D +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__A 0x1C3001E +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__A 0x1C3001F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__A 0x1C30020 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__A 0x1C30021 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__A 0x1C30022 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__A 0x1C30023 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__A 0x1C30024 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__A 0x1C30025 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__A 0x1C30026 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__A 0x1C30027 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__W 15 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__M 0x7FFF +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__B 0 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__M 0x7F +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__B 8 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__W 7 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__M 0x7F00 +#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__A 0x1C30028 +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__A 0x1C30029 +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__A 0x1C3002A +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__A 0x1C3002B +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__A 0x1C3002C +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__A 0x1C3002D +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__A 0x1C3002E +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__A 0x1C3002F +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__A 0x1C30030 +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__W 12 +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__M 0xFFF +#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__A 0x1C30031 +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__PRE 0x0 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__A 0x1C30032 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__A 0x1C30033 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__A 0x1C30034 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__A 0x1C30035 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__W 15 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__M 0x7FFF +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__B 0 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__M 0x7F +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__PRE 0x0 + +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__B 8 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__W 7 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__M 0x7F00 +#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__PRE 0x0 + +#define VSB_TCMEQ_RAM__A 0x1C40000 + +#define VSB_TCMEQ_RAM_TCMEQ_RAM__B 0 +#define VSB_TCMEQ_RAM_TCMEQ_RAM__W 16 +#define VSB_TCMEQ_RAM_TCMEQ_RAM__M 0xFFFF +#define VSB_TCMEQ_RAM_TCMEQ_RAM__PRE 0x0 + +#define VSB_FCPRE_RAM__A 0x1C50000 + +#define VSB_FCPRE_RAM_FCPRE_RAM__B 0 +#define VSB_FCPRE_RAM_FCPRE_RAM__W 16 +#define VSB_FCPRE_RAM_FCPRE_RAM__M 0xFFFF +#define VSB_FCPRE_RAM_FCPRE_RAM__PRE 0x0 + +#define VSB_EQTAP_RAM__A 0x1C60000 + +#define VSB_EQTAP_RAM_EQTAP_RAM__B 0 +#define VSB_EQTAP_RAM_EQTAP_RAM__W 12 +#define VSB_EQTAP_RAM_EQTAP_RAM__M 0xFFF +#define VSB_EQTAP_RAM_EQTAP_RAM__PRE 0x0 + +#endif |