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Diffstat (limited to '')
-rw-r--r-- | drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h new file mode 100644 index 000000000..dee670b66 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_EML_FUNNEL + * (Prototype: FUNNEL_2X1) + ***************************************** + */ + +#define mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG 0x6000 + +#define mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG 0x6004 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 0x6EEC + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 0x6EF0 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 0x6EF4 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 0x6EF8 + +#define mmDCORE0_TPC0_EML_FUNNEL_ITCTRL 0x6F00 + +#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET 0x6FA0 + +#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR 0x6FA4 + +#define mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS 0x6FB0 + +#define mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS 0x6FB4 + +#define mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS 0x6FB8 + +#define mmDCORE0_TPC0_EML_FUNNEL_DEVID 0x6FC8 + +#define mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE 0x6FCC + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR4 0x6FD0 + +#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 0x6FD4 + +#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 0x6FD8 + +#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 0x6FDC + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR0 0x6FE0 + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR1 0x6FE4 + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR2 0x6FE8 + +#define mmDCORE0_TPC0_EML_FUNNEL_PIDR3 0x6FEC + +#define mmDCORE0_TPC0_EML_FUNNEL_CID0 0x6FF0 + +#define mmDCORE0_TPC0_EML_FUNNEL_CID1 0x6FF4 + +#define mmDCORE0_TPC0_EML_FUNNEL_CID2 0x6FF8 + +#define mmDCORE0_TPC0_EML_FUNNEL_CID3 0x6FFC + +#endif /* ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ */ |