diff options
Diffstat (limited to 'drivers/pinctrl/spear')
| -rw-r--r-- | drivers/pinctrl/spear/Kconfig | 57 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/Makefile | 11 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-plgpio.c | 737 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear.c | 409 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear.h | 455 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear1310.c | 2718 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear1340.c | 2034 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear300.c | 685 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear310.c | 408 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear320.c | 3449 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear3xx.c | 524 | ||||
| -rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear3xx.h | 93 |
12 files changed, 11580 insertions, 0 deletions
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig new file mode 100644 index 000000000..98f5a84cc --- /dev/null +++ b/drivers/pinctrl/spear/Kconfig @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# ST Microelectronics SPEAr PINCTRL drivers +# + +if PLAT_SPEAR + +config PINCTRL_SPEAR + bool + depends on OF + select PINMUX + help + This enables pin control drivers for SPEAr Platform + +config PINCTRL_SPEAR3XX + bool + depends on ARCH_SPEAR3XX + select PINCTRL_SPEAR + +config PINCTRL_SPEAR300 + bool "ST Microelectronics SPEAr300 SoC pin controller driver" + depends on MACH_SPEAR300 + select PINCTRL_SPEAR3XX + +config PINCTRL_SPEAR310 + bool "ST Microelectronics SPEAr310 SoC pin controller driver" + depends on MACH_SPEAR310 + select PINCTRL_SPEAR3XX + select PINCTRL_SPEAR_PLGPIO + +config PINCTRL_SPEAR320 + bool "ST Microelectronics SPEAr320 SoC pin controller driver" + depends on MACH_SPEAR320 + select PINCTRL_SPEAR3XX + select PINCTRL_SPEAR_PLGPIO + +config PINCTRL_SPEAR1310 + bool "ST Microelectronics SPEAr1310 SoC pin controller driver" + depends on MACH_SPEAR1310 + select PINCTRL_SPEAR + select PINCTRL_SPEAR_PLGPIO + +config PINCTRL_SPEAR1340 + bool "ST Microelectronics SPEAr1340 SoC pin controller driver" + depends on MACH_SPEAR1340 + select PINCTRL_SPEAR + select PINCTRL_SPEAR_PLGPIO + +config PINCTRL_SPEAR_PLGPIO + bool "SPEAr SoC PLGPIO Controller" + depends on GPIOLIB && PINCTRL_SPEAR + select GPIOLIB_IRQCHIP + help + Say yes here to support PLGPIO controller on ST Microelectronics SPEAr + SoCs. + +endif diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile new file mode 100644 index 000000000..da52d1755 --- /dev/null +++ b/drivers/pinctrl/spear/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +# SPEAr pinmux support + +obj-$(CONFIG_PINCTRL_SPEAR_PLGPIO) += pinctrl-plgpio.o +obj-y += pinctrl-spear.o +obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o +obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o +obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o +obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o +obj-$(CONFIG_PINCTRL_SPEAR1310) += pinctrl-spear1310.o +obj-$(CONFIG_PINCTRL_SPEAR1340) += pinctrl-spear1340.o diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c new file mode 100644 index 000000000..ada401ef4 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -0,0 +1,737 @@ +/* + * SPEAr platform PLGPIO driver + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@linaro.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/pinctrl/consumer.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/regmap.h> +#include <linux/spinlock.h> + +#define MAX_GPIO_PER_REG 32 +#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) +#define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ + * sizeof(int *)) + +/* + * plgpio pins in all machines are not one to one mapped, bitwise with registers + * bits. These set of macros define register masks for which below functions + * (pin_to_offset and offset_to_pin) are required to be called. + */ +#define PTO_ENB_REG 0x001 +#define PTO_WDATA_REG 0x002 +#define PTO_DIR_REG 0x004 +#define PTO_IE_REG 0x008 +#define PTO_RDATA_REG 0x010 +#define PTO_MIS_REG 0x020 + +struct plgpio_regs { + u32 enb; /* enable register */ + u32 wdata; /* write data register */ + u32 dir; /* direction set register */ + u32 rdata; /* read data register */ + u32 ie; /* interrupt enable register */ + u32 mis; /* mask interrupt status register */ + u32 eit; /* edge interrupt type */ +}; + +/* + * struct plgpio: plgpio driver specific structure + * + * lock: lock for guarding gpio registers + * base: base address of plgpio block + * chip: gpio framework specific chip information structure + * p2o: function ptr for pin to offset conversion. This is required only for + * machines where mapping b/w pin and offset is not 1-to-1. + * o2p: function ptr for offset to pin conversion. This is required only for + * machines where mapping b/w pin and offset is not 1-to-1. + * p2o_regs: mask of registers for which p2o and o2p are applicable + * regs: register offsets + * csave_regs: context save registers for standby/sleep/hibernate cases + */ +struct plgpio { + spinlock_t lock; + struct regmap *regmap; + struct clk *clk; + struct gpio_chip chip; + int (*p2o)(int pin); /* pin_to_offset */ + int (*o2p)(int offset); /* offset_to_pin */ + u32 p2o_regs; + struct plgpio_regs regs; +#ifdef CONFIG_PM_SLEEP + struct plgpio_regs *csave_regs; +#endif +}; + +/* register manipulation inline functions */ +static inline u32 is_plgpio_set(struct regmap *regmap, u32 pin, u32 reg) +{ + u32 offset = PIN_OFFSET(pin); + u32 reg_off = REG_OFFSET(0, reg, pin); + u32 val; + + regmap_read(regmap, reg_off, &val); + + return !!(val & (1 << offset)); +} + +static inline void plgpio_reg_set(struct regmap *regmap, u32 pin, u32 reg) +{ + u32 offset = PIN_OFFSET(pin); + u32 reg_off = REG_OFFSET(0, reg, pin); + u32 mask; + + mask = 1 << offset; + regmap_update_bits(regmap, reg_off, mask, mask); +} + +static inline void plgpio_reg_reset(struct regmap *regmap, u32 pin, u32 reg) +{ + u32 offset = PIN_OFFSET(pin); + u32 reg_off = REG_OFFSET(0, reg, pin); + u32 mask; + + mask = 1 << offset; + regmap_update_bits(regmap, reg_off, mask, 0); +} + + +/* gpio framework specific routines */ +static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct plgpio *plgpio = gpiochip_get_data(chip); + unsigned long flags; + + /* get correct offset for "offset" pin */ + if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) { + offset = plgpio->p2o(offset); + if (offset == -1) + return -EINVAL; + } + + spin_lock_irqsave(&plgpio->lock, flags); + plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.dir); + spin_unlock_irqrestore(&plgpio->lock, flags); + + return 0; +} + +static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct plgpio *plgpio = gpiochip_get_data(chip); + unsigned long flags; + unsigned dir_offset = offset, wdata_offset = offset, tmp; + + /* get correct offset for "offset" pin */ + if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) { + tmp = plgpio->p2o(offset); + if (tmp == -1) + return -EINVAL; + + if (plgpio->p2o_regs & PTO_DIR_REG) + dir_offset = tmp; + if (plgpio->p2o_regs & PTO_WDATA_REG) + wdata_offset = tmp; + } + + spin_lock_irqsave(&plgpio->lock, flags); + if (value) + plgpio_reg_set(plgpio->regmap, wdata_offset, + plgpio->regs.wdata); + else + plgpio_reg_reset(plgpio->regmap, wdata_offset, + plgpio->regs.wdata); + + plgpio_reg_reset(plgpio->regmap, dir_offset, plgpio->regs.dir); + spin_unlock_irqrestore(&plgpio->lock, flags); + + return 0; +} + +static int plgpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + struct plgpio *plgpio = gpiochip_get_data(chip); + + if (offset >= chip->ngpio) + return -EINVAL; + + /* get correct offset for "offset" pin */ + if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) { + offset = plgpio->p2o(offset); + if (offset == -1) + return -EINVAL; + } + + return is_plgpio_set(plgpio->regmap, offset, plgpio->regs.rdata); +} + +static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value) +{ + struct plgpio *plgpio = gpiochip_get_data(chip); + + if (offset >= chip->ngpio) + return; + + /* get correct offset for "offset" pin */ + if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) { + offset = plgpio->p2o(offset); + if (offset == -1) + return; + } + + if (value) + plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.wdata); + else + plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.wdata); +} + +static int plgpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct plgpio *plgpio = gpiochip_get_data(chip); + int gpio = chip->base + offset; + unsigned long flags; + int ret = 0; + + if (offset >= chip->ngpio) + return -EINVAL; + + ret = pinctrl_gpio_request(gpio); + if (ret) + return ret; + + if (!IS_ERR(plgpio->clk)) { + ret = clk_enable(plgpio->clk); + if (ret) + goto err0; + } + + if (plgpio->regs.enb == -1) + return 0; + + /* + * put gpio in IN mode before enabling it. This make enabling gpio safe + */ + ret = plgpio_direction_input(chip, offset); + if (ret) + goto err1; + + /* get correct offset for "offset" pin */ + if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) { + offset = plgpio->p2o(offset); + if (offset == -1) { + ret = -EINVAL; + goto err1; + } + } + + spin_lock_irqsave(&plgpio->lock, flags); + plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.enb); + spin_unlock_irqrestore(&plgpio->lock, flags); + return 0; + +err1: + if (!IS_ERR(plgpio->clk)) + clk_disable(plgpio->clk); +err0: + pinctrl_gpio_free(gpio); + return ret; +} + +static void plgpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct plgpio *plgpio = gpiochip_get_data(chip); + int gpio = chip->base + offset; + unsigned long flags; + + if (offset >= chip->ngpio) + return; + + if (plgpio->regs.enb == -1) + goto disable_clk; + + /* get correct offset for "offset" pin */ + if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) { + offset = plgpio->p2o(offset); + if (offset == -1) + return; + } + + spin_lock_irqsave(&plgpio->lock, flags); + plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.enb); + spin_unlock_irqrestore(&plgpio->lock, flags); + +disable_clk: + if (!IS_ERR(plgpio->clk)) + clk_disable(plgpio->clk); + + pinctrl_gpio_free(gpio); +} + +/* PLGPIO IRQ */ +static void plgpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct plgpio *plgpio = gpiochip_get_data(gc); + int offset = d->hwirq; + unsigned long flags; + + /* get correct offset for "offset" pin */ + if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) { + offset = plgpio->p2o(offset); + if (offset == -1) + return; + } + + spin_lock_irqsave(&plgpio->lock, flags); + plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.ie); + spin_unlock_irqrestore(&plgpio->lock, flags); +} + +static void plgpio_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct plgpio *plgpio = gpiochip_get_data(gc); + int offset = d->hwirq; + unsigned long flags; + + /* get correct offset for "offset" pin */ + if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) { + offset = plgpio->p2o(offset); + if (offset == -1) + return; + } + + spin_lock_irqsave(&plgpio->lock, flags); + plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.ie); + spin_unlock_irqrestore(&plgpio->lock, flags); +} + +static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct plgpio *plgpio = gpiochip_get_data(gc); + int offset = d->hwirq; + u32 reg_off; + unsigned int supported_type = 0, val; + + if (offset >= plgpio->chip.ngpio) + return -EINVAL; + + if (plgpio->regs.eit == -1) + supported_type = IRQ_TYPE_LEVEL_HIGH; + else + supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + + if (!(trigger & supported_type)) + return -EINVAL; + + if (plgpio->regs.eit == -1) + return 0; + + reg_off = REG_OFFSET(0, plgpio->regs.eit, offset); + regmap_read(plgpio->regmap, reg_off, &val); + + offset = PIN_OFFSET(offset); + if (trigger & IRQ_TYPE_EDGE_RISING) + regmap_write(plgpio->regmap, reg_off, val | (1 << offset)); + else + regmap_write(plgpio->regmap, reg_off, val & ~(1 << offset)); + + return 0; +} + +static struct irq_chip plgpio_irqchip = { + .name = "PLGPIO", + .irq_enable = plgpio_irq_enable, + .irq_disable = plgpio_irq_disable, + .irq_set_type = plgpio_irq_set_type, +}; + +static void plgpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct plgpio *plgpio = gpiochip_get_data(gc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); + int regs_count, count, pin, offset, i = 0; + u32 pending; + unsigned long pendingl; + + count = plgpio->chip.ngpio; + regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG); + + chained_irq_enter(irqchip, desc); + /* check all plgpio MIS registers for a possible interrupt */ + for (; i < regs_count; i++) { + regmap_read(plgpio->regmap, plgpio->regs.mis + + i * sizeof(int *), &pending); + if (!pending) + continue; + + /* clear interrupts */ + regmap_write(plgpio->regmap, plgpio->regs.mis + + i * sizeof(int *), ~pending); + /* + * clear extra bits in last register having gpios < MAX/REG + * ex: Suppose there are max 102 plgpios. then last register + * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits + * so, we must not take other 28 bits into consideration for + * checking interrupt. so clear those bits. + */ + count = count - i * MAX_GPIO_PER_REG; + if (count < MAX_GPIO_PER_REG) + pending &= (1 << count) - 1; + + pendingl = pending; + for_each_set_bit(offset, &pendingl, MAX_GPIO_PER_REG) { + /* get correct pin for "offset" */ + if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) { + pin = plgpio->o2p(offset); + if (pin == -1) + continue; + } else + pin = offset; + + /* get correct irq line number */ + pin = i * MAX_GPIO_PER_REG + pin; + generic_handle_domain_irq(gc->irq.domain, pin); + } + } + chained_irq_exit(irqchip, desc); +} + +/* + * pin to offset and offset to pin converter functions + * + * In spear310 there is inconsistency among bit positions in plgpio regiseters, + * for different plgpio pins. For example: for pin 27, bit offset is 23, pin + * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1 + */ +static int spear310_p2o(int pin) +{ + int offset = pin; + + if (pin <= 27) + offset += 4; + else if (pin <= 33) + offset = -1; + else if (pin <= 97) + offset -= 2; + else if (pin <= 101) + offset = 101 - pin; + else + offset = -1; + + return offset; +} + +static int spear310_o2p(int offset) +{ + if (offset <= 3) + return 101 - offset; + else if (offset <= 31) + return offset - 4; + else + return offset + 2; +} + +static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio) +{ + struct device_node *np = pdev->dev.of_node; + int ret = -EINVAL; + u32 val; + + if (of_machine_is_compatible("st,spear310")) { + plgpio->p2o = spear310_p2o; + plgpio->o2p = spear310_o2p; + plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG | + PTO_RDATA_REG | PTO_MIS_REG; + } + + if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) { + plgpio->chip.ngpio = val; + } else { + dev_err(&pdev->dev, "DT: Invalid ngpio field\n"); + goto end; + } + + if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val)) + plgpio->regs.enb = val; + else + plgpio->regs.enb = -1; + + if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) { + plgpio->regs.wdata = val; + } else { + dev_err(&pdev->dev, "DT: Invalid wdata reg\n"); + goto end; + } + + if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) { + plgpio->regs.dir = val; + } else { + dev_err(&pdev->dev, "DT: Invalid dir reg\n"); + goto end; + } + + if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) { + plgpio->regs.ie = val; + } else { + dev_err(&pdev->dev, "DT: Invalid ie reg\n"); + goto end; + } + + if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) { + plgpio->regs.rdata = val; + } else { + dev_err(&pdev->dev, "DT: Invalid rdata reg\n"); + goto end; + } + + if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) { + plgpio->regs.mis = val; + } else { + dev_err(&pdev->dev, "DT: Invalid mis reg\n"); + goto end; + } + + if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val)) + plgpio->regs.eit = val; + else + plgpio->regs.eit = -1; + + return 0; + +end: + return ret; +} + +static int plgpio_probe(struct platform_device *pdev) +{ + struct device_node *regmap_np; + struct plgpio *plgpio; + int ret, irq; + + plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); + if (!plgpio) + return -ENOMEM; + + regmap_np = of_parse_phandle(pdev->dev.of_node, "regmap", 0); + if (regmap_np) { + plgpio->regmap = device_node_to_regmap(regmap_np); + of_node_put(regmap_np); + if (IS_ERR(plgpio->regmap)) { + dev_err(&pdev->dev, "Retrieve regmap failed (%pe)\n", + plgpio->regmap); + return PTR_ERR(plgpio->regmap); + } + } else { + plgpio->regmap = device_node_to_regmap(pdev->dev.of_node); + if (IS_ERR(plgpio->regmap)) { + dev_err(&pdev->dev, "Init regmap failed (%pe)\n", + plgpio->regmap); + return PTR_ERR(plgpio->regmap); + } + } + + ret = plgpio_probe_dt(pdev, plgpio); + if (ret) { + dev_err(&pdev->dev, "DT probe failed\n"); + return ret; + } + + plgpio->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(plgpio->clk)) + dev_warn(&pdev->dev, "clk_get() failed, work without it\n"); + +#ifdef CONFIG_PM_SLEEP + plgpio->csave_regs = devm_kcalloc(&pdev->dev, + DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG), + sizeof(*plgpio->csave_regs), + GFP_KERNEL); + if (!plgpio->csave_regs) + return -ENOMEM; +#endif + + platform_set_drvdata(pdev, plgpio); + spin_lock_init(&plgpio->lock); + + plgpio->chip.base = -1; + plgpio->chip.request = plgpio_request; + plgpio->chip.free = plgpio_free; + plgpio->chip.direction_input = plgpio_direction_input; + plgpio->chip.direction_output = plgpio_direction_output; + plgpio->chip.get = plgpio_get_value; + plgpio->chip.set = plgpio_set_value; + plgpio->chip.label = dev_name(&pdev->dev); + plgpio->chip.parent = &pdev->dev; + plgpio->chip.owner = THIS_MODULE; + + if (!IS_ERR(plgpio->clk)) { + ret = clk_prepare(plgpio->clk); + if (ret) { + dev_err(&pdev->dev, "clk prepare failed\n"); + return ret; + } + } + + irq = platform_get_irq(pdev, 0); + if (irq > 0) { + struct gpio_irq_chip *girq; + + girq = &plgpio->chip.irq; + girq->chip = &plgpio_irqchip; + girq->parent_handler = plgpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + dev_info(&pdev->dev, "PLGPIO registering with IRQs\n"); + } else { + dev_info(&pdev->dev, "PLGPIO registering without IRQs\n"); + } + + ret = gpiochip_add_data(&plgpio->chip, plgpio); + if (ret) { + dev_err(&pdev->dev, "unable to add gpio chip\n"); + goto unprepare_clk; + } + + return 0; + +unprepare_clk: + if (!IS_ERR(plgpio->clk)) + clk_unprepare(plgpio->clk); + + return ret; +} + +#ifdef CONFIG_PM_SLEEP +static int plgpio_suspend(struct device *dev) +{ + struct plgpio *plgpio = dev_get_drvdata(dev); + int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); + u32 off; + + for (i = 0; i < reg_count; i++) { + off = i * sizeof(int *); + + if (plgpio->regs.enb != -1) + regmap_read(plgpio->regmap, plgpio->regs.enb + off, + &plgpio->csave_regs[i].enb); + if (plgpio->regs.eit != -1) + regmap_read(plgpio->regmap, plgpio->regs.eit + off, + &plgpio->csave_regs[i].eit); + regmap_read(plgpio->regmap, plgpio->regs.wdata + off, + &plgpio->csave_regs[i].wdata); + regmap_read(plgpio->regmap, plgpio->regs.dir + off, + &plgpio->csave_regs[i].dir); + regmap_read(plgpio->regmap, plgpio->regs.ie + off, + &plgpio->csave_regs[i].ie); + } + + return 0; +} + +/* + * This is used to correct the values in end registers. End registers contain + * extra bits that might be used for other purpose in platform. So, we shouldn't + * overwrite these bits. This macro, reads given register again, preserves other + * bit values (non-plgpio bits), and retain captured value (plgpio bits). + */ +#define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \ +{ \ + regmap_read(plgpio->regmap, plgpio->regs.__reg + _off, &_tmp); \ + _tmp &= ~_mask; \ + plgpio->csave_regs[i].__reg = \ + _tmp | (plgpio->csave_regs[i].__reg & _mask); \ +} + +static int plgpio_resume(struct device *dev) +{ + struct plgpio *plgpio = dev_get_drvdata(dev); + int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); + u32 off; + u32 mask, tmp; + + for (i = 0; i < reg_count; i++) { + off = i * sizeof(int *); + + if (i == reg_count - 1) { + mask = (1 << (plgpio->chip.ngpio - i * + MAX_GPIO_PER_REG)) - 1; + + if (plgpio->regs.enb != -1) + plgpio_prepare_reg(enb, off, mask, tmp); + + if (plgpio->regs.eit != -1) + plgpio_prepare_reg(eit, off, mask, tmp); + + plgpio_prepare_reg(wdata, off, mask, tmp); + plgpio_prepare_reg(dir, off, mask, tmp); + plgpio_prepare_reg(ie, off, mask, tmp); + } + + regmap_write(plgpio->regmap, plgpio->regs.wdata + off, + plgpio->csave_regs[i].wdata); + + regmap_write(plgpio->regmap, plgpio->regs.dir + off, + plgpio->csave_regs[i].dir); + + if (plgpio->regs.eit != -1) + regmap_write(plgpio->regmap, plgpio->regs.eit + off, + plgpio->csave_regs[i].eit); + + regmap_write(plgpio->regmap, plgpio->regs.ie + off, + plgpio->csave_regs[i].ie); + + if (plgpio->regs.enb != -1) + regmap_write(plgpio->regmap, plgpio->regs.enb + off, + plgpio->csave_regs[i].enb); + } + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume); + +static const struct of_device_id plgpio_of_match[] = { + { .compatible = "st,spear-plgpio" }, + {} +}; + +static struct platform_driver plgpio_driver = { + .probe = plgpio_probe, + .driver = { + .name = "spear-plgpio", + .pm = &plgpio_dev_pm_ops, + .of_match_table = plgpio_of_match, + }, +}; + +static int __init plgpio_init(void) +{ + return platform_driver_register(&plgpio_driver); +} +subsys_initcall(plgpio_init); diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c new file mode 100644 index 000000000..e0543c1ad --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -0,0 +1,409 @@ +/* + * Driver for the ST Microelectronics SPEAr pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <vireshk@kernel.org> + * + * Inspired from: + * - U300 Pinctl drivers + * - Tegra Pinctl drivers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_gpio.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "pinctrl-spear.h" + +#define DRIVER_NAME "spear-pinmux" + +static void muxregs_endisable(struct spear_pmx *pmx, + struct spear_muxreg *muxregs, u8 count, bool enable) +{ + struct spear_muxreg *muxreg; + u32 val, temp, j; + + for (j = 0; j < count; j++) { + muxreg = &muxregs[j]; + + val = pmx_readl(pmx, muxreg->reg); + val &= ~muxreg->mask; + + if (enable) + temp = muxreg->val; + else + temp = ~muxreg->val; + + val |= muxreg->mask & temp; + pmx_writel(pmx, val, muxreg->reg); + } +} + +static int set_mode(struct spear_pmx *pmx, int mode) +{ + struct spear_pmx_mode *pmx_mode = NULL; + int i; + u32 val; + + if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes) + return -EINVAL; + + for (i = 0; i < pmx->machdata->npmx_modes; i++) { + if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) { + pmx_mode = pmx->machdata->pmx_modes[i]; + break; + } + } + + if (!pmx_mode) + return -EINVAL; + + val = pmx_readl(pmx, pmx_mode->reg); + val &= ~pmx_mode->mask; + val |= pmx_mode->val; + pmx_writel(pmx, val, pmx_mode->reg); + + pmx->machdata->mode = pmx_mode->mode; + dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n", + pmx_mode->name ? pmx_mode->name : "no_name", + pmx_mode->reg); + + return 0; +} + +void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup, + unsigned count, u16 reg) +{ + int i, j; + + for (i = 0; i < count; i++) + for (j = 0; j < gpio_pingroup[i].nmuxregs; j++) + gpio_pingroup[i].muxregs[j].reg = reg; +} + +void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg) +{ + struct spear_pingroup *pgroup; + struct spear_modemux *modemux; + int i, j, group; + + for (group = 0; group < machdata->ngroups; group++) { + pgroup = machdata->groups[group]; + + for (i = 0; i < pgroup->nmodemuxs; i++) { + modemux = &pgroup->modemuxs[i]; + + for (j = 0; j < modemux->nmuxregs; j++) + if (modemux->muxregs[j].reg == 0xFFFF) + modemux->muxregs[j].reg = reg; + } + } +} + +static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->machdata->ngroups; +} + +static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->machdata->groups[group]->name; +} + +static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, unsigned *num_pins) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + *pins = pmx->machdata->groups[group]->pins; + *num_pins = pmx->machdata->groups[group]->npins; + + return 0; +} + +static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +static int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct device_node *np; + struct property *prop; + const char *function, *group; + int ret, index = 0, count = 0; + + /* calculate number of maps required */ + for_each_child_of_node(np_config, np) { + ret = of_property_read_string(np, "st,function", &function); + if (ret < 0) { + of_node_put(np); + return ret; + } + + ret = of_property_count_strings(np, "st,pins"); + if (ret < 0) { + of_node_put(np); + return ret; + } + + count += ret; + } + + if (!count) { + dev_err(pmx->dev, "No child nodes passed via DT\n"); + return -ENODEV; + } + + *map = kcalloc(count, sizeof(**map), GFP_KERNEL); + if (!*map) + return -ENOMEM; + + for_each_child_of_node(np_config, np) { + of_property_read_string(np, "st,function", &function); + of_property_for_each_string(np, "st,pins", prop, group) { + (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[index].data.mux.group = group; + (*map)[index].data.mux.function = function; + index++; + } + } + + *num_maps = count; + + return 0; +} + +static void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops spear_pinctrl_ops = { + .get_groups_count = spear_pinctrl_get_groups_cnt, + .get_group_name = spear_pinctrl_get_group_name, + .get_group_pins = spear_pinctrl_get_group_pins, + .pin_dbg_show = spear_pinctrl_pin_dbg_show, + .dt_node_to_map = spear_pinctrl_dt_node_to_map, + .dt_free_map = spear_pinctrl_dt_free_map, +}; + +static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->machdata->nfunctions; +} + +static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->machdata->functions[function]->name; +} + +static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, const char *const **groups, + unsigned * const ngroups) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + *groups = pmx->machdata->functions[function]->groups; + *ngroups = pmx->machdata->functions[function]->ngroups; + + return 0; +} + +static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, + unsigned function, unsigned group, bool enable) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct spear_pingroup *pgroup; + const struct spear_modemux *modemux; + int i; + bool found = false; + + pgroup = pmx->machdata->groups[group]; + + for (i = 0; i < pgroup->nmodemuxs; i++) { + modemux = &pgroup->modemuxs[i]; + + /* SoC have any modes */ + if (pmx->machdata->modes_supported) { + if (!(pmx->machdata->mode & modemux->modes)) + continue; + } + + found = true; + muxregs_endisable(pmx, modemux->muxregs, modemux->nmuxregs, + enable); + } + + if (!found) { + dev_err(pmx->dev, "pinmux group: %s not supported\n", + pgroup->name); + return -ENODEV; + } + + return 0; +} + +static int spear_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + return spear_pinctrl_endisable(pctldev, function, group, true); +} + +/* gpio with pinmux */ +static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx, + unsigned pin) +{ + struct spear_gpio_pingroup *gpio_pingroup; + int i, j; + + if (!pmx->machdata->gpio_pingroups) + return NULL; + + for (i = 0; i < pmx->machdata->ngpio_pingroups; i++) { + gpio_pingroup = &pmx->machdata->gpio_pingroups[i]; + + for (j = 0; j < gpio_pingroup->npins; j++) { + if (gpio_pingroup->pins[j] == pin) + return gpio_pingroup; + } + } + + return NULL; +} + +static int gpio_request_endisable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned offset, bool enable) +{ + struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct spear_pinctrl_machdata *machdata = pmx->machdata; + struct spear_gpio_pingroup *gpio_pingroup; + + /* + * Some SoC have configuration options applicable to group of pins, + * rather than a single pin. + */ + gpio_pingroup = get_gpio_pingroup(pmx, offset); + if (gpio_pingroup) + muxregs_endisable(pmx, gpio_pingroup->muxregs, + gpio_pingroup->nmuxregs, enable); + + /* + * SoC may need some extra configurations, or configurations for single + * pin + */ + if (machdata->gpio_request_endisable) + machdata->gpio_request_endisable(pmx, offset, enable); + + return 0; +} + +static int gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned offset) +{ + return gpio_request_endisable(pctldev, range, offset, true); +} + +static void gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned offset) +{ + gpio_request_endisable(pctldev, range, offset, false); +} + +static const struct pinmux_ops spear_pinmux_ops = { + .get_functions_count = spear_pinctrl_get_funcs_count, + .get_function_name = spear_pinctrl_get_func_name, + .get_function_groups = spear_pinctrl_get_func_groups, + .set_mux = spear_pinctrl_set_mux, + .gpio_request_enable = gpio_request_enable, + .gpio_disable_free = gpio_disable_free, +}; + +static struct pinctrl_desc spear_pinctrl_desc = { + .name = DRIVER_NAME, + .pctlops = &spear_pinctrl_ops, + .pmxops = &spear_pinmux_ops, + .owner = THIS_MODULE, +}; + +int spear_pinctrl_probe(struct platform_device *pdev, + struct spear_pinctrl_machdata *machdata) +{ + struct device_node *np = pdev->dev.of_node; + struct spear_pmx *pmx; + + if (!machdata) + return -ENODEV; + + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->regmap = device_node_to_regmap(np); + if (IS_ERR(pmx->regmap)) { + dev_err(&pdev->dev, "Init regmap failed (%pe).\n", + pmx->regmap); + return PTR_ERR(pmx->regmap); + } + + pmx->dev = &pdev->dev; + pmx->machdata = machdata; + + /* configure mode, if supported by SoC */ + if (machdata->modes_supported) { + int mode = 0; + + if (of_property_read_u32(np, "st,pinmux-mode", &mode)) { + dev_err(&pdev->dev, "OF: pinmux mode not passed\n"); + return -EINVAL; + } + + if (set_mode(pmx, mode)) { + dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n", + mode); + return -EINVAL; + } + } + + platform_set_drvdata(pdev, pmx); + + spear_pinctrl_desc.pins = machdata->pins; + spear_pinctrl_desc.npins = machdata->npins; + + pmx->pctl = devm_pinctrl_register(&pdev->dev, &spear_pinctrl_desc, pmx); + if (IS_ERR(pmx->pctl)) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return PTR_ERR(pmx->pctl); + } + + return 0; +} diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h new file mode 100644 index 000000000..63a0b5ea5 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear.h @@ -0,0 +1,455 @@ +/* + * Driver header file for the ST Microelectronics SPEAr pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <vireshk@kernel.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PINMUX_SPEAR_H__ +#define __PINMUX_SPEAR_H__ + +#include <linux/gpio/driver.h> +#include <linux/io.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/regmap.h> +#include <linux/types.h> + +struct platform_device; +struct device; +struct spear_pmx; + +/** + * struct spear_pmx_mode - SPEAr pmx mode + * @name: name of pmx mode + * @mode: mode id + * @reg: register for configuring this mode + * @mask: mask of this mode in reg + * @val: val to be configured at reg after doing (val & mask) + */ +struct spear_pmx_mode { + const char *const name; + u16 mode; + u16 reg; + u16 mask; + u32 val; +}; + +/** + * struct spear_muxreg - SPEAr mux reg configuration + * @reg: register offset + * @mask: mask bits + * @val: val to be written on mask bits + */ +struct spear_muxreg { + u16 reg; + u32 mask; + u32 val; +}; + +struct spear_gpio_pingroup { + const unsigned *pins; + unsigned npins; + struct spear_muxreg *muxregs; + u8 nmuxregs; +}; + +/* ste: set to enable */ +#define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \ +static struct spear_muxreg __pins##_muxregs[] = { \ + { \ + .reg = __muxreg, \ + .mask = __mask, \ + .val = __ste ? __mask : 0, \ + }, \ +} + +#define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \ +static struct spear_muxreg __pins##_muxregs[] = { \ + { \ + .reg = __muxreg1, \ + .mask = __mask, \ + .val = __ste1 ? __mask : 0, \ + }, { \ + .reg = __muxreg2, \ + .mask = __mask, \ + .val = __ste2 ? __mask : 0, \ + }, \ +} + +#define GPIO_PINGROUP(__pins) \ + { \ + .pins = __pins, \ + .npins = ARRAY_SIZE(__pins), \ + .muxregs = __pins##_muxregs, \ + .nmuxregs = ARRAY_SIZE(__pins##_muxregs), \ + } + +/** + * struct spear_modemux - SPEAr mode mux configuration + * @modes: mode ids supported by this group of muxregs + * @nmuxregs: number of muxreg configurations to be done for modes + * @muxregs: array of muxreg configurations to be done for modes + */ +struct spear_modemux { + u16 modes; + u8 nmuxregs; + struct spear_muxreg *muxregs; +}; + +/** + * struct spear_pingroup - SPEAr pin group configurations + * @name: name of pin group + * @pins: array containing pin numbers + * @npins: size of pins array + * @modemuxs: array of modemux configurations for this pin group + * @nmodemuxs: size of array modemuxs + * + * A representation of a group of pins in the SPEAr pin controller. Each group + * allows some parameter or parameters to be configured. + */ +struct spear_pingroup { + const char *name; + const unsigned *pins; + unsigned npins; + struct spear_modemux *modemuxs; + unsigned nmodemuxs; +}; + +/** + * struct spear_function - SPEAr pinctrl mux function + * @name: The name of the function, exported to pinctrl core. + * @groups: An array of pin groups that may select this function. + * @ngroups: The number of entries in @groups. + */ +struct spear_function { + const char *name; + const char *const *groups; + unsigned ngroups; +}; + +/** + * struct spear_pinctrl_machdata - SPEAr pin controller machine driver + * configuration + * @pins: An array describing all pins the pin controller affects. + * All pins which are also GPIOs must be listed first within the *array, + * and be numbered identically to the GPIO controller's *numbering. + * @npins: The numbmer of entries in @pins. + * @functions: An array describing all mux functions the SoC supports. + * @nfunctions: The numbmer of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The numbmer of entries in @groups. + * @gpio_pingroups: gpio pingroups + * @ngpio_pingroups: gpio pingroups count + * + * @modes_supported: Does SoC support modes + * @mode: mode configured from probe + * @pmx_modes: array of modes supported by SoC + * @npmx_modes: number of entries in pmx_modes. + */ +struct spear_pinctrl_machdata { + const struct pinctrl_pin_desc *pins; + unsigned npins; + struct spear_function **functions; + unsigned nfunctions; + struct spear_pingroup **groups; + unsigned ngroups; + struct spear_gpio_pingroup *gpio_pingroups; + void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset, + bool enable); + unsigned ngpio_pingroups; + + bool modes_supported; + u16 mode; + struct spear_pmx_mode **pmx_modes; + unsigned npmx_modes; +}; + +/** + * struct spear_pmx - SPEAr pinctrl mux + * @dev: pointer to struct dev of platform_device registered + * @pctl: pointer to struct pinctrl_dev + * @machdata: pointer to SoC or machine specific structure + * @regmap: regmap of pinmux controller + */ +struct spear_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + struct spear_pinctrl_machdata *machdata; + struct regmap *regmap; +}; + +/* exported routines */ +static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) +{ + u32 val; + + regmap_read(pmx->regmap, reg, &val); + return val; +} + +static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) +{ + regmap_write(pmx->regmap, reg, val); +} + +void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); +void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup, + unsigned count, u16 reg); +int spear_pinctrl_probe(struct platform_device *pdev, + struct spear_pinctrl_machdata *machdata); + +#define SPEAR_PIN_0_TO_101 \ + PINCTRL_PIN(0, "PLGPIO0"), \ + PINCTRL_PIN(1, "PLGPIO1"), \ + PINCTRL_PIN(2, "PLGPIO2"), \ + PINCTRL_PIN(3, "PLGPIO3"), \ + PINCTRL_PIN(4, "PLGPIO4"), \ + PINCTRL_PIN(5, "PLGPIO5"), \ + PINCTRL_PIN(6, "PLGPIO6"), \ + PINCTRL_PIN(7, "PLGPIO7"), \ + PINCTRL_PIN(8, "PLGPIO8"), \ + PINCTRL_PIN(9, "PLGPIO9"), \ + PINCTRL_PIN(10, "PLGPIO10"), \ + PINCTRL_PIN(11, "PLGPIO11"), \ + PINCTRL_PIN(12, "PLGPIO12"), \ + PINCTRL_PIN(13, "PLGPIO13"), \ + PINCTRL_PIN(14, "PLGPIO14"), \ + PINCTRL_PIN(15, "PLGPIO15"), \ + PINCTRL_PIN(16, "PLGPIO16"), \ + PINCTRL_PIN(17, "PLGPIO17"), \ + PINCTRL_PIN(18, "PLGPIO18"), \ + PINCTRL_PIN(19, "PLGPIO19"), \ + PINCTRL_PIN(20, "PLGPIO20"), \ + PINCTRL_PIN(21, "PLGPIO21"), \ + PINCTRL_PIN(22, "PLGPIO22"), \ + PINCTRL_PIN(23, "PLGPIO23"), \ + PINCTRL_PIN(24, "PLGPIO24"), \ + PINCTRL_PIN(25, "PLGPIO25"), \ + PINCTRL_PIN(26, "PLGPIO26"), \ + PINCTRL_PIN(27, "PLGPIO27"), \ + PINCTRL_PIN(28, "PLGPIO28"), \ + PINCTRL_PIN(29, "PLGPIO29"), \ + PINCTRL_PIN(30, "PLGPIO30"), \ + PINCTRL_PIN(31, "PLGPIO31"), \ + PINCTRL_PIN(32, "PLGPIO32"), \ + PINCTRL_PIN(33, "PLGPIO33"), \ + PINCTRL_PIN(34, "PLGPIO34"), \ + PINCTRL_PIN(35, "PLGPIO35"), \ + PINCTRL_PIN(36, "PLGPIO36"), \ + PINCTRL_PIN(37, "PLGPIO37"), \ + PINCTRL_PIN(38, "PLGPIO38"), \ + PINCTRL_PIN(39, "PLGPIO39"), \ + PINCTRL_PIN(40, "PLGPIO40"), \ + PINCTRL_PIN(41, "PLGPIO41"), \ + PINCTRL_PIN(42, "PLGPIO42"), \ + PINCTRL_PIN(43, "PLGPIO43"), \ + PINCTRL_PIN(44, "PLGPIO44"), \ + PINCTRL_PIN(45, "PLGPIO45"), \ + PINCTRL_PIN(46, "PLGPIO46"), \ + PINCTRL_PIN(47, "PLGPIO47"), \ + PINCTRL_PIN(48, "PLGPIO48"), \ + PINCTRL_PIN(49, "PLGPIO49"), \ + PINCTRL_PIN(50, "PLGPIO50"), \ + PINCTRL_PIN(51, "PLGPIO51"), \ + PINCTRL_PIN(52, "PLGPIO52"), \ + PINCTRL_PIN(53, "PLGPIO53"), \ + PINCTRL_PIN(54, "PLGPIO54"), \ + PINCTRL_PIN(55, "PLGPIO55"), \ + PINCTRL_PIN(56, "PLGPIO56"), \ + PINCTRL_PIN(57, "PLGPIO57"), \ + PINCTRL_PIN(58, "PLGPIO58"), \ + PINCTRL_PIN(59, "PLGPIO59"), \ + PINCTRL_PIN(60, "PLGPIO60"), \ + PINCTRL_PIN(61, "PLGPIO61"), \ + PINCTRL_PIN(62, "PLGPIO62"), \ + PINCTRL_PIN(63, "PLGPIO63"), \ + PINCTRL_PIN(64, "PLGPIO64"), \ + PINCTRL_PIN(65, "PLGPIO65"), \ + PINCTRL_PIN(66, "PLGPIO66"), \ + PINCTRL_PIN(67, "PLGPIO67"), \ + PINCTRL_PIN(68, "PLGPIO68"), \ + PINCTRL_PIN(69, "PLGPIO69"), \ + PINCTRL_PIN(70, "PLGPIO70"), \ + PINCTRL_PIN(71, "PLGPIO71"), \ + PINCTRL_PIN(72, "PLGPIO72"), \ + PINCTRL_PIN(73, "PLGPIO73"), \ + PINCTRL_PIN(74, "PLGPIO74"), \ + PINCTRL_PIN(75, "PLGPIO75"), \ + PINCTRL_PIN(76, "PLGPIO76"), \ + PINCTRL_PIN(77, "PLGPIO77"), \ + PINCTRL_PIN(78, "PLGPIO78"), \ + PINCTRL_PIN(79, "PLGPIO79"), \ + PINCTRL_PIN(80, "PLGPIO80"), \ + PINCTRL_PIN(81, "PLGPIO81"), \ + PINCTRL_PIN(82, "PLGPIO82"), \ + PINCTRL_PIN(83, "PLGPIO83"), \ + PINCTRL_PIN(84, "PLGPIO84"), \ + PINCTRL_PIN(85, "PLGPIO85"), \ + PINCTRL_PIN(86, "PLGPIO86"), \ + PINCTRL_PIN(87, "PLGPIO87"), \ + PINCTRL_PIN(88, "PLGPIO88"), \ + PINCTRL_PIN(89, "PLGPIO89"), \ + PINCTRL_PIN(90, "PLGPIO90"), \ + PINCTRL_PIN(91, "PLGPIO91"), \ + PINCTRL_PIN(92, "PLGPIO92"), \ + PINCTRL_PIN(93, "PLGPIO93"), \ + PINCTRL_PIN(94, "PLGPIO94"), \ + PINCTRL_PIN(95, "PLGPIO95"), \ + PINCTRL_PIN(96, "PLGPIO96"), \ + PINCTRL_PIN(97, "PLGPIO97"), \ + PINCTRL_PIN(98, "PLGPIO98"), \ + PINCTRL_PIN(99, "PLGPIO99"), \ + PINCTRL_PIN(100, "PLGPIO100"), \ + PINCTRL_PIN(101, "PLGPIO101") + +#define SPEAR_PIN_102_TO_245 \ + PINCTRL_PIN(102, "PLGPIO102"), \ + PINCTRL_PIN(103, "PLGPIO103"), \ + PINCTRL_PIN(104, "PLGPIO104"), \ + PINCTRL_PIN(105, "PLGPIO105"), \ + PINCTRL_PIN(106, "PLGPIO106"), \ + PINCTRL_PIN(107, "PLGPIO107"), \ + PINCTRL_PIN(108, "PLGPIO108"), \ + PINCTRL_PIN(109, "PLGPIO109"), \ + PINCTRL_PIN(110, "PLGPIO110"), \ + PINCTRL_PIN(111, "PLGPIO111"), \ + PINCTRL_PIN(112, "PLGPIO112"), \ + PINCTRL_PIN(113, "PLGPIO113"), \ + PINCTRL_PIN(114, "PLGPIO114"), \ + PINCTRL_PIN(115, "PLGPIO115"), \ + PINCTRL_PIN(116, "PLGPIO116"), \ + PINCTRL_PIN(117, "PLGPIO117"), \ + PINCTRL_PIN(118, "PLGPIO118"), \ + PINCTRL_PIN(119, "PLGPIO119"), \ + PINCTRL_PIN(120, "PLGPIO120"), \ + PINCTRL_PIN(121, "PLGPIO121"), \ + PINCTRL_PIN(122, "PLGPIO122"), \ + PINCTRL_PIN(123, "PLGPIO123"), \ + PINCTRL_PIN(124, "PLGPIO124"), \ + PINCTRL_PIN(125, "PLGPIO125"), \ + PINCTRL_PIN(126, "PLGPIO126"), \ + PINCTRL_PIN(127, "PLGPIO127"), \ + PINCTRL_PIN(128, "PLGPIO128"), \ + PINCTRL_PIN(129, "PLGPIO129"), \ + PINCTRL_PIN(130, "PLGPIO130"), \ + PINCTRL_PIN(131, "PLGPIO131"), \ + PINCTRL_PIN(132, "PLGPIO132"), \ + PINCTRL_PIN(133, "PLGPIO133"), \ + PINCTRL_PIN(134, "PLGPIO134"), \ + PINCTRL_PIN(135, "PLGPIO135"), \ + PINCTRL_PIN(136, "PLGPIO136"), \ + PINCTRL_PIN(137, "PLGPIO137"), \ + PINCTRL_PIN(138, "PLGPIO138"), \ + PINCTRL_PIN(139, "PLGPIO139"), \ + PINCTRL_PIN(140, "PLGPIO140"), \ + PINCTRL_PIN(141, "PLGPIO141"), \ + PINCTRL_PIN(142, "PLGPIO142"), \ + PINCTRL_PIN(143, "PLGPIO143"), \ + PINCTRL_PIN(144, "PLGPIO144"), \ + PINCTRL_PIN(145, "PLGPIO145"), \ + PINCTRL_PIN(146, "PLGPIO146"), \ + PINCTRL_PIN(147, "PLGPIO147"), \ + PINCTRL_PIN(148, "PLGPIO148"), \ + PINCTRL_PIN(149, "PLGPIO149"), \ + PINCTRL_PIN(150, "PLGPIO150"), \ + PINCTRL_PIN(151, "PLGPIO151"), \ + PINCTRL_PIN(152, "PLGPIO152"), \ + PINCTRL_PIN(153, "PLGPIO153"), \ + PINCTRL_PIN(154, "PLGPIO154"), \ + PINCTRL_PIN(155, "PLGPIO155"), \ + PINCTRL_PIN(156, "PLGPIO156"), \ + PINCTRL_PIN(157, "PLGPIO157"), \ + PINCTRL_PIN(158, "PLGPIO158"), \ + PINCTRL_PIN(159, "PLGPIO159"), \ + PINCTRL_PIN(160, "PLGPIO160"), \ + PINCTRL_PIN(161, "PLGPIO161"), \ + PINCTRL_PIN(162, "PLGPIO162"), \ + PINCTRL_PIN(163, "PLGPIO163"), \ + PINCTRL_PIN(164, "PLGPIO164"), \ + PINCTRL_PIN(165, "PLGPIO165"), \ + PINCTRL_PIN(166, "PLGPIO166"), \ + PINCTRL_PIN(167, "PLGPIO167"), \ + PINCTRL_PIN(168, "PLGPIO168"), \ + PINCTRL_PIN(169, "PLGPIO169"), \ + PINCTRL_PIN(170, "PLGPIO170"), \ + PINCTRL_PIN(171, "PLGPIO171"), \ + PINCTRL_PIN(172, "PLGPIO172"), \ + PINCTRL_PIN(173, "PLGPIO173"), \ + PINCTRL_PIN(174, "PLGPIO174"), \ + PINCTRL_PIN(175, "PLGPIO175"), \ + PINCTRL_PIN(176, "PLGPIO176"), \ + PINCTRL_PIN(177, "PLGPIO177"), \ + PINCTRL_PIN(178, "PLGPIO178"), \ + PINCTRL_PIN(179, "PLGPIO179"), \ + PINCTRL_PIN(180, "PLGPIO180"), \ + PINCTRL_PIN(181, "PLGPIO181"), \ + PINCTRL_PIN(182, "PLGPIO182"), \ + PINCTRL_PIN(183, "PLGPIO183"), \ + PINCTRL_PIN(184, "PLGPIO184"), \ + PINCTRL_PIN(185, "PLGPIO185"), \ + PINCTRL_PIN(186, "PLGPIO186"), \ + PINCTRL_PIN(187, "PLGPIO187"), \ + PINCTRL_PIN(188, "PLGPIO188"), \ + PINCTRL_PIN(189, "PLGPIO189"), \ + PINCTRL_PIN(190, "PLGPIO190"), \ + PINCTRL_PIN(191, "PLGPIO191"), \ + PINCTRL_PIN(192, "PLGPIO192"), \ + PINCTRL_PIN(193, "PLGPIO193"), \ + PINCTRL_PIN(194, "PLGPIO194"), \ + PINCTRL_PIN(195, "PLGPIO195"), \ + PINCTRL_PIN(196, "PLGPIO196"), \ + PINCTRL_PIN(197, "PLGPIO197"), \ + PINCTRL_PIN(198, "PLGPIO198"), \ + PINCTRL_PIN(199, "PLGPIO199"), \ + PINCTRL_PIN(200, "PLGPIO200"), \ + PINCTRL_PIN(201, "PLGPIO201"), \ + PINCTRL_PIN(202, "PLGPIO202"), \ + PINCTRL_PIN(203, "PLGPIO203"), \ + PINCTRL_PIN(204, "PLGPIO204"), \ + PINCTRL_PIN(205, "PLGPIO205"), \ + PINCTRL_PIN(206, "PLGPIO206"), \ + PINCTRL_PIN(207, "PLGPIO207"), \ + PINCTRL_PIN(208, "PLGPIO208"), \ + PINCTRL_PIN(209, "PLGPIO209"), \ + PINCTRL_PIN(210, "PLGPIO210"), \ + PINCTRL_PIN(211, "PLGPIO211"), \ + PINCTRL_PIN(212, "PLGPIO212"), \ + PINCTRL_PIN(213, "PLGPIO213"), \ + PINCTRL_PIN(214, "PLGPIO214"), \ + PINCTRL_PIN(215, "PLGPIO215"), \ + PINCTRL_PIN(216, "PLGPIO216"), \ + PINCTRL_PIN(217, "PLGPIO217"), \ + PINCTRL_PIN(218, "PLGPIO218"), \ + PINCTRL_PIN(219, "PLGPIO219"), \ + PINCTRL_PIN(220, "PLGPIO220"), \ + PINCTRL_PIN(221, "PLGPIO221"), \ + PINCTRL_PIN(222, "PLGPIO222"), \ + PINCTRL_PIN(223, "PLGPIO223"), \ + PINCTRL_PIN(224, "PLGPIO224"), \ + PINCTRL_PIN(225, "PLGPIO225"), \ + PINCTRL_PIN(226, "PLGPIO226"), \ + PINCTRL_PIN(227, "PLGPIO227"), \ + PINCTRL_PIN(228, "PLGPIO228"), \ + PINCTRL_PIN(229, "PLGPIO229"), \ + PINCTRL_PIN(230, "PLGPIO230"), \ + PINCTRL_PIN(231, "PLGPIO231"), \ + PINCTRL_PIN(232, "PLGPIO232"), \ + PINCTRL_PIN(233, "PLGPIO233"), \ + PINCTRL_PIN(234, "PLGPIO234"), \ + PINCTRL_PIN(235, "PLGPIO235"), \ + PINCTRL_PIN(236, "PLGPIO236"), \ + PINCTRL_PIN(237, "PLGPIO237"), \ + PINCTRL_PIN(238, "PLGPIO238"), \ + PINCTRL_PIN(239, "PLGPIO239"), \ + PINCTRL_PIN(240, "PLGPIO240"), \ + PINCTRL_PIN(241, "PLGPIO241"), \ + PINCTRL_PIN(242, "PLGPIO242"), \ + PINCTRL_PIN(243, "PLGPIO243"), \ + PINCTRL_PIN(244, "PLGPIO244"), \ + PINCTRL_PIN(245, "PLGPIO245") + +#endif /* __PINMUX_SPEAR_H__ */ diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c new file mode 100644 index 000000000..0180eb544 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear1310.c @@ -0,0 +1,2718 @@ +/* + * Driver for the ST Microelectronics SPEAr1310 pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <vireshk@kernel.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "pinctrl-spear.h" + +#define DRIVER_NAME "spear1310-pinmux" + +/* pins */ +static const struct pinctrl_pin_desc spear1310_pins[] = { + SPEAR_PIN_0_TO_101, + SPEAR_PIN_102_TO_245, +}; + +/* registers */ +#define PERIP_CFG 0x3B0 + #define MCIF_SEL_SHIFT 5 + #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT) + #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT) + #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT) + #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT) + +#define PCIE_SATA_CFG 0x3A4 + #define PCIE_SATA2_SEL_PCIE (0 << 31) + #define PCIE_SATA1_SEL_PCIE (0 << 30) + #define PCIE_SATA0_SEL_PCIE (0 << 29) + #define PCIE_SATA2_SEL_SATA (1 << 31) + #define PCIE_SATA1_SEL_SATA (1 << 30) + #define PCIE_SATA0_SEL_SATA (1 << 29) + #define SATA2_CFG_TX_CLK_EN (1 << 27) + #define SATA2_CFG_RX_CLK_EN (1 << 26) + #define SATA2_CFG_POWERUP_RESET (1 << 25) + #define SATA2_CFG_PM_CLK_EN (1 << 24) + #define SATA1_CFG_TX_CLK_EN (1 << 23) + #define SATA1_CFG_RX_CLK_EN (1 << 22) + #define SATA1_CFG_POWERUP_RESET (1 << 21) + #define SATA1_CFG_PM_CLK_EN (1 << 20) + #define SATA0_CFG_TX_CLK_EN (1 << 19) + #define SATA0_CFG_RX_CLK_EN (1 << 18) + #define SATA0_CFG_POWERUP_RESET (1 << 17) + #define SATA0_CFG_PM_CLK_EN (1 << 16) + #define PCIE2_CFG_DEVICE_PRESENT (1 << 11) + #define PCIE2_CFG_POWERUP_RESET (1 << 10) + #define PCIE2_CFG_CORE_CLK_EN (1 << 9) + #define PCIE2_CFG_AUX_CLK_EN (1 << 8) + #define PCIE1_CFG_DEVICE_PRESENT (1 << 7) + #define PCIE1_CFG_POWERUP_RESET (1 << 6) + #define PCIE1_CFG_CORE_CLK_EN (1 << 5) + #define PCIE1_CFG_AUX_CLK_EN (1 << 4) + #define PCIE0_CFG_DEVICE_PRESENT (1 << 3) + #define PCIE0_CFG_POWERUP_RESET (1 << 2) + #define PCIE0_CFG_CORE_CLK_EN (1 << 1) + #define PCIE0_CFG_AUX_CLK_EN (1 << 0) + +#define PAD_FUNCTION_EN_0 0x650 + #define PMX_UART0_MASK (1 << 1) + #define PMX_I2C0_MASK (1 << 2) + #define PMX_I2S0_MASK (1 << 3) + #define PMX_SSP0_MASK (1 << 4) + #define PMX_CLCD1_MASK (1 << 5) + #define PMX_EGPIO00_MASK (1 << 6) + #define PMX_EGPIO01_MASK (1 << 7) + #define PMX_EGPIO02_MASK (1 << 8) + #define PMX_EGPIO03_MASK (1 << 9) + #define PMX_EGPIO04_MASK (1 << 10) + #define PMX_EGPIO05_MASK (1 << 11) + #define PMX_EGPIO06_MASK (1 << 12) + #define PMX_EGPIO07_MASK (1 << 13) + #define PMX_EGPIO08_MASK (1 << 14) + #define PMX_EGPIO09_MASK (1 << 15) + #define PMX_SMI_MASK (1 << 16) + #define PMX_NAND8_MASK (1 << 17) + #define PMX_GMIICLK_MASK (1 << 18) + #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19) + #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20) + #define PMX_GMIID47_MASK (1 << 21) + #define PMX_MDC_MDIO_MASK (1 << 22) + #define PMX_MCI_DATA8_15_MASK (1 << 23) + #define PMX_NFAD23_MASK (1 << 24) + #define PMX_NFAD24_MASK (1 << 25) + #define PMX_NFAD25_MASK (1 << 26) + #define PMX_NFCE3_MASK (1 << 27) + #define PMX_NFWPRT3_MASK (1 << 28) + #define PMX_NFRSTPWDWN0_MASK (1 << 29) + #define PMX_NFRSTPWDWN1_MASK (1 << 30) + #define PMX_NFRSTPWDWN2_MASK (1 << 31) + +#define PAD_FUNCTION_EN_1 0x654 + #define PMX_NFRSTPWDWN3_MASK (1 << 0) + #define PMX_SMINCS2_MASK (1 << 1) + #define PMX_SMINCS3_MASK (1 << 2) + #define PMX_CLCD2_MASK (1 << 3) + #define PMX_KBD_ROWCOL68_MASK (1 << 4) + #define PMX_EGPIO10_MASK (1 << 5) + #define PMX_EGPIO11_MASK (1 << 6) + #define PMX_EGPIO12_MASK (1 << 7) + #define PMX_EGPIO13_MASK (1 << 8) + #define PMX_EGPIO14_MASK (1 << 9) + #define PMX_EGPIO15_MASK (1 << 10) + #define PMX_UART0_MODEM_MASK (1 << 11) + #define PMX_GPT0_TMR0_MASK (1 << 12) + #define PMX_GPT0_TMR1_MASK (1 << 13) + #define PMX_GPT1_TMR0_MASK (1 << 14) + #define PMX_GPT1_TMR1_MASK (1 << 15) + #define PMX_I2S1_MASK (1 << 16) + #define PMX_KBD_ROWCOL25_MASK (1 << 17) + #define PMX_NFIO8_15_MASK (1 << 18) + #define PMX_KBD_COL1_MASK (1 << 19) + #define PMX_NFCE1_MASK (1 << 20) + #define PMX_KBD_COL0_MASK (1 << 21) + #define PMX_NFCE2_MASK (1 << 22) + #define PMX_KBD_ROW1_MASK (1 << 23) + #define PMX_NFWPRT1_MASK (1 << 24) + #define PMX_KBD_ROW0_MASK (1 << 25) + #define PMX_NFWPRT2_MASK (1 << 26) + #define PMX_MCIDATA0_MASK (1 << 27) + #define PMX_MCIDATA1_MASK (1 << 28) + #define PMX_MCIDATA2_MASK (1 << 29) + #define PMX_MCIDATA3_MASK (1 << 30) + #define PMX_MCIDATA4_MASK (1 << 31) + +#define PAD_FUNCTION_EN_2 0x658 + #define PMX_MCIDATA5_MASK (1 << 0) + #define PMX_MCIDATA6_MASK (1 << 1) + #define PMX_MCIDATA7_MASK (1 << 2) + #define PMX_MCIDATA1SD_MASK (1 << 3) + #define PMX_MCIDATA2SD_MASK (1 << 4) + #define PMX_MCIDATA3SD_MASK (1 << 5) + #define PMX_MCIADDR0ALE_MASK (1 << 6) + #define PMX_MCIADDR1CLECLK_MASK (1 << 7) + #define PMX_MCIADDR2_MASK (1 << 8) + #define PMX_MCICECF_MASK (1 << 9) + #define PMX_MCICEXD_MASK (1 << 10) + #define PMX_MCICESDMMC_MASK (1 << 11) + #define PMX_MCICDCF1_MASK (1 << 12) + #define PMX_MCICDCF2_MASK (1 << 13) + #define PMX_MCICDXD_MASK (1 << 14) + #define PMX_MCICDSDMMC_MASK (1 << 15) + #define PMX_MCIDATADIR_MASK (1 << 16) + #define PMX_MCIDMARQWP_MASK (1 << 17) + #define PMX_MCIIORDRE_MASK (1 << 18) + #define PMX_MCIIOWRWE_MASK (1 << 19) + #define PMX_MCIRESETCF_MASK (1 << 20) + #define PMX_MCICS0CE_MASK (1 << 21) + #define PMX_MCICFINTR_MASK (1 << 22) + #define PMX_MCIIORDY_MASK (1 << 23) + #define PMX_MCICS1_MASK (1 << 24) + #define PMX_MCIDMAACK_MASK (1 << 25) + #define PMX_MCISDCMD_MASK (1 << 26) + #define PMX_MCILEDS_MASK (1 << 27) + #define PMX_TOUCH_XY_MASK (1 << 28) + #define PMX_SSP0_CS0_MASK (1 << 29) + #define PMX_SSP0_CS1_2_MASK (1 << 30) + +#define PAD_DIRECTION_SEL_0 0x65C +#define PAD_DIRECTION_SEL_1 0x660 +#define PAD_DIRECTION_SEL_2 0x664 + +/* combined macros */ +#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \ + PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ + PMX_RXCLK_RDV_TXEN_D03_MASK | \ + PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK) + +#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \ + PMX_EGPIO02_MASK | \ + PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \ + PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \ + PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \ + PMX_EGPIO09_MASK) +#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \ + PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \ + PMX_EGPIO14_MASK | PMX_EGPIO15_MASK) + +#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ + PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \ + PMX_KBD_COL1_MASK) + +#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \ + PMX_NFAD24_MASK | PMX_NFAD25_MASK | \ + PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \ + PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \ + PMX_NFCE3_MASK) +#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK + +#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK) +#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \ + PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \ + PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ + PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK) + +#define PMX_MCIFALL_1_MASK 0xF8000000 +#define PMX_MCIFALL_2_MASK 0x0FFFFFFF + +#define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \ + PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \ + PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \ + PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \ + PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \ + PMX_NFCE2_MASK) +#define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ + PMX_SSP0_CS1_2_MASK) + +#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK) +#define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \ + PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ + PMX_GMIID47_MASK) +#define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\ + PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \ + PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK) +#define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ + PMX_SSP0_CS1_2_MASK) + +#define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \ + PCIE##x##_CFG_AUX_CLK_EN | \ + PCIE##x##_CFG_CORE_CLK_EN | \ + PCIE##x##_CFG_POWERUP_RESET | \ + PCIE##x##_CFG_DEVICE_PRESENT) +#define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \ + SATA##x##_CFG_PM_CLK_EN | \ + SATA##x##_CFG_POWERUP_RESET | \ + SATA##x##_CFG_RX_CLK_EN | \ + SATA##x##_CFG_TX_CLK_EN) + +/* Pad multiplexing for i2c0 device */ +static const unsigned i2c0_pins[] = { 102, 103 }; +static struct spear_muxreg i2c0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_I2C0_MASK, + .val = PMX_I2C0_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_I2C0_MASK, + .val = PMX_I2C0_MASK, + }, +}; + +static struct spear_modemux i2c0_modemux[] = { + { + .muxregs = i2c0_muxreg, + .nmuxregs = ARRAY_SIZE(i2c0_muxreg), + }, +}; + +static struct spear_pingroup i2c0_pingroup = { + .name = "i2c0_grp", + .pins = i2c0_pins, + .npins = ARRAY_SIZE(i2c0_pins), + .modemuxs = i2c0_modemux, + .nmodemuxs = ARRAY_SIZE(i2c0_modemux), +}; + +static const char *const i2c0_grps[] = { "i2c0_grp" }; +static struct spear_function i2c0_function = { + .name = "i2c0", + .groups = i2c0_grps, + .ngroups = ARRAY_SIZE(i2c0_grps), +}; + +/* Pad multiplexing for ssp0 device */ +static const unsigned ssp0_pins[] = { 109, 110, 111, 112 }; +static struct spear_muxreg ssp0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_SSP0_MASK, + .val = PMX_SSP0_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_SSP0_MASK, + .val = PMX_SSP0_MASK, + }, +}; + +static struct spear_modemux ssp0_modemux[] = { + { + .muxregs = ssp0_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_muxreg), + }, +}; + +static struct spear_pingroup ssp0_pingroup = { + .name = "ssp0_grp", + .pins = ssp0_pins, + .npins = ARRAY_SIZE(ssp0_pins), + .modemuxs = ssp0_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_modemux), +}; + +/* Pad multiplexing for ssp0_cs0 device */ +static const unsigned ssp0_cs0_pins[] = { 96 }; +static struct spear_muxreg ssp0_cs0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_SSP0_CS0_MASK, + .val = PMX_SSP0_CS0_MASK, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_SSP0_CS0_MASK, + .val = PMX_SSP0_CS0_MASK, + }, +}; + +static struct spear_modemux ssp0_cs0_modemux[] = { + { + .muxregs = ssp0_cs0_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg), + }, +}; + +static struct spear_pingroup ssp0_cs0_pingroup = { + .name = "ssp0_cs0_grp", + .pins = ssp0_cs0_pins, + .npins = ARRAY_SIZE(ssp0_cs0_pins), + .modemuxs = ssp0_cs0_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux), +}; + +/* ssp0_cs1_2 device */ +static const unsigned ssp0_cs1_2_pins[] = { 94, 95 }; +static struct spear_muxreg ssp0_cs1_2_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_SSP0_CS1_2_MASK, + .val = PMX_SSP0_CS1_2_MASK, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_SSP0_CS1_2_MASK, + .val = PMX_SSP0_CS1_2_MASK, + }, +}; + +static struct spear_modemux ssp0_cs1_2_modemux[] = { + { + .muxregs = ssp0_cs1_2_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg), + }, +}; + +static struct spear_pingroup ssp0_cs1_2_pingroup = { + .name = "ssp0_cs1_2_grp", + .pins = ssp0_cs1_2_pins, + .npins = ARRAY_SIZE(ssp0_cs1_2_pins), + .modemuxs = ssp0_cs1_2_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux), +}; + +static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp", + "ssp0_cs1_2_grp" }; +static struct spear_function ssp0_function = { + .name = "ssp0", + .groups = ssp0_grps, + .ngroups = ARRAY_SIZE(ssp0_grps), +}; + +/* Pad multiplexing for i2s0 device */ +static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 }; +static struct spear_muxreg i2s0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_I2S0_MASK, + .val = PMX_I2S0_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_I2S0_MASK, + .val = PMX_I2S0_MASK, + }, +}; + +static struct spear_modemux i2s0_modemux[] = { + { + .muxregs = i2s0_muxreg, + .nmuxregs = ARRAY_SIZE(i2s0_muxreg), + }, +}; + +static struct spear_pingroup i2s0_pingroup = { + .name = "i2s0_grp", + .pins = i2s0_pins, + .npins = ARRAY_SIZE(i2s0_pins), + .modemuxs = i2s0_modemux, + .nmodemuxs = ARRAY_SIZE(i2s0_modemux), +}; + +static const char *const i2s0_grps[] = { "i2s0_grp" }; +static struct spear_function i2s0_function = { + .name = "i2s0", + .groups = i2s0_grps, + .ngroups = ARRAY_SIZE(i2s0_grps), +}; + +/* Pad multiplexing for i2s1 device */ +static const unsigned i2s1_pins[] = { 0, 1, 2, 3 }; +static struct spear_muxreg i2s1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_I2S1_MASK, + .val = PMX_I2S1_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_I2S1_MASK, + .val = PMX_I2S1_MASK, + }, +}; + +static struct spear_modemux i2s1_modemux[] = { + { + .muxregs = i2s1_muxreg, + .nmuxregs = ARRAY_SIZE(i2s1_muxreg), + }, +}; + +static struct spear_pingroup i2s1_pingroup = { + .name = "i2s1_grp", + .pins = i2s1_pins, + .npins = ARRAY_SIZE(i2s1_pins), + .modemuxs = i2s1_modemux, + .nmodemuxs = ARRAY_SIZE(i2s1_modemux), +}; + +static const char *const i2s1_grps[] = { "i2s1_grp" }; +static struct spear_function i2s1_function = { + .name = "i2s1", + .groups = i2s1_grps, + .ngroups = ARRAY_SIZE(i2s1_grps), +}; + +/* Pad multiplexing for clcd device */ +static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120, + 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, + 135, 136, 137, 138, 139, 140, 141, 142 }; +static struct spear_muxreg clcd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_CLCD1_MASK, + .val = PMX_CLCD1_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_CLCD1_MASK, + .val = PMX_CLCD1_MASK, + }, +}; + +static struct spear_modemux clcd_modemux[] = { + { + .muxregs = clcd_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_muxreg), + }, +}; + +static struct spear_pingroup clcd_pingroup = { + .name = "clcd_grp", + .pins = clcd_pins, + .npins = ARRAY_SIZE(clcd_pins), + .modemuxs = clcd_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_modemux), +}; + +static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 }; +static struct spear_muxreg clcd_high_res_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_CLCD2_MASK, + .val = PMX_CLCD2_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_CLCD2_MASK, + .val = PMX_CLCD2_MASK, + }, +}; + +static struct spear_modemux clcd_high_res_modemux[] = { + { + .muxregs = clcd_high_res_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg), + }, +}; + +static struct spear_pingroup clcd_high_res_pingroup = { + .name = "clcd_high_res_grp", + .pins = clcd_high_res_pins, + .npins = ARRAY_SIZE(clcd_high_res_pins), + .modemuxs = clcd_high_res_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux), +}; + +static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" }; +static struct spear_function clcd_function = { + .name = "clcd", + .groups = clcd_grps, + .ngroups = ARRAY_SIZE(clcd_grps), +}; + +static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145, + 146, 147, 148, 149, 150, 151, 152 }; +static struct spear_muxreg arm_gpio_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_EGPIO_0_GRP_MASK, + .val = PMX_EGPIO_0_GRP_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_EGPIO_1_GRP_MASK, + .val = PMX_EGPIO_1_GRP_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_EGPIO_0_GRP_MASK, + .val = PMX_EGPIO_0_GRP_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_EGPIO_1_GRP_MASK, + .val = PMX_EGPIO_1_GRP_MASK, + }, +}; + +static struct spear_modemux arm_gpio_modemux[] = { + { + .muxregs = arm_gpio_muxreg, + .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg), + }, +}; + +static struct spear_pingroup arm_gpio_pingroup = { + .name = "arm_gpio_grp", + .pins = arm_gpio_pins, + .npins = ARRAY_SIZE(arm_gpio_pins), + .modemuxs = arm_gpio_modemux, + .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux), +}; + +static const char *const arm_gpio_grps[] = { "arm_gpio_grp" }; +static struct spear_function arm_gpio_function = { + .name = "arm_gpio", + .groups = arm_gpio_grps, + .ngroups = ARRAY_SIZE(arm_gpio_grps), +}; + +/* Pad multiplexing for smi 2 chips device */ +static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 }; +static struct spear_muxreg smi_2_chips_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_SMI_MASK, + .val = PMX_SMI_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_SMI_MASK, + .val = PMX_SMI_MASK, + }, +}; + +static struct spear_modemux smi_2_chips_modemux[] = { + { + .muxregs = smi_2_chips_muxreg, + .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg), + }, +}; + +static struct spear_pingroup smi_2_chips_pingroup = { + .name = "smi_2_chips_grp", + .pins = smi_2_chips_pins, + .npins = ARRAY_SIZE(smi_2_chips_pins), + .modemuxs = smi_2_chips_modemux, + .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux), +}; + +static const unsigned smi_4_chips_pins[] = { 54, 55 }; +static struct spear_muxreg smi_4_chips_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_SMI_MASK, + .val = PMX_SMI_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, + .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_SMI_MASK, + .val = PMX_SMI_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, + .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, + }, +}; + +static struct spear_modemux smi_4_chips_modemux[] = { + { + .muxregs = smi_4_chips_muxreg, + .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg), + }, +}; + +static struct spear_pingroup smi_4_chips_pingroup = { + .name = "smi_4_chips_grp", + .pins = smi_4_chips_pins, + .npins = ARRAY_SIZE(smi_4_chips_pins), + .modemuxs = smi_4_chips_modemux, + .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux), +}; + +static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" }; +static struct spear_function smi_function = { + .name = "smi", + .groups = smi_grps, + .ngroups = ARRAY_SIZE(smi_grps), +}; + +/* Pad multiplexing for gmii device */ +static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180, + 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, + 195, 196, 197, 198, 199, 200 }; +static struct spear_muxreg gmii_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_GMII_MASK, + .val = PMX_GMII_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_GMII_MASK, + .val = PMX_GMII_MASK, + }, +}; + +static struct spear_modemux gmii_modemux[] = { + { + .muxregs = gmii_muxreg, + .nmuxregs = ARRAY_SIZE(gmii_muxreg), + }, +}; + +static struct spear_pingroup gmii_pingroup = { + .name = "gmii_grp", + .pins = gmii_pins, + .npins = ARRAY_SIZE(gmii_pins), + .modemuxs = gmii_modemux, + .nmodemuxs = ARRAY_SIZE(gmii_modemux), +}; + +static const char *const gmii_grps[] = { "gmii_grp" }; +static struct spear_function gmii_function = { + .name = "gmii", + .groups = gmii_grps, + .ngroups = ARRAY_SIZE(gmii_grps), +}; + +/* Pad multiplexing for rgmii device */ +static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, + 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175, + 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 }; +static struct spear_muxreg rgmii_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_RGMII_REG0_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_RGMII_REG1_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_RGMII_REG2_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_RGMII_REG0_MASK, + .val = PMX_RGMII_REG0_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_RGMII_REG1_MASK, + .val = PMX_RGMII_REG1_MASK, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_RGMII_REG2_MASK, + .val = PMX_RGMII_REG2_MASK, + }, +}; + +static struct spear_modemux rgmii_modemux[] = { + { + .muxregs = rgmii_muxreg, + .nmuxregs = ARRAY_SIZE(rgmii_muxreg), + }, +}; + +static struct spear_pingroup rgmii_pingroup = { + .name = "rgmii_grp", + .pins = rgmii_pins, + .npins = ARRAY_SIZE(rgmii_pins), + .modemuxs = rgmii_modemux, + .nmodemuxs = ARRAY_SIZE(rgmii_modemux), +}; + +static const char *const rgmii_grps[] = { "rgmii_grp" }; +static struct spear_function rgmii_function = { + .name = "rgmii", + .groups = rgmii_grps, + .ngroups = ARRAY_SIZE(rgmii_grps), +}; + +/* Pad multiplexing for smii_0_1_2 device */ +static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, + 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, + 51, 52, 53, 54, 55 }; +static struct spear_muxreg smii_0_1_2_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_SMII_0_1_2_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_SMII_0_1_2_MASK, + .val = PMX_SMII_0_1_2_MASK, + }, +}; + +static struct spear_modemux smii_0_1_2_modemux[] = { + { + .muxregs = smii_0_1_2_muxreg, + .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg), + }, +}; + +static struct spear_pingroup smii_0_1_2_pingroup = { + .name = "smii_0_1_2_grp", + .pins = smii_0_1_2_pins, + .npins = ARRAY_SIZE(smii_0_1_2_pins), + .modemuxs = smii_0_1_2_modemux, + .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux), +}; + +static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" }; +static struct spear_function smii_0_1_2_function = { + .name = "smii_0_1_2", + .groups = smii_0_1_2_grps, + .ngroups = ARRAY_SIZE(smii_0_1_2_grps), +}; + +/* Pad multiplexing for ras_mii_txclk device */ +static const unsigned ras_mii_txclk_pins[] = { 98, 99 }; +static struct spear_muxreg ras_mii_txclk_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_NFCE2_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_NFCE2_MASK, + .val = PMX_NFCE2_MASK, + }, +}; + +static struct spear_modemux ras_mii_txclk_modemux[] = { + { + .muxregs = ras_mii_txclk_muxreg, + .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg), + }, +}; + +static struct spear_pingroup ras_mii_txclk_pingroup = { + .name = "ras_mii_txclk_grp", + .pins = ras_mii_txclk_pins, + .npins = ARRAY_SIZE(ras_mii_txclk_pins), + .modemuxs = ras_mii_txclk_modemux, + .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux), +}; + +static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" }; +static struct spear_function ras_mii_txclk_function = { + .name = "ras_mii_txclk", + .groups = ras_mii_txclk_grps, + .ngroups = ARRAY_SIZE(ras_mii_txclk_grps), +}; + +/* Pad multiplexing for nand 8bit device (cs0 only) */ +static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64, + 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, + 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, + 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, + 212 }; +static struct spear_muxreg nand_8bit_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_NAND8BIT_0_MASK, + .val = PMX_NAND8BIT_0_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_NAND8BIT_1_MASK, + .val = PMX_NAND8BIT_1_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_NAND8BIT_0_MASK, + .val = PMX_NAND8BIT_0_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_NAND8BIT_1_MASK, + .val = PMX_NAND8BIT_1_MASK, + }, +}; + +static struct spear_modemux nand_8bit_modemux[] = { + { + .muxregs = nand_8bit_muxreg, + .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg), + }, +}; + +static struct spear_pingroup nand_8bit_pingroup = { + .name = "nand_8bit_grp", + .pins = nand_8bit_pins, + .npins = ARRAY_SIZE(nand_8bit_pins), + .modemuxs = nand_8bit_modemux, + .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux), +}; + +/* Pad multiplexing for nand 16bit device */ +static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209, + 210 }; +static struct spear_muxreg nand_16bit_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_NAND16BIT_1_MASK, + .val = PMX_NAND16BIT_1_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_NAND16BIT_1_MASK, + .val = PMX_NAND16BIT_1_MASK, + }, +}; + +static struct spear_modemux nand_16bit_modemux[] = { + { + .muxregs = nand_16bit_muxreg, + .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg), + }, +}; + +static struct spear_pingroup nand_16bit_pingroup = { + .name = "nand_16bit_grp", + .pins = nand_16bit_pins, + .npins = ARRAY_SIZE(nand_16bit_pins), + .modemuxs = nand_16bit_modemux, + .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux), +}; + +/* Pad multiplexing for nand 4 chips */ +static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 }; +static struct spear_muxreg nand_4_chips_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_NAND_4CHIPS_MASK, + .val = PMX_NAND_4CHIPS_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_NAND_4CHIPS_MASK, + .val = PMX_NAND_4CHIPS_MASK, + }, +}; + +static struct spear_modemux nand_4_chips_modemux[] = { + { + .muxregs = nand_4_chips_muxreg, + .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg), + }, +}; + +static struct spear_pingroup nand_4_chips_pingroup = { + .name = "nand_4_chips_grp", + .pins = nand_4_chips_pins, + .npins = ARRAY_SIZE(nand_4_chips_pins), + .modemuxs = nand_4_chips_modemux, + .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux), +}; + +static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp", + "nand_4_chips_grp" }; +static struct spear_function nand_function = { + .name = "nand", + .groups = nand_grps, + .ngroups = ARRAY_SIZE(nand_grps), +}; + +/* Pad multiplexing for keyboard_6x6 device */ +static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212 }; +static struct spear_muxreg keyboard_6x6_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK | + PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | + PMX_NFWPRT2_MASK, + .val = PMX_KEYBOARD_6X6_MASK, + }, +}; + +static struct spear_modemux keyboard_6x6_modemux[] = { + { + .muxregs = keyboard_6x6_muxreg, + .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg), + }, +}; + +static struct spear_pingroup keyboard_6x6_pingroup = { + .name = "keyboard_6x6_grp", + .pins = keyboard_6x6_pins, + .npins = ARRAY_SIZE(keyboard_6x6_pins), + .modemuxs = keyboard_6x6_modemux, + .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux), +}; + +/* Pad multiplexing for keyboard_rowcol6_8 device */ +static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 }; +static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_KBD_ROWCOL68_MASK, + .val = PMX_KBD_ROWCOL68_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_KBD_ROWCOL68_MASK, + .val = PMX_KBD_ROWCOL68_MASK, + }, +}; + +static struct spear_modemux keyboard_rowcol6_8_modemux[] = { + { + .muxregs = keyboard_rowcol6_8_muxreg, + .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg), + }, +}; + +static struct spear_pingroup keyboard_rowcol6_8_pingroup = { + .name = "keyboard_rowcol6_8_grp", + .pins = keyboard_rowcol6_8_pins, + .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins), + .modemuxs = keyboard_rowcol6_8_modemux, + .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux), +}; + +static const char *const keyboard_grps[] = { "keyboard_6x6_grp", + "keyboard_rowcol6_8_grp" }; +static struct spear_function keyboard_function = { + .name = "keyboard", + .groups = keyboard_grps, + .ngroups = ARRAY_SIZE(keyboard_grps), +}; + +/* Pad multiplexing for uart0 device */ +static const unsigned uart0_pins[] = { 100, 101 }; +static struct spear_muxreg uart0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_UART0_MASK, + .val = PMX_UART0_MASK, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_UART0_MASK, + .val = PMX_UART0_MASK, + }, +}; + +static struct spear_modemux uart0_modemux[] = { + { + .muxregs = uart0_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_muxreg), + }, +}; + +static struct spear_pingroup uart0_pingroup = { + .name = "uart0_grp", + .pins = uart0_pins, + .npins = ARRAY_SIZE(uart0_pins), + .modemuxs = uart0_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_modemux), +}; + +/* Pad multiplexing for uart0_modem device */ +static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 }; +static struct spear_muxreg uart0_modem_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_UART0_MODEM_MASK, + .val = PMX_UART0_MODEM_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_UART0_MODEM_MASK, + .val = PMX_UART0_MODEM_MASK, + }, +}; + +static struct spear_modemux uart0_modem_modemux[] = { + { + .muxregs = uart0_modem_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg), + }, +}; + +static struct spear_pingroup uart0_modem_pingroup = { + .name = "uart0_modem_grp", + .pins = uart0_modem_pins, + .npins = ARRAY_SIZE(uart0_modem_pins), + .modemuxs = uart0_modem_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux), +}; + +static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" }; +static struct spear_function uart0_function = { + .name = "uart0", + .groups = uart0_grps, + .ngroups = ARRAY_SIZE(uart0_grps), +}; + +/* Pad multiplexing for gpt0_tmr0 device */ +static const unsigned gpt0_tmr0_pins[] = { 10, 11 }; +static struct spear_muxreg gpt0_tmr0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_GPT0_TMR0_MASK, + .val = PMX_GPT0_TMR0_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_GPT0_TMR0_MASK, + .val = PMX_GPT0_TMR0_MASK, + }, +}; + +static struct spear_modemux gpt0_tmr0_modemux[] = { + { + .muxregs = gpt0_tmr0_muxreg, + .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg), + }, +}; + +static struct spear_pingroup gpt0_tmr0_pingroup = { + .name = "gpt0_tmr0_grp", + .pins = gpt0_tmr0_pins, + .npins = ARRAY_SIZE(gpt0_tmr0_pins), + .modemuxs = gpt0_tmr0_modemux, + .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux), +}; + +/* Pad multiplexing for gpt0_tmr1 device */ +static const unsigned gpt0_tmr1_pins[] = { 8, 9 }; +static struct spear_muxreg gpt0_tmr1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_GPT0_TMR1_MASK, + .val = PMX_GPT0_TMR1_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_GPT0_TMR1_MASK, + .val = PMX_GPT0_TMR1_MASK, + }, +}; + +static struct spear_modemux gpt0_tmr1_modemux[] = { + { + .muxregs = gpt0_tmr1_muxreg, + .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg), + }, +}; + +static struct spear_pingroup gpt0_tmr1_pingroup = { + .name = "gpt0_tmr1_grp", + .pins = gpt0_tmr1_pins, + .npins = ARRAY_SIZE(gpt0_tmr1_pins), + .modemuxs = gpt0_tmr1_modemux, + .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux), +}; + +static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" }; +static struct spear_function gpt0_function = { + .name = "gpt0", + .groups = gpt0_grps, + .ngroups = ARRAY_SIZE(gpt0_grps), +}; + +/* Pad multiplexing for gpt1_tmr0 device */ +static const unsigned gpt1_tmr0_pins[] = { 6, 7 }; +static struct spear_muxreg gpt1_tmr0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_GPT1_TMR0_MASK, + .val = PMX_GPT1_TMR0_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_GPT1_TMR0_MASK, + .val = PMX_GPT1_TMR0_MASK, + }, +}; + +static struct spear_modemux gpt1_tmr0_modemux[] = { + { + .muxregs = gpt1_tmr0_muxreg, + .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg), + }, +}; + +static struct spear_pingroup gpt1_tmr0_pingroup = { + .name = "gpt1_tmr0_grp", + .pins = gpt1_tmr0_pins, + .npins = ARRAY_SIZE(gpt1_tmr0_pins), + .modemuxs = gpt1_tmr0_modemux, + .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux), +}; + +/* Pad multiplexing for gpt1_tmr1 device */ +static const unsigned gpt1_tmr1_pins[] = { 4, 5 }; +static struct spear_muxreg gpt1_tmr1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_GPT1_TMR1_MASK, + .val = PMX_GPT1_TMR1_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_GPT1_TMR1_MASK, + .val = PMX_GPT1_TMR1_MASK, + }, +}; + +static struct spear_modemux gpt1_tmr1_modemux[] = { + { + .muxregs = gpt1_tmr1_muxreg, + .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg), + }, +}; + +static struct spear_pingroup gpt1_tmr1_pingroup = { + .name = "gpt1_tmr1_grp", + .pins = gpt1_tmr1_pins, + .npins = ARRAY_SIZE(gpt1_tmr1_pins), + .modemuxs = gpt1_tmr1_modemux, + .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux), +}; + +static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" }; +static struct spear_function gpt1_function = { + .name = "gpt1", + .groups = gpt1_grps, + .ngroups = ARRAY_SIZE(gpt1_grps), +}; + +/* Pad multiplexing for mcif device */ +static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214, + 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, + 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, + 243, 244, 245 }; +#define MCIF_MUXREG \ + { \ + .reg = PAD_FUNCTION_EN_0, \ + .mask = PMX_MCI_DATA8_15_MASK, \ + .val = PMX_MCI_DATA8_15_MASK, \ + }, { \ + .reg = PAD_FUNCTION_EN_1, \ + .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ + PMX_NFWPRT2_MASK, \ + .val = PMX_MCIFALL_1_MASK, \ + }, { \ + .reg = PAD_FUNCTION_EN_2, \ + .mask = PMX_MCIFALL_2_MASK, \ + .val = PMX_MCIFALL_2_MASK, \ + }, { \ + .reg = PAD_DIRECTION_SEL_0, \ + .mask = PMX_MCI_DATA8_15_MASK, \ + .val = PMX_MCI_DATA8_15_MASK, \ + }, { \ + .reg = PAD_DIRECTION_SEL_1, \ + .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ + PMX_NFWPRT2_MASK, \ + .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ + PMX_NFWPRT2_MASK, \ + }, { \ + .reg = PAD_DIRECTION_SEL_2, \ + .mask = PMX_MCIFALL_2_MASK, \ + .val = PMX_MCIFALL_2_MASK, \ + } + +/* sdhci device */ +static struct spear_muxreg sdhci_muxreg[] = { + MCIF_MUXREG, + { + .reg = PERIP_CFG, + .mask = MCIF_SEL_MASK, + .val = MCIF_SEL_SD, + }, +}; + +static struct spear_modemux sdhci_modemux[] = { + { + .muxregs = sdhci_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_muxreg), + }, +}; + +static struct spear_pingroup sdhci_pingroup = { + .name = "sdhci_grp", + .pins = mcif_pins, + .npins = ARRAY_SIZE(mcif_pins), + .modemuxs = sdhci_modemux, + .nmodemuxs = ARRAY_SIZE(sdhci_modemux), +}; + +static const char *const sdhci_grps[] = { "sdhci_grp" }; +static struct spear_function sdhci_function = { + .name = "sdhci", + .groups = sdhci_grps, + .ngroups = ARRAY_SIZE(sdhci_grps), +}; + +/* cf device */ +static struct spear_muxreg cf_muxreg[] = { + MCIF_MUXREG, + { + .reg = PERIP_CFG, + .mask = MCIF_SEL_MASK, + .val = MCIF_SEL_CF, + }, +}; + +static struct spear_modemux cf_modemux[] = { + { + .muxregs = cf_muxreg, + .nmuxregs = ARRAY_SIZE(cf_muxreg), + }, +}; + +static struct spear_pingroup cf_pingroup = { + .name = "cf_grp", + .pins = mcif_pins, + .npins = ARRAY_SIZE(mcif_pins), + .modemuxs = cf_modemux, + .nmodemuxs = ARRAY_SIZE(cf_modemux), +}; + +static const char *const cf_grps[] = { "cf_grp" }; +static struct spear_function cf_function = { + .name = "cf", + .groups = cf_grps, + .ngroups = ARRAY_SIZE(cf_grps), +}; + +/* xd device */ +static struct spear_muxreg xd_muxreg[] = { + MCIF_MUXREG, + { + .reg = PERIP_CFG, + .mask = MCIF_SEL_MASK, + .val = MCIF_SEL_XD, + }, +}; + +static struct spear_modemux xd_modemux[] = { + { + .muxregs = xd_muxreg, + .nmuxregs = ARRAY_SIZE(xd_muxreg), + }, +}; + +static struct spear_pingroup xd_pingroup = { + .name = "xd_grp", + .pins = mcif_pins, + .npins = ARRAY_SIZE(mcif_pins), + .modemuxs = xd_modemux, + .nmodemuxs = ARRAY_SIZE(xd_modemux), +}; + +static const char *const xd_grps[] = { "xd_grp" }; +static struct spear_function xd_function = { + .name = "xd", + .groups = xd_grps, + .ngroups = ARRAY_SIZE(xd_grps), +}; + +/* Pad multiplexing for touch_xy device */ +static const unsigned touch_xy_pins[] = { 97 }; +static struct spear_muxreg touch_xy_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_TOUCH_XY_MASK, + .val = PMX_TOUCH_XY_MASK, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_TOUCH_XY_MASK, + .val = PMX_TOUCH_XY_MASK, + }, +}; + +static struct spear_modemux touch_xy_modemux[] = { + { + .muxregs = touch_xy_muxreg, + .nmuxregs = ARRAY_SIZE(touch_xy_muxreg), + }, +}; + +static struct spear_pingroup touch_xy_pingroup = { + .name = "touch_xy_grp", + .pins = touch_xy_pins, + .npins = ARRAY_SIZE(touch_xy_pins), + .modemuxs = touch_xy_modemux, + .nmodemuxs = ARRAY_SIZE(touch_xy_modemux), +}; + +static const char *const touch_xy_grps[] = { "touch_xy_grp" }; +static struct spear_function touch_xy_function = { + .name = "touchscreen", + .groups = touch_xy_grps, + .ngroups = ARRAY_SIZE(touch_xy_grps), +}; + +/* Pad multiplexing for uart1 device */ +/* Muxed with I2C */ +static const unsigned uart1_dis_i2c_pins[] = { 102, 103 }; +static struct spear_muxreg uart1_dis_i2c_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_I2C0_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_I2C0_MASK, + .val = PMX_I2C0_MASK, + }, +}; + +static struct spear_modemux uart1_dis_i2c_modemux[] = { + { + .muxregs = uart1_dis_i2c_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg), + }, +}; + +static struct spear_pingroup uart_1_dis_i2c_pingroup = { + .name = "uart1_disable_i2c_grp", + .pins = uart1_dis_i2c_pins, + .npins = ARRAY_SIZE(uart1_dis_i2c_pins), + .modemuxs = uart1_dis_i2c_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux), +}; + +/* Muxed with SD/MMC */ +static const unsigned uart1_dis_sd_pins[] = { 214, 215 }; +static struct spear_muxreg uart1_dis_sd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_MCIDATA1_MASK | + PMX_MCIDATA2_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_MCIDATA1_MASK | + PMX_MCIDATA2_MASK, + .val = PMX_MCIDATA1_MASK | + PMX_MCIDATA2_MASK, + }, +}; + +static struct spear_modemux uart1_dis_sd_modemux[] = { + { + .muxregs = uart1_dis_sd_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg), + }, +}; + +static struct spear_pingroup uart_1_dis_sd_pingroup = { + .name = "uart1_disable_sd_grp", + .pins = uart1_dis_sd_pins, + .npins = ARRAY_SIZE(uart1_dis_sd_pins), + .modemuxs = uart1_dis_sd_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux), +}; + +static const char *const uart1_grps[] = { "uart1_disable_i2c_grp", + "uart1_disable_sd_grp" }; +static struct spear_function uart1_function = { + .name = "uart1", + .groups = uart1_grps, + .ngroups = ARRAY_SIZE(uart1_grps), +}; + +/* Pad multiplexing for uart2_3 device */ +static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 }; +static struct spear_muxreg uart2_3_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_I2S0_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_I2S0_MASK, + .val = PMX_I2S0_MASK, + }, +}; + +static struct spear_modemux uart2_3_modemux[] = { + { + .muxregs = uart2_3_muxreg, + .nmuxregs = ARRAY_SIZE(uart2_3_muxreg), + }, +}; + +static struct spear_pingroup uart_2_3_pingroup = { + .name = "uart2_3_grp", + .pins = uart2_3_pins, + .npins = ARRAY_SIZE(uart2_3_pins), + .modemuxs = uart2_3_modemux, + .nmodemuxs = ARRAY_SIZE(uart2_3_modemux), +}; + +static const char *const uart2_3_grps[] = { "uart2_3_grp" }; +static struct spear_function uart2_3_function = { + .name = "uart2_3", + .groups = uart2_3_grps, + .ngroups = ARRAY_SIZE(uart2_3_grps), +}; + +/* Pad multiplexing for uart4 device */ +static const unsigned uart4_pins[] = { 108, 113 }; +static struct spear_muxreg uart4_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK, + .val = PMX_I2S0_MASK | PMX_CLCD1_MASK, + }, +}; + +static struct spear_modemux uart4_modemux[] = { + { + .muxregs = uart4_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_muxreg), + }, +}; + +static struct spear_pingroup uart_4_pingroup = { + .name = "uart4_grp", + .pins = uart4_pins, + .npins = ARRAY_SIZE(uart4_pins), + .modemuxs = uart4_modemux, + .nmodemuxs = ARRAY_SIZE(uart4_modemux), +}; + +static const char *const uart4_grps[] = { "uart4_grp" }; +static struct spear_function uart4_function = { + .name = "uart4", + .groups = uart4_grps, + .ngroups = ARRAY_SIZE(uart4_grps), +}; + +/* Pad multiplexing for uart5 device */ +static const unsigned uart5_pins[] = { 114, 115 }; +static struct spear_muxreg uart5_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_CLCD1_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_CLCD1_MASK, + .val = PMX_CLCD1_MASK, + }, +}; + +static struct spear_modemux uart5_modemux[] = { + { + .muxregs = uart5_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_muxreg), + }, +}; + +static struct spear_pingroup uart_5_pingroup = { + .name = "uart5_grp", + .pins = uart5_pins, + .npins = ARRAY_SIZE(uart5_pins), + .modemuxs = uart5_modemux, + .nmodemuxs = ARRAY_SIZE(uart5_modemux), +}; + +static const char *const uart5_grps[] = { "uart5_grp" }; +static struct spear_function uart5_function = { + .name = "uart5", + .groups = uart5_grps, + .ngroups = ARRAY_SIZE(uart5_grps), +}; + +/* Pad multiplexing for rs485_0_1_tdm_0_1 device */ +static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121, + 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, + 136, 137 }; +static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_CLCD1_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_CLCD1_MASK, + .val = PMX_CLCD1_MASK, + }, +}; + +static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = { + { + .muxregs = rs485_0_1_tdm_0_1_muxreg, + .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg), + }, +}; + +static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = { + .name = "rs485_0_1_tdm_0_1_grp", + .pins = rs485_0_1_tdm_0_1_pins, + .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins), + .modemuxs = rs485_0_1_tdm_0_1_modemux, + .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux), +}; + +static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" }; +static struct spear_function rs485_0_1_tdm_0_1_function = { + .name = "rs485_0_1_tdm_0_1", + .groups = rs485_0_1_tdm_0_1_grps, + .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps), +}; + +/* Pad multiplexing for i2c_1_2 device */ +static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 }; +static struct spear_muxreg i2c_1_2_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_CLCD1_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_CLCD1_MASK, + .val = PMX_CLCD1_MASK, + }, +}; + +static struct spear_modemux i2c_1_2_modemux[] = { + { + .muxregs = i2c_1_2_muxreg, + .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg), + }, +}; + +static struct spear_pingroup i2c_1_2_pingroup = { + .name = "i2c_1_2_grp", + .pins = i2c_1_2_pins, + .npins = ARRAY_SIZE(i2c_1_2_pins), + .modemuxs = i2c_1_2_modemux, + .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux), +}; + +static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" }; +static struct spear_function i2c_1_2_function = { + .name = "i2c_1_2", + .groups = i2c_1_2_grps, + .ngroups = ARRAY_SIZE(i2c_1_2_grps), +}; + +/* Pad multiplexing for i2c3_dis_smi_clcd device */ +/* Muxed with SMI & CLCD */ +static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 }; +static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_CLCD1_MASK | PMX_SMI_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_CLCD1_MASK | PMX_SMI_MASK, + .val = PMX_CLCD1_MASK | PMX_SMI_MASK, + }, +}; + +static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = { + { + .muxregs = i2c3_dis_smi_clcd_muxreg, + .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg), + }, +}; + +static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = { + .name = "i2c3_dis_smi_clcd_grp", + .pins = i2c3_dis_smi_clcd_pins, + .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins), + .modemuxs = i2c3_dis_smi_clcd_modemux, + .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux), +}; + +/* Pad multiplexing for i2c3_dis_sd_i2s0 device */ +/* Muxed with SD/MMC & I2S1 */ +static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 }; +static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, + .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, + }, +}; + +static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = { + { + .muxregs = i2c3_dis_sd_i2s0_muxreg, + .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg), + }, +}; + +static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = { + .name = "i2c3_dis_sd_i2s0_grp", + .pins = i2c3_dis_sd_i2s0_pins, + .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins), + .modemuxs = i2c3_dis_sd_i2s0_modemux, + .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux), +}; + +static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp", + "i2c3_dis_sd_i2s0_grp" }; +static struct spear_function i2c3_unction = { + .name = "i2c3_i2s1", + .groups = i2c3_grps, + .ngroups = ARRAY_SIZE(i2c3_grps), +}; + +/* Pad multiplexing for i2c_4_5_dis_smi device */ +/* Muxed with SMI */ +static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 }; +static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_SMI_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_SMI_MASK, + .val = PMX_SMI_MASK, + }, +}; + +static struct spear_modemux i2c_4_5_dis_smi_modemux[] = { + { + .muxregs = i2c_4_5_dis_smi_muxreg, + .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg), + }, +}; + +static struct spear_pingroup i2c_4_5_dis_smi_pingroup = { + .name = "i2c_4_5_dis_smi_grp", + .pins = i2c_4_5_dis_smi_pins, + .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins), + .modemuxs = i2c_4_5_dis_smi_modemux, + .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux), +}; + +/* Pad multiplexing for i2c4_dis_sd device */ +/* Muxed with SD/MMC */ +static const unsigned i2c4_dis_sd_pins[] = { 217, 218 }; +static struct spear_muxreg i2c4_dis_sd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_MCIDATA4_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_MCIDATA5_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_MCIDATA4_MASK, + .val = PMX_MCIDATA4_MASK, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_MCIDATA5_MASK, + .val = PMX_MCIDATA5_MASK, + }, +}; + +static struct spear_modemux i2c4_dis_sd_modemux[] = { + { + .muxregs = i2c4_dis_sd_muxreg, + .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg), + }, +}; + +static struct spear_pingroup i2c4_dis_sd_pingroup = { + .name = "i2c4_dis_sd_grp", + .pins = i2c4_dis_sd_pins, + .npins = ARRAY_SIZE(i2c4_dis_sd_pins), + .modemuxs = i2c4_dis_sd_modemux, + .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux), +}; + +/* Pad multiplexing for i2c5_dis_sd device */ +/* Muxed with SD/MMC */ +static const unsigned i2c5_dis_sd_pins[] = { 219, 220 }; +static struct spear_muxreg i2c5_dis_sd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_MCIDATA6_MASK | + PMX_MCIDATA7_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_MCIDATA6_MASK | + PMX_MCIDATA7_MASK, + .val = PMX_MCIDATA6_MASK | + PMX_MCIDATA7_MASK, + }, +}; + +static struct spear_modemux i2c5_dis_sd_modemux[] = { + { + .muxregs = i2c5_dis_sd_muxreg, + .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg), + }, +}; + +static struct spear_pingroup i2c5_dis_sd_pingroup = { + .name = "i2c5_dis_sd_grp", + .pins = i2c5_dis_sd_pins, + .npins = ARRAY_SIZE(i2c5_dis_sd_pins), + .modemuxs = i2c5_dis_sd_modemux, + .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux), +}; + +static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp", + "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" }; +static struct spear_function i2c_4_5_function = { + .name = "i2c_4_5", + .groups = i2c_4_5_grps, + .ngroups = ARRAY_SIZE(i2c_4_5_grps), +}; + +/* Pad multiplexing for i2c_6_7_dis_kbd device */ +/* Muxed with KBD */ +static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 }; +static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_KBD_ROWCOL25_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_KBD_ROWCOL25_MASK, + .val = PMX_KBD_ROWCOL25_MASK, + }, +}; + +static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = { + { + .muxregs = i2c_6_7_dis_kbd_muxreg, + .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg), + }, +}; + +static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = { + .name = "i2c_6_7_dis_kbd_grp", + .pins = i2c_6_7_dis_kbd_pins, + .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins), + .modemuxs = i2c_6_7_dis_kbd_modemux, + .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux), +}; + +/* Pad multiplexing for i2c6_dis_sd device */ +/* Muxed with SD/MMC */ +static const unsigned i2c6_dis_sd_pins[] = { 236, 237 }; +static struct spear_muxreg i2c6_dis_sd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_MCIIORDRE_MASK | + PMX_MCIIOWRWE_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_MCIIORDRE_MASK | + PMX_MCIIOWRWE_MASK, + .val = PMX_MCIIORDRE_MASK | + PMX_MCIIOWRWE_MASK, + }, +}; + +static struct spear_modemux i2c6_dis_sd_modemux[] = { + { + .muxregs = i2c6_dis_sd_muxreg, + .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg), + }, +}; + +static struct spear_pingroup i2c6_dis_sd_pingroup = { + .name = "i2c6_dis_sd_grp", + .pins = i2c6_dis_sd_pins, + .npins = ARRAY_SIZE(i2c6_dis_sd_pins), + .modemuxs = i2c6_dis_sd_modemux, + .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux), +}; + +/* Pad multiplexing for i2c7_dis_sd device */ +static const unsigned i2c7_dis_sd_pins[] = { 238, 239 }; +static struct spear_muxreg i2c7_dis_sd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_MCIRESETCF_MASK | + PMX_MCICS0CE_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_MCIRESETCF_MASK | + PMX_MCICS0CE_MASK, + .val = PMX_MCIRESETCF_MASK | + PMX_MCICS0CE_MASK, + }, +}; + +static struct spear_modemux i2c7_dis_sd_modemux[] = { + { + .muxregs = i2c7_dis_sd_muxreg, + .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg), + }, +}; + +static struct spear_pingroup i2c7_dis_sd_pingroup = { + .name = "i2c7_dis_sd_grp", + .pins = i2c7_dis_sd_pins, + .npins = ARRAY_SIZE(i2c7_dis_sd_pins), + .modemuxs = i2c7_dis_sd_modemux, + .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux), +}; + +static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp", + "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" }; +static struct spear_function i2c_6_7_function = { + .name = "i2c_6_7", + .groups = i2c_6_7_grps, + .ngroups = ARRAY_SIZE(i2c_6_7_grps), +}; + +/* Pad multiplexing for can0_dis_nor device */ +/* Muxed with NOR */ +static const unsigned can0_dis_nor_pins[] = { 56, 57 }; +static struct spear_muxreg can0_dis_nor_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_NFRSTPWDWN2_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_NFRSTPWDWN3_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_NFRSTPWDWN2_MASK, + .val = PMX_NFRSTPWDWN2_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_NFRSTPWDWN3_MASK, + .val = PMX_NFRSTPWDWN3_MASK, + }, +}; + +static struct spear_modemux can0_dis_nor_modemux[] = { + { + .muxregs = can0_dis_nor_muxreg, + .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg), + }, +}; + +static struct spear_pingroup can0_dis_nor_pingroup = { + .name = "can0_dis_nor_grp", + .pins = can0_dis_nor_pins, + .npins = ARRAY_SIZE(can0_dis_nor_pins), + .modemuxs = can0_dis_nor_modemux, + .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux), +}; + +/* Pad multiplexing for can0_dis_sd device */ +/* Muxed with SD/MMC */ +static const unsigned can0_dis_sd_pins[] = { 240, 241 }; +static struct spear_muxreg can0_dis_sd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, + .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, + }, +}; + +static struct spear_modemux can0_dis_sd_modemux[] = { + { + .muxregs = can0_dis_sd_muxreg, + .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg), + }, +}; + +static struct spear_pingroup can0_dis_sd_pingroup = { + .name = "can0_dis_sd_grp", + .pins = can0_dis_sd_pins, + .npins = ARRAY_SIZE(can0_dis_sd_pins), + .modemuxs = can0_dis_sd_modemux, + .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux), +}; + +static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp" +}; +static struct spear_function can0_function = { + .name = "can0", + .groups = can0_grps, + .ngroups = ARRAY_SIZE(can0_grps), +}; + +/* Pad multiplexing for can1_dis_sd device */ +/* Muxed with SD/MMC */ +static const unsigned can1_dis_sd_pins[] = { 242, 243 }; +static struct spear_muxreg can1_dis_sd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, + .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, + }, +}; + +static struct spear_modemux can1_dis_sd_modemux[] = { + { + .muxregs = can1_dis_sd_muxreg, + .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg), + }, +}; + +static struct spear_pingroup can1_dis_sd_pingroup = { + .name = "can1_dis_sd_grp", + .pins = can1_dis_sd_pins, + .npins = ARRAY_SIZE(can1_dis_sd_pins), + .modemuxs = can1_dis_sd_modemux, + .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux), +}; + +/* Pad multiplexing for can1_dis_kbd device */ +/* Muxed with KBD */ +static const unsigned can1_dis_kbd_pins[] = { 201, 202 }; +static struct spear_muxreg can1_dis_kbd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_KBD_ROWCOL25_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_KBD_ROWCOL25_MASK, + .val = PMX_KBD_ROWCOL25_MASK, + }, +}; + +static struct spear_modemux can1_dis_kbd_modemux[] = { + { + .muxregs = can1_dis_kbd_muxreg, + .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg), + }, +}; + +static struct spear_pingroup can1_dis_kbd_pingroup = { + .name = "can1_dis_kbd_grp", + .pins = can1_dis_kbd_pins, + .npins = ARRAY_SIZE(can1_dis_kbd_pins), + .modemuxs = can1_dis_kbd_modemux, + .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux), +}; + +static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp" +}; +static struct spear_function can1_function = { + .name = "can1", + .groups = can1_grps, + .ngroups = ARRAY_SIZE(can1_grps), +}; + +/* Pad multiplexing for (ras-ip) pci device */ +static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18, + 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, + 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, + 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 }; + +static struct spear_muxreg pci_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_MCI_DATA8_15_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_PCI_REG1_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_PCI_REG2_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_0, + .mask = PMX_MCI_DATA8_15_MASK, + .val = PMX_MCI_DATA8_15_MASK, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_PCI_REG1_MASK, + .val = PMX_PCI_REG1_MASK, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_PCI_REG2_MASK, + .val = PMX_PCI_REG2_MASK, + }, +}; + +static struct spear_modemux pci_modemux[] = { + { + .muxregs = pci_muxreg, + .nmuxregs = ARRAY_SIZE(pci_muxreg), + }, +}; + +static struct spear_pingroup pci_pingroup = { + .name = "pci_grp", + .pins = pci_pins, + .npins = ARRAY_SIZE(pci_pins), + .modemuxs = pci_modemux, + .nmodemuxs = ARRAY_SIZE(pci_modemux), +}; + +static const char *const pci_grps[] = { "pci_grp" }; +static struct spear_function pci_function = { + .name = "pci", + .groups = pci_grps, + .ngroups = ARRAY_SIZE(pci_grps), +}; + +/* pad multiplexing for (fix-part) pcie0 device */ +static struct spear_muxreg pcie0_muxreg[] = { + { + .reg = PCIE_SATA_CFG, + .mask = PCIE_CFG_VAL(0), + .val = PCIE_CFG_VAL(0), + }, +}; + +static struct spear_modemux pcie0_modemux[] = { + { + .muxregs = pcie0_muxreg, + .nmuxregs = ARRAY_SIZE(pcie0_muxreg), + }, +}; + +static struct spear_pingroup pcie0_pingroup = { + .name = "pcie0_grp", + .modemuxs = pcie0_modemux, + .nmodemuxs = ARRAY_SIZE(pcie0_modemux), +}; + +/* pad multiplexing for (fix-part) pcie1 device */ +static struct spear_muxreg pcie1_muxreg[] = { + { + .reg = PCIE_SATA_CFG, + .mask = PCIE_CFG_VAL(1), + .val = PCIE_CFG_VAL(1), + }, +}; + +static struct spear_modemux pcie1_modemux[] = { + { + .muxregs = pcie1_muxreg, + .nmuxregs = ARRAY_SIZE(pcie1_muxreg), + }, +}; + +static struct spear_pingroup pcie1_pingroup = { + .name = "pcie1_grp", + .modemuxs = pcie1_modemux, + .nmodemuxs = ARRAY_SIZE(pcie1_modemux), +}; + +/* pad multiplexing for (fix-part) pcie2 device */ +static struct spear_muxreg pcie2_muxreg[] = { + { + .reg = PCIE_SATA_CFG, + .mask = PCIE_CFG_VAL(2), + .val = PCIE_CFG_VAL(2), + }, +}; + +static struct spear_modemux pcie2_modemux[] = { + { + .muxregs = pcie2_muxreg, + .nmuxregs = ARRAY_SIZE(pcie2_muxreg), + }, +}; + +static struct spear_pingroup pcie2_pingroup = { + .name = "pcie2_grp", + .modemuxs = pcie2_modemux, + .nmodemuxs = ARRAY_SIZE(pcie2_modemux), +}; + +static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" +}; +static struct spear_function pcie_function = { + .name = "pci_express", + .groups = pcie_grps, + .ngroups = ARRAY_SIZE(pcie_grps), +}; + +/* pad multiplexing for sata0 device */ +static struct spear_muxreg sata0_muxreg[] = { + { + .reg = PCIE_SATA_CFG, + .mask = SATA_CFG_VAL(0), + .val = SATA_CFG_VAL(0), + }, +}; + +static struct spear_modemux sata0_modemux[] = { + { + .muxregs = sata0_muxreg, + .nmuxregs = ARRAY_SIZE(sata0_muxreg), + }, +}; + +static struct spear_pingroup sata0_pingroup = { + .name = "sata0_grp", + .modemuxs = sata0_modemux, + .nmodemuxs = ARRAY_SIZE(sata0_modemux), +}; + +/* pad multiplexing for sata1 device */ +static struct spear_muxreg sata1_muxreg[] = { + { + .reg = PCIE_SATA_CFG, + .mask = SATA_CFG_VAL(1), + .val = SATA_CFG_VAL(1), + }, +}; + +static struct spear_modemux sata1_modemux[] = { + { + .muxregs = sata1_muxreg, + .nmuxregs = ARRAY_SIZE(sata1_muxreg), + }, +}; + +static struct spear_pingroup sata1_pingroup = { + .name = "sata1_grp", + .modemuxs = sata1_modemux, + .nmodemuxs = ARRAY_SIZE(sata1_modemux), +}; + +/* pad multiplexing for sata2 device */ +static struct spear_muxreg sata2_muxreg[] = { + { + .reg = PCIE_SATA_CFG, + .mask = SATA_CFG_VAL(2), + .val = SATA_CFG_VAL(2), + }, +}; + +static struct spear_modemux sata2_modemux[] = { + { + .muxregs = sata2_muxreg, + .nmuxregs = ARRAY_SIZE(sata2_muxreg), + }, +}; + +static struct spear_pingroup sata2_pingroup = { + .name = "sata2_grp", + .modemuxs = sata2_modemux, + .nmodemuxs = ARRAY_SIZE(sata2_modemux), +}; + +static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp" +}; +static struct spear_function sata_function = { + .name = "sata", + .groups = sata_grps, + .ngroups = ARRAY_SIZE(sata_grps), +}; + +/* Pad multiplexing for ssp1_dis_kbd device */ +static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 }; +static struct spear_muxreg ssp1_dis_kbd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | + PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | + PMX_NFCE2_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_1, + .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | + PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | + PMX_NFCE2_MASK, + .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | + PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | + PMX_NFCE2_MASK, + }, +}; + +static struct spear_modemux ssp1_dis_kbd_modemux[] = { + { + .muxregs = ssp1_dis_kbd_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg), + }, +}; + +static struct spear_pingroup ssp1_dis_kbd_pingroup = { + .name = "ssp1_dis_kbd_grp", + .pins = ssp1_dis_kbd_pins, + .npins = ARRAY_SIZE(ssp1_dis_kbd_pins), + .modemuxs = ssp1_dis_kbd_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux), +}; + +/* Pad multiplexing for ssp1_dis_sd device */ +static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 }; +static struct spear_muxreg ssp1_dis_sd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | + PMX_MCICECF_MASK | PMX_MCICEXD_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | + PMX_MCICECF_MASK | PMX_MCICEXD_MASK, + .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | + PMX_MCICECF_MASK | PMX_MCICEXD_MASK, + }, +}; + +static struct spear_modemux ssp1_dis_sd_modemux[] = { + { + .muxregs = ssp1_dis_sd_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg), + }, +}; + +static struct spear_pingroup ssp1_dis_sd_pingroup = { + .name = "ssp1_dis_sd_grp", + .pins = ssp1_dis_sd_pins, + .npins = ARRAY_SIZE(ssp1_dis_sd_pins), + .modemuxs = ssp1_dis_sd_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux), +}; + +static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp", + "ssp1_dis_sd_grp" }; +static struct spear_function ssp1_function = { + .name = "ssp1", + .groups = ssp1_grps, + .ngroups = ARRAY_SIZE(ssp1_grps), +}; + +/* Pad multiplexing for gpt64 device */ +static const unsigned gpt64_pins[] = { 230, 231, 232, 245 }; +static struct spear_muxreg gpt64_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK + | PMX_MCILEDS_MASK, + .val = 0, + }, { + .reg = PAD_DIRECTION_SEL_2, + .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK + | PMX_MCILEDS_MASK, + .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK + | PMX_MCILEDS_MASK, + }, +}; + +static struct spear_modemux gpt64_modemux[] = { + { + .muxregs = gpt64_muxreg, + .nmuxregs = ARRAY_SIZE(gpt64_muxreg), + }, +}; + +static struct spear_pingroup gpt64_pingroup = { + .name = "gpt64_grp", + .pins = gpt64_pins, + .npins = ARRAY_SIZE(gpt64_pins), + .modemuxs = gpt64_modemux, + .nmodemuxs = ARRAY_SIZE(gpt64_modemux), +}; + +static const char *const gpt64_grps[] = { "gpt64_grp" }; +static struct spear_function gpt64_function = { + .name = "gpt64", + .groups = gpt64_grps, + .ngroups = ARRAY_SIZE(gpt64_grps), +}; + +/* pingroups */ +static struct spear_pingroup *spear1310_pingroups[] = { + &i2c0_pingroup, + &ssp0_pingroup, + &i2s0_pingroup, + &i2s1_pingroup, + &clcd_pingroup, + &clcd_high_res_pingroup, + &arm_gpio_pingroup, + &smi_2_chips_pingroup, + &smi_4_chips_pingroup, + &gmii_pingroup, + &rgmii_pingroup, + &smii_0_1_2_pingroup, + &ras_mii_txclk_pingroup, + &nand_8bit_pingroup, + &nand_16bit_pingroup, + &nand_4_chips_pingroup, + &keyboard_6x6_pingroup, + &keyboard_rowcol6_8_pingroup, + &uart0_pingroup, + &uart0_modem_pingroup, + &gpt0_tmr0_pingroup, + &gpt0_tmr1_pingroup, + &gpt1_tmr0_pingroup, + &gpt1_tmr1_pingroup, + &sdhci_pingroup, + &cf_pingroup, + &xd_pingroup, + &touch_xy_pingroup, + &ssp0_cs0_pingroup, + &ssp0_cs1_2_pingroup, + &uart_1_dis_i2c_pingroup, + &uart_1_dis_sd_pingroup, + &uart_2_3_pingroup, + &uart_4_pingroup, + &uart_5_pingroup, + &rs485_0_1_tdm_0_1_pingroup, + &i2c_1_2_pingroup, + &i2c3_dis_smi_clcd_pingroup, + &i2c3_dis_sd_i2s0_pingroup, + &i2c_4_5_dis_smi_pingroup, + &i2c4_dis_sd_pingroup, + &i2c5_dis_sd_pingroup, + &i2c_6_7_dis_kbd_pingroup, + &i2c6_dis_sd_pingroup, + &i2c7_dis_sd_pingroup, + &can0_dis_nor_pingroup, + &can0_dis_sd_pingroup, + &can1_dis_sd_pingroup, + &can1_dis_kbd_pingroup, + &pci_pingroup, + &pcie0_pingroup, + &pcie1_pingroup, + &pcie2_pingroup, + &sata0_pingroup, + &sata1_pingroup, + &sata2_pingroup, + &ssp1_dis_kbd_pingroup, + &ssp1_dis_sd_pingroup, + &gpt64_pingroup, +}; + +/* functions */ +static struct spear_function *spear1310_functions[] = { + &i2c0_function, + &ssp0_function, + &i2s0_function, + &i2s1_function, + &clcd_function, + &arm_gpio_function, + &smi_function, + &gmii_function, + &rgmii_function, + &smii_0_1_2_function, + &ras_mii_txclk_function, + &nand_function, + &keyboard_function, + &uart0_function, + &gpt0_function, + &gpt1_function, + &sdhci_function, + &cf_function, + &xd_function, + &touch_xy_function, + &uart1_function, + &uart2_3_function, + &uart4_function, + &uart5_function, + &rs485_0_1_tdm_0_1_function, + &i2c_1_2_function, + &i2c3_unction, + &i2c_4_5_function, + &i2c_6_7_function, + &can0_function, + &can1_function, + &pci_function, + &pcie_function, + &sata_function, + &ssp1_function, + &gpt64_function, +}; + +static const unsigned pin18[] = { 18, }; +static const unsigned pin19[] = { 19, }; +static const unsigned pin20[] = { 20, }; +static const unsigned pin21[] = { 21, }; +static const unsigned pin22[] = { 22, }; +static const unsigned pin23[] = { 23, }; +static const unsigned pin54[] = { 54, }; +static const unsigned pin55[] = { 55, }; +static const unsigned pin56[] = { 56, }; +static const unsigned pin57[] = { 57, }; +static const unsigned pin58[] = { 58, }; +static const unsigned pin59[] = { 59, }; +static const unsigned pin60[] = { 60, }; +static const unsigned pin61[] = { 61, }; +static const unsigned pin62[] = { 62, }; +static const unsigned pin63[] = { 63, }; +static const unsigned pin143[] = { 143, }; +static const unsigned pin144[] = { 144, }; +static const unsigned pin145[] = { 145, }; +static const unsigned pin146[] = { 146, }; +static const unsigned pin147[] = { 147, }; +static const unsigned pin148[] = { 148, }; +static const unsigned pin149[] = { 149, }; +static const unsigned pin150[] = { 150, }; +static const unsigned pin151[] = { 151, }; +static const unsigned pin152[] = { 152, }; +static const unsigned pin205[] = { 205, }; +static const unsigned pin206[] = { 206, }; +static const unsigned pin211[] = { 211, }; +static const unsigned pin212[] = { 212, }; +static const unsigned pin213[] = { 213, }; +static const unsigned pin214[] = { 214, }; +static const unsigned pin215[] = { 215, }; +static const unsigned pin216[] = { 216, }; +static const unsigned pin217[] = { 217, }; +static const unsigned pin218[] = { 218, }; +static const unsigned pin219[] = { 219, }; +static const unsigned pin220[] = { 220, }; +static const unsigned pin221[] = { 221, }; +static const unsigned pin222[] = { 222, }; +static const unsigned pin223[] = { 223, }; +static const unsigned pin224[] = { 224, }; +static const unsigned pin225[] = { 225, }; +static const unsigned pin226[] = { 226, }; +static const unsigned pin227[] = { 227, }; +static const unsigned pin228[] = { 228, }; +static const unsigned pin229[] = { 229, }; +static const unsigned pin230[] = { 230, }; +static const unsigned pin231[] = { 231, }; +static const unsigned pin232[] = { 232, }; +static const unsigned pin233[] = { 233, }; +static const unsigned pin234[] = { 234, }; +static const unsigned pin235[] = { 235, }; +static const unsigned pin236[] = { 236, }; +static const unsigned pin237[] = { 237, }; +static const unsigned pin238[] = { 238, }; +static const unsigned pin239[] = { 239, }; +static const unsigned pin240[] = { 240, }; +static const unsigned pin241[] = { 241, }; +static const unsigned pin242[] = { 242, }; +static const unsigned pin243[] = { 243, }; +static const unsigned pin244[] = { 244, }; +static const unsigned pin245[] = { 245, }; + +static const unsigned pin_grp0[] = { 173, 174, }; +static const unsigned pin_grp1[] = { 175, 185, 188, 197, 198, }; +static const unsigned pin_grp2[] = { 176, 177, 178, 179, 184, 186, 187, 189, + 190, 191, 192, }; +static const unsigned pin_grp3[] = { 180, 181, 182, 183, 193, 194, 195, 196, }; +static const unsigned pin_grp4[] = { 199, 200, }; +static const unsigned pin_grp5[] = { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, + 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; +static const unsigned pin_grp6[] = { 86, 87, 88, 89, 90, 91, 92, 93, }; +static const unsigned pin_grp7[] = { 98, 99, }; +static const unsigned pin_grp8[] = { 158, 159, 160, 161, 162, 163, 164, 165, + 166, 167, 168, 169, 170, 171, 172, }; + +/* Define muxreg arrays */ +DEFINE_2_MUXREG(i2c0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2C0_MASK, 0, 1); +DEFINE_2_MUXREG(ssp0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SSP0_MASK, 0, 1); +DEFINE_2_MUXREG(ssp0_cs0_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS0_MASK, 0, 1); +DEFINE_2_MUXREG(ssp0_cs1_2_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS1_2_MASK, 0, 1); +DEFINE_2_MUXREG(i2s0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2S0_MASK, 0, 1); +DEFINE_2_MUXREG(i2s1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_I2S1_MASK, 0, 1); +DEFINE_2_MUXREG(clcd_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_CLCD1_MASK, 0, 1); +DEFINE_2_MUXREG(clcd_high_res_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_CLCD2_MASK, 0, 1); +DEFINE_2_MUXREG(pin18, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO15_MASK, 0, 1); +DEFINE_2_MUXREG(pin19, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO14_MASK, 0, 1); +DEFINE_2_MUXREG(pin20, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO13_MASK, 0, 1); +DEFINE_2_MUXREG(pin21, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO12_MASK, 0, 1); +DEFINE_2_MUXREG(pin22, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO11_MASK, 0, 1); +DEFINE_2_MUXREG(pin23, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO10_MASK, 0, 1); +DEFINE_2_MUXREG(pin143, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO00_MASK, 0, 1); +DEFINE_2_MUXREG(pin144, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO01_MASK, 0, 1); +DEFINE_2_MUXREG(pin145, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO02_MASK, 0, 1); +DEFINE_2_MUXREG(pin146, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO03_MASK, 0, 1); +DEFINE_2_MUXREG(pin147, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO04_MASK, 0, 1); +DEFINE_2_MUXREG(pin148, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO05_MASK, 0, 1); +DEFINE_2_MUXREG(pin149, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO06_MASK, 0, 1); +DEFINE_2_MUXREG(pin150, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO07_MASK, 0, 1); +DEFINE_2_MUXREG(pin151, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO08_MASK, 0, 1); +DEFINE_2_MUXREG(pin152, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO09_MASK, 0, 1); +DEFINE_2_MUXREG(smi_2_chips_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SMI_MASK, 0, 1); +DEFINE_2_MUXREG(pin54, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS3_MASK, 0, 1); +DEFINE_2_MUXREG(pin55, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS2_MASK, 0, 1); +DEFINE_2_MUXREG(pin56, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFRSTPWDWN3_MASK, 0, 1); +DEFINE_2_MUXREG(pin57, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN2_MASK, 0, 1); +DEFINE_2_MUXREG(pin58, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN1_MASK, 0, 1); +DEFINE_2_MUXREG(pin59, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN0_MASK, 0, 1); +DEFINE_2_MUXREG(pin60, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFWPRT3_MASK, 0, 1); +DEFINE_2_MUXREG(pin61, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFCE3_MASK, 0, 1); +DEFINE_2_MUXREG(pin62, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD25_MASK, 0, 1); +DEFINE_2_MUXREG(pin63, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD24_MASK, 0, 1); +DEFINE_2_MUXREG(pin_grp0, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICLK_MASK, 0, 1); +DEFINE_2_MUXREG(pin_grp1, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK, 0, 1); +DEFINE_2_MUXREG(pin_grp2, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_RXCLK_RDV_TXEN_D03_MASK, 0, 1); +DEFINE_2_MUXREG(pin_grp3, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIID47_MASK, 0, 1); +DEFINE_2_MUXREG(pin_grp4, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MDC_MDIO_MASK, 0, 1); +DEFINE_2_MUXREG(pin_grp5, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD23_MASK, 0, 1); +DEFINE_2_MUXREG(pin_grp6, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MCI_DATA8_15_MASK, 0, 1); +DEFINE_2_MUXREG(pin_grp7, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFCE2_MASK, 0, 1); +DEFINE_2_MUXREG(pin_grp8, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND8_MASK, 0, 1); +DEFINE_2_MUXREG(nand_16bit_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND16BIT_1_MASK, 0, 1); +DEFINE_2_MUXREG(pin205, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL1_MASK | PMX_NFCE1_MASK, 0, 1); +DEFINE_2_MUXREG(pin206, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL0_MASK | PMX_NFCE2_MASK, 0, 1); +DEFINE_2_MUXREG(pin211, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK, 0, 1); +DEFINE_2_MUXREG(pin212, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK, 0, 1); +DEFINE_2_MUXREG(pin213, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA0_MASK, 0, 1); +DEFINE_2_MUXREG(pin214, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA1_MASK, 0, 1); +DEFINE_2_MUXREG(pin215, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA2_MASK, 0, 1); +DEFINE_2_MUXREG(pin216, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA3_MASK, 0, 1); +DEFINE_2_MUXREG(pin217, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA4_MASK, 0, 1); +DEFINE_2_MUXREG(pin218, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA5_MASK, 0, 1); +DEFINE_2_MUXREG(pin219, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA6_MASK, 0, 1); +DEFINE_2_MUXREG(pin220, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA7_MASK, 0, 1); +DEFINE_2_MUXREG(pin221, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA1SD_MASK, 0, 1); +DEFINE_2_MUXREG(pin222, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA2SD_MASK, 0, 1); +DEFINE_2_MUXREG(pin223, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA3SD_MASK, 0, 1); +DEFINE_2_MUXREG(pin224, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR0ALE_MASK, 0, 1); +DEFINE_2_MUXREG(pin225, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR1CLECLK_MASK, 0, 1); +DEFINE_2_MUXREG(pin226, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR2_MASK, 0, 1); +DEFINE_2_MUXREG(pin227, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICECF_MASK, 0, 1); +DEFINE_2_MUXREG(pin228, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICEXD_MASK, 0, 1); +DEFINE_2_MUXREG(pin229, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICESDMMC_MASK, 0, 1); +DEFINE_2_MUXREG(pin230, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF1_MASK, 0, 1); +DEFINE_2_MUXREG(pin231, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF2_MASK, 0, 1); +DEFINE_2_MUXREG(pin232, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDXD_MASK, 0, 1); +DEFINE_2_MUXREG(pin233, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDSDMMC_MASK, 0, 1); +DEFINE_2_MUXREG(pin234, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATADIR_MASK, 0, 1); +DEFINE_2_MUXREG(pin235, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMARQWP_MASK, 0, 1); +DEFINE_2_MUXREG(pin236, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDRE_MASK, 0, 1); +DEFINE_2_MUXREG(pin237, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIOWRWE_MASK, 0, 1); +DEFINE_2_MUXREG(pin238, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIRESETCF_MASK, 0, 1); +DEFINE_2_MUXREG(pin239, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS0CE_MASK, 0, 1); +DEFINE_2_MUXREG(pin240, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICFINTR_MASK, 0, 1); +DEFINE_2_MUXREG(pin241, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDY_MASK, 0, 1); +DEFINE_2_MUXREG(pin242, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS1_MASK, 0, 1); +DEFINE_2_MUXREG(pin243, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMAACK_MASK, 0, 1); +DEFINE_2_MUXREG(pin244, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCISDCMD_MASK, 0, 1); +DEFINE_2_MUXREG(pin245, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCILEDS_MASK, 0, 1); +DEFINE_2_MUXREG(keyboard_rowcol6_8_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROWCOL68_MASK, 0, 1); +DEFINE_2_MUXREG(uart0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_UART0_MASK, 0, 1); +DEFINE_2_MUXREG(uart0_modem_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_UART0_MODEM_MASK, 0, 1); +DEFINE_2_MUXREG(gpt0_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR0_MASK, 0, 1); +DEFINE_2_MUXREG(gpt0_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR1_MASK, 0, 1); +DEFINE_2_MUXREG(gpt1_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR0_MASK, 0, 1); +DEFINE_2_MUXREG(gpt1_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR1_MASK, 0, 1); +DEFINE_2_MUXREG(touch_xy_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_TOUCH_XY_MASK, 0, 1); + +static struct spear_gpio_pingroup spear1310_gpio_pingroup[] = { + GPIO_PINGROUP(i2c0_pins), + GPIO_PINGROUP(ssp0_pins), + GPIO_PINGROUP(ssp0_cs0_pins), + GPIO_PINGROUP(ssp0_cs1_2_pins), + GPIO_PINGROUP(i2s0_pins), + GPIO_PINGROUP(i2s1_pins), + GPIO_PINGROUP(clcd_pins), + GPIO_PINGROUP(clcd_high_res_pins), + GPIO_PINGROUP(pin18), + GPIO_PINGROUP(pin19), + GPIO_PINGROUP(pin20), + GPIO_PINGROUP(pin21), + GPIO_PINGROUP(pin22), + GPIO_PINGROUP(pin23), + GPIO_PINGROUP(pin143), + GPIO_PINGROUP(pin144), + GPIO_PINGROUP(pin145), + GPIO_PINGROUP(pin146), + GPIO_PINGROUP(pin147), + GPIO_PINGROUP(pin148), + GPIO_PINGROUP(pin149), + GPIO_PINGROUP(pin150), + GPIO_PINGROUP(pin151), + GPIO_PINGROUP(pin152), + GPIO_PINGROUP(smi_2_chips_pins), + GPIO_PINGROUP(pin54), + GPIO_PINGROUP(pin55), + GPIO_PINGROUP(pin56), + GPIO_PINGROUP(pin57), + GPIO_PINGROUP(pin58), + GPIO_PINGROUP(pin59), + GPIO_PINGROUP(pin60), + GPIO_PINGROUP(pin61), + GPIO_PINGROUP(pin62), + GPIO_PINGROUP(pin63), + GPIO_PINGROUP(pin_grp0), + GPIO_PINGROUP(pin_grp1), + GPIO_PINGROUP(pin_grp2), + GPIO_PINGROUP(pin_grp3), + GPIO_PINGROUP(pin_grp4), + GPIO_PINGROUP(pin_grp5), + GPIO_PINGROUP(pin_grp6), + GPIO_PINGROUP(pin_grp7), + GPIO_PINGROUP(pin_grp8), + GPIO_PINGROUP(nand_16bit_pins), + GPIO_PINGROUP(pin205), + GPIO_PINGROUP(pin206), + GPIO_PINGROUP(pin211), + GPIO_PINGROUP(pin212), + GPIO_PINGROUP(pin213), + GPIO_PINGROUP(pin214), + GPIO_PINGROUP(pin215), + GPIO_PINGROUP(pin216), + GPIO_PINGROUP(pin217), + GPIO_PINGROUP(pin218), + GPIO_PINGROUP(pin219), + GPIO_PINGROUP(pin220), + GPIO_PINGROUP(pin221), + GPIO_PINGROUP(pin222), + GPIO_PINGROUP(pin223), + GPIO_PINGROUP(pin224), + GPIO_PINGROUP(pin225), + GPIO_PINGROUP(pin226), + GPIO_PINGROUP(pin227), + GPIO_PINGROUP(pin228), + GPIO_PINGROUP(pin229), + GPIO_PINGROUP(pin230), + GPIO_PINGROUP(pin231), + GPIO_PINGROUP(pin232), + GPIO_PINGROUP(pin233), + GPIO_PINGROUP(pin234), + GPIO_PINGROUP(pin235), + GPIO_PINGROUP(pin236), + GPIO_PINGROUP(pin237), + GPIO_PINGROUP(pin238), + GPIO_PINGROUP(pin239), + GPIO_PINGROUP(pin240), + GPIO_PINGROUP(pin241), + GPIO_PINGROUP(pin242), + GPIO_PINGROUP(pin243), + GPIO_PINGROUP(pin244), + GPIO_PINGROUP(pin245), + GPIO_PINGROUP(keyboard_rowcol6_8_pins), + GPIO_PINGROUP(uart0_pins), + GPIO_PINGROUP(uart0_modem_pins), + GPIO_PINGROUP(gpt0_tmr0_pins), + GPIO_PINGROUP(gpt0_tmr1_pins), + GPIO_PINGROUP(gpt1_tmr0_pins), + GPIO_PINGROUP(gpt1_tmr1_pins), + GPIO_PINGROUP(touch_xy_pins), +}; + +static struct spear_pinctrl_machdata spear1310_machdata = { + .pins = spear1310_pins, + .npins = ARRAY_SIZE(spear1310_pins), + .groups = spear1310_pingroups, + .ngroups = ARRAY_SIZE(spear1310_pingroups), + .functions = spear1310_functions, + .nfunctions = ARRAY_SIZE(spear1310_functions), + .gpio_pingroups = spear1310_gpio_pingroup, + .ngpio_pingroups = ARRAY_SIZE(spear1310_gpio_pingroup), + .modes_supported = false, +}; + +static const struct of_device_id spear1310_pinctrl_of_match[] = { + { + .compatible = "st,spear1310-pinmux", + }, + {}, +}; + +static int spear1310_pinctrl_probe(struct platform_device *pdev) +{ + return spear_pinctrl_probe(pdev, &spear1310_machdata); +} + +static struct platform_driver spear1310_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = spear1310_pinctrl_of_match, + }, + .probe = spear1310_pinctrl_probe, +}; + +static int __init spear1310_pinctrl_init(void) +{ + return platform_driver_register(&spear1310_pinctrl_driver); +} +arch_initcall(spear1310_pinctrl_init); diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c new file mode 100644 index 000000000..0ca961219 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear1340.c @@ -0,0 +1,2034 @@ +/* + * Driver for the ST Microelectronics SPEAr1340 pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <vireshk@kernel.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "pinctrl-spear.h" + +#define DRIVER_NAME "spear1340-pinmux" + +/* pins */ +static const struct pinctrl_pin_desc spear1340_pins[] = { + SPEAR_PIN_0_TO_101, + SPEAR_PIN_102_TO_245, + PINCTRL_PIN(246, "PLGPIO246"), + PINCTRL_PIN(247, "PLGPIO247"), + PINCTRL_PIN(248, "PLGPIO248"), + PINCTRL_PIN(249, "PLGPIO249"), + PINCTRL_PIN(250, "PLGPIO250"), + PINCTRL_PIN(251, "PLGPIO251"), +}; + +/* In SPEAr1340 there are two levels of pad muxing */ +/* - pads as gpio OR peripherals */ +#define PAD_FUNCTION_EN_1 0x668 +#define PAD_FUNCTION_EN_2 0x66C +#define PAD_FUNCTION_EN_3 0x670 +#define PAD_FUNCTION_EN_4 0x674 +#define PAD_FUNCTION_EN_5 0x690 +#define PAD_FUNCTION_EN_6 0x694 +#define PAD_FUNCTION_EN_7 0x698 +#define PAD_FUNCTION_EN_8 0x69C + +/* - If peripherals, then primary OR alternate peripheral */ +#define PAD_SHARED_IP_EN_1 0x6A0 +#define PAD_SHARED_IP_EN_2 0x6A4 + +/* + * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8 + * registers with 32 bits each for handling gpio pads, register 8 has only 26 + * relevant bits. + */ +/* macro's for making pads as gpio's */ +#define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE +#define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF +#define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF + +/* macro's for making pads as peripherals */ +#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE +#define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000 +#define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000 +#define I2C1_REG0_MASK 0x01080000 +#define SPDIF_IN_REG0_MASK 0x00100000 +#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000 +#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000 +#define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000 +#define VIP_AND_CAM3_REG0_MASK 0xFC200000 +#define VIP_AND_CAM3_REG1_MASK 0x0000000F +#define VIP_REG1_MASK 0x00001EF0 +#define VIP_AND_CAM2_REG1_MASK 0x007FE100 +#define VIP_AND_CAM1_REG1_MASK 0xFF800000 +#define VIP_AND_CAM1_REG2_MASK 0x00000003 +#define VIP_AND_CAM0_REG2_MASK 0x00001FFC +#define SMI_REG2_MASK 0x0021E000 +#define SSP0_REG2_MASK 0x001E0000 +#define TS_AND_SSP0_CS2_REG2_MASK 0x00400000 +#define UART0_REG2_MASK 0x01800000 +#define UART1_REG2_MASK 0x06000000 +#define I2S_IN_REG2_MASK 0xF8000000 +#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE +#define I2S_OUT_REG3_MASK 0x000001EF +#define I2S_IN_REG3_MASK 0x00000010 +#define GMAC_REG3_MASK 0xFFFFFE00 +#define GMAC_REG4_MASK 0x0000001F +#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20 +#define SSP0_CS3_REG4_MASK 0x00000020 +#define I2C0_REG4_MASK 0x000000C0 +#define CEC0_REG4_MASK 0x00000100 +#define CEC1_REG4_MASK 0x00000200 +#define SPDIF_OUT_REG4_MASK 0x00000400 +#define CLCD_REG4_MASK 0x7FFFF800 +#define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000 +#define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF +#define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001 +#define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE +#define MCIF_REG6_MASK 0xF8C00000 +#define MCIF_REG7_MASK 0x000043FF +#define FSMC_8BIT_REG7_MASK 0x07FFBC00 + +/* other registers */ +#define PERIP_CFG 0x42C + /* PERIP_CFG register masks */ + #define SSP_CS_CTL_HW 0 + #define SSP_CS_CTL_SW 1 + #define SSP_CS_CTL_MASK 1 + #define SSP_CS_CTL_SHIFT 21 + #define SSP_CS_VAL_MASK 1 + #define SSP_CS_VAL_SHIFT 20 + #define SSP_CS_SEL_CS0 0 + #define SSP_CS_SEL_CS1 1 + #define SSP_CS_SEL_CS2 2 + #define SSP_CS_SEL_MASK 3 + #define SSP_CS_SEL_SHIFT 18 + + #define I2S_CHNL_2_0 (0) + #define I2S_CHNL_3_1 (1) + #define I2S_CHNL_5_1 (2) + #define I2S_CHNL_7_1 (3) + #define I2S_CHNL_PLAY_SHIFT (4) + #define I2S_CHNL_PLAY_MASK (3 << 4) + #define I2S_CHNL_REC_SHIFT (6) + #define I2S_CHNL_REC_MASK (3 << 6) + + #define SPDIF_OUT_ENB_MASK (1 << 2) + #define SPDIF_OUT_ENB_SHIFT 2 + + #define MCIF_SEL_SD 1 + #define MCIF_SEL_CF 2 + #define MCIF_SEL_XD 3 + #define MCIF_SEL_MASK 3 + #define MCIF_SEL_SHIFT 0 + +#define GMAC_CLK_CFG 0x248 + #define GMAC_PHY_IF_GMII_VAL (0 << 3) + #define GMAC_PHY_IF_RGMII_VAL (1 << 3) + #define GMAC_PHY_IF_SGMII_VAL (2 << 3) + #define GMAC_PHY_IF_RMII_VAL (4 << 3) + #define GMAC_PHY_IF_SEL_MASK (7 << 3) + #define GMAC_PHY_INPUT_ENB_VAL 0 + #define GMAC_PHY_SYNT_ENB_VAL 1 + #define GMAC_PHY_CLK_MASK 1 + #define GMAC_PHY_CLK_SHIFT 2 + #define GMAC_PHY_125M_PAD_VAL 0 + #define GMAC_PHY_PLL2_VAL 1 + #define GMAC_PHY_OSC3_VAL 2 + #define GMAC_PHY_INPUT_CLK_MASK 3 + #define GMAC_PHY_INPUT_CLK_SHIFT 0 + +#define PCIE_SATA_CFG 0x424 + /* PCIE CFG MASks */ + #define PCIE_CFG_DEVICE_PRESENT (1 << 11) + #define PCIE_CFG_POWERUP_RESET (1 << 10) + #define PCIE_CFG_CORE_CLK_EN (1 << 9) + #define PCIE_CFG_AUX_CLK_EN (1 << 8) + #define SATA_CFG_TX_CLK_EN (1 << 4) + #define SATA_CFG_RX_CLK_EN (1 << 3) + #define SATA_CFG_POWERUP_RESET (1 << 2) + #define SATA_CFG_PM_CLK_EN (1 << 1) + #define PCIE_SATA_SEL_PCIE (0) + #define PCIE_SATA_SEL_SATA (1) + #define SATA_PCIE_CFG_MASK 0xF1F + #define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \ + PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\ + PCIE_CFG_DEVICE_PRESENT) + #define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \ + SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \ + SATA_CFG_TX_CLK_EN) + +/* Macro's for second level of pmx - pads as primary OR alternate peripheral */ +/* Write 0 to enable FSMC_16_BIT */ +#define KBD_ROW_COL_MASK (1 << 0) + +/* Write 0 to enable UART0_ENH */ +#define GPT_MASK (1 << 1) /* Only clk & cpt */ + +/* Write 0 to enable PWM1 */ +#define KBD_COL5_MASK (1 << 2) + +/* Write 0 to enable PWM2 */ +#define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */ + +/* Write 0 to enable PWM3 */ +#define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */ + +/* Write 0 to enable PWM0 */ +#define SSP0_CS1_MASK (1 << 5) + +/* Write 0 to enable VIP */ +#define CAM3_MASK (1 << 6) + +/* Write 0 to enable VIP */ +#define CAM2_MASK (1 << 7) + +/* Write 0 to enable VIP */ +#define CAM1_MASK (1 << 8) + +/* Write 0 to enable VIP */ +#define CAM0_MASK (1 << 9) + +/* Write 0 to enable TS */ +#define SSP0_CS2_MASK (1 << 10) + +/* Write 0 to enable FSMC PNOR */ +#define MCIF_MASK (1 << 11) + +/* Write 0 to enable CLCD */ +#define ARM_TRACE_MASK (1 << 12) + +/* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */ +#define MIPHY_DBG_MASK (1 << 13) + +/* + * Pad multiplexing for making all pads as gpio's. This is done to override the + * values passed from bootloader and start from scratch. + */ +static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 }; +static struct spear_muxreg pads_as_gpio_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PADS_AS_GPIO_REG0_MASK, + .val = 0x0, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = PADS_AS_GPIO_REGS_MASK, + .val = 0x0, + }, { + .reg = PAD_FUNCTION_EN_3, + .mask = PADS_AS_GPIO_REGS_MASK, + .val = 0x0, + }, { + .reg = PAD_FUNCTION_EN_4, + .mask = PADS_AS_GPIO_REGS_MASK, + .val = 0x0, + }, { + .reg = PAD_FUNCTION_EN_5, + .mask = PADS_AS_GPIO_REGS_MASK, + .val = 0x0, + }, { + .reg = PAD_FUNCTION_EN_6, + .mask = PADS_AS_GPIO_REGS_MASK, + .val = 0x0, + }, { + .reg = PAD_FUNCTION_EN_7, + .mask = PADS_AS_GPIO_REGS_MASK, + .val = 0x0, + }, { + .reg = PAD_FUNCTION_EN_8, + .mask = PADS_AS_GPIO_REG7_MASK, + .val = 0x0, + }, +}; + +static struct spear_modemux pads_as_gpio_modemux[] = { + { + .muxregs = pads_as_gpio_muxreg, + .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg), + }, +}; + +static struct spear_pingroup pads_as_gpio_pingroup = { + .name = "pads_as_gpio_grp", + .pins = pads_as_gpio_pins, + .npins = ARRAY_SIZE(pads_as_gpio_pins), + .modemuxs = pads_as_gpio_modemux, + .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux), +}; + +static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" }; +static struct spear_function pads_as_gpio_function = { + .name = "pads_as_gpio", + .groups = pads_as_gpio_grps, + .ngroups = ARRAY_SIZE(pads_as_gpio_grps), +}; + +/* Pad multiplexing for fsmc_8bit device */ +static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240, + 241, 242, 243, 244, 245, 246, 247, 248, 249 }; +static struct spear_muxreg fsmc_8bit_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_8, + .mask = FSMC_8BIT_REG7_MASK, + .val = FSMC_8BIT_REG7_MASK, + } +}; + +static struct spear_modemux fsmc_8bit_modemux[] = { + { + .muxregs = fsmc_8bit_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), + }, +}; + +static struct spear_pingroup fsmc_8bit_pingroup = { + .name = "fsmc_8bit_grp", + .pins = fsmc_8bit_pins, + .npins = ARRAY_SIZE(fsmc_8bit_pins), + .modemuxs = fsmc_8bit_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), +}; + +/* Pad multiplexing for fsmc_16bit device */ +static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 }; +static struct spear_muxreg fsmc_16bit_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = KBD_ROW_COL_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, + .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, + }, +}; + +static struct spear_modemux fsmc_16bit_modemux[] = { + { + .muxregs = fsmc_16bit_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), + }, +}; + +static struct spear_pingroup fsmc_16bit_pingroup = { + .name = "fsmc_16bit_grp", + .pins = fsmc_16bit_pins, + .npins = ARRAY_SIZE(fsmc_16bit_pins), + .modemuxs = fsmc_16bit_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), +}; + +/* pad multiplexing for fsmc_pnor device */ +static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198, + 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, + 215, 216, 217 }; +static struct spear_muxreg fsmc_pnor_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = MCIF_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_7, + .mask = FSMC_PNOR_AND_MCIF_REG6_MASK, + .val = FSMC_PNOR_AND_MCIF_REG6_MASK, + }, +}; + +static struct spear_modemux fsmc_pnor_modemux[] = { + { + .muxregs = fsmc_pnor_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg), + }, +}; + +static struct spear_pingroup fsmc_pnor_pingroup = { + .name = "fsmc_pnor_grp", + .pins = fsmc_pnor_pins, + .npins = ARRAY_SIZE(fsmc_pnor_pins), + .modemuxs = fsmc_pnor_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux), +}; + +static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp", + "fsmc_pnor_grp" }; +static struct spear_function fsmc_function = { + .name = "fsmc", + .groups = fsmc_grps, + .ngroups = ARRAY_SIZE(fsmc_grps), +}; + +/* pad multiplexing for keyboard rows-cols device */ +static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 10 }; +static struct spear_muxreg keyboard_row_col_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = KBD_ROW_COL_MASK, + .val = KBD_ROW_COL_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, + .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, + }, +}; + +static struct spear_modemux keyboard_row_col_modemux[] = { + { + .muxregs = keyboard_row_col_muxreg, + .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg), + }, +}; + +static struct spear_pingroup keyboard_row_col_pingroup = { + .name = "keyboard_row_col_grp", + .pins = keyboard_row_col_pins, + .npins = ARRAY_SIZE(keyboard_row_col_pins), + .modemuxs = keyboard_row_col_modemux, + .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux), +}; + +/* pad multiplexing for keyboard col5 device */ +static const unsigned keyboard_col5_pins[] = { 17 }; +static struct spear_muxreg keyboard_col5_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = KBD_COL5_MASK, + .val = KBD_COL5_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PWM1_AND_KBD_COL5_REG0_MASK, + .val = PWM1_AND_KBD_COL5_REG0_MASK, + }, +}; + +static struct spear_modemux keyboard_col5_modemux[] = { + { + .muxregs = keyboard_col5_muxreg, + .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg), + }, +}; + +static struct spear_pingroup keyboard_col5_pingroup = { + .name = "keyboard_col5_grp", + .pins = keyboard_col5_pins, + .npins = ARRAY_SIZE(keyboard_col5_pins), + .modemuxs = keyboard_col5_modemux, + .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux), +}; + +static const char *const keyboard_grps[] = { "keyboard_row_col_grp", + "keyboard_col5_grp" }; +static struct spear_function keyboard_function = { + .name = "keyboard", + .groups = keyboard_grps, + .ngroups = ARRAY_SIZE(keyboard_grps), +}; + +/* pad multiplexing for spdif_in device */ +static const unsigned spdif_in_pins[] = { 19 }; +static struct spear_muxreg spdif_in_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = SPDIF_IN_REG0_MASK, + .val = SPDIF_IN_REG0_MASK, + }, +}; + +static struct spear_modemux spdif_in_modemux[] = { + { + .muxregs = spdif_in_muxreg, + .nmuxregs = ARRAY_SIZE(spdif_in_muxreg), + }, +}; + +static struct spear_pingroup spdif_in_pingroup = { + .name = "spdif_in_grp", + .pins = spdif_in_pins, + .npins = ARRAY_SIZE(spdif_in_pins), + .modemuxs = spdif_in_modemux, + .nmodemuxs = ARRAY_SIZE(spdif_in_modemux), +}; + +static const char *const spdif_in_grps[] = { "spdif_in_grp" }; +static struct spear_function spdif_in_function = { + .name = "spdif_in", + .groups = spdif_in_grps, + .ngroups = ARRAY_SIZE(spdif_in_grps), +}; + +/* pad multiplexing for spdif_out device */ +static const unsigned spdif_out_pins[] = { 137 }; +static struct spear_muxreg spdif_out_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_5, + .mask = SPDIF_OUT_REG4_MASK, + .val = SPDIF_OUT_REG4_MASK, + }, { + .reg = PERIP_CFG, + .mask = SPDIF_OUT_ENB_MASK, + .val = SPDIF_OUT_ENB_MASK, + } +}; + +static struct spear_modemux spdif_out_modemux[] = { + { + .muxregs = spdif_out_muxreg, + .nmuxregs = ARRAY_SIZE(spdif_out_muxreg), + }, +}; + +static struct spear_pingroup spdif_out_pingroup = { + .name = "spdif_out_grp", + .pins = spdif_out_pins, + .npins = ARRAY_SIZE(spdif_out_pins), + .modemuxs = spdif_out_modemux, + .nmodemuxs = ARRAY_SIZE(spdif_out_modemux), +}; + +static const char *const spdif_out_grps[] = { "spdif_out_grp" }; +static struct spear_function spdif_out_function = { + .name = "spdif_out", + .groups = spdif_out_grps, + .ngroups = ARRAY_SIZE(spdif_out_grps), +}; + +/* pad multiplexing for gpt_0_1 device */ +static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 }; +static struct spear_muxreg gpt_0_1_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, + .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = UART0_ENH_AND_GPT_REG0_MASK | + PWM2_AND_GPT0_TMR0_CPT_REG0_MASK | + PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, + .val = UART0_ENH_AND_GPT_REG0_MASK | + PWM2_AND_GPT0_TMR0_CPT_REG0_MASK | + PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, + }, +}; + +static struct spear_modemux gpt_0_1_modemux[] = { + { + .muxregs = gpt_0_1_muxreg, + .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg), + }, +}; + +static struct spear_pingroup gpt_0_1_pingroup = { + .name = "gpt_0_1_grp", + .pins = gpt_0_1_pins, + .npins = ARRAY_SIZE(gpt_0_1_pins), + .modemuxs = gpt_0_1_modemux, + .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux), +}; + +static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" }; +static struct spear_function gpt_0_1_function = { + .name = "gpt_0_1", + .groups = gpt_0_1_grps, + .ngroups = ARRAY_SIZE(gpt_0_1_grps), +}; + +/* pad multiplexing for pwm0 device */ +static const unsigned pwm0_pins[] = { 24 }; +static struct spear_muxreg pwm0_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = SSP0_CS1_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PWM0_AND_SSP0_CS1_REG0_MASK, + .val = PWM0_AND_SSP0_CS1_REG0_MASK, + }, +}; + +static struct spear_modemux pwm0_modemux[] = { + { + .muxregs = pwm0_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_muxreg), + }, +}; + +static struct spear_pingroup pwm0_pingroup = { + .name = "pwm0_grp", + .pins = pwm0_pins, + .npins = ARRAY_SIZE(pwm0_pins), + .modemuxs = pwm0_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_modemux), +}; + +/* pad multiplexing for pwm1 device */ +static const unsigned pwm1_pins[] = { 17 }; +static struct spear_muxreg pwm1_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = KBD_COL5_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PWM1_AND_KBD_COL5_REG0_MASK, + .val = PWM1_AND_KBD_COL5_REG0_MASK, + }, +}; + +static struct spear_modemux pwm1_modemux[] = { + { + .muxregs = pwm1_muxreg, + .nmuxregs = ARRAY_SIZE(pwm1_muxreg), + }, +}; + +static struct spear_pingroup pwm1_pingroup = { + .name = "pwm1_grp", + .pins = pwm1_pins, + .npins = ARRAY_SIZE(pwm1_pins), + .modemuxs = pwm1_modemux, + .nmodemuxs = ARRAY_SIZE(pwm1_modemux), +}; + +/* pad multiplexing for pwm2 device */ +static const unsigned pwm2_pins[] = { 21 }; +static struct spear_muxreg pwm2_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = GPT0_TMR0_CPT_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, + .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, + }, +}; + +static struct spear_modemux pwm2_modemux[] = { + { + .muxregs = pwm2_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_muxreg), + }, +}; + +static struct spear_pingroup pwm2_pingroup = { + .name = "pwm2_grp", + .pins = pwm2_pins, + .npins = ARRAY_SIZE(pwm2_pins), + .modemuxs = pwm2_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_modemux), +}; + +/* pad multiplexing for pwm3 device */ +static const unsigned pwm3_pins[] = { 22 }; +static struct spear_muxreg pwm3_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = GPT0_TMR1_CLK_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, + .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, + }, +}; + +static struct spear_modemux pwm3_modemux[] = { + { + .muxregs = pwm3_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_muxreg), + }, +}; + +static struct spear_pingroup pwm3_pingroup = { + .name = "pwm3_grp", + .pins = pwm3_pins, + .npins = ARRAY_SIZE(pwm3_pins), + .modemuxs = pwm3_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_modemux), +}; + +static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp", + "pwm3_grp" }; +static struct spear_function pwm_function = { + .name = "pwm", + .groups = pwm_grps, + .ngroups = ARRAY_SIZE(pwm_grps), +}; + +/* pad multiplexing for vip_mux device */ +static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 }; +static struct spear_muxreg vip_mux_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = VIP_REG1_MASK, + .val = VIP_REG1_MASK, + }, +}; + +static struct spear_modemux vip_mux_modemux[] = { + { + .muxregs = vip_mux_muxreg, + .nmuxregs = ARRAY_SIZE(vip_mux_muxreg), + }, +}; + +static struct spear_pingroup vip_mux_pingroup = { + .name = "vip_mux_grp", + .pins = vip_mux_pins, + .npins = ARRAY_SIZE(vip_mux_pins), + .modemuxs = vip_mux_modemux, + .nmodemuxs = ARRAY_SIZE(vip_mux_modemux), +}; + +/* pad multiplexing for vip_mux_cam0 (disables cam0) device */ +static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, + 73, 74, 75 }; +static struct spear_muxreg vip_mux_cam0_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = CAM0_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_3, + .mask = VIP_AND_CAM0_REG2_MASK, + .val = VIP_AND_CAM0_REG2_MASK, + }, +}; + +static struct spear_modemux vip_mux_cam0_modemux[] = { + { + .muxregs = vip_mux_cam0_muxreg, + .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg), + }, +}; + +static struct spear_pingroup vip_mux_cam0_pingroup = { + .name = "vip_mux_cam0_grp", + .pins = vip_mux_cam0_pins, + .npins = ARRAY_SIZE(vip_mux_cam0_pins), + .modemuxs = vip_mux_cam0_modemux, + .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux), +}; + +/* pad multiplexing for vip_mux_cam1 (disables cam1) device */ +static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, + 62, 63, 64 }; +static struct spear_muxreg vip_mux_cam1_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = CAM1_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = VIP_AND_CAM1_REG1_MASK, + .val = VIP_AND_CAM1_REG1_MASK, + }, { + .reg = PAD_FUNCTION_EN_3, + .mask = VIP_AND_CAM1_REG2_MASK, + .val = VIP_AND_CAM1_REG2_MASK, + }, +}; + +static struct spear_modemux vip_mux_cam1_modemux[] = { + { + .muxregs = vip_mux_cam1_muxreg, + .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg), + }, +}; + +static struct spear_pingroup vip_mux_cam1_pingroup = { + .name = "vip_mux_cam1_grp", + .pins = vip_mux_cam1_pins, + .npins = ARRAY_SIZE(vip_mux_cam1_pins), + .modemuxs = vip_mux_cam1_modemux, + .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux), +}; + +/* pad multiplexing for vip_mux_cam2 (disables cam2) device */ +static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, + 51, 52, 53 }; +static struct spear_muxreg vip_mux_cam2_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = CAM2_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = VIP_AND_CAM2_REG1_MASK, + .val = VIP_AND_CAM2_REG1_MASK, + }, +}; + +static struct spear_modemux vip_mux_cam2_modemux[] = { + { + .muxregs = vip_mux_cam2_muxreg, + .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg), + }, +}; + +static struct spear_pingroup vip_mux_cam2_pingroup = { + .name = "vip_mux_cam2_grp", + .pins = vip_mux_cam2_pins, + .npins = ARRAY_SIZE(vip_mux_cam2_pins), + .modemuxs = vip_mux_cam2_modemux, + .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux), +}; + +/* pad multiplexing for vip_mux_cam3 (disables cam3) device */ +static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34 }; +static struct spear_muxreg vip_mux_cam3_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = CAM3_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = VIP_AND_CAM3_REG0_MASK, + .val = VIP_AND_CAM3_REG0_MASK, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = VIP_AND_CAM3_REG1_MASK, + .val = VIP_AND_CAM3_REG1_MASK, + }, +}; + +static struct spear_modemux vip_mux_cam3_modemux[] = { + { + .muxregs = vip_mux_cam3_muxreg, + .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg), + }, +}; + +static struct spear_pingroup vip_mux_cam3_pingroup = { + .name = "vip_mux_cam3_grp", + .pins = vip_mux_cam3_pins, + .npins = ARRAY_SIZE(vip_mux_cam3_pins), + .modemuxs = vip_mux_cam3_modemux, + .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux), +}; + +static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" , + "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" }; +static struct spear_function vip_function = { + .name = "vip", + .groups = vip_grps, + .ngroups = ARRAY_SIZE(vip_grps), +}; + +/* pad multiplexing for cam0 device */ +static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 +}; +static struct spear_muxreg cam0_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = CAM0_MASK, + .val = CAM0_MASK, + }, { + .reg = PAD_FUNCTION_EN_3, + .mask = VIP_AND_CAM0_REG2_MASK, + .val = VIP_AND_CAM0_REG2_MASK, + }, +}; + +static struct spear_modemux cam0_modemux[] = { + { + .muxregs = cam0_muxreg, + .nmuxregs = ARRAY_SIZE(cam0_muxreg), + }, +}; + +static struct spear_pingroup cam0_pingroup = { + .name = "cam0_grp", + .pins = cam0_pins, + .npins = ARRAY_SIZE(cam0_pins), + .modemuxs = cam0_modemux, + .nmodemuxs = ARRAY_SIZE(cam0_modemux), +}; + +static const char *const cam0_grps[] = { "cam0_grp" }; +static struct spear_function cam0_function = { + .name = "cam0", + .groups = cam0_grps, + .ngroups = ARRAY_SIZE(cam0_grps), +}; + +/* pad multiplexing for cam1 device */ +static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 +}; +static struct spear_muxreg cam1_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = CAM1_MASK, + .val = CAM1_MASK, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = VIP_AND_CAM1_REG1_MASK, + .val = VIP_AND_CAM1_REG1_MASK, + }, { + .reg = PAD_FUNCTION_EN_3, + .mask = VIP_AND_CAM1_REG2_MASK, + .val = VIP_AND_CAM1_REG2_MASK, + }, +}; + +static struct spear_modemux cam1_modemux[] = { + { + .muxregs = cam1_muxreg, + .nmuxregs = ARRAY_SIZE(cam1_muxreg), + }, +}; + +static struct spear_pingroup cam1_pingroup = { + .name = "cam1_grp", + .pins = cam1_pins, + .npins = ARRAY_SIZE(cam1_pins), + .modemuxs = cam1_modemux, + .nmodemuxs = ARRAY_SIZE(cam1_modemux), +}; + +static const char *const cam1_grps[] = { "cam1_grp" }; +static struct spear_function cam1_function = { + .name = "cam1", + .groups = cam1_grps, + .ngroups = ARRAY_SIZE(cam1_grps), +}; + +/* pad multiplexing for cam2 device */ +static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 +}; +static struct spear_muxreg cam2_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = CAM2_MASK, + .val = CAM2_MASK, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = VIP_AND_CAM2_REG1_MASK, + .val = VIP_AND_CAM2_REG1_MASK, + }, +}; + +static struct spear_modemux cam2_modemux[] = { + { + .muxregs = cam2_muxreg, + .nmuxregs = ARRAY_SIZE(cam2_muxreg), + }, +}; + +static struct spear_pingroup cam2_pingroup = { + .name = "cam2_grp", + .pins = cam2_pins, + .npins = ARRAY_SIZE(cam2_pins), + .modemuxs = cam2_modemux, + .nmodemuxs = ARRAY_SIZE(cam2_modemux), +}; + +static const char *const cam2_grps[] = { "cam2_grp" }; +static struct spear_function cam2_function = { + .name = "cam2", + .groups = cam2_grps, + .ngroups = ARRAY_SIZE(cam2_grps), +}; + +/* pad multiplexing for cam3 device */ +static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 +}; +static struct spear_muxreg cam3_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = CAM3_MASK, + .val = CAM3_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = VIP_AND_CAM3_REG0_MASK, + .val = VIP_AND_CAM3_REG0_MASK, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = VIP_AND_CAM3_REG1_MASK, + .val = VIP_AND_CAM3_REG1_MASK, + }, +}; + +static struct spear_modemux cam3_modemux[] = { + { + .muxregs = cam3_muxreg, + .nmuxregs = ARRAY_SIZE(cam3_muxreg), + }, +}; + +static struct spear_pingroup cam3_pingroup = { + .name = "cam3_grp", + .pins = cam3_pins, + .npins = ARRAY_SIZE(cam3_pins), + .modemuxs = cam3_modemux, + .nmodemuxs = ARRAY_SIZE(cam3_modemux), +}; + +static const char *const cam3_grps[] = { "cam3_grp" }; +static struct spear_function cam3_function = { + .name = "cam3", + .groups = cam3_grps, + .ngroups = ARRAY_SIZE(cam3_grps), +}; + +/* pad multiplexing for smi device */ +static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 }; +static struct spear_muxreg smi_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_3, + .mask = SMI_REG2_MASK, + .val = SMI_REG2_MASK, + }, +}; + +static struct spear_modemux smi_modemux[] = { + { + .muxregs = smi_muxreg, + .nmuxregs = ARRAY_SIZE(smi_muxreg), + }, +}; + +static struct spear_pingroup smi_pingroup = { + .name = "smi_grp", + .pins = smi_pins, + .npins = ARRAY_SIZE(smi_pins), + .modemuxs = smi_modemux, + .nmodemuxs = ARRAY_SIZE(smi_modemux), +}; + +static const char *const smi_grps[] = { "smi_grp" }; +static struct spear_function smi_function = { + .name = "smi", + .groups = smi_grps, + .ngroups = ARRAY_SIZE(smi_grps), +}; + +/* pad multiplexing for ssp0 device */ +static const unsigned ssp0_pins[] = { 80, 81, 82, 83 }; +static struct spear_muxreg ssp0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_3, + .mask = SSP0_REG2_MASK, + .val = SSP0_REG2_MASK, + }, +}; + +static struct spear_modemux ssp0_modemux[] = { + { + .muxregs = ssp0_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_muxreg), + }, +}; + +static struct spear_pingroup ssp0_pingroup = { + .name = "ssp0_grp", + .pins = ssp0_pins, + .npins = ARRAY_SIZE(ssp0_pins), + .modemuxs = ssp0_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_modemux), +}; + +/* pad multiplexing for ssp0_cs1 device */ +static const unsigned ssp0_cs1_pins[] = { 24 }; +static struct spear_muxreg ssp0_cs1_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = SSP0_CS1_MASK, + .val = SSP0_CS1_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PWM0_AND_SSP0_CS1_REG0_MASK, + .val = PWM0_AND_SSP0_CS1_REG0_MASK, + }, +}; + +static struct spear_modemux ssp0_cs1_modemux[] = { + { + .muxregs = ssp0_cs1_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg), + }, +}; + +static struct spear_pingroup ssp0_cs1_pingroup = { + .name = "ssp0_cs1_grp", + .pins = ssp0_cs1_pins, + .npins = ARRAY_SIZE(ssp0_cs1_pins), + .modemuxs = ssp0_cs1_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux), +}; + +/* pad multiplexing for ssp0_cs2 device */ +static const unsigned ssp0_cs2_pins[] = { 85 }; +static struct spear_muxreg ssp0_cs2_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = SSP0_CS2_MASK, + .val = SSP0_CS2_MASK, + }, { + .reg = PAD_FUNCTION_EN_3, + .mask = TS_AND_SSP0_CS2_REG2_MASK, + .val = TS_AND_SSP0_CS2_REG2_MASK, + }, +}; + +static struct spear_modemux ssp0_cs2_modemux[] = { + { + .muxregs = ssp0_cs2_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg), + }, +}; + +static struct spear_pingroup ssp0_cs2_pingroup = { + .name = "ssp0_cs2_grp", + .pins = ssp0_cs2_pins, + .npins = ARRAY_SIZE(ssp0_cs2_pins), + .modemuxs = ssp0_cs2_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux), +}; + +/* pad multiplexing for ssp0_cs3 device */ +static const unsigned ssp0_cs3_pins[] = { 132 }; +static struct spear_muxreg ssp0_cs3_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_5, + .mask = SSP0_CS3_REG4_MASK, + .val = SSP0_CS3_REG4_MASK, + }, +}; + +static struct spear_modemux ssp0_cs3_modemux[] = { + { + .muxregs = ssp0_cs3_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg), + }, +}; + +static struct spear_pingroup ssp0_cs3_pingroup = { + .name = "ssp0_cs3_grp", + .pins = ssp0_cs3_pins, + .npins = ARRAY_SIZE(ssp0_cs3_pins), + .modemuxs = ssp0_cs3_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux), +}; + +static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp", + "ssp0_cs2_grp", "ssp0_cs3_grp" }; +static struct spear_function ssp0_function = { + .name = "ssp0", + .groups = ssp0_grps, + .ngroups = ARRAY_SIZE(ssp0_grps), +}; + +/* pad multiplexing for uart0 device */ +static const unsigned uart0_pins[] = { 86, 87 }; +static struct spear_muxreg uart0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_3, + .mask = UART0_REG2_MASK, + .val = UART0_REG2_MASK, + }, +}; + +static struct spear_modemux uart0_modemux[] = { + { + .muxregs = uart0_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_muxreg), + }, +}; + +static struct spear_pingroup uart0_pingroup = { + .name = "uart0_grp", + .pins = uart0_pins, + .npins = ARRAY_SIZE(uart0_pins), + .modemuxs = uart0_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_modemux), +}; + +/* pad multiplexing for uart0_enh device */ +static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 }; +static struct spear_muxreg uart0_enh_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = GPT_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = UART0_ENH_AND_GPT_REG0_MASK, + .val = UART0_ENH_AND_GPT_REG0_MASK, + }, +}; + +static struct spear_modemux uart0_enh_modemux[] = { + { + .muxregs = uart0_enh_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg), + }, +}; + +static struct spear_pingroup uart0_enh_pingroup = { + .name = "uart0_enh_grp", + .pins = uart0_enh_pins, + .npins = ARRAY_SIZE(uart0_enh_pins), + .modemuxs = uart0_enh_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux), +}; + +static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" }; +static struct spear_function uart0_function = { + .name = "uart0", + .groups = uart0_grps, + .ngroups = ARRAY_SIZE(uart0_grps), +}; + +/* pad multiplexing for uart1 device */ +static const unsigned uart1_pins[] = { 88, 89 }; +static struct spear_muxreg uart1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_3, + .mask = UART1_REG2_MASK, + .val = UART1_REG2_MASK, + }, +}; + +static struct spear_modemux uart1_modemux[] = { + { + .muxregs = uart1_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_muxreg), + }, +}; + +static struct spear_pingroup uart1_pingroup = { + .name = "uart1_grp", + .pins = uart1_pins, + .npins = ARRAY_SIZE(uart1_pins), + .modemuxs = uart1_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modemux), +}; + +static const char *const uart1_grps[] = { "uart1_grp" }; +static struct spear_function uart1_function = { + .name = "uart1", + .groups = uart1_grps, + .ngroups = ARRAY_SIZE(uart1_grps), +}; + +/* pad multiplexing for i2s_in device */ +static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 }; +static struct spear_muxreg i2s_in_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_3, + .mask = I2S_IN_REG2_MASK, + .val = I2S_IN_REG2_MASK, + }, { + .reg = PAD_FUNCTION_EN_4, + .mask = I2S_IN_REG3_MASK, + .val = I2S_IN_REG3_MASK, + }, +}; + +static struct spear_modemux i2s_in_modemux[] = { + { + .muxregs = i2s_in_muxreg, + .nmuxregs = ARRAY_SIZE(i2s_in_muxreg), + }, +}; + +static struct spear_pingroup i2s_in_pingroup = { + .name = "i2s_in_grp", + .pins = i2s_in_pins, + .npins = ARRAY_SIZE(i2s_in_pins), + .modemuxs = i2s_in_modemux, + .nmodemuxs = ARRAY_SIZE(i2s_in_modemux), +}; + +/* pad multiplexing for i2s_out device */ +static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 }; +static struct spear_muxreg i2s_out_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_4, + .mask = I2S_OUT_REG3_MASK, + .val = I2S_OUT_REG3_MASK, + }, +}; + +static struct spear_modemux i2s_out_modemux[] = { + { + .muxregs = i2s_out_muxreg, + .nmuxregs = ARRAY_SIZE(i2s_out_muxreg), + }, +}; + +static struct spear_pingroup i2s_out_pingroup = { + .name = "i2s_out_grp", + .pins = i2s_out_pins, + .npins = ARRAY_SIZE(i2s_out_pins), + .modemuxs = i2s_out_modemux, + .nmodemuxs = ARRAY_SIZE(i2s_out_modemux), +}; + +static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" }; +static struct spear_function i2s_function = { + .name = "i2s", + .groups = i2s_grps, + .ngroups = ARRAY_SIZE(i2s_grps), +}; + +/* pad multiplexing for gmac device */ +static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, + 126, 127, 128, 129, 130, 131 }; +#define GMAC_MUXREG \ + { \ + .reg = PAD_FUNCTION_EN_4, \ + .mask = GMAC_REG3_MASK, \ + .val = GMAC_REG3_MASK, \ + }, { \ + .reg = PAD_FUNCTION_EN_5, \ + .mask = GMAC_REG4_MASK, \ + .val = GMAC_REG4_MASK, \ + } + +/* pad multiplexing for gmii device */ +static struct spear_muxreg gmii_muxreg[] = { + GMAC_MUXREG, + { + .reg = GMAC_CLK_CFG, + .mask = GMAC_PHY_IF_SEL_MASK, + .val = GMAC_PHY_IF_GMII_VAL, + }, +}; + +static struct spear_modemux gmii_modemux[] = { + { + .muxregs = gmii_muxreg, + .nmuxregs = ARRAY_SIZE(gmii_muxreg), + }, +}; + +static struct spear_pingroup gmii_pingroup = { + .name = "gmii_grp", + .pins = gmac_pins, + .npins = ARRAY_SIZE(gmac_pins), + .modemuxs = gmii_modemux, + .nmodemuxs = ARRAY_SIZE(gmii_modemux), +}; + +/* pad multiplexing for rgmii device */ +static struct spear_muxreg rgmii_muxreg[] = { + GMAC_MUXREG, + { + .reg = GMAC_CLK_CFG, + .mask = GMAC_PHY_IF_SEL_MASK, + .val = GMAC_PHY_IF_RGMII_VAL, + }, +}; + +static struct spear_modemux rgmii_modemux[] = { + { + .muxregs = rgmii_muxreg, + .nmuxregs = ARRAY_SIZE(rgmii_muxreg), + }, +}; + +static struct spear_pingroup rgmii_pingroup = { + .name = "rgmii_grp", + .pins = gmac_pins, + .npins = ARRAY_SIZE(gmac_pins), + .modemuxs = rgmii_modemux, + .nmodemuxs = ARRAY_SIZE(rgmii_modemux), +}; + +/* pad multiplexing for rmii device */ +static struct spear_muxreg rmii_muxreg[] = { + GMAC_MUXREG, + { + .reg = GMAC_CLK_CFG, + .mask = GMAC_PHY_IF_SEL_MASK, + .val = GMAC_PHY_IF_RMII_VAL, + }, +}; + +static struct spear_modemux rmii_modemux[] = { + { + .muxregs = rmii_muxreg, + .nmuxregs = ARRAY_SIZE(rmii_muxreg), + }, +}; + +static struct spear_pingroup rmii_pingroup = { + .name = "rmii_grp", + .pins = gmac_pins, + .npins = ARRAY_SIZE(gmac_pins), + .modemuxs = rmii_modemux, + .nmodemuxs = ARRAY_SIZE(rmii_modemux), +}; + +/* pad multiplexing for sgmii device */ +static struct spear_muxreg sgmii_muxreg[] = { + GMAC_MUXREG, + { + .reg = GMAC_CLK_CFG, + .mask = GMAC_PHY_IF_SEL_MASK, + .val = GMAC_PHY_IF_SGMII_VAL, + }, +}; + +static struct spear_modemux sgmii_modemux[] = { + { + .muxregs = sgmii_muxreg, + .nmuxregs = ARRAY_SIZE(sgmii_muxreg), + }, +}; + +static struct spear_pingroup sgmii_pingroup = { + .name = "sgmii_grp", + .pins = gmac_pins, + .npins = ARRAY_SIZE(gmac_pins), + .modemuxs = sgmii_modemux, + .nmodemuxs = ARRAY_SIZE(sgmii_modemux), +}; + +static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp", + "sgmii_grp" }; +static struct spear_function gmac_function = { + .name = "gmac", + .groups = gmac_grps, + .ngroups = ARRAY_SIZE(gmac_grps), +}; + +/* pad multiplexing for i2c0 device */ +static const unsigned i2c0_pins[] = { 133, 134 }; +static struct spear_muxreg i2c0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_5, + .mask = I2C0_REG4_MASK, + .val = I2C0_REG4_MASK, + }, +}; + +static struct spear_modemux i2c0_modemux[] = { + { + .muxregs = i2c0_muxreg, + .nmuxregs = ARRAY_SIZE(i2c0_muxreg), + }, +}; + +static struct spear_pingroup i2c0_pingroup = { + .name = "i2c0_grp", + .pins = i2c0_pins, + .npins = ARRAY_SIZE(i2c0_pins), + .modemuxs = i2c0_modemux, + .nmodemuxs = ARRAY_SIZE(i2c0_modemux), +}; + +static const char *const i2c0_grps[] = { "i2c0_grp" }; +static struct spear_function i2c0_function = { + .name = "i2c0", + .groups = i2c0_grps, + .ngroups = ARRAY_SIZE(i2c0_grps), +}; + +/* pad multiplexing for i2c1 device */ +static const unsigned i2c1_pins[] = { 18, 23 }; +static struct spear_muxreg i2c1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = I2C1_REG0_MASK, + .val = I2C1_REG0_MASK, + }, +}; + +static struct spear_modemux i2c1_modemux[] = { + { + .muxregs = i2c1_muxreg, + .nmuxregs = ARRAY_SIZE(i2c1_muxreg), + }, +}; + +static struct spear_pingroup i2c1_pingroup = { + .name = "i2c1_grp", + .pins = i2c1_pins, + .npins = ARRAY_SIZE(i2c1_pins), + .modemuxs = i2c1_modemux, + .nmodemuxs = ARRAY_SIZE(i2c1_modemux), +}; + +static const char *const i2c1_grps[] = { "i2c1_grp" }; +static struct spear_function i2c1_function = { + .name = "i2c1", + .groups = i2c1_grps, + .ngroups = ARRAY_SIZE(i2c1_grps), +}; + +/* pad multiplexing for cec0 device */ +static const unsigned cec0_pins[] = { 135 }; +static struct spear_muxreg cec0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_5, + .mask = CEC0_REG4_MASK, + .val = CEC0_REG4_MASK, + }, +}; + +static struct spear_modemux cec0_modemux[] = { + { + .muxregs = cec0_muxreg, + .nmuxregs = ARRAY_SIZE(cec0_muxreg), + }, +}; + +static struct spear_pingroup cec0_pingroup = { + .name = "cec0_grp", + .pins = cec0_pins, + .npins = ARRAY_SIZE(cec0_pins), + .modemuxs = cec0_modemux, + .nmodemuxs = ARRAY_SIZE(cec0_modemux), +}; + +static const char *const cec0_grps[] = { "cec0_grp" }; +static struct spear_function cec0_function = { + .name = "cec0", + .groups = cec0_grps, + .ngroups = ARRAY_SIZE(cec0_grps), +}; + +/* pad multiplexing for cec1 device */ +static const unsigned cec1_pins[] = { 136 }; +static struct spear_muxreg cec1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_5, + .mask = CEC1_REG4_MASK, + .val = CEC1_REG4_MASK, + }, +}; + +static struct spear_modemux cec1_modemux[] = { + { + .muxregs = cec1_muxreg, + .nmuxregs = ARRAY_SIZE(cec1_muxreg), + }, +}; + +static struct spear_pingroup cec1_pingroup = { + .name = "cec1_grp", + .pins = cec1_pins, + .npins = ARRAY_SIZE(cec1_pins), + .modemuxs = cec1_modemux, + .nmodemuxs = ARRAY_SIZE(cec1_modemux), +}; + +static const char *const cec1_grps[] = { "cec1_grp" }; +static struct spear_function cec1_function = { + .name = "cec1", + .groups = cec1_grps, + .ngroups = ARRAY_SIZE(cec1_grps), +}; + +/* pad multiplexing for mcif devices */ +static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200, + 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, + 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, + 229, 230, 231, 232, 237 }; +#define MCIF_MUXREG \ + { \ + .reg = PAD_SHARED_IP_EN_1, \ + .mask = MCIF_MASK, \ + .val = MCIF_MASK, \ + }, { \ + .reg = PAD_FUNCTION_EN_7, \ + .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ + .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ + }, { \ + .reg = PAD_FUNCTION_EN_8, \ + .mask = MCIF_REG7_MASK, \ + .val = MCIF_REG7_MASK, \ + } + +/* Pad multiplexing for sdhci device */ +static struct spear_muxreg sdhci_muxreg[] = { + MCIF_MUXREG, + { + .reg = PERIP_CFG, + .mask = MCIF_SEL_MASK, + .val = MCIF_SEL_SD, + }, +}; + +static struct spear_modemux sdhci_modemux[] = { + { + .muxregs = sdhci_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_muxreg), + }, +}; + +static struct spear_pingroup sdhci_pingroup = { + .name = "sdhci_grp", + .pins = mcif_pins, + .npins = ARRAY_SIZE(mcif_pins), + .modemuxs = sdhci_modemux, + .nmodemuxs = ARRAY_SIZE(sdhci_modemux), +}; + +static const char *const sdhci_grps[] = { "sdhci_grp" }; +static struct spear_function sdhci_function = { + .name = "sdhci", + .groups = sdhci_grps, + .ngroups = ARRAY_SIZE(sdhci_grps), +}; + +/* Pad multiplexing for cf device */ +static struct spear_muxreg cf_muxreg[] = { + MCIF_MUXREG, + { + .reg = PERIP_CFG, + .mask = MCIF_SEL_MASK, + .val = MCIF_SEL_CF, + }, +}; + +static struct spear_modemux cf_modemux[] = { + { + .muxregs = cf_muxreg, + .nmuxregs = ARRAY_SIZE(cf_muxreg), + }, +}; + +static struct spear_pingroup cf_pingroup = { + .name = "cf_grp", + .pins = mcif_pins, + .npins = ARRAY_SIZE(mcif_pins), + .modemuxs = cf_modemux, + .nmodemuxs = ARRAY_SIZE(cf_modemux), +}; + +static const char *const cf_grps[] = { "cf_grp" }; +static struct spear_function cf_function = { + .name = "cf", + .groups = cf_grps, + .ngroups = ARRAY_SIZE(cf_grps), +}; + +/* Pad multiplexing for xd device */ +static struct spear_muxreg xd_muxreg[] = { + MCIF_MUXREG, + { + .reg = PERIP_CFG, + .mask = MCIF_SEL_MASK, + .val = MCIF_SEL_XD, + }, +}; + +static struct spear_modemux xd_modemux[] = { + { + .muxregs = xd_muxreg, + .nmuxregs = ARRAY_SIZE(xd_muxreg), + }, +}; + +static struct spear_pingroup xd_pingroup = { + .name = "xd_grp", + .pins = mcif_pins, + .npins = ARRAY_SIZE(mcif_pins), + .modemuxs = xd_modemux, + .nmodemuxs = ARRAY_SIZE(xd_modemux), +}; + +static const char *const xd_grps[] = { "xd_grp" }; +static struct spear_function xd_function = { + .name = "xd", + .groups = xd_grps, + .ngroups = ARRAY_SIZE(xd_grps), +}; + +/* pad multiplexing for clcd device */ +static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145, + 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, + 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, + 188, 189, 190, 191 }; +static struct spear_muxreg clcd_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_5, + .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, + .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, + }, { + .reg = PAD_FUNCTION_EN_6, + .mask = CLCD_AND_ARM_TRACE_REG5_MASK, + .val = CLCD_AND_ARM_TRACE_REG5_MASK, + }, { + .reg = PAD_FUNCTION_EN_7, + .mask = CLCD_AND_ARM_TRACE_REG6_MASK, + .val = CLCD_AND_ARM_TRACE_REG6_MASK, + }, +}; + +static struct spear_modemux clcd_modemux[] = { + { + .muxregs = clcd_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_muxreg), + }, +}; + +static struct spear_pingroup clcd_pingroup = { + .name = "clcd_grp", + .pins = clcd_pins, + .npins = ARRAY_SIZE(clcd_pins), + .modemuxs = clcd_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_modemux), +}; + +/* Disable cld runtime to save panel damage */ +static struct spear_muxreg clcd_sleep_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_5, + .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, + .val = 0x0, + }, { + .reg = PAD_FUNCTION_EN_6, + .mask = CLCD_AND_ARM_TRACE_REG5_MASK, + .val = 0x0, + }, { + .reg = PAD_FUNCTION_EN_7, + .mask = CLCD_AND_ARM_TRACE_REG6_MASK, + .val = 0x0, + }, +}; + +static struct spear_modemux clcd_sleep_modemux[] = { + { + .muxregs = clcd_sleep_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg), + }, +}; + +static struct spear_pingroup clcd_sleep_pingroup = { + .name = "clcd_sleep_grp", + .pins = clcd_pins, + .npins = ARRAY_SIZE(clcd_pins), + .modemuxs = clcd_sleep_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux), +}; + +static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" }; +static struct spear_function clcd_function = { + .name = "clcd", + .groups = clcd_grps, + .ngroups = ARRAY_SIZE(clcd_grps), +}; + +/* pad multiplexing for arm_trace device */ +static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164, + 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, + 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, + 193, 194, 195, 196, 197, 198, 199, 200 }; +static struct spear_muxreg arm_trace_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = ARM_TRACE_MASK, + .val = ARM_TRACE_MASK, + }, { + .reg = PAD_FUNCTION_EN_5, + .mask = CLCD_AND_ARM_TRACE_REG4_MASK, + .val = CLCD_AND_ARM_TRACE_REG4_MASK, + }, { + .reg = PAD_FUNCTION_EN_6, + .mask = CLCD_AND_ARM_TRACE_REG5_MASK, + .val = CLCD_AND_ARM_TRACE_REG5_MASK, + }, { + .reg = PAD_FUNCTION_EN_7, + .mask = CLCD_AND_ARM_TRACE_REG6_MASK, + .val = CLCD_AND_ARM_TRACE_REG6_MASK, + }, +}; + +static struct spear_modemux arm_trace_modemux[] = { + { + .muxregs = arm_trace_muxreg, + .nmuxregs = ARRAY_SIZE(arm_trace_muxreg), + }, +}; + +static struct spear_pingroup arm_trace_pingroup = { + .name = "arm_trace_grp", + .pins = arm_trace_pins, + .npins = ARRAY_SIZE(arm_trace_pins), + .modemuxs = arm_trace_modemux, + .nmodemuxs = ARRAY_SIZE(arm_trace_modemux), +}; + +static const char *const arm_trace_grps[] = { "arm_trace_grp" }; +static struct spear_function arm_trace_function = { + .name = "arm_trace", + .groups = arm_trace_grps, + .ngroups = ARRAY_SIZE(arm_trace_grps), +}; + +/* pad multiplexing for miphy_dbg device */ +static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, + 132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, + 148, 149, 150, 151, 152, 153, 154, 155, 156, 157 }; +static struct spear_muxreg miphy_dbg_muxreg[] = { + { + .reg = PAD_SHARED_IP_EN_1, + .mask = MIPHY_DBG_MASK, + .val = MIPHY_DBG_MASK, + }, { + .reg = PAD_FUNCTION_EN_5, + .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, + .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, + }, +}; + +static struct spear_modemux miphy_dbg_modemux[] = { + { + .muxregs = miphy_dbg_muxreg, + .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg), + }, +}; + +static struct spear_pingroup miphy_dbg_pingroup = { + .name = "miphy_dbg_grp", + .pins = miphy_dbg_pins, + .npins = ARRAY_SIZE(miphy_dbg_pins), + .modemuxs = miphy_dbg_modemux, + .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux), +}; + +static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" }; +static struct spear_function miphy_dbg_function = { + .name = "miphy_dbg", + .groups = miphy_dbg_grps, + .ngroups = ARRAY_SIZE(miphy_dbg_grps), +}; + +/* pad multiplexing for pcie device */ +static const unsigned pcie_pins[] = { 250 }; +static struct spear_muxreg pcie_muxreg[] = { + { + .reg = PCIE_SATA_CFG, + .mask = SATA_PCIE_CFG_MASK, + .val = PCIE_CFG_VAL, + }, +}; + +static struct spear_modemux pcie_modemux[] = { + { + .muxregs = pcie_muxreg, + .nmuxregs = ARRAY_SIZE(pcie_muxreg), + }, +}; + +static struct spear_pingroup pcie_pingroup = { + .name = "pcie_grp", + .pins = pcie_pins, + .npins = ARRAY_SIZE(pcie_pins), + .modemuxs = pcie_modemux, + .nmodemuxs = ARRAY_SIZE(pcie_modemux), +}; + +static const char *const pcie_grps[] = { "pcie_grp" }; +static struct spear_function pcie_function = { + .name = "pcie", + .groups = pcie_grps, + .ngroups = ARRAY_SIZE(pcie_grps), +}; + +/* pad multiplexing for sata device */ +static const unsigned sata_pins[] = { 250 }; +static struct spear_muxreg sata_muxreg[] = { + { + .reg = PCIE_SATA_CFG, + .mask = SATA_PCIE_CFG_MASK, + .val = SATA_CFG_VAL, + }, +}; + +static struct spear_modemux sata_modemux[] = { + { + .muxregs = sata_muxreg, + .nmuxregs = ARRAY_SIZE(sata_muxreg), + }, +}; + +static struct spear_pingroup sata_pingroup = { + .name = "sata_grp", + .pins = sata_pins, + .npins = ARRAY_SIZE(sata_pins), + .modemuxs = sata_modemux, + .nmodemuxs = ARRAY_SIZE(sata_modemux), +}; + +static const char *const sata_grps[] = { "sata_grp" }; +static struct spear_function sata_function = { + .name = "sata", + .groups = sata_grps, + .ngroups = ARRAY_SIZE(sata_grps), +}; + +/* pingroups */ +static struct spear_pingroup *spear1340_pingroups[] = { + &pads_as_gpio_pingroup, + &fsmc_8bit_pingroup, + &fsmc_16bit_pingroup, + &fsmc_pnor_pingroup, + &keyboard_row_col_pingroup, + &keyboard_col5_pingroup, + &spdif_in_pingroup, + &spdif_out_pingroup, + &gpt_0_1_pingroup, + &pwm0_pingroup, + &pwm1_pingroup, + &pwm2_pingroup, + &pwm3_pingroup, + &vip_mux_pingroup, + &vip_mux_cam0_pingroup, + &vip_mux_cam1_pingroup, + &vip_mux_cam2_pingroup, + &vip_mux_cam3_pingroup, + &cam0_pingroup, + &cam1_pingroup, + &cam2_pingroup, + &cam3_pingroup, + &smi_pingroup, + &ssp0_pingroup, + &ssp0_cs1_pingroup, + &ssp0_cs2_pingroup, + &ssp0_cs3_pingroup, + &uart0_pingroup, + &uart0_enh_pingroup, + &uart1_pingroup, + &i2s_in_pingroup, + &i2s_out_pingroup, + &gmii_pingroup, + &rgmii_pingroup, + &rmii_pingroup, + &sgmii_pingroup, + &i2c0_pingroup, + &i2c1_pingroup, + &cec0_pingroup, + &cec1_pingroup, + &sdhci_pingroup, + &cf_pingroup, + &xd_pingroup, + &clcd_sleep_pingroup, + &clcd_pingroup, + &arm_trace_pingroup, + &miphy_dbg_pingroup, + &pcie_pingroup, + &sata_pingroup, +}; + +/* functions */ +static struct spear_function *spear1340_functions[] = { + &pads_as_gpio_function, + &fsmc_function, + &keyboard_function, + &spdif_in_function, + &spdif_out_function, + &gpt_0_1_function, + &pwm_function, + &vip_function, + &cam0_function, + &cam1_function, + &cam2_function, + &cam3_function, + &smi_function, + &ssp0_function, + &uart0_function, + &uart1_function, + &i2s_function, + &gmac_function, + &i2c0_function, + &i2c1_function, + &cec0_function, + &cec1_function, + &sdhci_function, + &cf_function, + &xd_function, + &clcd_function, + &arm_trace_function, + &miphy_dbg_function, + &pcie_function, + &sata_function, +}; + +static void gpio_request_endisable(struct spear_pmx *pmx, int pin, + bool enable) +{ + unsigned int regoffset, regindex, bitoffset; + unsigned int val; + + /* pin++ as gpio configuration starts from 2nd bit of base register */ + pin++; + + regindex = pin / 32; + bitoffset = pin % 32; + + if (regindex <= 3) + regoffset = PAD_FUNCTION_EN_1 + regindex * sizeof(int *); + else + regoffset = PAD_FUNCTION_EN_5 + (regindex - 4) * sizeof(int *); + + val = pmx_readl(pmx, regoffset); + if (enable) + val &= ~(0x1 << bitoffset); + else + val |= 0x1 << bitoffset; + + pmx_writel(pmx, val, regoffset); +} + +static struct spear_pinctrl_machdata spear1340_machdata = { + .pins = spear1340_pins, + .npins = ARRAY_SIZE(spear1340_pins), + .groups = spear1340_pingroups, + .ngroups = ARRAY_SIZE(spear1340_pingroups), + .functions = spear1340_functions, + .nfunctions = ARRAY_SIZE(spear1340_functions), + .gpio_request_endisable = gpio_request_endisable, + .modes_supported = false, +}; + +static const struct of_device_id spear1340_pinctrl_of_match[] = { + { + .compatible = "st,spear1340-pinmux", + }, + {}, +}; + +static int spear1340_pinctrl_probe(struct platform_device *pdev) +{ + return spear_pinctrl_probe(pdev, &spear1340_machdata); +} + +static struct platform_driver spear1340_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = spear1340_pinctrl_of_match, + }, + .probe = spear1340_pinctrl_probe, +}; + +static int __init spear1340_pinctrl_init(void) +{ + return platform_driver_register(&spear1340_pinctrl_driver); +} +arch_initcall(spear1340_pinctrl_init); diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c new file mode 100644 index 000000000..d53a04597 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear300.c @@ -0,0 +1,685 @@ +/* + * Driver for the ST Microelectronics SPEAr300 pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <vireshk@kernel.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "pinctrl-spear3xx.h" + +#define DRIVER_NAME "spear300-pinmux" + +/* addresses */ +#define PMX_CONFIG_REG 0x00 +#define MODE_CONFIG_REG 0x04 + +/* modes */ +#define NAND_MODE (1 << 0) +#define NOR_MODE (1 << 1) +#define PHOTO_FRAME_MODE (1 << 2) +#define LEND_IP_PHONE_MODE (1 << 3) +#define HEND_IP_PHONE_MODE (1 << 4) +#define LEND_WIFI_PHONE_MODE (1 << 5) +#define HEND_WIFI_PHONE_MODE (1 << 6) +#define ATA_PABX_WI2S_MODE (1 << 7) +#define ATA_PABX_I2S_MODE (1 << 8) +#define CAML_LCDW_MODE (1 << 9) +#define CAMU_LCD_MODE (1 << 10) +#define CAMU_WLCD_MODE (1 << 11) +#define CAML_LCD_MODE (1 << 12) + +static struct spear_pmx_mode pmx_mode_nand = { + .name = "nand", + .mode = NAND_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x00, +}; + +static struct spear_pmx_mode pmx_mode_nor = { + .name = "nor", + .mode = NOR_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x01, +}; + +static struct spear_pmx_mode pmx_mode_photo_frame = { + .name = "photo frame mode", + .mode = PHOTO_FRAME_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x02, +}; + +static struct spear_pmx_mode pmx_mode_lend_ip_phone = { + .name = "lend ip phone mode", + .mode = LEND_IP_PHONE_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x03, +}; + +static struct spear_pmx_mode pmx_mode_hend_ip_phone = { + .name = "hend ip phone mode", + .mode = HEND_IP_PHONE_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x04, +}; + +static struct spear_pmx_mode pmx_mode_lend_wifi_phone = { + .name = "lend wifi phone mode", + .mode = LEND_WIFI_PHONE_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x05, +}; + +static struct spear_pmx_mode pmx_mode_hend_wifi_phone = { + .name = "hend wifi phone mode", + .mode = HEND_WIFI_PHONE_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x06, +}; + +static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = { + .name = "ata pabx wi2s mode", + .mode = ATA_PABX_WI2S_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x07, +}; + +static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = { + .name = "ata pabx i2s mode", + .mode = ATA_PABX_I2S_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x08, +}; + +static struct spear_pmx_mode pmx_mode_caml_lcdw = { + .name = "caml lcdw mode", + .mode = CAML_LCDW_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x0C, +}; + +static struct spear_pmx_mode pmx_mode_camu_lcd = { + .name = "camu lcd mode", + .mode = CAMU_LCD_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x0D, +}; + +static struct spear_pmx_mode pmx_mode_camu_wlcd = { + .name = "camu wlcd mode", + .mode = CAMU_WLCD_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0xE, +}; + +static struct spear_pmx_mode pmx_mode_caml_lcd = { + .name = "caml lcd mode", + .mode = CAML_LCD_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x0000000F, + .val = 0x0F, +}; + +static struct spear_pmx_mode *spear300_pmx_modes[] = { + &pmx_mode_nand, + &pmx_mode_nor, + &pmx_mode_photo_frame, + &pmx_mode_lend_ip_phone, + &pmx_mode_hend_ip_phone, + &pmx_mode_lend_wifi_phone, + &pmx_mode_hend_wifi_phone, + &pmx_mode_ata_pabx_wi2s, + &pmx_mode_ata_pabx_i2s, + &pmx_mode_caml_lcdw, + &pmx_mode_camu_lcd, + &pmx_mode_camu_wlcd, + &pmx_mode_caml_lcd, +}; + +/* fsmc_2chips_pins */ +static const unsigned fsmc_2chips_pins[] = { 1, 97 }; +static struct spear_muxreg fsmc_2chips_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK, + .val = 0, + }, +}; + +static struct spear_modemux fsmc_2chips_modemux[] = { + { + .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .muxregs = fsmc_2chips_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg), + }, +}; + +static struct spear_pingroup fsmc_2chips_pingroup = { + .name = "fsmc_2chips_grp", + .pins = fsmc_2chips_pins, + .npins = ARRAY_SIZE(fsmc_2chips_pins), + .modemuxs = fsmc_2chips_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux), +}; + +/* fsmc_4chips_pins */ +static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 }; +static struct spear_muxreg fsmc_4chips_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, + .val = 0, + }, +}; + +static struct spear_modemux fsmc_4chips_modemux[] = { + { + .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .muxregs = fsmc_4chips_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg), + }, +}; + +static struct spear_pingroup fsmc_4chips_pingroup = { + .name = "fsmc_4chips_grp", + .pins = fsmc_4chips_pins, + .npins = ARRAY_SIZE(fsmc_4chips_pins), + .modemuxs = fsmc_4chips_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux), +}; + +static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp" +}; +static struct spear_function fsmc_function = { + .name = "fsmc", + .groups = fsmc_grps, + .ngroups = ARRAY_SIZE(fsmc_grps), +}; + +/* clcd_lcdmode_pins */ +static const unsigned clcd_lcdmode_pins[] = { 49, 50 }; +static struct spear_muxreg clcd_lcdmode_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux clcd_lcdmode_modemux[] = { + { + .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | + CAMU_LCD_MODE | CAML_LCD_MODE, + .muxregs = clcd_lcdmode_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg), + }, +}; + +static struct spear_pingroup clcd_lcdmode_pingroup = { + .name = "clcd_lcdmode_grp", + .pins = clcd_lcdmode_pins, + .npins = ARRAY_SIZE(clcd_lcdmode_pins), + .modemuxs = clcd_lcdmode_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux), +}; + +/* clcd_pfmode_pins */ +static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 }; +static struct spear_muxreg clcd_pfmode_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux clcd_pfmode_modemux[] = { + { + .modes = PHOTO_FRAME_MODE, + .muxregs = clcd_pfmode_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg), + }, +}; + +static struct spear_pingroup clcd_pfmode_pingroup = { + .name = "clcd_pfmode_grp", + .pins = clcd_pfmode_pins, + .npins = ARRAY_SIZE(clcd_pfmode_pins), + .modemuxs = clcd_pfmode_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux), +}; + +static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp" +}; +static struct spear_function clcd_function = { + .name = "clcd", + .groups = clcd_grps, + .ngroups = ARRAY_SIZE(clcd_grps), +}; + +/* tdm_pins */ +static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 }; +static struct spear_muxreg tdm_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_modemux tdm_modemux[] = { + { + .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE + | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE + | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .muxregs = tdm_muxreg, + .nmuxregs = ARRAY_SIZE(tdm_muxreg), + }, +}; + +static struct spear_pingroup tdm_pingroup = { + .name = "tdm_grp", + .pins = tdm_pins, + .npins = ARRAY_SIZE(tdm_pins), + .modemuxs = tdm_modemux, + .nmodemuxs = ARRAY_SIZE(tdm_modemux), +}; + +static const char *const tdm_grps[] = { "tdm_grp" }; +static struct spear_function tdm_function = { + .name = "tdm", + .groups = tdm_grps, + .ngroups = ARRAY_SIZE(tdm_grps), +}; + +/* i2c_clk_pins */ +static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 }; +static struct spear_muxreg i2c_clk_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux i2c_clk_modemux[] = { + { + .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE + | CAML_LCD_MODE, + .muxregs = i2c_clk_muxreg, + .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg), + }, +}; + +static struct spear_pingroup i2c_clk_pingroup = { + .name = "i2c_clk_grp_grp", + .pins = i2c_clk_pins, + .npins = ARRAY_SIZE(i2c_clk_pins), + .modemuxs = i2c_clk_modemux, + .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux), +}; + +static const char *const i2c_grps[] = { "i2c_clk_grp" }; +static struct spear_function i2c_function = { + .name = "i2c1", + .groups = i2c_grps, + .ngroups = ARRAY_SIZE(i2c_grps), +}; + +/* caml_pins */ +static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 }; +static struct spear_muxreg caml_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux caml_modemux[] = { + { + .modes = CAML_LCDW_MODE | CAML_LCD_MODE, + .muxregs = caml_muxreg, + .nmuxregs = ARRAY_SIZE(caml_muxreg), + }, +}; + +static struct spear_pingroup caml_pingroup = { + .name = "caml_grp", + .pins = caml_pins, + .npins = ARRAY_SIZE(caml_pins), + .modemuxs = caml_modemux, + .nmodemuxs = ARRAY_SIZE(caml_modemux), +}; + +/* camu_pins */ +static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 }; +static struct spear_muxreg camu_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux camu_modemux[] = { + { + .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE, + .muxregs = camu_muxreg, + .nmuxregs = ARRAY_SIZE(camu_muxreg), + }, +}; + +static struct spear_pingroup camu_pingroup = { + .name = "camu_grp", + .pins = camu_pins, + .npins = ARRAY_SIZE(camu_pins), + .modemuxs = camu_modemux, + .nmodemuxs = ARRAY_SIZE(camu_modemux), +}; + +static const char *const cam_grps[] = { "caml_grp", "camu_grp" }; +static struct spear_function cam_function = { + .name = "cam", + .groups = cam_grps, + .ngroups = ARRAY_SIZE(cam_grps), +}; + +/* dac_pins */ +static const unsigned dac_pins[] = { 43, 44 }; +static struct spear_muxreg dac_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK, + .val = 0, + }, +}; + +static struct spear_modemux dac_modemux[] = { + { + .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .muxregs = dac_muxreg, + .nmuxregs = ARRAY_SIZE(dac_muxreg), + }, +}; + +static struct spear_pingroup dac_pingroup = { + .name = "dac_grp", + .pins = dac_pins, + .npins = ARRAY_SIZE(dac_pins), + .modemuxs = dac_modemux, + .nmodemuxs = ARRAY_SIZE(dac_modemux), +}; + +static const char *const dac_grps[] = { "dac_grp" }; +static struct spear_function dac_function = { + .name = "dac", + .groups = dac_grps, + .ngroups = ARRAY_SIZE(dac_grps), +}; + +/* i2s_pins */ +static const unsigned i2s_pins[] = { 39, 40, 41, 42 }; +static struct spear_muxreg i2s_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux i2s_modemux[] = { + { + .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE + | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .muxregs = i2s_muxreg, + .nmuxregs = ARRAY_SIZE(i2s_muxreg), + }, +}; + +static struct spear_pingroup i2s_pingroup = { + .name = "i2s_grp", + .pins = i2s_pins, + .npins = ARRAY_SIZE(i2s_pins), + .modemuxs = i2s_modemux, + .nmodemuxs = ARRAY_SIZE(i2s_modemux), +}; + +static const char *const i2s_grps[] = { "i2s_grp" }; +static struct spear_function i2s_function = { + .name = "i2s", + .groups = i2s_grps, + .ngroups = ARRAY_SIZE(i2s_grps), +}; + +/* sdhci_4bit_pins */ +static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 }; +static struct spear_muxreg sdhci_4bit_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + .val = 0, + }, +}; + +static struct spear_modemux sdhci_4bit_modemux[] = { + { + .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE, + .muxregs = sdhci_4bit_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg), + }, +}; + +static struct spear_pingroup sdhci_4bit_pingroup = { + .name = "sdhci_4bit_grp", + .pins = sdhci_4bit_pins, + .npins = ARRAY_SIZE(sdhci_4bit_pins), + .modemuxs = sdhci_4bit_modemux, + .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux), +}; + +/* sdhci_8bit_pins */ +static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, + 33 }; +static struct spear_muxreg sdhci_8bit_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux sdhci_8bit_modemux[] = { + { + .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE, + .muxregs = sdhci_8bit_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg), + }, +}; + +static struct spear_pingroup sdhci_8bit_pingroup = { + .name = "sdhci_8bit_grp", + .pins = sdhci_8bit_pins, + .npins = ARRAY_SIZE(sdhci_8bit_pins), + .modemuxs = sdhci_8bit_modemux, + .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux), +}; + +static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" }; +static struct spear_function sdhci_function = { + .name = "sdhci", + .groups = sdhci_grps, + .ngroups = ARRAY_SIZE(sdhci_grps), +}; + +/* gpio1_0_to_3_pins */ +static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 }; +static struct spear_muxreg gpio1_0_to_3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux gpio1_0_to_3_modemux[] = { + { + .modes = PHOTO_FRAME_MODE, + .muxregs = gpio1_0_to_3_muxreg, + .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg), + }, +}; + +static struct spear_pingroup gpio1_0_to_3_pingroup = { + .name = "gpio1_0_to_3_grp", + .pins = gpio1_0_to_3_pins, + .npins = ARRAY_SIZE(gpio1_0_to_3_pins), + .modemuxs = gpio1_0_to_3_modemux, + .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux), +}; + +/* gpio1_4_to_7_pins */ +static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 }; + +static struct spear_muxreg gpio1_4_to_7_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux gpio1_4_to_7_modemux[] = { + { + .modes = PHOTO_FRAME_MODE, + .muxregs = gpio1_4_to_7_muxreg, + .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg), + }, +}; + +static struct spear_pingroup gpio1_4_to_7_pingroup = { + .name = "gpio1_4_to_7_grp", + .pins = gpio1_4_to_7_pins, + .npins = ARRAY_SIZE(gpio1_4_to_7_pins), + .modemuxs = gpio1_4_to_7_modemux, + .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux), +}; + +static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" +}; +static struct spear_function gpio1_function = { + .name = "gpio1", + .groups = gpio1_grps, + .ngroups = ARRAY_SIZE(gpio1_grps), +}; + +/* pingroups */ +static struct spear_pingroup *spear300_pingroups[] = { + SPEAR3XX_COMMON_PINGROUPS, + &fsmc_2chips_pingroup, + &fsmc_4chips_pingroup, + &clcd_lcdmode_pingroup, + &clcd_pfmode_pingroup, + &tdm_pingroup, + &i2c_clk_pingroup, + &caml_pingroup, + &camu_pingroup, + &dac_pingroup, + &i2s_pingroup, + &sdhci_4bit_pingroup, + &sdhci_8bit_pingroup, + &gpio1_0_to_3_pingroup, + &gpio1_4_to_7_pingroup, +}; + +/* functions */ +static struct spear_function *spear300_functions[] = { + SPEAR3XX_COMMON_FUNCTIONS, + &fsmc_function, + &clcd_function, + &tdm_function, + &i2c_function, + &cam_function, + &dac_function, + &i2s_function, + &sdhci_function, + &gpio1_function, +}; + +static const struct of_device_id spear300_pinctrl_of_match[] = { + { + .compatible = "st,spear300-pinmux", + }, + {}, +}; + +static int spear300_pinctrl_probe(struct platform_device *pdev) +{ + spear3xx_machdata.groups = spear300_pingroups; + spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups); + spear3xx_machdata.functions = spear300_functions; + spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions); + spear3xx_machdata.gpio_pingroups = NULL; + spear3xx_machdata.ngpio_pingroups = 0; + + spear3xx_machdata.modes_supported = true; + spear3xx_machdata.pmx_modes = spear300_pmx_modes; + spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes); + + pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); + + return spear_pinctrl_probe(pdev, &spear3xx_machdata); +} + +static struct platform_driver spear300_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = spear300_pinctrl_of_match, + }, + .probe = spear300_pinctrl_probe, +}; + +static int __init spear300_pinctrl_init(void) +{ + return platform_driver_register(&spear300_pinctrl_driver); +} +arch_initcall(spear300_pinctrl_init); diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c new file mode 100644 index 000000000..9d9facc4a --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear310.c @@ -0,0 +1,408 @@ +/* + * Driver for the ST Microelectronics SPEAr310 pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <vireshk@kernel.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "pinctrl-spear3xx.h" + +#define DRIVER_NAME "spear310-pinmux" + +/* addresses */ +#define PMX_CONFIG_REG 0x08 + +/* emi_cs_0_to_5_pins */ +static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 }; +static struct spear_muxreg emi_cs_0_to_5_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_modemux emi_cs_0_to_5_modemux[] = { + { + .muxregs = emi_cs_0_to_5_muxreg, + .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg), + }, +}; + +static struct spear_pingroup emi_cs_0_to_5_pingroup = { + .name = "emi_cs_0_to_5_grp", + .pins = emi_cs_0_to_5_pins, + .npins = ARRAY_SIZE(emi_cs_0_to_5_pins), + .modemuxs = emi_cs_0_to_5_modemux, + .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux), +}; + +static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" }; +static struct spear_function emi_cs_0_to_5_function = { + .name = "emi", + .groups = emi_cs_0_to_5_grps, + .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps), +}; + +/* uart1_pins */ +static const unsigned uart1_pins[] = { 0, 1 }; +static struct spear_muxreg uart1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart1_modemux[] = { + { + .muxregs = uart1_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_muxreg), + }, +}; + +static struct spear_pingroup uart1_pingroup = { + .name = "uart1_grp", + .pins = uart1_pins, + .npins = ARRAY_SIZE(uart1_pins), + .modemuxs = uart1_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modemux), +}; + +static const char *const uart1_grps[] = { "uart1_grp" }; +static struct spear_function uart1_function = { + .name = "uart1", + .groups = uart1_grps, + .ngroups = ARRAY_SIZE(uart1_grps), +}; + +/* uart2_pins */ +static const unsigned uart2_pins[] = { 43, 44 }; +static struct spear_muxreg uart2_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart2_modemux[] = { + { + .muxregs = uart2_muxreg, + .nmuxregs = ARRAY_SIZE(uart2_muxreg), + }, +}; + +static struct spear_pingroup uart2_pingroup = { + .name = "uart2_grp", + .pins = uart2_pins, + .npins = ARRAY_SIZE(uart2_pins), + .modemuxs = uart2_modemux, + .nmodemuxs = ARRAY_SIZE(uart2_modemux), +}; + +static const char *const uart2_grps[] = { "uart2_grp" }; +static struct spear_function uart2_function = { + .name = "uart2", + .groups = uart2_grps, + .ngroups = ARRAY_SIZE(uart2_grps), +}; + +/* uart3_pins */ +static const unsigned uart3_pins[] = { 37, 38 }; +static struct spear_muxreg uart3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart3_modemux[] = { + { + .muxregs = uart3_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_muxreg), + }, +}; + +static struct spear_pingroup uart3_pingroup = { + .name = "uart3_grp", + .pins = uart3_pins, + .npins = ARRAY_SIZE(uart3_pins), + .modemuxs = uart3_modemux, + .nmodemuxs = ARRAY_SIZE(uart3_modemux), +}; + +static const char *const uart3_grps[] = { "uart3_grp" }; +static struct spear_function uart3_function = { + .name = "uart3", + .groups = uart3_grps, + .ngroups = ARRAY_SIZE(uart3_grps), +}; + +/* uart4_pins */ +static const unsigned uart4_pins[] = { 39, 40 }; +static struct spear_muxreg uart4_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart4_modemux[] = { + { + .muxregs = uart4_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_muxreg), + }, +}; + +static struct spear_pingroup uart4_pingroup = { + .name = "uart4_grp", + .pins = uart4_pins, + .npins = ARRAY_SIZE(uart4_pins), + .modemuxs = uart4_modemux, + .nmodemuxs = ARRAY_SIZE(uart4_modemux), +}; + +static const char *const uart4_grps[] = { "uart4_grp" }; +static struct spear_function uart4_function = { + .name = "uart4", + .groups = uart4_grps, + .ngroups = ARRAY_SIZE(uart4_grps), +}; + +/* uart5_pins */ +static const unsigned uart5_pins[] = { 41, 42 }; +static struct spear_muxreg uart5_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_modemux uart5_modemux[] = { + { + .muxregs = uart5_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_muxreg), + }, +}; + +static struct spear_pingroup uart5_pingroup = { + .name = "uart5_grp", + .pins = uart5_pins, + .npins = ARRAY_SIZE(uart5_pins), + .modemuxs = uart5_modemux, + .nmodemuxs = ARRAY_SIZE(uart5_modemux), +}; + +static const char *const uart5_grps[] = { "uart5_grp" }; +static struct spear_function uart5_function = { + .name = "uart5", + .groups = uart5_grps, + .ngroups = ARRAY_SIZE(uart5_grps), +}; + +/* fsmc_pins */ +static const unsigned fsmc_pins[] = { 34, 35, 36 }; +static struct spear_muxreg fsmc_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_modemux fsmc_modemux[] = { + { + .muxregs = fsmc_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_muxreg), + }, +}; + +static struct spear_pingroup fsmc_pingroup = { + .name = "fsmc_grp", + .pins = fsmc_pins, + .npins = ARRAY_SIZE(fsmc_pins), + .modemuxs = fsmc_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_modemux), +}; + +static const char *const fsmc_grps[] = { "fsmc_grp" }; +static struct spear_function fsmc_function = { + .name = "fsmc", + .groups = fsmc_grps, + .ngroups = ARRAY_SIZE(fsmc_grps), +}; + +/* rs485_0_pins */ +static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 }; +static struct spear_muxreg rs485_0_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux rs485_0_modemux[] = { + { + .muxregs = rs485_0_muxreg, + .nmuxregs = ARRAY_SIZE(rs485_0_muxreg), + }, +}; + +static struct spear_pingroup rs485_0_pingroup = { + .name = "rs485_0_grp", + .pins = rs485_0_pins, + .npins = ARRAY_SIZE(rs485_0_pins), + .modemuxs = rs485_0_modemux, + .nmodemuxs = ARRAY_SIZE(rs485_0_modemux), +}; + +static const char *const rs485_0_grps[] = { "rs485_0" }; +static struct spear_function rs485_0_function = { + .name = "rs485_0", + .groups = rs485_0_grps, + .ngroups = ARRAY_SIZE(rs485_0_grps), +}; + +/* rs485_1_pins */ +static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 }; +static struct spear_muxreg rs485_1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux rs485_1_modemux[] = { + { + .muxregs = rs485_1_muxreg, + .nmuxregs = ARRAY_SIZE(rs485_1_muxreg), + }, +}; + +static struct spear_pingroup rs485_1_pingroup = { + .name = "rs485_1_grp", + .pins = rs485_1_pins, + .npins = ARRAY_SIZE(rs485_1_pins), + .modemuxs = rs485_1_modemux, + .nmodemuxs = ARRAY_SIZE(rs485_1_modemux), +}; + +static const char *const rs485_1_grps[] = { "rs485_1" }; +static struct spear_function rs485_1_function = { + .name = "rs485_1", + .groups = rs485_1_grps, + .ngroups = ARRAY_SIZE(rs485_1_grps), +}; + +/* tdm_pins */ +static const unsigned tdm_pins[] = { 10, 11, 12, 13 }; +static struct spear_muxreg tdm_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_modemux tdm_modemux[] = { + { + .muxregs = tdm_muxreg, + .nmuxregs = ARRAY_SIZE(tdm_muxreg), + }, +}; + +static struct spear_pingroup tdm_pingroup = { + .name = "tdm_grp", + .pins = tdm_pins, + .npins = ARRAY_SIZE(tdm_pins), + .modemuxs = tdm_modemux, + .nmodemuxs = ARRAY_SIZE(tdm_modemux), +}; + +static const char *const tdm_grps[] = { "tdm_grp" }; +static struct spear_function tdm_function = { + .name = "tdm", + .groups = tdm_grps, + .ngroups = ARRAY_SIZE(tdm_grps), +}; + +/* pingroups */ +static struct spear_pingroup *spear310_pingroups[] = { + SPEAR3XX_COMMON_PINGROUPS, + &emi_cs_0_to_5_pingroup, + &uart1_pingroup, + &uart2_pingroup, + &uart3_pingroup, + &uart4_pingroup, + &uart5_pingroup, + &fsmc_pingroup, + &rs485_0_pingroup, + &rs485_1_pingroup, + &tdm_pingroup, +}; + +/* functions */ +static struct spear_function *spear310_functions[] = { + SPEAR3XX_COMMON_FUNCTIONS, + &emi_cs_0_to_5_function, + &uart1_function, + &uart2_function, + &uart3_function, + &uart4_function, + &uart5_function, + &fsmc_function, + &rs485_0_function, + &rs485_1_function, + &tdm_function, +}; + +static const struct of_device_id spear310_pinctrl_of_match[] = { + { + .compatible = "st,spear310-pinmux", + }, + {}, +}; + +static int spear310_pinctrl_probe(struct platform_device *pdev) +{ + spear3xx_machdata.groups = spear310_pingroups; + spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups); + spear3xx_machdata.functions = spear310_functions; + spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions); + + pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); + pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups, + spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG); + + spear3xx_machdata.modes_supported = false; + + return spear_pinctrl_probe(pdev, &spear3xx_machdata); +} + +static struct platform_driver spear310_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = spear310_pinctrl_of_match, + }, + .probe = spear310_pinctrl_probe, +}; + +static int __init spear310_pinctrl_init(void) +{ + return platform_driver_register(&spear310_pinctrl_driver); +} +arch_initcall(spear310_pinctrl_init); diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c new file mode 100644 index 000000000..e629e3035 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear320.c @@ -0,0 +1,3449 @@ +/* + * Driver for the ST Microelectronics SPEAr320 pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <vireshk@kernel.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "pinctrl-spear3xx.h" + +#define DRIVER_NAME "spear320-pinmux" + +/* addresses */ +#define PMX_CONFIG_REG 0x0C +#define MODE_CONFIG_REG 0x10 +#define MODE_EXT_CONFIG_REG 0x18 + +/* modes */ +#define AUTO_NET_SMII_MODE (1 << 0) +#define AUTO_NET_MII_MODE (1 << 1) +#define AUTO_EXP_MODE (1 << 2) +#define SMALL_PRINTERS_MODE (1 << 3) +#define EXTENDED_MODE (1 << 4) + +static struct spear_pmx_mode pmx_mode_auto_net_smii = { + .name = "Automation Networking SMII mode", + .mode = AUTO_NET_SMII_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x00000007, + .val = 0x0, +}; + +static struct spear_pmx_mode pmx_mode_auto_net_mii = { + .name = "Automation Networking MII mode", + .mode = AUTO_NET_MII_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x00000007, + .val = 0x1, +}; + +static struct spear_pmx_mode pmx_mode_auto_exp = { + .name = "Automation Expanded mode", + .mode = AUTO_EXP_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x00000007, + .val = 0x2, +}; + +static struct spear_pmx_mode pmx_mode_small_printers = { + .name = "Small Printers mode", + .mode = SMALL_PRINTERS_MODE, + .reg = MODE_CONFIG_REG, + .mask = 0x00000007, + .val = 0x3, +}; + +static struct spear_pmx_mode pmx_mode_extended = { + .name = "extended mode", + .mode = EXTENDED_MODE, + .reg = MODE_EXT_CONFIG_REG, + .mask = 0x00000001, + .val = 0x1, +}; + +static struct spear_pmx_mode *spear320_pmx_modes[] = { + &pmx_mode_auto_net_smii, + &pmx_mode_auto_net_mii, + &pmx_mode_auto_exp, + &pmx_mode_small_printers, + &pmx_mode_extended, +}; + +/* Extended mode registers and their offsets */ +#define EXT_CTRL_REG 0x0018 + #define MII_MDIO_MASK (1 << 4) + #define MII_MDIO_10_11_VAL 0 + #define MII_MDIO_81_VAL (1 << 4) + #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5) + #define MAC_MODE_MII 0 + #define MAC_MODE_RMII 1 + #define MAC_MODE_SMII 2 + #define MAC_MODE_SS_SMII 3 + #define MAC_MODE_MASK 0x3 + #define MAC1_MODE_SHIFT 16 + #define MAC2_MODE_SHIFT 18 + +#define IP_SEL_PAD_0_9_REG 0x00A4 + #define PMX_PL_0_1_MASK (0x3F << 0) + #define PMX_UART2_PL_0_1_VAL 0x0 + #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3)) + + #define PMX_PL_2_3_MASK (0x3F << 6) + #define PMX_I2C2_PL_2_3_VAL 0x0 + #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9)) + #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9)) + + #define PMX_PL_4_5_MASK (0x3F << 12) + #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15)) + #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15)) + #define PMX_PL_5_MASK (0x7 << 15) + #define PMX_TOUCH_Y_PL_5_VAL 0x0 + + #define PMX_PL_6_7_MASK (0x3F << 18) + #define PMX_PL_6_MASK (0x7 << 18) + #define PMX_PL_7_MASK (0x7 << 21) + #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21)) + #define PMX_PWM_3_PL_6_VAL (0x2 << 18) + #define PMX_PWM_2_PL_7_VAL (0x2 << 21) + #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21)) + + #define PMX_PL_8_9_MASK (0x3F << 24) + #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27)) + #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27)) + #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27)) + +#define IP_SEL_PAD_10_19_REG 0x00A8 + #define PMX_PL_10_11_MASK (0x3F << 0) + #define PMX_SMII_PL_10_11_VAL 0 + #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3)) + + #define PMX_PL_12_MASK (0x7 << 6) + #define PMX_PWM3_PL_12_VAL 0 + #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6) + + #define PMX_PL_13_14_MASK (0x3F << 9) + #define PMX_PL_13_MASK (0x7 << 9) + #define PMX_PL_14_MASK (0x7 << 12) + #define PMX_SSP2_PL_13_14_15_16_VAL 0 + #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12)) + #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12)) + #define PMX_PWM2_PL_13_VAL (0x2 << 9) + #define PMX_PWM1_PL_14_VAL (0x2 << 12) + + #define PMX_PL_15_MASK (0x7 << 15) + #define PMX_PWM0_PL_15_VAL (0x2 << 15) + #define PMX_PL_15_16_MASK (0x3F << 15) + #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18)) + #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18)) + + #define PMX_PL_17_18_MASK (0x3F << 21) + #define PMX_SSP1_PL_17_18_19_20_VAL 0 + #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24)) + + #define PMX_PL_19_MASK (0x7 << 27) + #define PMX_I2C2_PL_19_VAL (0x1 << 27) + #define PMX_RMII_PL_19_VAL (0x4 << 27) + +#define IP_SEL_PAD_20_29_REG 0x00AC + #define PMX_PL_20_MASK (0x7 << 0) + #define PMX_I2C2_PL_20_VAL (0x1 << 0) + #define PMX_RMII_PL_20_VAL (0x4 << 0) + + #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3) + #define PMX_SMII_PL_21_TO_27_VAL 0 + #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21)) + + #define PMX_PL_28_29_MASK (0x3F << 24) + #define PMX_PL_28_MASK (0x7 << 24) + #define PMX_PL_29_MASK (0x7 << 27) + #define PMX_UART1_PL_28_29_VAL 0 + #define PMX_PWM_3_PL_28_VAL (0x4 << 24) + #define PMX_PWM_2_PL_29_VAL (0x4 << 27) + +#define IP_SEL_PAD_30_39_REG 0x00B0 + #define PMX_PL_30_31_MASK (0x3F << 0) + #define PMX_CAN1_PL_30_31_VAL (0) + #define PMX_PL_30_MASK (0x7 << 0) + #define PMX_PL_31_MASK (0x7 << 3) + #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0) + #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3) + #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3) + + #define PMX_PL_32_33_MASK (0x3F << 6) + #define PMX_CAN0_PL_32_33_VAL 0 + #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9)) + #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9)) + + #define PMX_PL_34_MASK (0x7 << 12) + #define PMX_PWM2_PL_34_VAL 0 + #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12) + #define PMX_SSP2_PL_34_VAL (0x4 << 12) + + #define PMX_PL_35_MASK (0x7 << 15) + #define PMX_I2S_REF_CLK_PL_35_VAL 0 + #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15) + #define PMX_SSP2_PL_35_VAL (0x4 << 15) + + #define PMX_PL_36_MASK (0x7 << 18) + #define PMX_TOUCH_X_PL_36_VAL 0 + #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18) + #define PMX_SSP1_PL_36_VAL (0x4 << 18) + + #define PMX_PL_37_38_MASK (0x3F << 21) + #define PMX_PWM0_1_PL_37_38_VAL 0 + #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24)) + #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24)) + + #define PMX_PL_39_MASK (0x7 << 27) + #define PMX_I2S_PL_39_VAL 0 + #define PMX_UART4_PL_39_VAL (0x2 << 27) + #define PMX_SSP1_PL_39_VAL (0x4 << 27) + +#define IP_SEL_PAD_40_49_REG 0x00B4 + #define PMX_PL_40_MASK (0x7 << 0) + #define PMX_I2S_PL_40_VAL 0 + #define PMX_UART4_PL_40_VAL (0x2 << 0) + #define PMX_PWM3_PL_40_VAL (0x4 << 0) + + #define PMX_PL_41_42_MASK (0x3F << 3) + #define PMX_PL_41_MASK (0x7 << 3) + #define PMX_PL_42_MASK (0x7 << 6) + #define PMX_I2S_PL_41_42_VAL 0 + #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6)) + #define PMX_PWM2_PL_41_VAL (0x4 << 3) + #define PMX_PWM1_PL_42_VAL (0x4 << 6) + + #define PMX_PL_43_MASK (0x7 << 9) + #define PMX_SDHCI_PL_43_VAL 0 + #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9) + #define PMX_PWM0_PL_43_VAL (0x4 << 9) + + #define PMX_PL_44_45_MASK (0x3F << 12) + #define PMX_SDHCI_PL_44_45_VAL 0 + #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15)) + #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15)) + + #define PMX_PL_46_47_MASK (0x3F << 18) + #define PMX_SDHCI_PL_46_47_VAL 0 + #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21)) + #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21)) + + #define PMX_PL_48_49_MASK (0x3F << 24) + #define PMX_SDHCI_PL_48_49_VAL 0 + #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27)) + #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27)) + +#define IP_SEL_PAD_50_59_REG 0x00B8 + #define PMX_PL_50_51_MASK (0x3F << 0) + #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3)) + #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3)) + #define PMX_PL_50_MASK (0x7 << 0) + #define PMX_PL_51_MASK (0x7 << 3) + #define PMX_SDHCI_PL_50_VAL 0 + #define PMX_SDHCI_CD_PL_51_VAL 0 + + #define PMX_PL_52_53_MASK (0x3F << 6) + #define PMX_FSMC_PL_52_53_VAL 0 + #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9)) + #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9)) + + #define PMX_PL_54_55_56_MASK (0x1FF << 12) + #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18)) + + #define PMX_PL_57_MASK (0x7 << 21) + #define PMX_FSMC_PL_57_VAL 0 + #define PMX_PWM3_PL_57_VAL (0x4 << 21) + + #define PMX_PL_58_59_MASK (0x3F << 24) + #define PMX_PL_58_MASK (0x7 << 24) + #define PMX_PL_59_MASK (0x7 << 27) + #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27)) + #define PMX_PWM2_PL_58_VAL (0x4 << 24) + #define PMX_PWM1_PL_59_VAL (0x4 << 27) + +#define IP_SEL_PAD_60_69_REG 0x00BC + #define PMX_PL_60_MASK (0x7 << 0) + #define PMX_FSMC_PL_60_VAL 0 + #define PMX_PWM0_PL_60_VAL (0x4 << 0) + + #define PMX_PL_61_TO_64_MASK (0xFFF << 3) + #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12)) + #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12)) + + #define PMX_PL_65_TO_68_MASK (0xFFF << 15) + #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24)) + #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24)) + + #define PMX_PL_69_MASK (0x7 << 27) + #define PMX_CLCD_PL_69_VAL (0) + #define PMX_EMI_PL_69_VAL (0x2 << 27) + #define PMX_SPP_PL_69_VAL (0x3 << 27) + #define PMX_UART5_PL_69_VAL (0x4 << 27) + +#define IP_SEL_PAD_70_79_REG 0x00C0 + #define PMX_PL_70_MASK (0x7 << 0) + #define PMX_CLCD_PL_70_VAL (0) + #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0) + #define PMX_SPP_PL_70_VAL (0x3 << 0) + #define PMX_UART5_PL_70_VAL (0x4 << 0) + + #define PMX_PL_71_72_MASK (0x3F << 3) + #define PMX_CLCD_PL_71_72_VAL (0) + #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6)) + #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6)) + #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6)) + + #define PMX_PL_73_MASK (0x7 << 9) + #define PMX_CLCD_PL_73_VAL (0) + #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9) + #define PMX_SPP_PL_73_VAL (0x3 << 9) + #define PMX_UART3_PL_73_VAL (0x4 << 9) + + #define PMX_PL_74_MASK (0x7 << 12) + #define PMX_CLCD_PL_74_VAL (0) + #define PMX_EMI_PL_74_VAL (0x2 << 12) + #define PMX_SPP_PL_74_VAL (0x3 << 12) + #define PMX_UART3_PL_74_VAL (0x4 << 12) + + #define PMX_PL_75_76_MASK (0x3F << 15) + #define PMX_CLCD_PL_75_76_VAL (0) + #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18)) + #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18)) + #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18)) + + #define PMX_PL_77_78_79_MASK (0x1FF << 21) + #define PMX_CLCD_PL_77_78_79_VAL (0) + #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27)) + #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27)) + #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27)) + +#define IP_SEL_PAD_80_89_REG 0x00C4 + #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0) + #define PMX_CLCD_PL_80_TO_85_VAL 0 + #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15)) + #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15)) + #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15)) + #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15)) + + #define PMX_PL_86_87_MASK (0x3F << 18) + #define PMX_PL_86_MASK (0x7 << 18) + #define PMX_PL_87_MASK (0x7 << 21) + #define PMX_CLCD_PL_86_87_VAL 0 + #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21)) + #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21)) + #define PMX_PWM3_PL_86_VAL (0x4 << 18) + #define PMX_PWM2_PL_87_VAL (0x4 << 21) + + #define PMX_PL_88_89_MASK (0x3F << 24) + #define PMX_CLCD_PL_88_89_VAL 0 + #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27)) + #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27)) + #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27)) + #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27)) + +#define IP_SEL_PAD_90_99_REG 0x00C8 + #define PMX_PL_90_91_MASK (0x3F << 0) + #define PMX_CLCD_PL_90_91_VAL 0 + #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3)) + #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3)) + #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3)) + #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3)) + + #define PMX_PL_92_93_MASK (0x3F << 6) + #define PMX_CLCD_PL_92_93_VAL 0 + #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9)) + #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9)) + #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9)) + #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9)) + + #define PMX_PL_94_95_MASK (0x3F << 12) + #define PMX_CLCD_PL_94_95_VAL 0 + #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15)) + #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15)) + #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15)) + #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15)) + + #define PMX_PL_96_97_MASK (0x3F << 18) + #define PMX_CLCD_PL_96_97_VAL 0 + #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21)) + #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21)) + #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21)) + #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21)) + + #define PMX_PL_98_MASK (0x7 << 24) + #define PMX_CLCD_PL_98_VAL 0 + #define PMX_I2C1_PL_98_VAL (0x2 << 24) + #define PMX_UART3_PL_98_VAL (0x4 << 24) + + #define PMX_PL_99_MASK (0x7 << 27) + #define PMX_SDHCI_PL_99_VAL 0 + #define PMX_I2C1_PL_99_VAL (0x2 << 27) + #define PMX_UART3_PL_99_VAL (0x4 << 27) + +#define IP_SEL_MIX_PAD_REG 0x00CC + #define PMX_PL_100_101_MASK (0x3F << 0) + #define PMX_SDHCI_PL_100_101_VAL 0 + #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3)) + + #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8) + #define PMX_SSP1_PORT_94_TO_97_VAL 0 + #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8) + #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8) + #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8) + #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8) + + #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11) + #define PMX_SSP2_PORT_90_TO_93_VAL 0 + #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11) + #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11) + #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11) + #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11) + + #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14) + #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0 + #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14) + #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14) + #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14) + + #define PMX_UART3_PORT_SEL_MASK (0x7 << 16) + #define PMX_UART3_PORT_94_VAL 0 + #define PMX_UART3_PORT_73_VAL (0x1 << 16) + #define PMX_UART3_PORT_52_VAL (0x2 << 16) + #define PMX_UART3_PORT_41_VAL (0x3 << 16) + #define PMX_UART3_PORT_15_VAL (0x4 << 16) + #define PMX_UART3_PORT_8_VAL (0x5 << 16) + #define PMX_UART3_PORT_99_VAL (0x6 << 16) + + #define PMX_UART4_PORT_SEL_MASK (0x7 << 19) + #define PMX_UART4_PORT_92_VAL 0 + #define PMX_UART4_PORT_71_VAL (0x1 << 19) + #define PMX_UART4_PORT_39_VAL (0x2 << 19) + #define PMX_UART4_PORT_13_VAL (0x3 << 19) + #define PMX_UART4_PORT_6_VAL (0x4 << 19) + #define PMX_UART4_PORT_101_VAL (0x5 << 19) + + #define PMX_UART5_PORT_SEL_MASK (0x3 << 22) + #define PMX_UART5_PORT_90_VAL 0 + #define PMX_UART5_PORT_69_VAL (0x1 << 22) + #define PMX_UART5_PORT_37_VAL (0x2 << 22) + #define PMX_UART5_PORT_4_VAL (0x3 << 22) + + #define PMX_UART6_PORT_SEL_MASK (0x1 << 24) + #define PMX_UART6_PORT_88_VAL 0 + #define PMX_UART6_PORT_2_VAL (0x1 << 24) + + #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25) + #define PMX_I2C1_PORT_8_9_VAL 0 + #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25) + + #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26) + #define PMX_I2C2_PORT_96_97_VAL 0 + #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26) + #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26) + #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26) + #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26) + + #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29) + #define PMX_SDHCI_CD_PORT_12_VAL 0 + #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29) + +/* Pad multiplexing for CLCD device */ +static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, + 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, + 97 }; +static struct spear_muxreg clcd_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_69_MASK, + .val = PMX_CLCD_PL_69_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | + PMX_PL_74_MASK | PMX_PL_75_76_MASK | + PMX_PL_77_78_79_MASK, + .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL | + PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL | + PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL, + }, { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | + PMX_PL_88_89_MASK, + .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL | + PMX_CLCD_PL_88_89_VAL, + }, { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | + PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK, + .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL | + PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL | + PMX_CLCD_PL_98_VAL, + }, +}; + +static struct spear_modemux clcd_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = clcd_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_muxreg), + }, +}; + +static struct spear_pingroup clcd_pingroup = { + .name = "clcd_grp", + .pins = clcd_pins, + .npins = ARRAY_SIZE(clcd_pins), + .modemuxs = clcd_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_modemux), +}; + +static const char *const clcd_grps[] = { "clcd_grp" }; +static struct spear_function clcd_function = { + .name = "clcd", + .groups = clcd_grps, + .ngroups = ARRAY_SIZE(clcd_grps), +}; + +/* Pad multiplexing for EMI (Parallel NOR flash) device */ +static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, + 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, + 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, + 93, 94, 95, 96, 97 }; +static struct spear_muxreg emi_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg emi_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, + .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, + }, { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK | + PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK, + .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL | + PMX_FSMC_EMI_PL_54_55_56_VAL | + PMX_FSMC_EMI_PL_58_59_VAL, + }, { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_69_MASK, + .val = PMX_EMI_PL_69_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | + PMX_PL_74_MASK | PMX_PL_75_76_MASK | + PMX_PL_77_78_79_MASK, + .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | + PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL | + PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL, + }, { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | + PMX_PL_88_89_MASK, + .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL | + PMX_EMI_PL_88_89_VAL, + }, { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | + PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, + .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL | + PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = EMI_FSMC_DYNAMIC_MUX_MASK, + .val = EMI_FSMC_DYNAMIC_MUX_MASK, + }, +}; + +static struct spear_modemux emi_modemux[] = { + { + .modes = AUTO_EXP_MODE | EXTENDED_MODE, + .muxregs = emi_muxreg, + .nmuxregs = ARRAY_SIZE(emi_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = emi_ext_muxreg, + .nmuxregs = ARRAY_SIZE(emi_ext_muxreg), + }, +}; + +static struct spear_pingroup emi_pingroup = { + .name = "emi_grp", + .pins = emi_pins, + .npins = ARRAY_SIZE(emi_pins), + .modemuxs = emi_modemux, + .nmodemuxs = ARRAY_SIZE(emi_modemux), +}; + +static const char *const emi_grps[] = { "emi_grp" }; +static struct spear_function emi_function = { + .name = "emi", + .groups = emi_grps, + .ngroups = ARRAY_SIZE(emi_grps), +}; + +/* Pad multiplexing for FSMC (NAND flash) device */ +static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60, + 61, 62, 63, 64, 65, 66, 67, 68 }; +static struct spear_muxreg fsmc_8bit_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK | + PMX_PL_57_MASK | PMX_PL_58_59_MASK, + .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL | + PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL, + }, { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK | + PMX_PL_65_TO_68_MASK, + .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL | + PMX_FSMC_PL_65_TO_68_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = EMI_FSMC_DYNAMIC_MUX_MASK, + .val = EMI_FSMC_DYNAMIC_MUX_MASK, + }, +}; + +static struct spear_modemux fsmc_8bit_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = fsmc_8bit_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), + }, +}; + +static struct spear_pingroup fsmc_8bit_pingroup = { + .name = "fsmc_8bit_grp", + .pins = fsmc_8bit_pins, + .npins = ARRAY_SIZE(fsmc_8bit_pins), + .modemuxs = fsmc_8bit_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), +}; + +static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56, + 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 }; +static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg fsmc_16bit_muxreg[] = { + { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, + .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK, + .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | + PMX_FSMC_EMI_PL_73_VAL, + } +}; + +static struct spear_modemux fsmc_16bit_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = fsmc_8bit_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), + }, { + .modes = AUTO_EXP_MODE | EXTENDED_MODE, + .muxregs = fsmc_16bit_autoexp_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = fsmc_16bit_muxreg, + .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), + }, +}; + +static struct spear_pingroup fsmc_16bit_pingroup = { + .name = "fsmc_16bit_grp", + .pins = fsmc_16bit_pins, + .npins = ARRAY_SIZE(fsmc_16bit_pins), + .modemuxs = fsmc_16bit_modemux, + .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), +}; + +static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" }; +static struct spear_function fsmc_function = { + .name = "fsmc", + .groups = fsmc_grps, + .ngroups = ARRAY_SIZE(fsmc_grps), +}; + +/* Pad multiplexing for SPP device */ +static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85 }; +static struct spear_muxreg spp_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_69_MASK, + .val = PMX_SPP_PL_69_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | + PMX_PL_74_MASK | PMX_PL_75_76_MASK | + PMX_PL_77_78_79_MASK, + .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL | + PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL | + PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL, + }, { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK, + .val = PMX_SPP_PL_80_TO_85_VAL, + }, +}; + +static struct spear_modemux spp_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = spp_muxreg, + .nmuxregs = ARRAY_SIZE(spp_muxreg), + }, +}; + +static struct spear_pingroup spp_pingroup = { + .name = "spp_grp", + .pins = spp_pins, + .npins = ARRAY_SIZE(spp_pins), + .modemuxs = spp_modemux, + .nmodemuxs = ARRAY_SIZE(spp_modemux), +}; + +static const char *const spp_grps[] = { "spp_grp" }; +static struct spear_function spp_function = { + .name = "spp", + .groups = spp_grps, + .ngroups = ARRAY_SIZE(spp_grps), +}; + +/* Pad multiplexing for SDHCI device */ +static const unsigned sdhci_led_pins[] = { 34 }; +static struct spear_muxreg sdhci_led_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg sdhci_led_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_34_MASK, + .val = PMX_PWM2_PL_34_VAL, + }, +}; + +static struct spear_modemux sdhci_led_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, + .muxregs = sdhci_led_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = sdhci_led_ext_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg), + }, +}; + +static struct spear_pingroup sdhci_led_pingroup = { + .name = "sdhci_led_grp", + .pins = sdhci_led_pins, + .npins = ARRAY_SIZE(sdhci_led_pins), + .modemuxs = sdhci_led_modemux, + .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux), +}; + +static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49, + 50}; +static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51 +}; +static struct spear_muxreg sdhci_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg sdhci_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK | + PMX_PL_48_49_MASK, + .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL | + PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL, + }, { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_50_MASK, + .val = PMX_SDHCI_PL_50_VAL, + }, { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_99_MASK, + .val = PMX_SDHCI_PL_99_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_PL_100_101_MASK, + .val = PMX_SDHCI_PL_100_101_VAL, + }, +}; + +static struct spear_muxreg sdhci_cd_12_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_12_MASK, + .val = PMX_SDHCI_CD_PL_12_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SDHCI_CD_PORT_SEL_MASK, + .val = PMX_SDHCI_CD_PORT_12_VAL, + }, +}; + +static struct spear_muxreg sdhci_cd_51_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_51_MASK, + .val = PMX_SDHCI_CD_PL_51_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SDHCI_CD_PORT_SEL_MASK, + .val = PMX_SDHCI_CD_PORT_51_VAL, + }, +}; + +#define pmx_sdhci_common_modemux \ + { \ + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \ + SMALL_PRINTERS_MODE | EXTENDED_MODE, \ + .muxregs = sdhci_muxreg, \ + .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \ + }, { \ + .modes = EXTENDED_MODE, \ + .muxregs = sdhci_ext_muxreg, \ + .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \ + } + +static struct spear_modemux sdhci_modemux[][3] = { + { + /* select pin 12 for cd */ + pmx_sdhci_common_modemux, + { + .modes = EXTENDED_MODE, + .muxregs = sdhci_cd_12_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg), + }, + }, { + /* select pin 51 for cd */ + pmx_sdhci_common_modemux, + { + .modes = EXTENDED_MODE, + .muxregs = sdhci_cd_51_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg), + }, + } +}; + +static struct spear_pingroup sdhci_pingroup[] = { + { + .name = "sdhci_cd_12_grp", + .pins = sdhci_cd_12_pins, + .npins = ARRAY_SIZE(sdhci_cd_12_pins), + .modemuxs = sdhci_modemux[0], + .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]), + }, { + .name = "sdhci_cd_51_grp", + .pins = sdhci_cd_51_pins, + .npins = ARRAY_SIZE(sdhci_cd_51_pins), + .modemuxs = sdhci_modemux[1], + .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]), + }, +}; + +static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp", + "sdhci_led_grp" }; + +static struct spear_function sdhci_function = { + .name = "sdhci", + .groups = sdhci_grps, + .ngroups = ARRAY_SIZE(sdhci_grps), +}; + +/* Pad multiplexing for I2S device */ +static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 }; +static struct spear_muxreg i2s_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg i2s_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_35_MASK | PMX_PL_39_MASK, + .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK, + .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL, + }, +}; + +static struct spear_modemux i2s_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, + .muxregs = i2s_muxreg, + .nmuxregs = ARRAY_SIZE(i2s_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = i2s_ext_muxreg, + .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg), + }, +}; + +static struct spear_pingroup i2s_pingroup = { + .name = "i2s_grp", + .pins = i2s_pins, + .npins = ARRAY_SIZE(i2s_pins), + .modemuxs = i2s_modemux, + .nmodemuxs = ARRAY_SIZE(i2s_modemux), +}; + +static const char *const i2s_grps[] = { "i2s_grp" }; +static struct spear_function i2s_function = { + .name = "i2s", + .groups = i2s_grps, + .ngroups = ARRAY_SIZE(i2s_grps), +}; + +/* Pad multiplexing for UART1 device */ +static const unsigned uart1_pins[] = { 28, 29 }; +static struct spear_muxreg uart1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg uart1_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_28_29_MASK, + .val = PMX_UART1_PL_28_29_VAL, + }, +}; + +static struct spear_modemux uart1_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE + | SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = uart1_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = uart1_ext_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg), + }, +}; + +static struct spear_pingroup uart1_pingroup = { + .name = "uart1_grp", + .pins = uart1_pins, + .npins = ARRAY_SIZE(uart1_pins), + .modemuxs = uart1_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modemux), +}; + +static const char *const uart1_grps[] = { "uart1_grp" }; +static struct spear_function uart1_function = { + .name = "uart1", + .groups = uart1_grps, + .ngroups = ARRAY_SIZE(uart1_grps), +}; + +/* Pad multiplexing for UART1 Modem device */ +static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 }; +static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 }; +static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 }; +static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 }; + +static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK, + .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL | + PMX_UART1_ENH_PL_6_7_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART1_ENH_PORT_SEL_MASK, + .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL, + }, +}; + +static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | + PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK | + PMX_PL_35_MASK | PMX_PL_36_MASK, + .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL | + PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | + PMX_UART1_ENH_PL_36_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART1_ENH_PORT_SEL_MASK, + .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL, + }, +}; + +static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | + PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK, + .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | + PMX_UART1_ENH_PL_36_VAL, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, + .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART1_ENH_PORT_SEL_MASK, + .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL, + }, +}; + +static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK, + .val = PMX_UART1_ENH_PL_80_TO_85_VAL, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, + .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART1_ENH_PORT_SEL_MASK, + .val = PMX_UART1_ENH_PORT_81_TO_85_VAL, + }, +}; + +static struct spear_modemux uart1_modem_2_to_7_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = uart1_modem_ext_2_to_7_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg), + }, +}; + +static struct spear_modemux uart1_modem_31_to_36_modemux[] = { + { + .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = uart1_modem_31_to_36_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = uart1_modem_ext_31_to_36_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg), + }, +}; + +static struct spear_modemux uart1_modem_34_to_45_modemux[] = { + { + .modes = AUTO_EXP_MODE | EXTENDED_MODE, + .muxregs = uart1_modem_34_to_45_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = uart1_modem_ext_34_to_45_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg), + }, +}; + +static struct spear_modemux uart1_modem_80_to_85_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = uart1_modem_ext_80_to_85_muxreg, + .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg), + }, +}; + +static struct spear_pingroup uart1_modem_pingroup[] = { + { + .name = "uart1_modem_2_to_7_grp", + .pins = uart1_modem_2_to_7_pins, + .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins), + .modemuxs = uart1_modem_2_to_7_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux), + }, { + .name = "uart1_modem_31_to_36_grp", + .pins = uart1_modem_31_to_36_pins, + .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins), + .modemuxs = uart1_modem_31_to_36_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux), + }, { + .name = "uart1_modem_34_to_45_grp", + .pins = uart1_modem_34_to_45_pins, + .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins), + .modemuxs = uart1_modem_34_to_45_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux), + }, { + .name = "uart1_modem_80_to_85_grp", + .pins = uart1_modem_80_to_85_pins, + .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins), + .modemuxs = uart1_modem_80_to_85_modemux, + .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux), + }, +}; + +static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp", + "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp", + "uart1_modem_80_to_85_grp" }; +static struct spear_function uart1_modem_function = { + .name = "uart1_modem", + .groups = uart1_modem_grps, + .ngroups = ARRAY_SIZE(uart1_modem_grps), +}; + +/* Pad multiplexing for UART2 device */ +static const unsigned uart2_pins[] = { 0, 1 }; +static struct spear_muxreg uart2_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg uart2_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_0_1_MASK, + .val = PMX_UART2_PL_0_1_VAL, + }, +}; + +static struct spear_modemux uart2_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE + | SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = uart2_muxreg, + .nmuxregs = ARRAY_SIZE(uart2_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = uart2_ext_muxreg, + .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg), + }, +}; + +static struct spear_pingroup uart2_pingroup = { + .name = "uart2_grp", + .pins = uart2_pins, + .npins = ARRAY_SIZE(uart2_pins), + .modemuxs = uart2_modemux, + .nmodemuxs = ARRAY_SIZE(uart2_modemux), +}; + +static const char *const uart2_grps[] = { "uart2_grp" }; +static struct spear_function uart2_function = { + .name = "uart2", + .groups = uart2_grps, + .ngroups = ARRAY_SIZE(uart2_grps), +}; + +/* Pad multiplexing for uart3 device */ +static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 }, + { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } }; + +static struct spear_muxreg uart3_ext_8_9_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_8_9_MASK, + .val = PMX_UART3_PL_8_9_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_8_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_15_16_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_15_16_MASK, + .val = PMX_UART3_PL_15_16_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_15_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_41_42_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_41_42_MASK, + .val = PMX_UART3_PL_41_42_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_41_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_52_53_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_52_53_MASK, + .val = PMX_UART3_PL_52_53_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_52_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_73_74_muxreg[] = { + { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_73_MASK | PMX_PL_74_MASK, + .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_73_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_94_95_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_94_95_MASK, + .val = PMX_UART3_PL_94_95_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_94_VAL, + }, +}; + +static struct spear_muxreg uart3_ext_98_99_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, + .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART3_PORT_SEL_MASK, + .val = PMX_UART3_PORT_99_VAL, + }, +}; + +static struct spear_modemux uart3_modemux[][1] = { + { + /* Select signals on pins 8_9 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_8_9_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg), + }, + }, { + /* Select signals on pins 15_16 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_15_16_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg), + }, + }, { + /* Select signals on pins 41_42 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_41_42_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg), + }, + }, { + /* Select signals on pins 52_53 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_52_53_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg), + }, + }, { + /* Select signals on pins 73_74 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_73_74_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg), + }, + }, { + /* Select signals on pins 94_95 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_94_95_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg), + }, + }, { + /* Select signals on pins 98_99 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart3_ext_98_99_muxreg, + .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg), + }, + }, +}; + +static struct spear_pingroup uart3_pingroup[] = { + { + .name = "uart3_8_9_grp", + .pins = uart3_pins[0], + .npins = ARRAY_SIZE(uart3_pins[0]), + .modemuxs = uart3_modemux[0], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]), + }, { + .name = "uart3_15_16_grp", + .pins = uart3_pins[1], + .npins = ARRAY_SIZE(uart3_pins[1]), + .modemuxs = uart3_modemux[1], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]), + }, { + .name = "uart3_41_42_grp", + .pins = uart3_pins[2], + .npins = ARRAY_SIZE(uart3_pins[2]), + .modemuxs = uart3_modemux[2], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]), + }, { + .name = "uart3_52_53_grp", + .pins = uart3_pins[3], + .npins = ARRAY_SIZE(uart3_pins[3]), + .modemuxs = uart3_modemux[3], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]), + }, { + .name = "uart3_73_74_grp", + .pins = uart3_pins[4], + .npins = ARRAY_SIZE(uart3_pins[4]), + .modemuxs = uart3_modemux[4], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]), + }, { + .name = "uart3_94_95_grp", + .pins = uart3_pins[5], + .npins = ARRAY_SIZE(uart3_pins[5]), + .modemuxs = uart3_modemux[5], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]), + }, { + .name = "uart3_98_99_grp", + .pins = uart3_pins[6], + .npins = ARRAY_SIZE(uart3_pins[6]), + .modemuxs = uart3_modemux[6], + .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]), + }, +}; + +static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp", + "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp", + "uart3_94_95_grp", "uart3_98_99_grp" }; + +static struct spear_function uart3_function = { + .name = "uart3", + .groups = uart3_grps, + .ngroups = ARRAY_SIZE(uart3_grps), +}; + +/* Pad multiplexing for uart4 device */ +static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 }, + { 71, 72 }, { 92, 93 }, { 100, 101 } }; + +static struct spear_muxreg uart4_ext_6_7_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_6_7_MASK, + .val = PMX_UART4_PL_6_7_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_6_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_13_14_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_13_14_MASK, + .val = PMX_UART4_PL_13_14_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_13_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_39_40_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_39_MASK, + .val = PMX_UART4_PL_39_VAL, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_40_MASK, + .val = PMX_UART4_PL_40_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_39_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_71_72_muxreg[] = { + { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_71_72_MASK, + .val = PMX_UART4_PL_71_72_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_71_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_92_93_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_92_93_MASK, + .val = PMX_UART4_PL_92_93_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PORT_92_VAL, + }, +}; + +static struct spear_muxreg uart4_ext_100_101_muxreg[] = { + { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_PL_100_101_MASK | + PMX_UART4_PORT_SEL_MASK, + .val = PMX_UART4_PL_100_101_VAL | + PMX_UART4_PORT_101_VAL, + }, +}; + +static struct spear_modemux uart4_modemux[][1] = { + { + /* Select signals on pins 6_7 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_6_7_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg), + }, + }, { + /* Select signals on pins 13_14 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_13_14_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg), + }, + }, { + /* Select signals on pins 39_40 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_39_40_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg), + }, + }, { + /* Select signals on pins 71_72 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_71_72_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg), + }, + }, { + /* Select signals on pins 92_93 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_92_93_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg), + }, + }, { + /* Select signals on pins 100_101_ */ + { + .modes = EXTENDED_MODE, + .muxregs = uart4_ext_100_101_muxreg, + .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg), + }, + }, +}; + +static struct spear_pingroup uart4_pingroup[] = { + { + .name = "uart4_6_7_grp", + .pins = uart4_pins[0], + .npins = ARRAY_SIZE(uart4_pins[0]), + .modemuxs = uart4_modemux[0], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]), + }, { + .name = "uart4_13_14_grp", + .pins = uart4_pins[1], + .npins = ARRAY_SIZE(uart4_pins[1]), + .modemuxs = uart4_modemux[1], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]), + }, { + .name = "uart4_39_40_grp", + .pins = uart4_pins[2], + .npins = ARRAY_SIZE(uart4_pins[2]), + .modemuxs = uart4_modemux[2], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]), + }, { + .name = "uart4_71_72_grp", + .pins = uart4_pins[3], + .npins = ARRAY_SIZE(uart4_pins[3]), + .modemuxs = uart4_modemux[3], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]), + }, { + .name = "uart4_92_93_grp", + .pins = uart4_pins[4], + .npins = ARRAY_SIZE(uart4_pins[4]), + .modemuxs = uart4_modemux[4], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]), + }, { + .name = "uart4_100_101_grp", + .pins = uart4_pins[5], + .npins = ARRAY_SIZE(uart4_pins[5]), + .modemuxs = uart4_modemux[5], + .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]), + }, +}; + +static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp", + "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", + "uart4_100_101_grp" }; + +static struct spear_function uart4_function = { + .name = "uart4", + .groups = uart4_grps, + .ngroups = ARRAY_SIZE(uart4_grps), +}; + +/* Pad multiplexing for uart5 device */ +static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 }, + { 90, 91 } }; + +static struct spear_muxreg uart5_ext_4_5_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_I2C_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_4_5_MASK, + .val = PMX_UART5_PL_4_5_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART5_PORT_SEL_MASK, + .val = PMX_UART5_PORT_4_VAL, + }, +}; + +static struct spear_muxreg uart5_ext_37_38_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_37_38_MASK, + .val = PMX_UART5_PL_37_38_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART5_PORT_SEL_MASK, + .val = PMX_UART5_PORT_37_VAL, + }, +}; + +static struct spear_muxreg uart5_ext_69_70_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_69_MASK, + .val = PMX_UART5_PL_69_VAL, + }, { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_70_MASK, + .val = PMX_UART5_PL_70_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART5_PORT_SEL_MASK, + .val = PMX_UART5_PORT_69_VAL, + }, +}; + +static struct spear_muxreg uart5_ext_90_91_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK, + .val = PMX_UART5_PL_90_91_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART5_PORT_SEL_MASK, + .val = PMX_UART5_PORT_90_VAL, + }, +}; + +static struct spear_modemux uart5_modemux[][1] = { + { + /* Select signals on pins 4_5 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart5_ext_4_5_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg), + }, + }, { + /* Select signals on pins 37_38 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart5_ext_37_38_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg), + }, + }, { + /* Select signals on pins 69_70 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart5_ext_69_70_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg), + }, + }, { + /* Select signals on pins 90_91 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart5_ext_90_91_muxreg, + .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg), + }, + }, +}; + +static struct spear_pingroup uart5_pingroup[] = { + { + .name = "uart5_4_5_grp", + .pins = uart5_pins[0], + .npins = ARRAY_SIZE(uart5_pins[0]), + .modemuxs = uart5_modemux[0], + .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]), + }, { + .name = "uart5_37_38_grp", + .pins = uart5_pins[1], + .npins = ARRAY_SIZE(uart5_pins[1]), + .modemuxs = uart5_modemux[1], + .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]), + }, { + .name = "uart5_69_70_grp", + .pins = uart5_pins[2], + .npins = ARRAY_SIZE(uart5_pins[2]), + .modemuxs = uart5_modemux[2], + .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]), + }, { + .name = "uart5_90_91_grp", + .pins = uart5_pins[3], + .npins = ARRAY_SIZE(uart5_pins[3]), + .modemuxs = uart5_modemux[3], + .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]), + }, +}; + +static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp", + "uart5_69_70_grp", "uart5_90_91_grp" }; +static struct spear_function uart5_function = { + .name = "uart5", + .groups = uart5_grps, + .ngroups = ARRAY_SIZE(uart5_grps), +}; + +/* Pad multiplexing for uart6 device */ +static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } }; +static struct spear_muxreg uart6_ext_2_3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_2_3_MASK, + .val = PMX_UART6_PL_2_3_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART6_PORT_SEL_MASK, + .val = PMX_UART6_PORT_2_VAL, + }, +}; + +static struct spear_muxreg uart6_ext_88_89_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_88_89_MASK, + .val = PMX_UART6_PL_88_89_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_UART6_PORT_SEL_MASK, + .val = PMX_UART6_PORT_88_VAL, + }, +}; + +static struct spear_modemux uart6_modemux[][1] = { + { + /* Select signals on pins 2_3 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart6_ext_2_3_muxreg, + .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg), + }, + }, { + /* Select signals on pins 88_89 */ + { + .modes = EXTENDED_MODE, + .muxregs = uart6_ext_88_89_muxreg, + .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg), + }, + }, +}; + +static struct spear_pingroup uart6_pingroup[] = { + { + .name = "uart6_2_3_grp", + .pins = uart6_pins[0], + .npins = ARRAY_SIZE(uart6_pins[0]), + .modemuxs = uart6_modemux[0], + .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]), + }, { + .name = "uart6_88_89_grp", + .pins = uart6_pins[1], + .npins = ARRAY_SIZE(uart6_pins[1]), + .modemuxs = uart6_modemux[1], + .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]), + }, +}; + +static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" }; +static struct spear_function uart6_function = { + .name = "uart6", + .groups = uart6_grps, + .ngroups = ARRAY_SIZE(uart6_grps), +}; + +/* UART - RS485 pmx */ +static const unsigned rs485_pins[] = { 77, 78, 79 }; +static struct spear_muxreg rs485_muxreg[] = { + { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_77_78_79_MASK, + .val = PMX_RS485_PL_77_78_79_VAL, + }, +}; + +static struct spear_modemux rs485_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = rs485_muxreg, + .nmuxregs = ARRAY_SIZE(rs485_muxreg), + }, +}; + +static struct spear_pingroup rs485_pingroup = { + .name = "rs485_grp", + .pins = rs485_pins, + .npins = ARRAY_SIZE(rs485_pins), + .modemuxs = rs485_modemux, + .nmodemuxs = ARRAY_SIZE(rs485_modemux), +}; + +static const char *const rs485_grps[] = { "rs485_grp" }; +static struct spear_function rs485_function = { + .name = "rs485", + .groups = rs485_grps, + .ngroups = ARRAY_SIZE(rs485_grps), +}; + +/* Pad multiplexing for Touchscreen device */ +static const unsigned touchscreen_pins[] = { 5, 36 }; +static struct spear_muxreg touchscreen_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg touchscreen_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_5_MASK, + .val = PMX_TOUCH_Y_PL_5_VAL, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_36_MASK, + .val = PMX_TOUCH_X_PL_36_VAL, + }, +}; + +static struct spear_modemux touchscreen_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, + .muxregs = touchscreen_muxreg, + .nmuxregs = ARRAY_SIZE(touchscreen_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = touchscreen_ext_muxreg, + .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg), + }, +}; + +static struct spear_pingroup touchscreen_pingroup = { + .name = "touchscreen_grp", + .pins = touchscreen_pins, + .npins = ARRAY_SIZE(touchscreen_pins), + .modemuxs = touchscreen_modemux, + .nmodemuxs = ARRAY_SIZE(touchscreen_modemux), +}; + +static const char *const touchscreen_grps[] = { "touchscreen_grp" }; +static struct spear_function touchscreen_function = { + .name = "touchscreen", + .groups = touchscreen_grps, + .ngroups = ARRAY_SIZE(touchscreen_grps), +}; + +/* Pad multiplexing for CAN device */ +static const unsigned can0_pins[] = { 32, 33 }; +static struct spear_muxreg can0_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg can0_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_32_33_MASK, + .val = PMX_CAN0_PL_32_33_VAL, + }, +}; + +static struct spear_modemux can0_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE + | EXTENDED_MODE, + .muxregs = can0_muxreg, + .nmuxregs = ARRAY_SIZE(can0_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = can0_ext_muxreg, + .nmuxregs = ARRAY_SIZE(can0_ext_muxreg), + }, +}; + +static struct spear_pingroup can0_pingroup = { + .name = "can0_grp", + .pins = can0_pins, + .npins = ARRAY_SIZE(can0_pins), + .modemuxs = can0_modemux, + .nmodemuxs = ARRAY_SIZE(can0_modemux), +}; + +static const char *const can0_grps[] = { "can0_grp" }; +static struct spear_function can0_function = { + .name = "can0", + .groups = can0_grps, + .ngroups = ARRAY_SIZE(can0_grps), +}; + +static const unsigned can1_pins[] = { 30, 31 }; +static struct spear_muxreg can1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg can1_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_30_31_MASK, + .val = PMX_CAN1_PL_30_31_VAL, + }, +}; + +static struct spear_modemux can1_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE + | EXTENDED_MODE, + .muxregs = can1_muxreg, + .nmuxregs = ARRAY_SIZE(can1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = can1_ext_muxreg, + .nmuxregs = ARRAY_SIZE(can1_ext_muxreg), + }, +}; + +static struct spear_pingroup can1_pingroup = { + .name = "can1_grp", + .pins = can1_pins, + .npins = ARRAY_SIZE(can1_pins), + .modemuxs = can1_modemux, + .nmodemuxs = ARRAY_SIZE(can1_modemux), +}; + +static const char *const can1_grps[] = { "can1_grp" }; +static struct spear_function can1_function = { + .name = "can1", + .groups = can1_grps, + .ngroups = ARRAY_SIZE(can1_grps), +}; + +/* Pad multiplexing for PWM0_1 device */ +static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 }, + { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } }; + +static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_8_9_MASK, + .val = PMX_PWM_0_1_PL_8_9_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_14_MASK | PMX_PL_15_MASK, + .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_30_MASK | PMX_PL_31_MASK, + .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_net_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = { + { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_37_38_MASK, + .val = PMX_PWM0_1_PL_37_38_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK , + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_42_MASK | PMX_PL_43_MASK, + .val = PMX_PWM1_PL_42_VAL | + PMX_PWM0_PL_43_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_59_MASK, + .val = PMX_PWM1_PL_59_VAL, + }, { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_60_MASK, + .val = PMX_PWM0_PL_60_VAL, + }, +}; + +static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_88_89_MASK, + .val = PMX_PWM0_1_PL_88_89_VAL, + }, +}; + +static struct spear_modemux pwm0_1_pin_8_9_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_8_9_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_14_15_modemux[] = { + { + .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = pwm0_1_autoexpsmallpri_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_14_15_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_30_31_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_30_31_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_37_38_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, + .muxregs = pwm0_1_net_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_37_38_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_42_43_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_42_43_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_59_60_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_59_60_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg), + }, +}; + +static struct spear_modemux pwm0_1_pin_88_89_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm0_1_pin_88_89_muxreg, + .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg), + }, +}; + +static struct spear_pingroup pwm0_1_pingroup[] = { + { + .name = "pwm0_1_pin_8_9_grp", + .pins = pwm0_1_pins[0], + .npins = ARRAY_SIZE(pwm0_1_pins[0]), + .modemuxs = pwm0_1_pin_8_9_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux), + }, { + .name = "pwm0_1_pin_14_15_grp", + .pins = pwm0_1_pins[1], + .npins = ARRAY_SIZE(pwm0_1_pins[1]), + .modemuxs = pwm0_1_pin_14_15_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux), + }, { + .name = "pwm0_1_pin_30_31_grp", + .pins = pwm0_1_pins[2], + .npins = ARRAY_SIZE(pwm0_1_pins[2]), + .modemuxs = pwm0_1_pin_30_31_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux), + }, { + .name = "pwm0_1_pin_37_38_grp", + .pins = pwm0_1_pins[3], + .npins = ARRAY_SIZE(pwm0_1_pins[3]), + .modemuxs = pwm0_1_pin_37_38_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux), + }, { + .name = "pwm0_1_pin_42_43_grp", + .pins = pwm0_1_pins[4], + .npins = ARRAY_SIZE(pwm0_1_pins[4]), + .modemuxs = pwm0_1_pin_42_43_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux), + }, { + .name = "pwm0_1_pin_59_60_grp", + .pins = pwm0_1_pins[5], + .npins = ARRAY_SIZE(pwm0_1_pins[5]), + .modemuxs = pwm0_1_pin_59_60_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux), + }, { + .name = "pwm0_1_pin_88_89_grp", + .pins = pwm0_1_pins[6], + .npins = ARRAY_SIZE(pwm0_1_pins[6]), + .modemuxs = pwm0_1_pin_88_89_modemux, + .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux), + }, +}; + +static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp", + "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", + "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp" +}; + +static struct spear_function pwm0_1_function = { + .name = "pwm0_1", + .groups = pwm0_1_grps, + .ngroups = ARRAY_SIZE(pwm0_1_grps), +}; + +/* Pad multiplexing for PWM2 device */ +static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 }, + { 58 }, { 87 } }; +static struct spear_muxreg pwm2_net_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm2_pin_7_muxreg[] = { + { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_7_MASK, + .val = PMX_PWM_2_PL_7_VAL, + }, +}; + +static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm2_pin_13_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_13_MASK, + .val = PMX_PWM2_PL_13_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_29_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN1_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_29_MASK, + .val = PMX_PWM_2_PL_29_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_34_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, { + .reg = MODE_CONFIG_REG, + .mask = PMX_PWM_MASK, + .val = PMX_PWM_MASK, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_34_MASK, + .val = PMX_PWM2_PL_34_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_41_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_41_MASK, + .val = PMX_PWM2_PL_41_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_58_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_58_MASK, + .val = PMX_PWM2_PL_58_VAL, + }, +}; + +static struct spear_muxreg pwm2_pin_87_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_87_MASK, + .val = PMX_PWM2_PL_87_VAL, + }, +}; + +static struct spear_modemux pwm2_pin_7_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, + .muxregs = pwm2_net_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_7_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg), + }, +}; +static struct spear_modemux pwm2_pin_13_modemux[] = { + { + .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = pwm2_autoexpsmallpri_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_13_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg), + }, +}; +static struct spear_modemux pwm2_pin_29_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_29_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg), + }, +}; +static struct spear_modemux pwm2_pin_34_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_34_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg), + }, +}; + +static struct spear_modemux pwm2_pin_41_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_41_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg), + }, +}; + +static struct spear_modemux pwm2_pin_58_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_58_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg), + }, +}; + +static struct spear_modemux pwm2_pin_87_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm2_pin_87_muxreg, + .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg), + }, +}; + +static struct spear_pingroup pwm2_pingroup[] = { + { + .name = "pwm2_pin_7_grp", + .pins = pwm2_pins[0], + .npins = ARRAY_SIZE(pwm2_pins[0]), + .modemuxs = pwm2_pin_7_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux), + }, { + .name = "pwm2_pin_13_grp", + .pins = pwm2_pins[1], + .npins = ARRAY_SIZE(pwm2_pins[1]), + .modemuxs = pwm2_pin_13_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux), + }, { + .name = "pwm2_pin_29_grp", + .pins = pwm2_pins[2], + .npins = ARRAY_SIZE(pwm2_pins[2]), + .modemuxs = pwm2_pin_29_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux), + }, { + .name = "pwm2_pin_34_grp", + .pins = pwm2_pins[3], + .npins = ARRAY_SIZE(pwm2_pins[3]), + .modemuxs = pwm2_pin_34_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux), + }, { + .name = "pwm2_pin_41_grp", + .pins = pwm2_pins[4], + .npins = ARRAY_SIZE(pwm2_pins[4]), + .modemuxs = pwm2_pin_41_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux), + }, { + .name = "pwm2_pin_58_grp", + .pins = pwm2_pins[5], + .npins = ARRAY_SIZE(pwm2_pins[5]), + .modemuxs = pwm2_pin_58_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux), + }, { + .name = "pwm2_pin_87_grp", + .pins = pwm2_pins[6], + .npins = ARRAY_SIZE(pwm2_pins[6]), + .modemuxs = pwm2_pin_87_modemux, + .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux), + }, +}; + +static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp", + "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp", + "pwm2_pin_58_grp", "pwm2_pin_87_grp" }; +static struct spear_function pwm2_function = { + .name = "pwm2", + .groups = pwm2_grps, + .ngroups = ARRAY_SIZE(pwm2_grps), +}; + +/* Pad multiplexing for PWM3 device */ +static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 }, + { 86 } }; +static struct spear_muxreg pwm3_pin_6_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_6_MASK, + .val = PMX_PWM_3_PL_6_VAL, + }, +}; + +static struct spear_muxreg pwm3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg pwm3_pin_12_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_12_MASK, + .val = PMX_PWM3_PL_12_VAL, + }, +}; + +static struct spear_muxreg pwm3_pin_28_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_GPIO_PIN0_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_28_MASK, + .val = PMX_PWM_3_PL_28_VAL, + }, +}; + +static struct spear_muxreg pwm3_pin_40_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_40_MASK, + .val = PMX_PWM3_PL_40_VAL, + }, +}; + +static struct spear_muxreg pwm3_pin_57_muxreg[] = { + { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_57_MASK, + .val = PMX_PWM3_PL_57_VAL, + }, +}; + +static struct spear_muxreg pwm3_pin_86_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_86_MASK, + .val = PMX_PWM3_PL_86_VAL, + }, +}; + +static struct spear_modemux pwm3_pin_6_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_6_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_12_modemux[] = { + { + .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | + AUTO_NET_SMII_MODE | EXTENDED_MODE, + .muxregs = pwm3_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_12_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_28_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_28_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_40_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_40_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_57_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_57_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg), + }, +}; + +static struct spear_modemux pwm3_pin_86_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = pwm3_pin_86_muxreg, + .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg), + }, +}; + +static struct spear_pingroup pwm3_pingroup[] = { + { + .name = "pwm3_pin_6_grp", + .pins = pwm3_pins[0], + .npins = ARRAY_SIZE(pwm3_pins[0]), + .modemuxs = pwm3_pin_6_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux), + }, { + .name = "pwm3_pin_12_grp", + .pins = pwm3_pins[1], + .npins = ARRAY_SIZE(pwm3_pins[1]), + .modemuxs = pwm3_pin_12_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux), + }, { + .name = "pwm3_pin_28_grp", + .pins = pwm3_pins[2], + .npins = ARRAY_SIZE(pwm3_pins[2]), + .modemuxs = pwm3_pin_28_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux), + }, { + .name = "pwm3_pin_40_grp", + .pins = pwm3_pins[3], + .npins = ARRAY_SIZE(pwm3_pins[3]), + .modemuxs = pwm3_pin_40_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux), + }, { + .name = "pwm3_pin_57_grp", + .pins = pwm3_pins[4], + .npins = ARRAY_SIZE(pwm3_pins[4]), + .modemuxs = pwm3_pin_57_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux), + }, { + .name = "pwm3_pin_86_grp", + .pins = pwm3_pins[5], + .npins = ARRAY_SIZE(pwm3_pins[5]), + .modemuxs = pwm3_pin_86_modemux, + .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux), + }, +}; + +static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp", + "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp", + "pwm3_pin_86_grp" }; +static struct spear_function pwm3_function = { + .name = "pwm3", + .groups = pwm3_grps, + .ngroups = ARRAY_SIZE(pwm3_grps), +}; + +/* Pad multiplexing for SSP1 device */ +static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 }, + { 65, 68 }, { 94, 97 } }; +static struct spear_muxreg ssp1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg ssp1_ext_17_20_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK, + .val = PMX_SSP1_PL_17_18_19_20_VAL, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_20_MASK, + .val = PMX_SSP1_PL_17_18_19_20_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_17_TO_20_VAL, + }, +}; + +static struct spear_muxreg ssp1_ext_36_39_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK, + .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL | + PMX_SSP1_PL_39_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_36_TO_39_VAL, + }, +}; + +static struct spear_muxreg ssp1_ext_48_51_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_48_49_MASK, + .val = PMX_SSP1_PL_48_49_VAL, + }, { + .reg = IP_SEL_PAD_50_59_REG, + .mask = PMX_PL_50_51_MASK, + .val = PMX_SSP1_PL_50_51_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_48_TO_51_VAL, + }, +}; + +static struct spear_muxreg ssp1_ext_65_68_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_65_TO_68_MASK, + .val = PMX_SSP1_PL_65_TO_68_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_65_TO_68_VAL, + }, +}; + +static struct spear_muxreg ssp1_ext_94_97_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, + .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP1_PORT_SEL_MASK, + .val = PMX_SSP1_PORT_94_TO_97_VAL, + }, +}; + +static struct spear_modemux ssp1_17_20_modemux[] = { + { + .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE | + EXTENDED_MODE, + .muxregs = ssp1_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_17_20_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg), + }, +}; + +static struct spear_modemux ssp1_36_39_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_36_39_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg), + }, +}; + +static struct spear_modemux ssp1_48_51_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_48_51_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg), + }, +}; +static struct spear_modemux ssp1_65_68_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_65_68_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg), + }, +}; + +static struct spear_modemux ssp1_94_97_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp1_ext_94_97_muxreg, + .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg), + }, +}; + +static struct spear_pingroup ssp1_pingroup[] = { + { + .name = "ssp1_17_20_grp", + .pins = ssp1_pins[0], + .npins = ARRAY_SIZE(ssp1_pins[0]), + .modemuxs = ssp1_17_20_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux), + }, { + .name = "ssp1_36_39_grp", + .pins = ssp1_pins[1], + .npins = ARRAY_SIZE(ssp1_pins[1]), + .modemuxs = ssp1_36_39_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux), + }, { + .name = "ssp1_48_51_grp", + .pins = ssp1_pins[2], + .npins = ARRAY_SIZE(ssp1_pins[2]), + .modemuxs = ssp1_48_51_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux), + }, { + .name = "ssp1_65_68_grp", + .pins = ssp1_pins[3], + .npins = ARRAY_SIZE(ssp1_pins[3]), + .modemuxs = ssp1_65_68_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux), + }, { + .name = "ssp1_94_97_grp", + .pins = ssp1_pins[4], + .npins = ARRAY_SIZE(ssp1_pins[4]), + .modemuxs = ssp1_94_97_modemux, + .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux), + }, +}; + +static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp", + "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp" +}; +static struct spear_function ssp1_function = { + .name = "ssp1", + .groups = ssp1_grps, + .ngroups = ARRAY_SIZE(ssp1_grps), +}; + +/* Pad multiplexing for SSP2 device */ +static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 }, + { 61, 64 }, { 90, 93 } }; +static struct spear_muxreg ssp2_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg ssp2_ext_13_16_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK, + .val = PMX_SSP2_PL_13_14_15_16_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_13_TO_16_VAL, + }, +}; + +static struct spear_muxreg ssp2_ext_32_35_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK | + PMX_GPIO_PIN5_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_30_39_REG, + .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK, + .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL | + PMX_SSP2_PL_35_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_32_TO_35_VAL, + }, +}; + +static struct spear_muxreg ssp2_ext_44_47_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_40_49_REG, + .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK, + .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_44_TO_47_VAL, + }, +}; + +static struct spear_muxreg ssp2_ext_61_64_muxreg[] = { + { + .reg = IP_SEL_PAD_60_69_REG, + .mask = PMX_PL_61_TO_64_MASK, + .val = PMX_SSP2_PL_61_TO_64_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_61_TO_64_VAL, + }, +}; + +static struct spear_muxreg ssp2_ext_90_93_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK, + .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_SSP2_PORT_SEL_MASK, + .val = PMX_SSP2_PORT_90_TO_93_VAL, + }, +}; + +static struct spear_modemux ssp2_13_16_modemux[] = { + { + .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, + .muxregs = ssp2_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_13_16_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg), + }, +}; + +static struct spear_modemux ssp2_32_35_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_32_35_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg), + }, +}; + +static struct spear_modemux ssp2_44_47_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_44_47_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg), + }, +}; + +static struct spear_modemux ssp2_61_64_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_61_64_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg), + }, +}; + +static struct spear_modemux ssp2_90_93_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = ssp2_ext_90_93_muxreg, + .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg), + }, +}; + +static struct spear_pingroup ssp2_pingroup[] = { + { + .name = "ssp2_13_16_grp", + .pins = ssp2_pins[0], + .npins = ARRAY_SIZE(ssp2_pins[0]), + .modemuxs = ssp2_13_16_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux), + }, { + .name = "ssp2_32_35_grp", + .pins = ssp2_pins[1], + .npins = ARRAY_SIZE(ssp2_pins[1]), + .modemuxs = ssp2_32_35_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux), + }, { + .name = "ssp2_44_47_grp", + .pins = ssp2_pins[2], + .npins = ARRAY_SIZE(ssp2_pins[2]), + .modemuxs = ssp2_44_47_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux), + }, { + .name = "ssp2_61_64_grp", + .pins = ssp2_pins[3], + .npins = ARRAY_SIZE(ssp2_pins[3]), + .modemuxs = ssp2_61_64_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux), + }, { + .name = "ssp2_90_93_grp", + .pins = ssp2_pins[4], + .npins = ARRAY_SIZE(ssp2_pins[4]), + .modemuxs = ssp2_90_93_modemux, + .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux), + }, +}; + +static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp", + "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" }; +static struct spear_function ssp2_function = { + .name = "ssp2", + .groups = ssp2_grps, + .ngroups = ARRAY_SIZE(ssp2_grps), +}; + +/* Pad multiplexing for cadence mii2 as mii device */ +static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, + 90, 91, 92, 93, 94, 95, 96, 97 }; +static struct spear_muxreg mii2_muxreg[] = { + { + .reg = IP_SEL_PAD_80_89_REG, + .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | + PMX_PL_88_89_MASK, + .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL | + PMX_MII2_PL_88_89_VAL, + }, { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | + PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, + .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL | + PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | + (MAC_MODE_MASK << MAC1_MODE_SHIFT) | + MII_MDIO_MASK, + .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) | + (MAC_MODE_MII << MAC1_MODE_SHIFT) | + MII_MDIO_81_VAL, + }, +}; + +static struct spear_modemux mii2_modemux[] = { + { + .modes = EXTENDED_MODE, + .muxregs = mii2_muxreg, + .nmuxregs = ARRAY_SIZE(mii2_muxreg), + }, +}; + +static struct spear_pingroup mii2_pingroup = { + .name = "mii2_grp", + .pins = mii2_pins, + .npins = ARRAY_SIZE(mii2_pins), + .modemuxs = mii2_modemux, + .nmodemuxs = ARRAY_SIZE(mii2_modemux), +}; + +static const char *const mii2_grps[] = { "mii2_grp" }; +static struct spear_function mii2_function = { + .name = "mii2", + .groups = mii2_grps, + .ngroups = ARRAY_SIZE(mii2_grps), +}; + +/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */ +static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27 }; +static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; +static struct spear_muxreg mii0_1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, +}; + +static struct spear_muxreg smii0_1_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_10_11_MASK, + .val = PMX_SMII_PL_10_11_VAL, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_21_TO_27_MASK, + .val = PMX_SMII_PL_21_TO_27_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | + (MAC_MODE_MASK << MAC1_MODE_SHIFT) | + MII_MDIO_MASK, + .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT) + | (MAC_MODE_SMII << MAC1_MODE_SHIFT) + | MII_MDIO_10_11_VAL, + }, +}; + +static struct spear_muxreg rmii0_1_ext_muxreg[] = { + { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK | + PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK, + .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL | + PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL | + PMX_RMII_PL_19_VAL, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK, + .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL, + }, { + .reg = EXT_CTRL_REG, + .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | + (MAC_MODE_MASK << MAC1_MODE_SHIFT) | + MII_MDIO_MASK, + .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT) + | (MAC_MODE_RMII << MAC1_MODE_SHIFT) + | MII_MDIO_10_11_VAL, + }, +}; + +static struct spear_modemux mii0_1_modemux[][2] = { + { + /* configure as smii */ + { + .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | + SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = mii0_1_muxreg, + .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = smii0_1_ext_muxreg, + .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg), + }, + }, { + /* configure as rmii */ + { + .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | + SMALL_PRINTERS_MODE | EXTENDED_MODE, + .muxregs = mii0_1_muxreg, + .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), + }, { + .modes = EXTENDED_MODE, + .muxregs = rmii0_1_ext_muxreg, + .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg), + }, + }, +}; + +static struct spear_pingroup mii0_1_pingroup[] = { + { + .name = "smii0_1_grp", + .pins = smii0_1_pins, + .npins = ARRAY_SIZE(smii0_1_pins), + .modemuxs = mii0_1_modemux[0], + .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]), + }, { + .name = "rmii0_1_grp", + .pins = rmii0_1_pins, + .npins = ARRAY_SIZE(rmii0_1_pins), + .modemuxs = mii0_1_modemux[1], + .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]), + }, +}; + +static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" }; +static struct spear_function mii0_1_function = { + .name = "mii0_1", + .groups = mii0_1_grps, + .ngroups = ARRAY_SIZE(mii0_1_grps), +}; + +/* Pad multiplexing for i2c1 device */ +static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } }; +static struct spear_muxreg i2c1_ext_8_9_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_SSP_CS_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_8_9_MASK, + .val = PMX_I2C1_PL_8_9_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C1_PORT_SEL_MASK, + .val = PMX_I2C1_PORT_8_9_VAL, + }, +}; + +static struct spear_muxreg i2c1_ext_98_99_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, + .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C1_PORT_SEL_MASK, + .val = PMX_I2C1_PORT_98_99_VAL, + }, +}; + +static struct spear_modemux i2c1_modemux[][1] = { + { + /* Select signals on pins 8-9 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c1_ext_8_9_muxreg, + .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg), + }, + }, { + /* Select signals on pins 98-99 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c1_ext_98_99_muxreg, + .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg), + }, + }, +}; + +static struct spear_pingroup i2c1_pingroup[] = { + { + .name = "i2c1_8_9_grp", + .pins = i2c1_pins[0], + .npins = ARRAY_SIZE(i2c1_pins[0]), + .modemuxs = i2c1_modemux[0], + .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]), + }, { + .name = "i2c1_98_99_grp", + .pins = i2c1_pins[1], + .npins = ARRAY_SIZE(i2c1_pins[1]), + .modemuxs = i2c1_modemux[1], + .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]), + }, +}; + +static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" }; +static struct spear_function i2c1_function = { + .name = "i2c1", + .groups = i2c1_grps, + .ngroups = ARRAY_SIZE(i2c1_grps), +}; + +/* Pad multiplexing for i2c2 device */ +static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 }, + { 75, 76 }, { 96, 97 } }; +static struct spear_muxreg i2c2_ext_0_1_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_FIRDA_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_0_1_MASK, + .val = PMX_I2C2_PL_0_1_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_0_1_VAL, + }, +}; + +static struct spear_muxreg i2c2_ext_2_3_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_UART0_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_0_9_REG, + .mask = PMX_PL_2_3_MASK, + .val = PMX_I2C2_PL_2_3_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_2_3_VAL, + }, +}; + +static struct spear_muxreg i2c2_ext_19_20_muxreg[] = { + { + .reg = PMX_CONFIG_REG, + .mask = PMX_MII_MASK, + .val = 0, + }, { + .reg = IP_SEL_PAD_10_19_REG, + .mask = PMX_PL_19_MASK, + .val = PMX_I2C2_PL_19_VAL, + }, { + .reg = IP_SEL_PAD_20_29_REG, + .mask = PMX_PL_20_MASK, + .val = PMX_I2C2_PL_20_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_19_20_VAL, + }, +}; + +static struct spear_muxreg i2c2_ext_75_76_muxreg[] = { + { + .reg = IP_SEL_PAD_70_79_REG, + .mask = PMX_PL_75_76_MASK, + .val = PMX_I2C2_PL_75_76_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_75_76_VAL, + }, +}; + +static struct spear_muxreg i2c2_ext_96_97_muxreg[] = { + { + .reg = IP_SEL_PAD_90_99_REG, + .mask = PMX_PL_96_97_MASK, + .val = PMX_I2C2_PL_96_97_VAL, + }, { + .reg = IP_SEL_MIX_PAD_REG, + .mask = PMX_I2C2_PORT_SEL_MASK, + .val = PMX_I2C2_PORT_96_97_VAL, + }, +}; + +static struct spear_modemux i2c2_modemux[][1] = { + { + /* Select signals on pins 0_1 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_0_1_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg), + }, + }, { + /* Select signals on pins 2_3 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_2_3_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg), + }, + }, { + /* Select signals on pins 19_20 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_19_20_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg), + }, + }, { + /* Select signals on pins 75_76 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_75_76_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg), + }, + }, { + /* Select signals on pins 96_97 */ + { + .modes = EXTENDED_MODE, + .muxregs = i2c2_ext_96_97_muxreg, + .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg), + }, + }, +}; + +static struct spear_pingroup i2c2_pingroup[] = { + { + .name = "i2c2_0_1_grp", + .pins = i2c2_pins[0], + .npins = ARRAY_SIZE(i2c2_pins[0]), + .modemuxs = i2c2_modemux[0], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]), + }, { + .name = "i2c2_2_3_grp", + .pins = i2c2_pins[1], + .npins = ARRAY_SIZE(i2c2_pins[1]), + .modemuxs = i2c2_modemux[1], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]), + }, { + .name = "i2c2_19_20_grp", + .pins = i2c2_pins[2], + .npins = ARRAY_SIZE(i2c2_pins[2]), + .modemuxs = i2c2_modemux[2], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]), + }, { + .name = "i2c2_75_76_grp", + .pins = i2c2_pins[3], + .npins = ARRAY_SIZE(i2c2_pins[3]), + .modemuxs = i2c2_modemux[3], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]), + }, { + .name = "i2c2_96_97_grp", + .pins = i2c2_pins[4], + .npins = ARRAY_SIZE(i2c2_pins[4]), + .modemuxs = i2c2_modemux[4], + .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]), + }, +}; + +static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp", + "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" }; +static struct spear_function i2c2_function = { + .name = "i2c2", + .groups = i2c2_grps, + .ngroups = ARRAY_SIZE(i2c2_grps), +}; + +/* pingroups */ +static struct spear_pingroup *spear320_pingroups[] = { + SPEAR3XX_COMMON_PINGROUPS, + &clcd_pingroup, + &emi_pingroup, + &fsmc_8bit_pingroup, + &fsmc_16bit_pingroup, + &spp_pingroup, + &sdhci_led_pingroup, + &sdhci_pingroup[0], + &sdhci_pingroup[1], + &i2s_pingroup, + &uart1_pingroup, + &uart1_modem_pingroup[0], + &uart1_modem_pingroup[1], + &uart1_modem_pingroup[2], + &uart1_modem_pingroup[3], + &uart2_pingroup, + &uart3_pingroup[0], + &uart3_pingroup[1], + &uart3_pingroup[2], + &uart3_pingroup[3], + &uart3_pingroup[4], + &uart3_pingroup[5], + &uart3_pingroup[6], + &uart4_pingroup[0], + &uart4_pingroup[1], + &uart4_pingroup[2], + &uart4_pingroup[3], + &uart4_pingroup[4], + &uart4_pingroup[5], + &uart5_pingroup[0], + &uart5_pingroup[1], + &uart5_pingroup[2], + &uart5_pingroup[3], + &uart6_pingroup[0], + &uart6_pingroup[1], + &rs485_pingroup, + &touchscreen_pingroup, + &can0_pingroup, + &can1_pingroup, + &pwm0_1_pingroup[0], + &pwm0_1_pingroup[1], + &pwm0_1_pingroup[2], + &pwm0_1_pingroup[3], + &pwm0_1_pingroup[4], + &pwm0_1_pingroup[5], + &pwm0_1_pingroup[6], + &pwm2_pingroup[0], + &pwm2_pingroup[1], + &pwm2_pingroup[2], + &pwm2_pingroup[3], + &pwm2_pingroup[4], + &pwm2_pingroup[5], + &pwm2_pingroup[6], + &pwm3_pingroup[0], + &pwm3_pingroup[1], + &pwm3_pingroup[2], + &pwm3_pingroup[3], + &pwm3_pingroup[4], + &pwm3_pingroup[5], + &ssp1_pingroup[0], + &ssp1_pingroup[1], + &ssp1_pingroup[2], + &ssp1_pingroup[3], + &ssp1_pingroup[4], + &ssp2_pingroup[0], + &ssp2_pingroup[1], + &ssp2_pingroup[2], + &ssp2_pingroup[3], + &ssp2_pingroup[4], + &mii2_pingroup, + &mii0_1_pingroup[0], + &mii0_1_pingroup[1], + &i2c1_pingroup[0], + &i2c1_pingroup[1], + &i2c2_pingroup[0], + &i2c2_pingroup[1], + &i2c2_pingroup[2], + &i2c2_pingroup[3], + &i2c2_pingroup[4], +}; + +/* functions */ +static struct spear_function *spear320_functions[] = { + SPEAR3XX_COMMON_FUNCTIONS, + &clcd_function, + &emi_function, + &fsmc_function, + &spp_function, + &sdhci_function, + &i2s_function, + &uart1_function, + &uart1_modem_function, + &uart2_function, + &uart3_function, + &uart4_function, + &uart5_function, + &uart6_function, + &rs485_function, + &touchscreen_function, + &can0_function, + &can1_function, + &pwm0_1_function, + &pwm2_function, + &pwm3_function, + &ssp1_function, + &ssp2_function, + &mii2_function, + &mii0_1_function, + &i2c1_function, + &i2c2_function, +}; + +static const struct of_device_id spear320_pinctrl_of_match[] = { + { + .compatible = "st,spear320-pinmux", + }, + {}, +}; + +static int spear320_pinctrl_probe(struct platform_device *pdev) +{ + spear3xx_machdata.groups = spear320_pingroups; + spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups); + spear3xx_machdata.functions = spear320_functions; + spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions); + + spear3xx_machdata.modes_supported = true; + spear3xx_machdata.pmx_modes = spear320_pmx_modes; + spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes); + + pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); + pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups, + spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG); + + return spear_pinctrl_probe(pdev, &spear3xx_machdata); +} + +static struct platform_driver spear320_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = spear320_pinctrl_of_match, + }, + .probe = spear320_pinctrl_probe, +}; + +static int __init spear320_pinctrl_init(void) +{ + return platform_driver_register(&spear320_pinctrl_driver); +} +arch_initcall(spear320_pinctrl_init); diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c new file mode 100644 index 000000000..d3119aafe --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c @@ -0,0 +1,524 @@ +/* + * Driver for the ST Microelectronics SPEAr3xx pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <vireshk@kernel.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-spear3xx.h" + +/* pins */ +static const struct pinctrl_pin_desc spear3xx_pins[] = { + SPEAR_PIN_0_TO_101, +}; + +/* firda_pins */ +static const unsigned firda_pins[] = { 0, 1 }; +static struct spear_muxreg firda_muxreg[] = { + { + .reg = -1, + .mask = PMX_FIRDA_MASK, + .val = PMX_FIRDA_MASK, + }, +}; + +static struct spear_modemux firda_modemux[] = { + { + .modes = ~0, + .muxregs = firda_muxreg, + .nmuxregs = ARRAY_SIZE(firda_muxreg), + }, +}; + +struct spear_pingroup spear3xx_firda_pingroup = { + .name = "firda_grp", + .pins = firda_pins, + .npins = ARRAY_SIZE(firda_pins), + .modemuxs = firda_modemux, + .nmodemuxs = ARRAY_SIZE(firda_modemux), +}; + +static const char *const firda_grps[] = { "firda_grp" }; +struct spear_function spear3xx_firda_function = { + .name = "firda", + .groups = firda_grps, + .ngroups = ARRAY_SIZE(firda_grps), +}; + +/* i2c_pins */ +static const unsigned i2c_pins[] = { 4, 5 }; +static struct spear_muxreg i2c_muxreg[] = { + { + .reg = -1, + .mask = PMX_I2C_MASK, + .val = PMX_I2C_MASK, + }, +}; + +static struct spear_modemux i2c_modemux[] = { + { + .modes = ~0, + .muxregs = i2c_muxreg, + .nmuxregs = ARRAY_SIZE(i2c_muxreg), + }, +}; + +struct spear_pingroup spear3xx_i2c_pingroup = { + .name = "i2c0_grp", + .pins = i2c_pins, + .npins = ARRAY_SIZE(i2c_pins), + .modemuxs = i2c_modemux, + .nmodemuxs = ARRAY_SIZE(i2c_modemux), +}; + +static const char *const i2c_grps[] = { "i2c0_grp" }; +struct spear_function spear3xx_i2c_function = { + .name = "i2c0", + .groups = i2c_grps, + .ngroups = ARRAY_SIZE(i2c_grps), +}; + +/* ssp_cs_pins */ +static const unsigned ssp_cs_pins[] = { 34, 35, 36 }; +static struct spear_muxreg ssp_cs_muxreg[] = { + { + .reg = -1, + .mask = PMX_SSP_CS_MASK, + .val = PMX_SSP_CS_MASK, + }, +}; + +static struct spear_modemux ssp_cs_modemux[] = { + { + .modes = ~0, + .muxregs = ssp_cs_muxreg, + .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg), + }, +}; + +struct spear_pingroup spear3xx_ssp_cs_pingroup = { + .name = "ssp_cs_grp", + .pins = ssp_cs_pins, + .npins = ARRAY_SIZE(ssp_cs_pins), + .modemuxs = ssp_cs_modemux, + .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux), +}; + +static const char *const ssp_cs_grps[] = { "ssp_cs_grp" }; +struct spear_function spear3xx_ssp_cs_function = { + .name = "ssp_cs", + .groups = ssp_cs_grps, + .ngroups = ARRAY_SIZE(ssp_cs_grps), +}; + +/* ssp_pins */ +static const unsigned ssp_pins[] = { 6, 7, 8, 9 }; +static struct spear_muxreg ssp_muxreg[] = { + { + .reg = -1, + .mask = PMX_SSP_MASK, + .val = PMX_SSP_MASK, + }, +}; + +static struct spear_modemux ssp_modemux[] = { + { + .modes = ~0, + .muxregs = ssp_muxreg, + .nmuxregs = ARRAY_SIZE(ssp_muxreg), + }, +}; + +struct spear_pingroup spear3xx_ssp_pingroup = { + .name = "ssp0_grp", + .pins = ssp_pins, + .npins = ARRAY_SIZE(ssp_pins), + .modemuxs = ssp_modemux, + .nmodemuxs = ARRAY_SIZE(ssp_modemux), +}; + +static const char *const ssp_grps[] = { "ssp0_grp" }; +struct spear_function spear3xx_ssp_function = { + .name = "ssp0", + .groups = ssp_grps, + .ngroups = ARRAY_SIZE(ssp_grps), +}; + +/* mii_pins */ +static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27 }; +static struct spear_muxreg mii_muxreg[] = { + { + .reg = -1, + .mask = PMX_MII_MASK, + .val = PMX_MII_MASK, + }, +}; + +static struct spear_modemux mii_modemux[] = { + { + .modes = ~0, + .muxregs = mii_muxreg, + .nmuxregs = ARRAY_SIZE(mii_muxreg), + }, +}; + +struct spear_pingroup spear3xx_mii_pingroup = { + .name = "mii0_grp", + .pins = mii_pins, + .npins = ARRAY_SIZE(mii_pins), + .modemuxs = mii_modemux, + .nmodemuxs = ARRAY_SIZE(mii_modemux), +}; + +static const char *const mii_grps[] = { "mii0_grp" }; +struct spear_function spear3xx_mii_function = { + .name = "mii0", + .groups = mii_grps, + .ngroups = ARRAY_SIZE(mii_grps), +}; + +/* gpio0_pin0_pins */ +static const unsigned gpio0_pin0_pins[] = { 28 }; +static struct spear_muxreg gpio0_pin0_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN0_MASK, + .val = PMX_GPIO_PIN0_MASK, + }, +}; + +static struct spear_modemux gpio0_pin0_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin0_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin0_pingroup = { + .name = "gpio0_pin0_grp", + .pins = gpio0_pin0_pins, + .npins = ARRAY_SIZE(gpio0_pin0_pins), + .modemuxs = gpio0_pin0_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux), +}; + +/* gpio0_pin1_pins */ +static const unsigned gpio0_pin1_pins[] = { 29 }; +static struct spear_muxreg gpio0_pin1_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN1_MASK, + .val = PMX_GPIO_PIN1_MASK, + }, +}; + +static struct spear_modemux gpio0_pin1_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin1_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin1_pingroup = { + .name = "gpio0_pin1_grp", + .pins = gpio0_pin1_pins, + .npins = ARRAY_SIZE(gpio0_pin1_pins), + .modemuxs = gpio0_pin1_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux), +}; + +/* gpio0_pin2_pins */ +static const unsigned gpio0_pin2_pins[] = { 30 }; +static struct spear_muxreg gpio0_pin2_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN2_MASK, + .val = PMX_GPIO_PIN2_MASK, + }, +}; + +static struct spear_modemux gpio0_pin2_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin2_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin2_pingroup = { + .name = "gpio0_pin2_grp", + .pins = gpio0_pin2_pins, + .npins = ARRAY_SIZE(gpio0_pin2_pins), + .modemuxs = gpio0_pin2_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux), +}; + +/* gpio0_pin3_pins */ +static const unsigned gpio0_pin3_pins[] = { 31 }; +static struct spear_muxreg gpio0_pin3_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN3_MASK, + .val = PMX_GPIO_PIN3_MASK, + }, +}; + +static struct spear_modemux gpio0_pin3_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin3_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin3_pingroup = { + .name = "gpio0_pin3_grp", + .pins = gpio0_pin3_pins, + .npins = ARRAY_SIZE(gpio0_pin3_pins), + .modemuxs = gpio0_pin3_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux), +}; + +/* gpio0_pin4_pins */ +static const unsigned gpio0_pin4_pins[] = { 32 }; +static struct spear_muxreg gpio0_pin4_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN4_MASK, + .val = PMX_GPIO_PIN4_MASK, + }, +}; + +static struct spear_modemux gpio0_pin4_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin4_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin4_pingroup = { + .name = "gpio0_pin4_grp", + .pins = gpio0_pin4_pins, + .npins = ARRAY_SIZE(gpio0_pin4_pins), + .modemuxs = gpio0_pin4_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux), +}; + +/* gpio0_pin5_pins */ +static const unsigned gpio0_pin5_pins[] = { 33 }; +static struct spear_muxreg gpio0_pin5_muxreg[] = { + { + .reg = -1, + .mask = PMX_GPIO_PIN5_MASK, + .val = PMX_GPIO_PIN5_MASK, + }, +}; + +static struct spear_modemux gpio0_pin5_modemux[] = { + { + .modes = ~0, + .muxregs = gpio0_pin5_muxreg, + .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg), + }, +}; + +struct spear_pingroup spear3xx_gpio0_pin5_pingroup = { + .name = "gpio0_pin5_grp", + .pins = gpio0_pin5_pins, + .npins = ARRAY_SIZE(gpio0_pin5_pins), + .modemuxs = gpio0_pin5_modemux, + .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux), +}; + +static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp", + "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp", +}; +struct spear_function spear3xx_gpio0_function = { + .name = "gpio0", + .groups = gpio0_grps, + .ngroups = ARRAY_SIZE(gpio0_grps), +}; + +/* uart0_ext_pins */ +static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 }; +static struct spear_muxreg uart0_ext_muxreg[] = { + { + .reg = -1, + .mask = PMX_UART0_MODEM_MASK, + .val = PMX_UART0_MODEM_MASK, + }, +}; + +static struct spear_modemux uart0_ext_modemux[] = { + { + .modes = ~0, + .muxregs = uart0_ext_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg), + }, +}; + +struct spear_pingroup spear3xx_uart0_ext_pingroup = { + .name = "uart0_ext_grp", + .pins = uart0_ext_pins, + .npins = ARRAY_SIZE(uart0_ext_pins), + .modemuxs = uart0_ext_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux), +}; + +static const char *const uart0_ext_grps[] = { "uart0_ext_grp" }; +struct spear_function spear3xx_uart0_ext_function = { + .name = "uart0_ext", + .groups = uart0_ext_grps, + .ngroups = ARRAY_SIZE(uart0_ext_grps), +}; + +/* uart0_pins */ +static const unsigned uart0_pins[] = { 2, 3 }; +static struct spear_muxreg uart0_muxreg[] = { + { + .reg = -1, + .mask = PMX_UART0_MASK, + .val = PMX_UART0_MASK, + }, +}; + +static struct spear_modemux uart0_modemux[] = { + { + .modes = ~0, + .muxregs = uart0_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_muxreg), + }, +}; + +struct spear_pingroup spear3xx_uart0_pingroup = { + .name = "uart0_grp", + .pins = uart0_pins, + .npins = ARRAY_SIZE(uart0_pins), + .modemuxs = uart0_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_modemux), +}; + +static const char *const uart0_grps[] = { "uart0_grp" }; +struct spear_function spear3xx_uart0_function = { + .name = "uart0", + .groups = uart0_grps, + .ngroups = ARRAY_SIZE(uart0_grps), +}; + +/* timer_0_1_pins */ +static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 }; +static struct spear_muxreg timer_0_1_muxreg[] = { + { + .reg = -1, + .mask = PMX_TIMER_0_1_MASK, + .val = PMX_TIMER_0_1_MASK, + }, +}; + +static struct spear_modemux timer_0_1_modemux[] = { + { + .modes = ~0, + .muxregs = timer_0_1_muxreg, + .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg), + }, +}; + +struct spear_pingroup spear3xx_timer_0_1_pingroup = { + .name = "timer_0_1_grp", + .pins = timer_0_1_pins, + .npins = ARRAY_SIZE(timer_0_1_pins), + .modemuxs = timer_0_1_modemux, + .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux), +}; + +static const char *const timer_0_1_grps[] = { "timer_0_1_grp" }; +struct spear_function spear3xx_timer_0_1_function = { + .name = "timer_0_1", + .groups = timer_0_1_grps, + .ngroups = ARRAY_SIZE(timer_0_1_grps), +}; + +/* timer_2_3_pins */ +static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 }; +static struct spear_muxreg timer_2_3_muxreg[] = { + { + .reg = -1, + .mask = PMX_TIMER_2_3_MASK, + .val = PMX_TIMER_2_3_MASK, + }, +}; + +static struct spear_modemux timer_2_3_modemux[] = { + { + .modes = ~0, + .muxregs = timer_2_3_muxreg, + .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg), + }, +}; + +struct spear_pingroup spear3xx_timer_2_3_pingroup = { + .name = "timer_2_3_grp", + .pins = timer_2_3_pins, + .npins = ARRAY_SIZE(timer_2_3_pins), + .modemuxs = timer_2_3_modemux, + .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux), +}; + +static const char *const timer_2_3_grps[] = { "timer_2_3_grp" }; +struct spear_function spear3xx_timer_2_3_function = { + .name = "timer_2_3", + .groups = timer_2_3_grps, + .ngroups = ARRAY_SIZE(timer_2_3_grps), +}; + +/* Define muxreg arrays */ +DEFINE_MUXREG(firda_pins, 0, PMX_FIRDA_MASK, 0); +DEFINE_MUXREG(i2c_pins, 0, PMX_I2C_MASK, 0); +DEFINE_MUXREG(ssp_cs_pins, 0, PMX_SSP_CS_MASK, 0); +DEFINE_MUXREG(ssp_pins, 0, PMX_SSP_MASK, 0); +DEFINE_MUXREG(mii_pins, 0, PMX_MII_MASK, 0); +DEFINE_MUXREG(gpio0_pin0_pins, 0, PMX_GPIO_PIN0_MASK, 0); +DEFINE_MUXREG(gpio0_pin1_pins, 0, PMX_GPIO_PIN1_MASK, 0); +DEFINE_MUXREG(gpio0_pin2_pins, 0, PMX_GPIO_PIN2_MASK, 0); +DEFINE_MUXREG(gpio0_pin3_pins, 0, PMX_GPIO_PIN3_MASK, 0); +DEFINE_MUXREG(gpio0_pin4_pins, 0, PMX_GPIO_PIN4_MASK, 0); +DEFINE_MUXREG(gpio0_pin5_pins, 0, PMX_GPIO_PIN5_MASK, 0); +DEFINE_MUXREG(uart0_ext_pins, 0, PMX_UART0_MODEM_MASK, 0); +DEFINE_MUXREG(uart0_pins, 0, PMX_UART0_MASK, 0); +DEFINE_MUXREG(timer_0_1_pins, 0, PMX_TIMER_0_1_MASK, 0); +DEFINE_MUXREG(timer_2_3_pins, 0, PMX_TIMER_2_3_MASK, 0); + +static struct spear_gpio_pingroup spear3xx_gpio_pingroup[] = { + GPIO_PINGROUP(firda_pins), + GPIO_PINGROUP(i2c_pins), + GPIO_PINGROUP(ssp_cs_pins), + GPIO_PINGROUP(ssp_pins), + GPIO_PINGROUP(mii_pins), + GPIO_PINGROUP(gpio0_pin0_pins), + GPIO_PINGROUP(gpio0_pin1_pins), + GPIO_PINGROUP(gpio0_pin2_pins), + GPIO_PINGROUP(gpio0_pin3_pins), + GPIO_PINGROUP(gpio0_pin4_pins), + GPIO_PINGROUP(gpio0_pin5_pins), + GPIO_PINGROUP(uart0_ext_pins), + GPIO_PINGROUP(uart0_pins), + GPIO_PINGROUP(timer_0_1_pins), + GPIO_PINGROUP(timer_2_3_pins), +}; + +struct spear_pinctrl_machdata spear3xx_machdata = { + .pins = spear3xx_pins, + .npins = ARRAY_SIZE(spear3xx_pins), + .gpio_pingroups = spear3xx_gpio_pingroup, + .ngpio_pingroups = ARRAY_SIZE(spear3xx_gpio_pingroup), +}; diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h new file mode 100644 index 000000000..ce19dcf8f --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h @@ -0,0 +1,93 @@ +/* + * Header file for the ST Microelectronics SPEAr3xx pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <vireshk@kernel.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PINMUX_SPEAR3XX_H__ +#define __PINMUX_SPEAR3XX_H__ + +#include "pinctrl-spear.h" + +/* pad mux declarations */ +#define PMX_PWM_MASK (1 << 16) +#define PMX_FIRDA_MASK (1 << 14) +#define PMX_I2C_MASK (1 << 13) +#define PMX_SSP_CS_MASK (1 << 12) +#define PMX_SSP_MASK (1 << 11) +#define PMX_MII_MASK (1 << 10) +#define PMX_GPIO_PIN0_MASK (1 << 9) +#define PMX_GPIO_PIN1_MASK (1 << 8) +#define PMX_GPIO_PIN2_MASK (1 << 7) +#define PMX_GPIO_PIN3_MASK (1 << 6) +#define PMX_GPIO_PIN4_MASK (1 << 5) +#define PMX_GPIO_PIN5_MASK (1 << 4) +#define PMX_UART0_MODEM_MASK (1 << 3) +#define PMX_UART0_MASK (1 << 2) +#define PMX_TIMER_2_3_MASK (1 << 1) +#define PMX_TIMER_0_1_MASK (1 << 0) + +extern struct spear_pingroup spear3xx_firda_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup; +extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup; +extern struct spear_pingroup spear3xx_i2c_pingroup; +extern struct spear_pingroup spear3xx_mii_pingroup; +extern struct spear_pingroup spear3xx_ssp_cs_pingroup; +extern struct spear_pingroup spear3xx_ssp_pingroup; +extern struct spear_pingroup spear3xx_timer_0_1_pingroup; +extern struct spear_pingroup spear3xx_timer_2_3_pingroup; +extern struct spear_pingroup spear3xx_uart0_ext_pingroup; +extern struct spear_pingroup spear3xx_uart0_pingroup; + +#define SPEAR3XX_COMMON_PINGROUPS \ + &spear3xx_firda_pingroup, \ + &spear3xx_gpio0_pin0_pingroup, \ + &spear3xx_gpio0_pin1_pingroup, \ + &spear3xx_gpio0_pin2_pingroup, \ + &spear3xx_gpio0_pin3_pingroup, \ + &spear3xx_gpio0_pin4_pingroup, \ + &spear3xx_gpio0_pin5_pingroup, \ + &spear3xx_i2c_pingroup, \ + &spear3xx_mii_pingroup, \ + &spear3xx_ssp_cs_pingroup, \ + &spear3xx_ssp_pingroup, \ + &spear3xx_timer_0_1_pingroup, \ + &spear3xx_timer_2_3_pingroup, \ + &spear3xx_uart0_ext_pingroup, \ + &spear3xx_uart0_pingroup + +extern struct spear_function spear3xx_firda_function; +extern struct spear_function spear3xx_gpio0_function; +extern struct spear_function spear3xx_i2c_function; +extern struct spear_function spear3xx_mii_function; +extern struct spear_function spear3xx_ssp_cs_function; +extern struct spear_function spear3xx_ssp_function; +extern struct spear_function spear3xx_timer_0_1_function; +extern struct spear_function spear3xx_timer_2_3_function; +extern struct spear_function spear3xx_uart0_ext_function; +extern struct spear_function spear3xx_uart0_function; + +#define SPEAR3XX_COMMON_FUNCTIONS \ + &spear3xx_firda_function, \ + &spear3xx_gpio0_function, \ + &spear3xx_i2c_function, \ + &spear3xx_mii_function, \ + &spear3xx_ssp_cs_function, \ + &spear3xx_ssp_function, \ + &spear3xx_timer_0_1_function, \ + &spear3xx_timer_2_3_function, \ + &spear3xx_uart0_ext_function, \ + &spear3xx_uart0_function + +extern struct spear_pinctrl_machdata spear3xx_machdata; + +#endif /* __PINMUX_SPEAR3XX_H__ */ |