From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- .../bindings/iio/resolver/adi,ad2s90.yaml | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/resolver/adi,ad2s90.yaml (limited to 'Documentation/devicetree/bindings/iio/resolver') diff --git a/Documentation/devicetree/bindings/iio/resolver/adi,ad2s90.yaml b/Documentation/devicetree/bindings/iio/resolver/adi,ad2s90.yaml new file mode 100644 index 000000000..81e4bdfc1 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/resolver/adi,ad2s90.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD2S90 Resolver-to-Digital Converter + +maintainers: + - Matheus Tavares + +description: | + Datasheet: https://www.analog.com/en/products/ad2s90.html + +properties: + compatible: + const: adi,ad2s90 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 830000 + description: | + Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns + delay is expected between the application of a logic LO to CS and the + application of SCLK, as also specified. And since the delay is not + implemented in the spi code, to satisfy it, SCLK's period should be at + most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives + roughly 830000Hz. + + spi-cpol: true + + spi-cpha: true + +additionalProperties: false + +required: + - compatible + - reg + +dependencies: + spi-cpol: [ spi-cpha ] + spi-cpha: [ spi-cpol ] + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + resolver@0 { + compatible = "adi,ad2s90"; + reg = <0>; + spi-max-frequency = <830000>; + spi-cpol; + spi-cpha; + }; + }; +... -- cgit v1.2.3