From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- .../bindings/media/marvell,mmp2-ccic.yaml | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml (limited to 'Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml') diff --git a/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml b/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml new file mode 100644 index 000000000..b39b84c5f --- /dev/null +++ b/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019,2020 Lubomir Rintel +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP2 camera host interface bindings + +maintainers: + - Lubomir Rintel + +properties: + $nodename: + pattern: '^camera@[a-f0-9]+$' + + compatible: + const: marvell,mmp2-ccic + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + hsync-active: true + vsync-active: true + pclk-sample: true + bus-type: true + + clocks: + minItems: 1 + items: + - description: AXI bus interface clock + - description: Peripheral clock + - description: Parallel video bus interface clock + + clock-names: + const: axi + + '#clock-cells': + const: 0 + + clock-output-names: + const: mclk + +required: + - compatible + - reg + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include + #include + + camera@d420a000 { + compatible = "marvell,mmp2-ccic"; + reg = <0xd420a000 0x800>; + interrupts = <42>; + clocks = <&soc_clocks MMP2_CLK_CCIC0>; + clock-names = "axi"; + #clock-cells = <0>; + clock-output-names = "mclk"; + power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>; + + port { + camera0_0: endpoint { + remote-endpoint = <&ov7670_0>; + bus-type = <5>; /* Parallel */ + hsync-active = <1>; /* Active high */ + vsync-active = <1>; /* Active high */ + pclk-sample = <0>; /* Falling */ + }; + }; + }; + +... -- cgit v1.2.3