From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- .../devicetree/bindings/phy/calxeda-combophy.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/calxeda-combophy.yaml (limited to 'Documentation/devicetree/bindings/phy/calxeda-combophy.yaml') diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml new file mode 100644 index 000000000..41ee16e21 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank Combination PHYs binding for SATA + +description: | + The Calxeda Combination PHYs connect the SoC to the internal fabric + and to SATA connectors. The PHYs support multiple protocols (SATA, + SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC + controller). + Programming the PHYs is typically handled by those device drivers, + not by a dedicated PHY driver. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-combophy + + '#phy-cells': + const: 1 + + reg: + maxItems: 1 + + phydev: + description: device ID for programming the ComboPHY. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 31 + +required: + - compatible + - reg + - phydev + - '#phy-cells' + +additionalProperties: false + +examples: + - | + combophy5: combo-phy@fff5d000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff5d000 0x1000>; + phydev = <31>; + }; -- cgit v1.2.3