From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- .../devicetree/bindings/watchdog/arm,sp805.yaml | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/arm,sp805.yaml (limited to 'Documentation/devicetree/bindings/watchdog/arm,sp805.yaml') diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml b/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml new file mode 100644 index 000000000..a69cac8ec --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/arm,sp805.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM AMBA Primecell SP805 Watchdog + +maintainers: + - Viresh Kumar + +description: |+ + The Arm SP805 IP implements a watchdog device, which triggers an interrupt + after a configurable time period. If that interrupt has not been serviced + when the next interrupt would be triggered, the reset signal is asserted. + +allOf: + - $ref: /schemas/watchdog/watchdog.yaml# + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + const: arm,sp805 + required: + - compatible + +properties: + compatible: + items: + - const: arm,sp805 + - const: arm,primecell + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + clocks: + description: | + Clocks driving the watchdog timer hardware. The first clock is used + for the actual watchdog counter. The second clock drives the register + interface. + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: wdog_clk + - const: apb_pclk + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + watchdog@66090000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x66090000 0x1000>; + interrupts = ; + clocks = <&wdt_clk>, <&apb_pclk>; + clock-names = "wdog_clk", "apb_pclk"; + }; -- cgit v1.2.3