From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- arch/mips/alchemy/common/setup.c | 107 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 arch/mips/alchemy/common/setup.c (limited to 'arch/mips/alchemy/common/setup.c') diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c new file mode 100644 index 000000000..2388d6878 --- /dev/null +++ b/arch/mips/alchemy/common/setup.c @@ -0,0 +1,107 @@ +/* + * Copyright 2000, 2007-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. +#include +#include +#include /* for dma_default_coherent */ + +#include + +#include + +extern void __init board_setup(void); +extern void __init alchemy_set_lpj(void); + +static bool alchemy_dma_coherent(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + return false; + case ALCHEMY_CPU_AU1200: + /* Au1200 AB USB does not support coherent memory */ + if ((read_c0_prid() & PRID_REV_MASK) == 0) + return false; + return true; + default: + return true; + } +} + +void __init plat_mem_setup(void) +{ + alchemy_set_lpj(); + + if (au1xxx_cpu_needs_config_od()) + /* Various early Au1xx0 errata corrected by this */ + set_c0_config(1 << 19); /* Set Config[OD] */ + else + /* Clear to obtain best system bus performance */ + clear_c0_config(1 << 19); /* Clear Config[OD] */ + + dma_default_coherent = alchemy_dma_coherent(); + + board_setup(); /* board specific setup */ + + /* IO/MEM resources. */ + set_io_port_base(0); + ioport_resource.start = IOPORT_RESOURCE_START; + ioport_resource.end = IOPORT_RESOURCE_END; + iomem_resource.start = IOMEM_RESOURCE_START; + iomem_resource.end = IOMEM_RESOURCE_END; +} + +#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR +/* This routine should be valid for all Au1x based boards */ +phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) +{ + unsigned long start = ALCHEMY_PCI_MEMWIN_START; + unsigned long end = ALCHEMY_PCI_MEMWIN_END; + + /* Don't fixup 36-bit addresses */ + if ((phys_addr >> 32) != 0) + return phys_addr; + + /* Check for PCI memory window */ + if (phys_addr >= start && (phys_addr + size - 1) <= end) + return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr); + + /* default nop */ + return phys_addr; +} + +int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr, + unsigned long pfn, unsigned long size, pgprot_t prot) +{ + phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); + + return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot); +} +EXPORT_SYMBOL(io_remap_pfn_range); +#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */ -- cgit v1.2.3