From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- arch/sh/kernel/cpu/sh2/clock-sh7619.c | 74 +++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 arch/sh/kernel/cpu/sh2/clock-sh7619.c (limited to 'arch/sh/kernel/cpu/sh2/clock-sh7619.c') diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c new file mode 100644 index 000000000..d66d194c7 --- /dev/null +++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * arch/sh/kernel/cpu/sh2/clock-sh7619.c + * + * SH7619 support for the clock framework + * + * Copyright (C) 2006 Yoshinori Sato + * + * Based on clock-sh4.c + * Copyright (C) 2005 Paul Mundt + */ +#include +#include +#include +#include +#include +#include + +static const int pll1rate[] = {1,2}; +static const int pfc_divisors[] = {1,2,0,4}; +static unsigned int pll2_mult; + +static void master_clk_init(struct clk *clk) +{ + clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; +} + +static struct sh_clk_ops sh7619_master_clk_ops = { + .init = master_clk_init, +}; + +static unsigned long module_clk_recalc(struct clk *clk) +{ + int idx = (__raw_readw(FREQCR) & 0x0007); + return clk->parent->rate / pfc_divisors[idx]; +} + +static struct sh_clk_ops sh7619_module_clk_ops = { + .recalc = module_clk_recalc, +}; + +static unsigned long bus_clk_recalc(struct clk *clk) +{ + return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; +} + +static struct sh_clk_ops sh7619_bus_clk_ops = { + .recalc = bus_clk_recalc, +}; + +static struct sh_clk_ops sh7619_cpu_clk_ops = { + .recalc = followparent_recalc, +}; + +static struct sh_clk_ops *sh7619_clk_ops[] = { + &sh7619_master_clk_ops, + &sh7619_module_clk_ops, + &sh7619_bus_clk_ops, + &sh7619_cpu_clk_ops, +}; + +void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) +{ + if (test_mode_pin(MODE_PIN2 | MODE_PIN0) || + test_mode_pin(MODE_PIN2 | MODE_PIN1)) + pll2_mult = 2; + else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1)) + pll2_mult = 4; + + BUG_ON(!pll2_mult); + + if (idx < ARRAY_SIZE(sh7619_clk_ops)) + *ops = sh7619_clk_ops[idx]; +} -- cgit v1.2.3