From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- drivers/gpu/drm/i915/selftests/igt_reset.c | 51 ++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 drivers/gpu/drm/i915/selftests/igt_reset.c (limited to 'drivers/gpu/drm/i915/selftests/igt_reset.c') diff --git a/drivers/gpu/drm/i915/selftests/igt_reset.c b/drivers/gpu/drm/i915/selftests/igt_reset.c new file mode 100644 index 000000000..a2838c65f --- /dev/null +++ b/drivers/gpu/drm/i915/selftests/igt_reset.c @@ -0,0 +1,51 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2018 Intel Corporation + */ + +#include "igt_reset.h" + +#include "gt/intel_engine.h" +#include "gt/intel_gt.h" + +#include "../i915_drv.h" + +void igt_global_reset_lock(struct intel_gt *gt) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + + pr_debug("%s: current gpu_error=%08lx\n", __func__, gt->reset.flags); + + while (test_and_set_bit(I915_RESET_BACKOFF, >->reset.flags)) + wait_event(gt->reset.queue, + !test_bit(I915_RESET_BACKOFF, >->reset.flags)); + + for_each_engine(engine, gt, id) { + while (test_and_set_bit(I915_RESET_ENGINE + id, + >->reset.flags)) + wait_on_bit(>->reset.flags, I915_RESET_ENGINE + id, + TASK_UNINTERRUPTIBLE); + } +} + +void igt_global_reset_unlock(struct intel_gt *gt) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + + for_each_engine(engine, gt, id) + clear_and_wake_up_bit(I915_RESET_ENGINE + id, >->reset.flags); + + clear_bit(I915_RESET_BACKOFF, >->reset.flags); + wake_up_all(>->reset.queue); +} + +bool igt_force_reset(struct intel_gt *gt) +{ + intel_gt_set_wedged(gt); + intel_gt_reset(gt, 0, NULL); + + return !intel_gt_is_wedged(gt); +} -- cgit v1.2.3