From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- .../gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h (limited to 'drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h') diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h new file mode 100644 index 000000000..2d4a22680 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_axuser_regs.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_AXUSER + * (Prototype: AXUSER) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_ASID 0x400BE00 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_MMU_BP 0x400BE04 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_STRONG_ORDER 0x400BE08 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_NO_SNOOP 0x400BE0C + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_REDUCTION 0x400BE10 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_ATOMIC 0x400BE14 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_QOS 0x400BE18 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RSVD 0x400BE1C + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_EMEM_CPAGE 0x400BE20 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_CORE 0x400BE24 + +#define mmDCORE0_TPC0_CFG_AXUSER_E2E_COORD 0x400BE28 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_OVRD_LO 0x400BE30 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_WR_OVRD_HI 0x400BE34 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_OVRD_LO 0x400BE38 + +#define mmDCORE0_TPC0_CFG_AXUSER_HB_RD_OVRD_HI 0x400BE3C + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_COORD 0x400BE40 + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_LOCK 0x400BE44 + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_RSVD 0x400BE48 + +#define mmDCORE0_TPC0_CFG_AXUSER_LB_OVRD 0x400BE4C + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_AXUSER_REGS_H_ */ -- cgit v1.2.3