From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- drivers/pinctrl/mediatek/pinctrl-mt6797.c | 77 +++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6797.c (limited to 'drivers/pinctrl/mediatek/pinctrl-mt6797.c') diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c new file mode 100644 index 000000000..53f240491 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on pinctrl-mt6765.c + * + * Copyright (C) 2018 MediaTek Inc. + * + * Author: ZH Chen + * + * Copyright (C) Manivannan Sadhasivam + * + */ + +#include "pinctrl-mtk-mt6797.h" +#include "pinctrl-paris.h" + +/* + * MT6797 have multiple bases to program pin configuration listed as the below: + * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400, + * iocfg[r]:0x10002800, iocfg[t]:0x10002C00. + * _i_base could be used to indicate what base the pin should be mapped into. + */ + +static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = { + PIN_FIELD(0, 261, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = { + PIN_FIELD(0, 261, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6797_pin_di_range[] = { + PIN_FIELD(0, 261, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6797_pin_do_range[] = { + PIN_FIELD(0, 261, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range), +}; + +static const char * const mt6797_pinctrl_register_base_names[] = { + "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt", +}; + +static const struct mtk_pin_soc mt6797_data = { + .reg_cal = mt6797_reg_cals, + .pins = mtk_pins_mt6797, + .npins = ARRAY_SIZE(mtk_pins_mt6797), + .ngrps = ARRAY_SIZE(mtk_pins_mt6797), + .gpio_m = 0, + .base_names = mt6797_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names), +}; + +static const struct of_device_id mt6797_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data }, + { } +}; + +static struct platform_driver mt6797_pinctrl_driver = { + .driver = { + .name = "mt6797-pinctrl", + .of_match_table = mt6797_pinctrl_of_match, + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt6797_pinctrl_init(void) +{ + return platform_driver_register(&mt6797_pinctrl_driver); +} +arch_initcall(mt6797_pinctrl_init); -- cgit v1.2.3