From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- drivers/rtc/rtc-au1xxx.c | 118 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 drivers/rtc/rtc-au1xxx.c (limited to 'drivers/rtc/rtc-au1xxx.c') diff --git a/drivers/rtc/rtc-au1xxx.c b/drivers/rtc/rtc-au1xxx.c new file mode 100644 index 000000000..630ea5de6 --- /dev/null +++ b/drivers/rtc/rtc-au1xxx.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver. + * + * Copyright (C) 2008 Manuel Lauss + */ + +/* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz + * crystal. Counter 0, which keeps counting during sleep/powerdown, is + * used to count seconds since the beginning of the unix epoch. + * + * The counters must be configured and enabled by bootloader/board code; + * no checks as to whether they really get a proper 32.768kHz clock are + * made as this would take far too long. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* 32kHz clock enabled and detected */ +#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) + +static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + unsigned long t; + + t = alchemy_rdsys(AU1000_SYS_TOYREAD); + + rtc_time64_to_tm(t, tm); + + return 0; +} + +static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + unsigned long t; + + t = rtc_tm_to_time64(tm); + + alchemy_wrsys(t, AU1000_SYS_TOYWRITE); + + /* wait for the pending register write to succeed. This can + * take up to 6 seconds... + */ + while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S) + msleep(1); + + return 0; +} + +static const struct rtc_class_ops au1xtoy_rtc_ops = { + .read_time = au1xtoy_rtc_read_time, + .set_time = au1xtoy_rtc_set_time, +}; + +static int au1xtoy_rtc_probe(struct platform_device *pdev) +{ + struct rtc_device *rtcdev; + unsigned long t; + + t = alchemy_rdsys(AU1000_SYS_CNTRCTRL); + if (!(t & CNTR_OK)) { + dev_err(&pdev->dev, "counters not working; aborting.\n"); + return -ENODEV; + } + + /* set counter0 tickrate to 1Hz if necessary */ + if (alchemy_rdsys(AU1000_SYS_TOYTRIM) != 32767) { + /* wait until hardware gives access to TRIM register */ + t = 0x00100000; + while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T0S) && --t) + msleep(1); + + if (!t) { + /* timed out waiting for register access; assume + * counters are unusable. + */ + dev_err(&pdev->dev, "timeout waiting for access\n"); + return -ETIMEDOUT; + } + + /* set 1Hz TOY tick rate */ + alchemy_wrsys(32767, AU1000_SYS_TOYTRIM); + } + + /* wait until the hardware allows writes to the counter reg */ + while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S) + msleep(1); + + rtcdev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtcdev)) + return PTR_ERR(rtcdev); + + rtcdev->ops = &au1xtoy_rtc_ops; + rtcdev->range_max = U32_MAX; + + platform_set_drvdata(pdev, rtcdev); + + return devm_rtc_register_device(rtcdev); +} + +static struct platform_driver au1xrtc_driver = { + .driver = { + .name = "rtc-au1xxx", + }, +}; + +module_platform_driver_probe(au1xrtc_driver, au1xtoy_rtc_probe); + +MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver"); +MODULE_AUTHOR("Manuel Lauss "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:rtc-au1xxx"); -- cgit v1.2.3