From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- drivers/staging/rtl8723bs/include/hal_com_phycfg.h | 108 +++++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 drivers/staging/rtl8723bs/include/hal_com_phycfg.h (limited to 'drivers/staging/rtl8723bs/include/hal_com_phycfg.h') diff --git a/drivers/staging/rtl8723bs/include/hal_com_phycfg.h b/drivers/staging/rtl8723bs/include/hal_com_phycfg.h new file mode 100644 index 000000000..cb7c7ed74 --- /dev/null +++ b/drivers/staging/rtl8723bs/include/hal_com_phycfg.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __HAL_COM_PHYCFG_H__ +#define __HAL_COM_PHYCFG_H__ + +#define PathA 0x0 /* Useless */ +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +enum rate_section { + CCK = 0, + OFDM, + HT_MCS0_MCS7, +}; + +#define MAX_POWER_INDEX 0x3F + +enum { + TXPWR_LMT_FCC = 0, + TXPWR_LMT_MKK, + TXPWR_LMT_ETSI, + TXPWR_LMT_WW, + TXPWR_LMT_MAX_REGULATION_NUM, +}; + +/*------------------------------Define structure----------------------------*/ +struct bb_register_def { + u32 rfintfs; /* set software control: */ + /* 0x870~0x877[8 bytes] */ + + u32 rfintfo; /* output data: */ + /* 0x860~0x86f [16 bytes] */ + + u32 rfintfe; /* output enable: */ + /* 0x860~0x86f [16 bytes] */ + + u32 rf3wireOffset; /* LSSI data: */ + /* 0x840~0x84f [16 bytes] */ + + u32 rfHSSIPara2; /* wire parameter control2 : */ + /* 0x824~0x827, 0x82c~0x82f, + * 0x834~0x837, 0x83c~0x83f + */ + u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ + /* 0x8a0~0x8af [16 bytes] */ + + u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode + * 0x8b8-8bc for Path A and B */ + +}; + +u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath, + enum rate_section RateSection); + +u8 PHY_GetRateSectionIndexOfTxPowerByRate(struct adapter *padapter, u32 RegAddr, + u32 BitMask); + +void PHY_GetRateValuesOfTxPowerByRate(struct adapter *padapter, u32 RegAddr, + u32 BitMask, u32 Value, u8 *RateIndex, + s8 *PwrByRateVal, u8 *RateNum); + +u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate); + +void PHY_SetTxPowerIndexByRateSection(struct adapter *padapter, u8 RFPath, u8 Channel, + u8 RateSection); + +s8 PHY_GetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 RateIndex); + +void PHY_SetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 Rate, + s8 Value); + +void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path); + +void PHY_SetTxPowerIndexByRateArray(struct adapter *padapter, u8 RFPath, + enum channel_width BandWidth, u8 Channel, + u8 *Rates, u8 RateArraySize); + +void PHY_InitTxPowerByRate(struct adapter *padapter); + +void PHY_StoreTxPowerByRate(struct adapter *padapter, u32 RfPath, + u32 RegAddr, u32 BitMask, u32 Data); + +void PHY_TxPowerByRateConfiguration(struct adapter *padapter); + +u8 PHY_GetTxPowerIndexBase(struct adapter *padapter, u8 RFPath, u8 Rate, + enum channel_width BandWidth, u8 Channel); + +s8 phy_get_tx_pwr_lmt(struct adapter *adapter, u32 RegPwrTblSel, + enum channel_width Bandwidth, u8 RfPath, u8 DataRate, + u8 Channel); + +void PHY_SetTxPowerLimit(struct adapter *Adapter, u8 *Regulation, u8 *Bandwidth, + u8 *RateSection, u8 *RfPath, u8 *Channel, u8 *PowerLimit); + +void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter); + +void PHY_InitTxPowerLimit(struct adapter *Adapter); + +s8 PHY_GetTxPowerTrackingOffset(struct adapter *padapter, u8 Rate, u8 RFPath); + +void Hal_ChannelPlanToRegulation(struct adapter *Adapter, u16 ChannelPlan); + +#endif /* __HAL_COMMON_H__ */ -- cgit v1.2.3