From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- include/video/atmel_lcdc.h | 189 ++++ include/video/aty128.h | 423 +++++++ include/video/broadsheetfb.h | 74 ++ include/video/cirrus.h | 122 ++ include/video/cvisionppc.h | 51 + include/video/da8xx-fb.h | 94 ++ include/video/display_timing.h | 105 ++ include/video/edid.h | 10 + include/video/gbe.h | 315 ++++++ include/video/hecubafb.h | 51 + include/video/ili9320.h | 198 ++++ include/video/imx-ipu-image-convert.h | 198 ++++ include/video/imx-ipu-v3.h | 503 +++++++++ include/video/kyro.h | 91 ++ include/video/mach64.h | 1374 +++++++++++++++++++++++ include/video/maxinefb.h | 38 + include/video/metronomefb.h | 57 + include/video/mipi_display.h | 150 +++ include/video/mmp_disp.h | 345 ++++++ include/video/neomagic.h | 189 ++++ include/video/newport.h | 584 ++++++++++ include/video/of_display_timing.h | 36 + include/video/of_videomode.h | 17 + include/video/omap-panel-data.h | 71 ++ include/video/omapfb_dss.h | 874 +++++++++++++++ include/video/omapvrfb.h | 56 + include/video/permedia2.h | 254 +++++ include/video/platform_lcd.h | 18 + include/video/pm3fb.h | 1061 ++++++++++++++++++ include/video/pmag-ba-fb.h | 27 + include/video/pmagb-b-fb.h | 58 + include/video/pxa168fb.h | 120 ++ include/video/radeon.h | 1994 +++++++++++++++++++++++++++++++++ include/video/s1d13xxxfb.h | 174 +++ include/video/sa1100fb.h | 63 ++ include/video/samsung_fimd.h | 488 ++++++++ include/video/sh_mobile_lcdc.h | 196 ++++ include/video/sisfb.h | 24 + include/video/sstfb.h | 356 ++++++ include/video/tdfx.h | 209 ++++ include/video/tgafb.h | 280 +++++ include/video/trident.h | 147 +++ include/video/udlfb.h | 103 ++ include/video/uvesafb.h | 141 +++ include/video/vga.h | 461 ++++++++ include/video/videomode.h | 57 + include/video/w100fb.h | 147 +++ 47 files changed, 12593 insertions(+) create mode 100644 include/video/atmel_lcdc.h create mode 100644 include/video/aty128.h create mode 100644 include/video/broadsheetfb.h create mode 100644 include/video/cirrus.h create mode 100644 include/video/cvisionppc.h create mode 100644 include/video/da8xx-fb.h create mode 100644 include/video/display_timing.h create mode 100644 include/video/edid.h create mode 100644 include/video/gbe.h create mode 100644 include/video/hecubafb.h create mode 100644 include/video/ili9320.h create mode 100644 include/video/imx-ipu-image-convert.h create mode 100644 include/video/imx-ipu-v3.h create mode 100644 include/video/kyro.h create mode 100644 include/video/mach64.h create mode 100644 include/video/maxinefb.h create mode 100644 include/video/metronomefb.h create mode 100644 include/video/mipi_display.h create mode 100644 include/video/mmp_disp.h create mode 100644 include/video/neomagic.h create mode 100644 include/video/newport.h create mode 100644 include/video/of_display_timing.h create mode 100644 include/video/of_videomode.h create mode 100644 include/video/omap-panel-data.h create mode 100644 include/video/omapfb_dss.h create mode 100644 include/video/omapvrfb.h create mode 100644 include/video/permedia2.h create mode 100644 include/video/platform_lcd.h create mode 100644 include/video/pm3fb.h create mode 100644 include/video/pmag-ba-fb.h create mode 100644 include/video/pmagb-b-fb.h create mode 100644 include/video/pxa168fb.h create mode 100644 include/video/radeon.h create mode 100644 include/video/s1d13xxxfb.h create mode 100644 include/video/sa1100fb.h create mode 100644 include/video/samsung_fimd.h create mode 100644 include/video/sh_mobile_lcdc.h create mode 100644 include/video/sisfb.h create mode 100644 include/video/sstfb.h create mode 100644 include/video/tdfx.h create mode 100644 include/video/tgafb.h create mode 100644 include/video/trident.h create mode 100644 include/video/udlfb.h create mode 100644 include/video/uvesafb.h create mode 100644 include/video/vga.h create mode 100644 include/video/videomode.h create mode 100644 include/video/w100fb.h (limited to 'include/video') diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h new file mode 100644 index 000000000..43e497cde --- /dev/null +++ b/include/video/atmel_lcdc.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Header file for AT91/AT32 LCD Controller + * + * Data structure and register user interface + * + * Copyright (C) 2007 Atmel Corporation + */ +#ifndef __ATMEL_LCDC_H__ +#define __ATMEL_LCDC_H__ + +#include + +/* Way LCD wires are connected to the chip: + * Some Atmel chips use BGR color mode (instead of standard RGB) + * A swapped wiring onboard can bring to RGB mode. + */ +#define ATMEL_LCDC_WIRING_BGR 0 +#define ATMEL_LCDC_WIRING_RGB 1 + + + /* LCD Controller info data structure, stored in device platform_data */ +struct atmel_lcdfb_pdata { + unsigned int guard_time; + bool lcdcon_is_backlight; + bool lcdcon_pol_negative; + u8 default_bpp; + u8 lcd_wiring_mode; + unsigned int default_lcdcon2; + unsigned int default_dmacon; + void (*atmel_lcdfb_power_control)(struct atmel_lcdfb_pdata *pdata, int on); + struct fb_monspecs *default_monspecs; + + struct list_head pwr_gpios; +}; + +#define ATMEL_LCDC_DMABADDR1 0x00 +#define ATMEL_LCDC_DMABADDR2 0x04 +#define ATMEL_LCDC_DMAFRMPT1 0x08 +#define ATMEL_LCDC_DMAFRMPT2 0x0c +#define ATMEL_LCDC_DMAFRMADD1 0x10 +#define ATMEL_LCDC_DMAFRMADD2 0x14 + +#define ATMEL_LCDC_DMAFRMCFG 0x18 +#define ATMEL_LCDC_FRSIZE (0x7fffff << 0) +#define ATMEL_LCDC_BLENGTH_OFFSET 24 +#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET) + +#define ATMEL_LCDC_DMACON 0x1c +#define ATMEL_LCDC_DMAEN (0x1 << 0) +#define ATMEL_LCDC_DMARST (0x1 << 1) +#define ATMEL_LCDC_DMABUSY (0x1 << 2) +#define ATMEL_LCDC_DMAUPDT (0x1 << 3) +#define ATMEL_LCDC_DMA2DEN (0x1 << 4) + +#define ATMEL_LCDC_DMA2DCFG 0x20 +#define ATMEL_LCDC_ADDRINC_OFFSET 0 +#define ATMEL_LCDC_ADDRINC (0xffff) +#define ATMEL_LCDC_PIXELOFF_OFFSET 24 +#define ATMEL_LCDC_PIXELOFF (0x1f << 24) + +#define ATMEL_LCDC_LCDCON1 0x0800 +#define ATMEL_LCDC_BYPASS (1 << 0) +#define ATMEL_LCDC_CLKVAL_OFFSET 12 +#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) +#define ATMEL_LCDC_LINCNT (0x7ff << 21) + +#define ATMEL_LCDC_LCDCON2 0x0804 +#define ATMEL_LCDC_DISTYPE (3 << 0) +#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) +#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) +#define ATMEL_LCDC_DISTYPE_TFT (2 << 0) +#define ATMEL_LCDC_SCANMOD (1 << 2) +#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) +#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) +#define ATMEL_LCDC_IFWIDTH (3 << 3) +#define ATMEL_LCDC_IFWIDTH_4 (0 << 3) +#define ATMEL_LCDC_IFWIDTH_8 (1 << 3) +#define ATMEL_LCDC_IFWIDTH_16 (2 << 3) +#define ATMEL_LCDC_PIXELSIZE (7 << 5) +#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) +#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) +#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) +#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) +#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) +#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) +#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) +#define ATMEL_LCDC_INVVD (1 << 8) +#define ATMEL_LCDC_INVVD_NORMAL (0 << 8) +#define ATMEL_LCDC_INVVD_INVERTED (1 << 8) +#define ATMEL_LCDC_INVFRAME (1 << 9 ) +#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) +#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) +#define ATMEL_LCDC_INVLINE (1 << 10) +#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) +#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) +#define ATMEL_LCDC_INVCLK (1 << 11) +#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) +#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) +#define ATMEL_LCDC_INVDVAL (1 << 12) +#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) +#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) +#define ATMEL_LCDC_CLKMOD (1 << 15) +#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) +#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) +#define ATMEL_LCDC_MEMOR (1 << 31) +#define ATMEL_LCDC_MEMOR_BIG (0 << 31) +#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) + +#define ATMEL_LCDC_TIM1 0x0808 +#define ATMEL_LCDC_VFP (0xffU << 0) +#define ATMEL_LCDC_VBP_OFFSET 8 +#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET) +#define ATMEL_LCDC_VPW_OFFSET 16 +#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET) +#define ATMEL_LCDC_VHDLY_OFFSET 24 +#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET) + +#define ATMEL_LCDC_TIM2 0x080c +#define ATMEL_LCDC_HBP (0xffU << 0) +#define ATMEL_LCDC_HPW_OFFSET 8 +#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET) +#define ATMEL_LCDC_HFP_OFFSET 21 +#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET) + +#define ATMEL_LCDC_LCDFRMCFG 0x0810 +#define ATMEL_LCDC_LINEVAL (0x7ff << 0) +#define ATMEL_LCDC_HOZVAL_OFFSET 21 +#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) + +#define ATMEL_LCDC_FIFO 0x0814 +#define ATMEL_LCDC_FIFOTH (0xffff) + +#define ATMEL_LCDC_MVAL 0x0818 + +#define ATMEL_LCDC_DP1_2 0x081c +#define ATMEL_LCDC_DP4_7 0x0820 +#define ATMEL_LCDC_DP3_5 0x0824 +#define ATMEL_LCDC_DP2_3 0x0828 +#define ATMEL_LCDC_DP5_7 0x082c +#define ATMEL_LCDC_DP3_4 0x0830 +#define ATMEL_LCDC_DP4_5 0x0834 +#define ATMEL_LCDC_DP6_7 0x0838 +#define ATMEL_LCDC_DP1_2_VAL (0xff) +#define ATMEL_LCDC_DP4_7_VAL (0xfffffff) +#define ATMEL_LCDC_DP3_5_VAL (0xfffff) +#define ATMEL_LCDC_DP2_3_VAL (0xfff) +#define ATMEL_LCDC_DP5_7_VAL (0xfffffff) +#define ATMEL_LCDC_DP3_4_VAL (0xffff) +#define ATMEL_LCDC_DP4_5_VAL (0xfffff) +#define ATMEL_LCDC_DP6_7_VAL (0xfffffff) + +#define ATMEL_LCDC_PWRCON 0x083c +#define ATMEL_LCDC_PWR (1 << 0) +#define ATMEL_LCDC_GUARDT_OFFSET 1 +#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET) +#define ATMEL_LCDC_BUSY (1 << 31) + +#define ATMEL_LCDC_CONTRAST_CTR 0x0840 +#define ATMEL_LCDC_PS (3 << 0) +#define ATMEL_LCDC_PS_DIV1 (0 << 0) +#define ATMEL_LCDC_PS_DIV2 (1 << 0) +#define ATMEL_LCDC_PS_DIV4 (2 << 0) +#define ATMEL_LCDC_PS_DIV8 (3 << 0) +#define ATMEL_LCDC_POL (1 << 2) +#define ATMEL_LCDC_POL_NEGATIVE (0 << 2) +#define ATMEL_LCDC_POL_POSITIVE (1 << 2) +#define ATMEL_LCDC_ENA (1 << 3) +#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) +#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) + +#define ATMEL_LCDC_CONTRAST_VAL 0x0844 +#define ATMEL_LCDC_CVAL (0xff) + +#define ATMEL_LCDC_IER 0x0848 +#define ATMEL_LCDC_IDR 0x084c +#define ATMEL_LCDC_IMR 0x0850 +#define ATMEL_LCDC_ISR 0x0854 +#define ATMEL_LCDC_ICR 0x0858 +#define ATMEL_LCDC_LNI (1 << 0) +#define ATMEL_LCDC_LSTLNI (1 << 1) +#define ATMEL_LCDC_EOFI (1 << 2) +#define ATMEL_LCDC_UFLWI (1 << 4) +#define ATMEL_LCDC_OWRI (1 << 5) +#define ATMEL_LCDC_MERI (1 << 6) + +#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) + +#endif /* __ATMEL_LCDC_H__ */ diff --git a/include/video/aty128.h b/include/video/aty128.h new file mode 100644 index 000000000..cb6721ebf --- /dev/null +++ b/include/video/aty128.h @@ -0,0 +1,423 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $ + * linux/drivers/video/aty128.h + * Register definitions for ATI Rage128 boards + * + * Anthony Tong , 1999 + * Brad Douglas , 2000 + */ + +#ifndef REG_RAGE128_H +#define REG_RAGE128_H + +#define CLOCK_CNTL_INDEX 0x0008 +#define CLOCK_CNTL_DATA 0x000c +#define BIOS_0_SCRATCH 0x0010 +#define BUS_CNTL 0x0030 +#define BUS_CNTL1 0x0034 +#define GEN_INT_CNTL 0x0040 +#define CRTC_GEN_CNTL 0x0050 +#define CRTC_EXT_CNTL 0x0054 +#define DAC_CNTL 0x0058 +#define I2C_CNTL_1 0x0094 +#define PALETTE_INDEX 0x00b0 +#define PALETTE_DATA 0x00b4 +#define CNFG_CNTL 0x00e0 +#define GEN_RESET_CNTL 0x00f0 +#define CNFG_MEMSIZE 0x00f8 +#define MEM_CNTL 0x0140 +#define MEM_POWER_MISC 0x015c +#define AGP_BASE 0x0170 +#define AGP_CNTL 0x0174 +#define AGP_APER_OFFSET 0x0178 +#define PCI_GART_PAGE 0x017c +#define PC_NGUI_MODE 0x0180 +#define PC_NGUI_CTLSTAT 0x0184 +#define MPP_TB_CONFIG 0x01C0 +#define MPP_GP_CONFIG 0x01C8 +#define VIPH_CONTROL 0x01D0 +#define CRTC_H_TOTAL_DISP 0x0200 +#define CRTC_H_SYNC_STRT_WID 0x0204 +#define CRTC_V_TOTAL_DISP 0x0208 +#define CRTC_V_SYNC_STRT_WID 0x020c +#define CRTC_VLINE_CRNT_VLINE 0x0210 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC_OFFSET 0x0224 +#define CRTC_OFFSET_CNTL 0x0228 +#define CRTC_PITCH 0x022c +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define LVDS_GEN_CNTL 0x02d0 +#define DDA_CONFIG 0x02e0 +#define DDA_ON_OFF 0x02e4 +#define VGA_DDA_CONFIG 0x02e8 +#define VGA_DDA_ON_OFF 0x02ec +#define CRTC2_H_TOTAL_DISP 0x0300 +#define CRTC2_H_SYNC_STRT_WID 0x0304 +#define CRTC2_V_TOTAL_DISP 0x0308 +#define CRTC2_V_SYNC_STRT_WID 0x030c +#define CRTC2_VLINE_CRNT_VLINE 0x0310 +#define CRTC2_CRNT_FRAME 0x0314 +#define CRTC2_GUI_TRIG_VLINE 0x0318 +#define CRTC2_OFFSET 0x0324 +#define CRTC2_OFFSET_CNTL 0x0328 +#define CRTC2_PITCH 0x032c +#define DDA2_CONFIG 0x03e0 +#define DDA2_ON_OFF 0x03e4 +#define CRTC2_GEN_CNTL 0x03f8 +#define CRTC2_STATUS 0x03fc +#define OV0_SCALE_CNTL 0x0420 +#define SUBPIC_CNTL 0x0540 +#define PM4_BUFFER_OFFSET 0x0700 +#define PM4_BUFFER_CNTL 0x0704 +#define PM4_BUFFER_WM_CNTL 0x0708 +#define PM4_BUFFER_DL_RPTR_ADDR 0x070c +#define PM4_BUFFER_DL_RPTR 0x0710 +#define PM4_BUFFER_DL_WPTR 0x0714 +#define PM4_VC_FPU_SETUP 0x071c +#define PM4_FPU_CNTL 0x0720 +#define PM4_VC_FORMAT 0x0724 +#define PM4_VC_CNTL 0x0728 +#define PM4_VC_I01 0x072c +#define PM4_VC_VLOFF 0x0730 +#define PM4_VC_VLSIZE 0x0734 +#define PM4_IW_INDOFF 0x0738 +#define PM4_IW_INDSIZE 0x073c +#define PM4_FPU_FPX0 0x0740 +#define PM4_FPU_FPY0 0x0744 +#define PM4_FPU_FPX1 0x0748 +#define PM4_FPU_FPY1 0x074c +#define PM4_FPU_FPX2 0x0750 +#define PM4_FPU_FPY2 0x0754 +#define PM4_FPU_FPY3 0x0758 +#define PM4_FPU_FPY4 0x075c +#define PM4_FPU_FPY5 0x0760 +#define PM4_FPU_FPY6 0x0764 +#define PM4_FPU_FPR 0x0768 +#define PM4_FPU_FPG 0x076c +#define PM4_FPU_FPB 0x0770 +#define PM4_FPU_FPA 0x0774 +#define PM4_FPU_INTXY0 0x0780 +#define PM4_FPU_INTXY1 0x0784 +#define PM4_FPU_INTXY2 0x0788 +#define PM4_FPU_INTARGB 0x078c +#define PM4_FPU_FPTWICEAREA 0x0790 +#define PM4_FPU_DMAJOR01 0x0794 +#define PM4_FPU_DMAJOR12 0x0798 +#define PM4_FPU_DMAJOR02 0x079c +#define PM4_FPU_STAT 0x07a0 +#define PM4_STAT 0x07b8 +#define PM4_TEST_CNTL 0x07d0 +#define PM4_MICROCODE_ADDR 0x07d4 +#define PM4_MICROCODE_RADDR 0x07d8 +#define PM4_MICROCODE_DATAH 0x07dc +#define PM4_MICROCODE_DATAL 0x07e0 +#define PM4_CMDFIFO_ADDR 0x07e4 +#define PM4_CMDFIFO_DATAH 0x07e8 +#define PM4_CMDFIFO_DATAL 0x07ec +#define PM4_BUFFER_ADDR 0x07f0 +#define PM4_BUFFER_DATAH 0x07f4 +#define PM4_BUFFER_DATAL 0x07f8 +#define PM4_MICRO_CNTL 0x07fc +#define CAP0_TRIG_CNTL 0x0950 +#define CAP1_TRIG_CNTL 0x09c0 + +/****************************************************************************** + * GUI Block Memory Mapped Registers * + * These registers are FIFOed. * + *****************************************************************************/ +#define PM4_FIFO_DATA_EVEN 0x1000 +#define PM4_FIFO_DATA_ODD 0x1004 + +#define DST_OFFSET 0x1404 +#define DST_PITCH 0x1408 +#define DST_WIDTH 0x140c +#define DST_HEIGHT 0x1410 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define DST_X 0x141c +#define DST_Y 0x1420 +#define SRC_PITCH_OFFSET 0x1428 +#define DST_PITCH_OFFSET 0x142c +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_HEIGHT_WIDTH 0x143c +#define DP_GUI_MASTER_CNTL 0x146c +#define BRUSH_SCALE 0x1470 +#define BRUSH_Y_X 0x1474 +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DP_BRUSH_FRGD_CLR 0x147c +#define DST_WIDTH_X 0x1588 +#define DST_HEIGHT_WIDTH_8 0x158c +#define SRC_X_Y 0x1590 +#define DST_X_Y 0x1594 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_WIDTH_X_INCY 0x159c +#define DST_HEIGHT_Y 0x15a0 +#define DST_X_SUB 0x15a4 +#define DST_Y_SUB 0x15a8 +#define SRC_OFFSET 0x15ac +#define SRC_PITCH 0x15b0 +#define DST_HEIGHT_WIDTH_BW 0x15b4 +#define CLR_CMP_CNTL 0x15c0 +#define CLR_CMP_CLR_SRC 0x15c4 +#define CLR_CMP_CLR_DST 0x15c8 +#define CLR_CMP_MASK 0x15cc +#define DP_SRC_FRGD_CLR 0x15d8 +#define DP_SRC_BKGD_CLR 0x15dc +#define DST_BRES_ERR 0x1628 +#define DST_BRES_INC 0x162c +#define DST_BRES_DEC 0x1630 +#define DST_BRES_LNTH 0x1634 +#define DST_BRES_LNTH_SUB 0x1638 +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164c +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165c +#define GUI_DEBUG0 0x16a0 +#define GUI_DEBUG1 0x16a4 +#define GUI_TIMEOUT 0x16b0 +#define GUI_TIMEOUT0 0x16b4 +#define GUI_TIMEOUT1 0x16b8 +#define GUI_PROBE 0x16bc +#define DP_CNTL 0x16c0 +#define DP_DATATYPE 0x16c4 +#define DP_MIX 0x16c8 +#define DP_WRITE_MASK 0x16cc +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 +#define DEFAULT_OFFSET 0x16e0 +#define DEFAULT_PITCH 0x16e4 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +#define SC_TOP_LEFT 0x16ec +#define SC_BOTTOM_RIGHT 0x16f0 +#define SRC_SC_BOTTOM_RIGHT 0x16f4 +#define WAIT_UNTIL 0x1720 +#define CACHE_CNTL 0x1724 +#define GUI_STAT 0x1740 +#define PC_GUI_MODE 0x1744 +#define PC_GUI_CTLSTAT 0x1748 +#define PC_DEBUG_MODE 0x1760 +#define BRES_DST_ERR_DEC 0x1780 +#define TRAIL_BRES_T12_ERR_DEC 0x1784 +#define TRAIL_BRES_T12_INC 0x1788 +#define DP_T12_CNTL 0x178c +#define DST_BRES_T1_LNTH 0x1790 +#define DST_BRES_T2_LNTH 0x1794 +#define SCALE_SRC_HEIGHT_WIDTH 0x1994 +#define SCALE_OFFSET_0 0x1998 +#define SCALE_PITCH 0x199c +#define SCALE_X_INC 0x19a0 +#define SCALE_Y_INC 0x19a4 +#define SCALE_HACC 0x19a8 +#define SCALE_VACC 0x19ac +#define SCALE_DST_X_Y 0x19b0 +#define SCALE_DST_HEIGHT_WIDTH 0x19b4 +#define SCALE_3D_CNTL 0x1a00 +#define SCALE_3D_DATATYPE 0x1a20 +#define SETUP_CNTL 0x1bc4 +#define SOLID_COLOR 0x1bc8 +#define WINDOW_XY_OFFSET 0x1bcc +#define DRAW_LINE_POINT 0x1bd0 +#define SETUP_CNTL_PM4 0x1bd4 +#define DST_PITCH_OFFSET_C 0x1c80 +#define DP_GUI_MASTER_CNTL_C 0x1c84 +#define SC_TOP_LEFT_C 0x1c88 +#define SC_BOTTOM_RIGHT_C 0x1c8c + +#define CLR_CMP_MASK_3D 0x1A28 +#define MISC_3D_STATE_CNTL_REG 0x1CA0 +#define MC_SRC1_CNTL 0x19D8 +#define TEX_CNTL 0x1800 + +/* CONSTANTS */ +#define GUI_ACTIVE 0x80000000 +#define ENGINE_IDLE 0x0 + +#define PLL_WR_EN 0x00000080 + +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +#define PPLL_REF_DIV 0x0003 +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +#define HTOTAL_CNTL 0x0009 +#define X_MPLL_REF_FB_DIV 0x000a +#define XPLL_CNTL 0x000b +#define XDLL_CNTL 0x000c +#define XCLK_CNTL 0x000d +#define MPLL_CNTL 0x000e +#define MCLK_CNTL 0x000f +#define AGP_PLL_CNTL 0x0010 +#define FCP_CNTL 0x0012 +#define PLL_TEST_CNTL 0x0013 +#define P2PLL_CNTL 0x002a +#define P2PLL_REF_DIV 0x002b +#define P2PLL_DIV_0 0x002b +#define POWER_MANAGEMENT 0x002f + +#define PPLL_RESET 0x01 +#define PPLL_ATOMIC_UPDATE_EN 0x10000 +#define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000 +#define PPLL_REF_DIV_MASK 0x3FF +#define PPLL_FB3_DIV_MASK 0x7FF +#define PPLL_POST3_DIV_MASK 0x70000 +#define PPLL_ATOMIC_UPDATE_R 0x8000 +#define PPLL_ATOMIC_UPDATE_W 0x8000 +#define MEM_CFG_TYPE_MASK 0x3 +#define XCLK_SRC_SEL_MASK 0x7 +#define XPLL_FB_DIV_MASK 0xFF00 +#define X_MPLL_REF_DIV_MASK 0xFF + +/* CRTC control values (CRTC_GEN_CNTL) */ +#define CRTC_CSYNC_EN 0x00000010 + +#define CRTC2_DBL_SCAN_EN 0x00000001 +#define CRTC2_DISPLAY_DIS 0x00800000 +#define CRTC2_FIFO_EXTSENSE 0x00200000 +#define CRTC2_ICON_EN 0x00100000 +#define CRTC2_CUR_EN 0x00010000 +#define CRTC2_EN 0x02000000 +#define CRTC2_DISP_REQ_EN_B 0x04000000 + +#define CRTC_PIX_WIDTH_MASK 0x00000700 +#define CRTC_PIX_WIDTH_4BPP 0x00000100 +#define CRTC_PIX_WIDTH_8BPP 0x00000200 +#define CRTC_PIX_WIDTH_15BPP 0x00000300 +#define CRTC_PIX_WIDTH_16BPP 0x00000400 +#define CRTC_PIX_WIDTH_24BPP 0x00000500 +#define CRTC_PIX_WIDTH_32BPP 0x00000600 + +/* DAC_CNTL bit constants */ +#define DAC_8BIT_EN 0x00000100 +#define DAC_MASK 0xFF000000 +#define DAC_BLANKING 0x00000004 +#define DAC_RANGE_CNTL 0x00000003 +#define DAC_CLK_SEL 0x00000010 +#define DAC_PALETTE_ACCESS_CNTL 0x00000020 +#define DAC_PALETTE2_SNOOP_EN 0x00000040 +#define DAC_PDWN 0x00008000 + +/* CRTC_EXT_CNTL */ +#define CRT_CRTC_ON 0x00008000 + +/* GEN_RESET_CNTL bit constants */ +#define SOFT_RESET_GUI 0x00000001 +#define SOFT_RESET_VCLK 0x00000100 +#define SOFT_RESET_PCLK 0x00000200 +#define SOFT_RESET_ECP 0x00000400 +#define SOFT_RESET_DISPENG_XCLK 0x00000800 + +/* PC_GUI_CTLSTAT bit constants */ +#define PC_BUSY_INIT 0x10000000 +#define PC_BUSY_GUI 0x20000000 +#define PC_BUSY_NGUI 0x40000000 +#define PC_BUSY 0x80000000 + +#define BUS_MASTER_DIS 0x00000040 +#define PM4_BUFFER_CNTL_NONPM4 0x00000000 + +/* DP_DATATYPE bit constants */ +#define DST_8BPP 0x00000002 +#define DST_15BPP 0x00000003 +#define DST_16BPP 0x00000004 +#define DST_24BPP 0x00000005 +#define DST_32BPP 0x00000006 + +#define BRUSH_SOLIDCOLOR 0x00000d00 + +/* DP_GUI_MASTER_CNTL bit constants */ +#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_CLIP_DEFAULT 0x00000000 +#define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define GMC_SRC_DSTCOLOR 0x00003000 +#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define GMC_DP_SRC_RECT 0x02000000 +#define GMC_3D_FCN_EN_CLR 0x00000000 +#define GMC_AUX_CLIP_CLEAR 0x20000000 +#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +#define GMC_WRITE_MASK_SET 0x40000000 +#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 + +/* DP_GUI_MASTER_CNTL ROP3 named constants */ +#define ROP3_PATCOPY 0x00f00000 +#define ROP3_SRCCOPY 0x00cc0000 + +#define SRC_DSTCOLOR 0x00030000 + +/* DP_CNTL bit constants */ +#define DST_X_RIGHT_TO_LEFT 0x00000000 +#define DST_X_LEFT_TO_RIGHT 0x00000001 +#define DST_Y_BOTTOM_TO_TOP 0x00000000 +#define DST_Y_TOP_TO_BOTTOM 0x00000002 +#define DST_X_MAJOR 0x00000000 +#define DST_Y_MAJOR 0x00000004 +#define DST_X_TILE 0x00000008 +#define DST_Y_TILE 0x00000010 +#define DST_LAST_PEL 0x00000020 +#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +#define DST_BRES_SIGN 0x00000100 +#define DST_HOST_BIG_ENDIAN_EN 0x00000200 +#define DST_POLYLINE_NONLAST 0x00008000 +#define DST_RASTER_STALL 0x00010000 +#define DST_POLY_EDGE 0x00040000 + +/* DP_MIX bit constants */ +#define DP_SRC_RECT 0x00000200 +#define DP_SRC_HOST 0x00000300 +#define DP_SRC_HOST_BYTEALIGN 0x00000400 + +/* LVDS_GEN_CNTL constants */ +#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 +#define LVDS_BL_MOD_LEVEL_SHIFT 8 +#define LVDS_BL_MOD_EN 0x00010000 +#define LVDS_DIGION 0x00040000 +#define LVDS_BLON 0x00080000 +#define LVDS_ON 0x00000001 +#define LVDS_DISPLAY_DIS 0x00000002 +#define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004 +#define LVDS_PANEL_24BITS_TFT 0x00000008 +#define LVDS_FRAME_MOD_NO 0x00000000 +#define LVDS_FRAME_MOD_2_LEVELS 0x00000010 +#define LVDS_FRAME_MOD_4_LEVELS 0x00000020 +#define LVDS_RST_FM 0x00000040 +#define LVDS_EN 0x00000080 + +/* CRTC2_GEN_CNTL constants */ +#define CRTC2_EN 0x02000000 + +/* POWER_MANAGEMENT constants */ +#define PWR_MGT_ON 0x00000001 +#define PWR_MGT_MODE_MASK 0x00000006 +#define PWR_MGT_MODE_PIN 0x00000000 +#define PWR_MGT_MODE_REGISTER 0x00000002 +#define PWR_MGT_MODE_TIMER 0x00000004 +#define PWR_MGT_MODE_PCI 0x00000006 +#define PWR_MGT_AUTO_PWR_UP_EN 0x00000008 +#define PWR_MGT_ACTIVITY_PIN_ON 0x00000010 +#define PWR_MGT_STANDBY_POL 0x00000020 +#define PWR_MGT_SUSPEND_POL 0x00000040 +#define PWR_MGT_SELF_REFRESH 0x00000080 +#define PWR_MGT_ACTIVITY_PIN_EN 0x00000100 +#define PWR_MGT_KEYBD_SNOOP 0x00000200 +#define PWR_MGT_TRISTATE_MEM_EN 0x00000800 +#define PWR_MGT_SELW4MS 0x00001000 +#define PWR_MGT_SLOWDOWN_MCLK 0x00002000 + +#define PMI_PMSCR_REG 0x60 + +/* used by ATI bug fix for hardware ROM */ +#define RAGE128_MPP_TB_CONFIG 0x01c0 + +#endif /* REG_RAGE128_H */ diff --git a/include/video/broadsheetfb.h b/include/video/broadsheetfb.h new file mode 100644 index 000000000..548d28f4e --- /dev/null +++ b/include/video/broadsheetfb.h @@ -0,0 +1,74 @@ +/* + * broadsheetfb.h - definitions for the broadsheet framebuffer driver + * + * Copyright (C) 2008 by Jaya Kumar + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + * + */ + +#ifndef _LINUX_BROADSHEETFB_H_ +#define _LINUX_BROADSHEETFB_H_ + +/* Broadsheet command defines */ +#define BS_CMD_INIT_SYS_RUN 0x06 +#define BS_CMD_INIT_DSPE_CFG 0x09 +#define BS_CMD_INIT_DSPE_TMG 0x0A +#define BS_CMD_INIT_ROTMODE 0x0B +#define BS_CMD_RD_REG 0x10 +#define BS_CMD_WR_REG 0x11 +#define BS_CMD_LD_IMG 0x20 +#define BS_CMD_LD_IMG_AREA 0x22 +#define BS_CMD_LD_IMG_END 0x23 +#define BS_CMD_WAIT_DSPE_TRG 0x28 +#define BS_CMD_WAIT_DSPE_FREND 0x29 +#define BS_CMD_RD_WFM_INFO 0x30 +#define BS_CMD_UPD_INIT 0x32 +#define BS_CMD_UPD_FULL 0x33 +#define BS_CMD_UPD_GDRV_CLR 0x37 + +/* Broadsheet register interface defines */ +#define BS_REG_REV 0x00 +#define BS_REG_PRC 0x02 + +/* Broadsheet pin interface specific defines */ +#define BS_CS 0x01 +#define BS_DC 0x02 +#define BS_WR 0x03 + +/* Broadsheet IO interface specific defines */ +#define BS_MMIO_CMD 0x01 +#define BS_MMIO_DATA 0x02 + +/* struct used by broadsheet. board specific stuff comes from *board */ +struct broadsheetfb_par { + struct fb_info *info; + struct broadsheet_board *board; + void (*write_reg)(struct broadsheetfb_par *, u16 reg, u16 val); + u16 (*read_reg)(struct broadsheetfb_par *, u16 reg); + wait_queue_head_t waitq; + int panel_index; + struct mutex io_lock; +}; + +/* board specific routines */ +struct broadsheet_board { + struct module *owner; + int (*init)(struct broadsheetfb_par *); + int (*wait_for_rdy)(struct broadsheetfb_par *); + void (*cleanup)(struct broadsheetfb_par *); + int (*get_panel_type)(void); + int (*setup_irq)(struct fb_info *); + + /* Functions for boards that use GPIO */ + void (*set_ctl)(struct broadsheetfb_par *, unsigned char, u8); + void (*set_hdb)(struct broadsheetfb_par *, u16); + u16 (*get_hdb)(struct broadsheetfb_par *); + + /* Functions for boards that have specialized MMIO */ + void (*mmio_write)(struct broadsheetfb_par *, int type, u16); + u16 (*mmio_read)(struct broadsheetfb_par *); +}; +#endif diff --git a/include/video/cirrus.h b/include/video/cirrus.h new file mode 100644 index 000000000..9a5e9ee30 --- /dev/null +++ b/include/video/cirrus.h @@ -0,0 +1,122 @@ +/* + * drivers/video/clgenfb.h - Cirrus Logic chipset constants + * + * Copyright 1999 Jeff Garzik + * + * Original clgenfb author: Frank Neumann + * + * Based on retz3fb.c and clgen.c: + * Copyright (C) 1997 Jes Sorensen + * Copyright (C) 1996 Frank Neumann + * + *************************************************************** + * + * Format this code with GNU indent '-kr -i8 -pcs' options. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + */ + +#ifndef __CLGENFB_H__ +#define __CLGENFB_H__ + +/* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */ +/* OLD COMMENT: these definitions might most of the time also work */ +/* OLD COMMENT: for other CL-GD542x/543x based boards.. */ + +/*** External/General Registers ***/ +#define CL_POS102 0x102 /* POS102 register */ +#define CL_VSSM 0x46e8 /* Adapter Sleep */ +#define CL_VSSM2 0x3c3 /* Motherboard Sleep */ + +/*** VGA Sequencer Registers ***/ +/* the following are from the "extension registers" group */ +#define CL_SEQR6 0x6 /* Unlock ALL Extensions */ +#define CL_SEQR7 0x7 /* Extended Sequencer Mode */ +#define CL_SEQR8 0x8 /* EEPROM Control */ +#define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */ +#define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */ +#define CL_SEQRB 0xb /* VCLK0 Numerator */ +#define CL_SEQRC 0xc /* VCLK1 Numerator */ +#define CL_SEQRD 0xd /* VCLK2 Numerator */ +#define CL_SEQRE 0xe /* VCLK3 Numerator */ +#define CL_SEQRF 0xf /* DRAM Control */ +#define CL_SEQR10 0x10 /* Graphics Cursor X Position */ +#define CL_SEQR11 0x11 /* Graphics Cursor Y Position */ +#define CL_SEQR12 0x12 /* Graphics Cursor Attributes */ +#define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */ +#define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */ +#define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */ +#define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */ +#define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */ +#define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */ +#define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */ +#define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */ +#define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */ +#define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */ +#define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */ +#define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */ +#define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */ + +/*** CRT Controller Registers ***/ +#define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */ +#define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */ +#define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */ +/* the following are from the "extension registers" group */ +#define CL_CRT19 0x19 /* Interlace End */ +#define CL_CRT1A 0x1a /* Interlace Control */ +#define CL_CRT1B 0x1b /* Extended Display Controls */ +#define CL_CRT1C 0x1c /* Sync adjust and genlock register */ +#define CL_CRT1D 0x1d /* Overlay Extended Control register */ +#define CL_CRT1E 0x1e /* Another overflow register */ +#define CL_CRT25 0x25 /* Part Status Register */ +#define CL_CRT27 0x27 /* ID Register */ +#define CL_CRT51 0x51 /* P4 disable "flicker fixer" */ + +/*** Graphics Controller Registers ***/ +/* the following are from the "extension registers" group */ +#define CL_GR9 0x9 /* Offset Register 0 */ +#define CL_GRA 0xa /* Offset Register 1 */ +#define CL_GRB 0xb /* Graphics Controller Mode Extensions */ +#define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */ +#define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */ +#define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */ +#define CL_GRF 0xf /* Display Compression Control register */ +#define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */ +#define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */ +#define CL_GR12 0x12 /* Background Color Byte 2 Register */ +#define CL_GR13 0x13 /* Foreground Color Byte 2 Register */ +#define CL_GR14 0x14 /* Background Color Byte 3 Register */ +#define CL_GR15 0x15 /* Foreground Color Byte 3 Register */ +/* the following are CL-GD5426/'28 specific blitter registers */ +#define CL_GR20 0x20 /* BLT Width Low */ +#define CL_GR21 0x21 /* BLT Width High */ +#define CL_GR22 0x22 /* BLT Height Low */ +#define CL_GR23 0x23 /* BLT Height High */ +#define CL_GR24 0x24 /* BLT Destination Pitch Low */ +#define CL_GR25 0x25 /* BLT Destination Pitch High */ +#define CL_GR26 0x26 /* BLT Source Pitch Low */ +#define CL_GR27 0x27 /* BLT Source Pitch High */ +#define CL_GR28 0x28 /* BLT Destination Start Low */ +#define CL_GR29 0x29 /* BLT Destination Start Mid */ +#define CL_GR2A 0x2a /* BLT Destination Start High */ +#define CL_GR2C 0x2c /* BLT Source Start Low */ +#define CL_GR2D 0x2d /* BLT Source Start Mid */ +#define CL_GR2E 0x2e /* BLT Source Start High */ +#define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */ +#define CL_GR30 0x30 /* BLT Mode */ +#define CL_GR31 0x31 /* BLT Start/Status */ +#define CL_GR32 0x32 /* BLT Raster Operation */ +#define CL_GR33 0x33 /* another P4 "compat" register.. */ +#define CL_GR34 0x34 /* Transparent Color Select Low */ +#define CL_GR35 0x35 /* Transparent Color Select High */ +#define CL_GR38 0x38 /* Source Transparent Color Mask Low */ +#define CL_GR39 0x39 /* Source Transparent Color Mask High */ + +/*** Attribute Controller Registers ***/ +#define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */ +#define CL_AR34 0x34 /* TEST */ + +#endif /* __CLGENFB_H__ */ diff --git a/include/video/cvisionppc.h b/include/video/cvisionppc.h new file mode 100644 index 000000000..11250eee9 --- /dev/null +++ b/include/video/cvisionppc.h @@ -0,0 +1,51 @@ +/* + * Phase5 CybervisionPPC (TVP4020) definitions for the Permedia2 framebuffer + * driver. + * + * Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) + * -------------------------------------------------------------------------- + * $Id: cvisionppc.h,v 1.8 1999/01/28 13:18:07 illo Exp $ + * -------------------------------------------------------------------------- + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef CVISIONPPC_H +#define CVISIONPPC_H + +#ifndef PM2FB_H +#include "pm2fb.h" +#endif + +struct cvppc_par { + unsigned char* pci_config; + unsigned char* pci_bridge; + u32 user_flags; +}; + +#define CSPPC_PCI_BRIDGE 0xfffe0000 +#define CSPPC_BRIDGE_ENDIAN 0x0000 +#define CSPPC_BRIDGE_INT 0x0010 + +#define CVPPC_PCI_CONFIG 0xfffc0000 +#define CVPPC_ROM_ADDRESS 0xe2000001 +#define CVPPC_REGS_REGION 0xef000000 +#define CVPPC_FB_APERTURE_ONE 0xe0000000 +#define CVPPC_FB_APERTURE_TWO 0xe1000000 +#define CVPPC_FB_SIZE 0x00800000 +#define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */ +#define CVPPC_MEM_CONFIG_NEW 0xed41c532 /* FIXME USA?? */ +#define CVPPC_MEMCLOCK 83000 /* in KHz */ + +/* CVPPC_BRIDGE_ENDIAN */ +#define CSPPCF_BRIDGE_BIG_ENDIAN 0x02 + +/* CVPPC_BRIDGE_INT */ +#define CSPPCF_BRIDGE_ACTIVE_INT2 0x01 + +#endif /* CVISIONPPC_H */ + +/***************************************************************************** + * That's all folks! + *****************************************************************************/ diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h new file mode 100644 index 000000000..1d19ae62b --- /dev/null +++ b/include/video/da8xx-fb.h @@ -0,0 +1,94 @@ +/* + * Header file for TI DA8XX LCD controller platform data. + * + * Copyright (C) 2008-2009 MontaVista Software Inc. + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef DA8XX_FB_H +#define DA8XX_FB_H + +enum panel_shade { + MONOCHROME = 0, + COLOR_ACTIVE, + COLOR_PASSIVE, +}; + +enum raster_load_mode { + LOAD_DATA = 1, + LOAD_PALETTE, +}; + +enum da8xx_frame_complete { + DA8XX_FRAME_WAIT, + DA8XX_FRAME_NOWAIT, +}; + +struct da8xx_lcdc_platform_data { + const char manu_name[10]; + void *controller_data; + const char type[25]; +}; + +struct lcd_ctrl_config { + enum panel_shade panel_shade; + + /* AC Bias Pin Frequency */ + int ac_bias; + + /* AC Bias Pin Transitions per Interrupt */ + int ac_bias_intrpt; + + /* DMA burst size */ + int dma_burst_sz; + + /* Bits per pixel */ + int bpp; + + /* FIFO DMA Request Delay */ + int fdd; + + /* TFT Alternative Signal Mapping (Only for active) */ + unsigned char tft_alt_mode; + + /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */ + unsigned char stn_565_mode; + + /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ + unsigned char mono_8bit_mode; + + /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ + unsigned char sync_edge; + + /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ + unsigned char raster_order; + + /* DMA FIFO threshold */ + int fifo_th; +}; + +struct lcd_sync_arg { + int back_porch; + int front_porch; + int pulse_width; +}; + +/* ioctls */ +#define FBIOGET_CONTRAST _IOR('F', 1, int) +#define FBIOPUT_CONTRAST _IOW('F', 2, int) +#define FBIGET_BRIGHTNESS _IOR('F', 3, int) +#define FBIPUT_BRIGHTNESS _IOW('F', 3, int) +#define FBIGET_COLOR _IOR('F', 5, int) +#define FBIPUT_COLOR _IOW('F', 6, int) +#define FBIPUT_HSYNC _IOW('F', 9, int) +#define FBIPUT_VSYNC _IOW('F', 10, int) + +/* Proprietary FB_SYNC_ flags */ +#define FB_SYNC_CLK_INVERT 0x40000000 + +#endif /* ifndef DA8XX_FB_H */ + diff --git a/include/video/display_timing.h b/include/video/display_timing.h new file mode 100644 index 000000000..37a017607 --- /dev/null +++ b/include/video/display_timing.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2012 Steffen Trumtrar + * + * description of display timings + */ + +#ifndef __LINUX_DISPLAY_TIMING_H +#define __LINUX_DISPLAY_TIMING_H + +#include +#include + +enum display_flags { + DISPLAY_FLAGS_HSYNC_LOW = BIT(0), + DISPLAY_FLAGS_HSYNC_HIGH = BIT(1), + DISPLAY_FLAGS_VSYNC_LOW = BIT(2), + DISPLAY_FLAGS_VSYNC_HIGH = BIT(3), + + /* data enable flag */ + DISPLAY_FLAGS_DE_LOW = BIT(4), + DISPLAY_FLAGS_DE_HIGH = BIT(5), + /* drive data on pos. edge */ + DISPLAY_FLAGS_PIXDATA_POSEDGE = BIT(6), + /* drive data on neg. edge */ + DISPLAY_FLAGS_PIXDATA_NEGEDGE = BIT(7), + DISPLAY_FLAGS_INTERLACED = BIT(8), + DISPLAY_FLAGS_DOUBLESCAN = BIT(9), + DISPLAY_FLAGS_DOUBLECLK = BIT(10), + /* drive sync on pos. edge */ + DISPLAY_FLAGS_SYNC_POSEDGE = BIT(11), + /* drive sync on neg. edge */ + DISPLAY_FLAGS_SYNC_NEGEDGE = BIT(12), +}; + +/* + * A single signal can be specified via a range of minimal and maximal values + * with a typical value, that lies somewhere inbetween. + */ +struct timing_entry { + u32 min; + u32 typ; + u32 max; +}; + +/* + * Single "mode" entry. This describes one set of signal timings a display can + * have in one setting. This struct can later be converted to struct videomode + * (see include/video/videomode.h). As each timing_entry can be defined as a + * range, one struct display_timing may become multiple struct videomodes. + * + * Example: hsync active high, vsync active low + * + * Active Video + * Video ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________ + * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync.. + * | | porch | | porch | + * + * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯ + * + * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________ + */ +struct display_timing { + struct timing_entry pixelclock; + + struct timing_entry hactive; /* hor. active video */ + struct timing_entry hfront_porch; /* hor. front porch */ + struct timing_entry hback_porch; /* hor. back porch */ + struct timing_entry hsync_len; /* hor. sync len */ + + struct timing_entry vactive; /* ver. active video */ + struct timing_entry vfront_porch; /* ver. front porch */ + struct timing_entry vback_porch; /* ver. back porch */ + struct timing_entry vsync_len; /* ver. sync len */ + + enum display_flags flags; /* display flags */ +}; + +/* + * This describes all timing settings a display provides. + * The native_mode is the default setting for this display. + * Drivers that can handle multiple videomodes should work with this struct and + * convert each entry to the desired end result. + */ +struct display_timings { + unsigned int num_timings; + unsigned int native_mode; + + struct display_timing **timings; +}; + +/* get one entry from struct display_timings */ +static inline struct display_timing *display_timings_get(const struct + display_timings *disp, + unsigned int index) +{ + if (disp->num_timings > index) + return disp->timings[index]; + else + return NULL; +} + +void display_timings_release(struct display_timings *disp); + +#endif diff --git a/include/video/edid.h b/include/video/edid.h new file mode 100644 index 000000000..f614371e9 --- /dev/null +++ b/include/video/edid.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __linux_video_edid_h__ +#define __linux_video_edid_h__ + +#include + +#ifdef CONFIG_X86 +extern struct edid_info edid_info; +#endif +#endif /* __linux_video_edid_h__ */ diff --git a/include/video/gbe.h b/include/video/gbe.h new file mode 100644 index 000000000..8b4d335d1 --- /dev/null +++ b/include/video/gbe.h @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * include/video/gbe.h -- SGI GBE (Graphics Back End) + * + * Copyright (C) 1999 Silicon Graphics, Inc. (Jeffrey Newquist) + */ + +#ifndef __GBE_H__ +#define __GBE_H__ + +struct sgi_gbe { + volatile uint32_t ctrlstat; /* general control */ + volatile uint32_t dotclock; /* dot clock PLL control */ + volatile uint32_t i2c; /* crt I2C control */ + volatile uint32_t sysclk; /* system clock PLL control */ + volatile uint32_t i2cfp; /* flat panel I2C control */ + volatile uint32_t id; /* device id/chip revision */ + volatile uint32_t config; /* power on configuration [1] */ + volatile uint32_t bist; /* internal bist status [1] */ + uint32_t _pad0[0x010000/4 - 8]; + volatile uint32_t vt_xy; /* current dot coords */ + volatile uint32_t vt_xymax; /* maximum dot coords */ + volatile uint32_t vt_vsync; /* vsync on/off */ + volatile uint32_t vt_hsync; /* hsync on/off */ + volatile uint32_t vt_vblank; /* vblank on/off */ + volatile uint32_t vt_hblank; /* hblank on/off */ + volatile uint32_t vt_flags; /* polarity of vt signals */ + volatile uint32_t vt_f2rf_lock; /* f2rf & framelck y coord */ + volatile uint32_t vt_intr01; /* intr 0,1 y coords */ + volatile uint32_t vt_intr23; /* intr 2,3 y coords */ + volatile uint32_t fp_hdrv; /* flat panel hdrv on/off */ + volatile uint32_t fp_vdrv; /* flat panel vdrv on/off */ + volatile uint32_t fp_de; /* flat panel de on/off */ + volatile uint32_t vt_hpixen; /* intrnl horiz pixel on/off */ + volatile uint32_t vt_vpixen; /* intrnl vert pixel on/off */ + volatile uint32_t vt_hcmap; /* cmap write (horiz) */ + volatile uint32_t vt_vcmap; /* cmap write (vert) */ + volatile uint32_t did_start_xy; /* eol/f did/xy reset val */ + volatile uint32_t crs_start_xy; /* eol/f crs/xy reset val */ + volatile uint32_t vc_start_xy; /* eol/f vc/xy reset val */ + uint32_t _pad1[0xffb0/4]; + volatile uint32_t ovr_width_tile;/*overlay plane ctrl 0 */ + volatile uint32_t ovr_inhwctrl; /* overlay plane ctrl 1 */ + volatile uint32_t ovr_control; /* overlay plane ctrl 1 */ + uint32_t _pad2[0xfff4/4]; + volatile uint32_t frm_size_tile;/* normal plane ctrl 0 */ + volatile uint32_t frm_size_pixel;/*normal plane ctrl 1 */ + volatile uint32_t frm_inhwctrl; /* normal plane ctrl 2 */ + volatile uint32_t frm_control; /* normal plane ctrl 3 */ + uint32_t _pad3[0xfff0/4]; + volatile uint32_t did_inhwctrl; /* DID control */ + volatile uint32_t did_control; /* DID shadow */ + uint32_t _pad4[0x7ff8/4]; + volatile uint32_t mode_regs[32];/* WID table */ + uint32_t _pad5[0x7f80/4]; + volatile uint32_t cmap[6144]; /* color map */ + uint32_t _pad6[0x2000/4]; + volatile uint32_t cm_fifo; /* color map fifo status */ + uint32_t _pad7[0x7ffc/4]; + volatile uint32_t gmap[256]; /* gamma map */ + uint32_t _pad8[0x7c00/4]; + volatile uint32_t gmap10[1024]; /* gamma map */ + uint32_t _pad9[0x7000/4]; + volatile uint32_t crs_pos; /* cusror control 0 */ + volatile uint32_t crs_ctl; /* cusror control 1 */ + volatile uint32_t crs_cmap[3]; /* crs cmap */ + uint32_t _pad10[0x7fec/4]; + volatile uint32_t crs_glyph[64];/* crs glyph */ + uint32_t _pad11[0x7f00/4]; + volatile uint32_t vc_0; /* video capture crtl 0 */ + volatile uint32_t vc_1; /* video capture crtl 1 */ + volatile uint32_t vc_2; /* video capture crtl 2 */ + volatile uint32_t vc_3; /* video capture crtl 3 */ + volatile uint32_t vc_4; /* video capture crtl 4 */ + volatile uint32_t vc_5; /* video capture crtl 5 */ + volatile uint32_t vc_6; /* video capture crtl 6 */ + volatile uint32_t vc_7; /* video capture crtl 7 */ + volatile uint32_t vc_8; /* video capture crtl 8 */ +}; + +#define MASK(msb, lsb) \ + ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) ) +#define GET(v, msb, lsb) \ + ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) ) +#define SET(v, f, msb, lsb) \ + ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) ) + +#define GET_GBE_FIELD(reg, field, v) \ + GET((v), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB) +#define SET_GBE_FIELD(reg, field, v, f) \ + SET((v), (f), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB) + +/* + * Bit mask information + */ +#define GBE_CTRLSTAT_CHIPID_MSB 3 +#define GBE_CTRLSTAT_CHIPID_LSB 0 +#define GBE_CTRLSTAT_SENSE_N_MSB 4 +#define GBE_CTRLSTAT_SENSE_N_LSB 4 +#define GBE_CTRLSTAT_PCLKSEL_MSB 29 +#define GBE_CTRLSTAT_PCLKSEL_LSB 28 + +#define GBE_DOTCLK_M_MSB 7 +#define GBE_DOTCLK_M_LSB 0 +#define GBE_DOTCLK_N_MSB 13 +#define GBE_DOTCLK_N_LSB 8 +#define GBE_DOTCLK_P_MSB 15 +#define GBE_DOTCLK_P_LSB 14 +#define GBE_DOTCLK_RUN_MSB 20 +#define GBE_DOTCLK_RUN_LSB 20 + +#define GBE_VT_XY_Y_MSB 23 +#define GBE_VT_XY_Y_LSB 12 +#define GBE_VT_XY_X_MSB 11 +#define GBE_VT_XY_X_LSB 0 +#define GBE_VT_XY_FREEZE_MSB 31 +#define GBE_VT_XY_FREEZE_LSB 31 + +#define GBE_FP_VDRV_ON_MSB 23 +#define GBE_FP_VDRV_ON_LSB 12 +#define GBE_FP_VDRV_OFF_MSB 11 +#define GBE_FP_VDRV_OFF_LSB 0 + +#define GBE_FP_HDRV_ON_MSB 23 +#define GBE_FP_HDRV_ON_LSB 12 +#define GBE_FP_HDRV_OFF_MSB 11 +#define GBE_FP_HDRV_OFF_LSB 0 + +#define GBE_FP_DE_ON_MSB 23 +#define GBE_FP_DE_ON_LSB 12 +#define GBE_FP_DE_OFF_MSB 11 +#define GBE_FP_DE_OFF_LSB 0 + +#define GBE_VT_VSYNC_VSYNC_ON_MSB 23 +#define GBE_VT_VSYNC_VSYNC_ON_LSB 12 +#define GBE_VT_VSYNC_VSYNC_OFF_MSB 11 +#define GBE_VT_VSYNC_VSYNC_OFF_LSB 0 + +#define GBE_VT_HSYNC_HSYNC_ON_MSB 23 +#define GBE_VT_HSYNC_HSYNC_ON_LSB 12 +#define GBE_VT_HSYNC_HSYNC_OFF_MSB 11 +#define GBE_VT_HSYNC_HSYNC_OFF_LSB 0 + +#define GBE_VT_VBLANK_VBLANK_ON_MSB 23 +#define GBE_VT_VBLANK_VBLANK_ON_LSB 12 +#define GBE_VT_VBLANK_VBLANK_OFF_MSB 11 +#define GBE_VT_VBLANK_VBLANK_OFF_LSB 0 + +#define GBE_VT_HBLANK_HBLANK_ON_MSB 23 +#define GBE_VT_HBLANK_HBLANK_ON_LSB 12 +#define GBE_VT_HBLANK_HBLANK_OFF_MSB 11 +#define GBE_VT_HBLANK_HBLANK_OFF_LSB 0 + +#define GBE_VT_FLAGS_F2RF_HIGH_MSB 6 +#define GBE_VT_FLAGS_F2RF_HIGH_LSB 6 +#define GBE_VT_FLAGS_SYNC_LOW_MSB 5 +#define GBE_VT_FLAGS_SYNC_LOW_LSB 5 +#define GBE_VT_FLAGS_SYNC_HIGH_MSB 4 +#define GBE_VT_FLAGS_SYNC_HIGH_LSB 4 +#define GBE_VT_FLAGS_HDRV_LOW_MSB 3 +#define GBE_VT_FLAGS_HDRV_LOW_LSB 3 +#define GBE_VT_FLAGS_HDRV_INVERT_MSB 2 +#define GBE_VT_FLAGS_HDRV_INVERT_LSB 2 +#define GBE_VT_FLAGS_VDRV_LOW_MSB 1 +#define GBE_VT_FLAGS_VDRV_LOW_LSB 1 +#define GBE_VT_FLAGS_VDRV_INVERT_MSB 0 +#define GBE_VT_FLAGS_VDRV_INVERT_LSB 0 + +#define GBE_VT_VCMAP_VCMAP_ON_MSB 23 +#define GBE_VT_VCMAP_VCMAP_ON_LSB 12 +#define GBE_VT_VCMAP_VCMAP_OFF_MSB 11 +#define GBE_VT_VCMAP_VCMAP_OFF_LSB 0 + +#define GBE_VT_HCMAP_HCMAP_ON_MSB 23 +#define GBE_VT_HCMAP_HCMAP_ON_LSB 12 +#define GBE_VT_HCMAP_HCMAP_OFF_MSB 11 +#define GBE_VT_HCMAP_HCMAP_OFF_LSB 0 + +#define GBE_VT_XYMAX_MAXX_MSB 11 +#define GBE_VT_XYMAX_MAXX_LSB 0 +#define GBE_VT_XYMAX_MAXY_MSB 23 +#define GBE_VT_XYMAX_MAXY_LSB 12 + +#define GBE_VT_HPIXEN_HPIXEN_ON_MSB 23 +#define GBE_VT_HPIXEN_HPIXEN_ON_LSB 12 +#define GBE_VT_HPIXEN_HPIXEN_OFF_MSB 11 +#define GBE_VT_HPIXEN_HPIXEN_OFF_LSB 0 + +#define GBE_VT_VPIXEN_VPIXEN_ON_MSB 23 +#define GBE_VT_VPIXEN_VPIXEN_ON_LSB 12 +#define GBE_VT_VPIXEN_VPIXEN_OFF_MSB 11 +#define GBE_VT_VPIXEN_VPIXEN_OFF_LSB 0 + +#define GBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0 +#define GBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0 + +#define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0 +#define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0 + +#define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13 +#define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13 + +#define GBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0 +#define GBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0 +#define GBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31 +#define GBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9 +#define GBE_FRM_CONTROL_FRM_LINEAR_MSB 1 +#define GBE_FRM_CONTROL_FRM_LINEAR_LSB 1 + +#define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0 +#define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0 + +#define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12 +#define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5 +#define GBE_FRM_SIZE_TILE_FRM_RHS_MSB 4 +#define GBE_FRM_SIZE_TILE_FRM_RHS_LSB 0 +#define GBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14 +#define GBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13 +#define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15 +#define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15 + +#define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31 +#define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16 + +#define GBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0 +#define GBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0 +#define GBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0 +#define GBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0 + +#define GBE_DID_START_XY_DID_STARTY_MSB 23 +#define GBE_DID_START_XY_DID_STARTY_LSB 12 +#define GBE_DID_START_XY_DID_STARTX_MSB 11 +#define GBE_DID_START_XY_DID_STARTX_LSB 0 + +#define GBE_CRS_START_XY_CRS_STARTY_MSB 23 +#define GBE_CRS_START_XY_CRS_STARTY_LSB 12 +#define GBE_CRS_START_XY_CRS_STARTX_MSB 11 +#define GBE_CRS_START_XY_CRS_STARTX_LSB 0 + +#define GBE_WID_AUX_MSB 12 +#define GBE_WID_AUX_LSB 11 +#define GBE_WID_GAMMA_MSB 10 +#define GBE_WID_GAMMA_LSB 10 +#define GBE_WID_CM_MSB 9 +#define GBE_WID_CM_LSB 5 +#define GBE_WID_TYP_MSB 4 +#define GBE_WID_TYP_LSB 2 +#define GBE_WID_BUF_MSB 1 +#define GBE_WID_BUF_LSB 0 + +#define GBE_VC_START_XY_VC_STARTY_MSB 23 +#define GBE_VC_START_XY_VC_STARTY_LSB 12 +#define GBE_VC_START_XY_VC_STARTX_MSB 11 +#define GBE_VC_START_XY_VC_STARTX_LSB 0 + +/* Constants */ + +#define GBE_FRM_DEPTH_8 0 +#define GBE_FRM_DEPTH_16 1 +#define GBE_FRM_DEPTH_32 2 + +#define GBE_CMODE_I8 0 +#define GBE_CMODE_I12 1 +#define GBE_CMODE_RG3B2 2 +#define GBE_CMODE_RGB4 3 +#define GBE_CMODE_ARGB5 4 +#define GBE_CMODE_RGB8 5 +#define GBE_CMODE_RGBA5 6 +#define GBE_CMODE_RGB10 7 + +#define GBE_BMODE_BOTH 3 + +#define GBE_CRS_MAGIC 54 +#define GBE_PIXEN_MAGIC_ON 19 +#define GBE_PIXEN_MAGIC_OFF 2 + +#define GBE_TLB_SIZE 128 + +/* [1] - only GBE revision 2 and later */ + +/* + * Video Timing Data Structure + */ + +struct gbe_timing_info { + int flags; + short width; /* Monitor resolution */ + short height; + int fields_sec; /* fields/sec (Hz -3 dec. places */ + int cfreq; /* pixel clock frequency (MHz -3 dec. places) */ + short htotal; /* Horizontal total pixels */ + short hblank_start; /* Horizontal blank start */ + short hblank_end; /* Horizontal blank end */ + short hsync_start; /* Horizontal sync start */ + short hsync_end; /* Horizontal sync end */ + short vtotal; /* Vertical total lines */ + short vblank_start; /* Vertical blank start */ + short vblank_end; /* Vertical blank end */ + short vsync_start; /* Vertical sync start */ + short vsync_end; /* Vertical sync end */ + short pll_m; /* PLL M parameter */ + short pll_n; /* PLL P parameter */ + short pll_p; /* PLL N parameter */ +}; + +/* Defines for gbe_vof_info_t flags */ + +#define GBE_VOF_UNKNOWNMON 1 +#define GBE_VOF_STEREO 2 +#define GBE_VOF_DO_GENSYNC 4 /* enable incoming sync */ +#define GBE_VOF_SYNC_ON_GREEN 8 /* sync on green */ +#define GBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */ +#define GBE_VOF_MAGICKEY 0x2000 /* Backdoor key */ + +#endif /* ! __GBE_H__ */ diff --git a/include/video/hecubafb.h b/include/video/hecubafb.h new file mode 100644 index 000000000..7b9952339 --- /dev/null +++ b/include/video/hecubafb.h @@ -0,0 +1,51 @@ +/* + * hecubafb.h - definitions for the hecuba framebuffer driver + * + * Copyright (C) 2008 by Jaya Kumar + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + * + */ + +#ifndef _LINUX_HECUBAFB_H_ +#define _LINUX_HECUBAFB_H_ + +/* Apollo controller specific defines */ +#define APOLLO_START_NEW_IMG 0xA0 +#define APOLLO_STOP_IMG_DATA 0xA1 +#define APOLLO_DISPLAY_IMG 0xA2 +#define APOLLO_ERASE_DISPLAY 0xA3 +#define APOLLO_INIT_DISPLAY 0xA4 + +/* Hecuba interface specific defines */ +#define HCB_WUP_BIT 0x01 +#define HCB_DS_BIT 0x02 +#define HCB_RW_BIT 0x04 +#define HCB_CD_BIT 0x08 +#define HCB_ACK_BIT 0x80 + +/* struct used by hecuba. board specific stuff comes from *board */ +struct hecubafb_par { + struct fb_info *info; + struct hecuba_board *board; + void (*send_command)(struct hecubafb_par *, unsigned char); + void (*send_data)(struct hecubafb_par *, unsigned char); +}; + +/* board specific routines +board drivers can implement wait_for_ack with interrupts if desired. if +wait_for_ack is called with clear=0, then go to sleep and return when ack +goes hi or if wait_for_ack with clear=1, then return when ack goes lo */ +struct hecuba_board { + struct module *owner; + void (*remove)(struct hecubafb_par *); + void (*set_ctl)(struct hecubafb_par *, unsigned char, unsigned char); + void (*set_data)(struct hecubafb_par *, unsigned char); + void (*wait_for_ack)(struct hecubafb_par *, int); + int (*init)(struct hecubafb_par *); +}; + + +#endif diff --git a/include/video/ili9320.h b/include/video/ili9320.h new file mode 100644 index 000000000..62f424f0b --- /dev/null +++ b/include/video/ili9320.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* include/video/ili9320.c + * + * ILI9320 LCD controller configuration control. + * + * Copyright 2007 Simtec Electronics + * Ben Dooks + * + * http://armlinux.simtec.co.uk/ +*/ + +#define ILI9320_REG(x) (x) + +#define ILI9320_INDEX ILI9320_REG(0x00) + +#define ILI9320_OSCILATION ILI9320_REG(0x00) +#define ILI9320_DRIVER ILI9320_REG(0x01) +#define ILI9320_DRIVEWAVE ILI9320_REG(0x02) +#define ILI9320_ENTRYMODE ILI9320_REG(0x03) +#define ILI9320_RESIZING ILI9320_REG(0x04) +#define ILI9320_DISPLAY1 ILI9320_REG(0x07) +#define ILI9320_DISPLAY2 ILI9320_REG(0x08) +#define ILI9320_DISPLAY3 ILI9320_REG(0x09) +#define ILI9320_DISPLAY4 ILI9320_REG(0x0A) +#define ILI9320_RGB_IF1 ILI9320_REG(0x0C) +#define ILI9320_FRAMEMAKER ILI9320_REG(0x0D) +#define ILI9320_RGB_IF2 ILI9320_REG(0x0F) + +#define ILI9320_POWER1 ILI9320_REG(0x10) +#define ILI9320_POWER2 ILI9320_REG(0x11) +#define ILI9320_POWER3 ILI9320_REG(0x12) +#define ILI9320_POWER4 ILI9320_REG(0x13) +#define ILI9320_GRAM_HORIZ_ADDR ILI9320_REG(0x20) +#define ILI9320_GRAM_VERT_ADD ILI9320_REG(0x21) +#define ILI9320_POWER7 ILI9320_REG(0x29) +#define ILI9320_FRAME_RATE_COLOUR ILI9320_REG(0x2B) + +#define ILI9320_GAMMA1 ILI9320_REG(0x30) +#define ILI9320_GAMMA2 ILI9320_REG(0x31) +#define ILI9320_GAMMA3 ILI9320_REG(0x32) +#define ILI9320_GAMMA4 ILI9320_REG(0x35) +#define ILI9320_GAMMA5 ILI9320_REG(0x36) +#define ILI9320_GAMMA6 ILI9320_REG(0x37) +#define ILI9320_GAMMA7 ILI9320_REG(0x38) +#define ILI9320_GAMMA8 ILI9320_REG(0x39) +#define ILI9320_GAMMA9 ILI9320_REG(0x3C) +#define ILI9320_GAMMA10 ILI9320_REG(0x3D) + +#define ILI9320_HORIZ_START ILI9320_REG(0x50) +#define ILI9320_HORIZ_END ILI9320_REG(0x51) +#define ILI9320_VERT_START ILI9320_REG(0x52) +#define ILI9320_VERT_END ILI9320_REG(0x53) + +#define ILI9320_DRIVER2 ILI9320_REG(0x60) +#define ILI9320_BASE_IMAGE ILI9320_REG(0x61) +#define ILI9320_VERT_SCROLL ILI9320_REG(0x6a) + +#define ILI9320_PARTIAL1_POSITION ILI9320_REG(0x80) +#define ILI9320_PARTIAL1_START ILI9320_REG(0x81) +#define ILI9320_PARTIAL1_END ILI9320_REG(0x82) +#define ILI9320_PARTIAL2_POSITION ILI9320_REG(0x83) +#define ILI9320_PARTIAL2_START ILI9320_REG(0x84) +#define ILI9320_PARTIAL2_END ILI9320_REG(0x85) + +#define ILI9320_INTERFACE1 ILI9320_REG(0x90) +#define ILI9320_INTERFACE2 ILI9320_REG(0x92) +#define ILI9320_INTERFACE3 ILI9320_REG(0x93) +#define ILI9320_INTERFACE4 ILI9320_REG(0x95) +#define ILI9320_INTERFACE5 ILI9320_REG(0x97) +#define ILI9320_INTERFACE6 ILI9320_REG(0x98) + +/* Register contents definitions. */ + +#define ILI9320_OSCILATION_OSC (1 << 0) + +#define ILI9320_DRIVER_SS (1 << 8) +#define ILI9320_DRIVER_SM (1 << 10) + +#define ILI9320_DRIVEWAVE_EOR (1 << 8) +#define ILI9320_DRIVEWAVE_BC (1 << 9) +#define ILI9320_DRIVEWAVE_MUSTSET (1 << 10) + +#define ILI9320_ENTRYMODE_AM (1 << 3) +#define ILI9320_ENTRYMODE_ID(x) ((x) << 4) +#define ILI9320_ENTRYMODE_ORG (1 << 7) +#define ILI9320_ENTRYMODE_HWM (1 << 8) +#define ILI9320_ENTRYMODE_BGR (1 << 12) +#define ILI9320_ENTRYMODE_DFM (1 << 14) +#define ILI9320_ENTRYMODE_TRI (1 << 15) + + +#define ILI9320_RESIZING_RSZ(x) ((x) << 0) +#define ILI9320_RESIZING_RCH(x) ((x) << 4) +#define ILI9320_RESIZING_RCV(x) ((x) << 8) + + +#define ILI9320_DISPLAY1_D(x) ((x) << 0) +#define ILI9320_DISPLAY1_CL (1 << 3) +#define ILI9320_DISPLAY1_DTE (1 << 4) +#define ILI9320_DISPLAY1_GON (1 << 5) +#define ILI9320_DISPLAY1_BASEE (1 << 8) +#define ILI9320_DISPLAY1_PTDE(x) ((x) << 12) + + +#define ILI9320_DISPLAY2_BP(x) ((x) << 0) +#define ILI9320_DISPLAY2_FP(x) ((x) << 8) + + +#define ILI9320_RGBIF1_RIM_RGB18 (0 << 0) +#define ILI9320_RGBIF1_RIM_RGB16 (1 << 0) +#define ILI9320_RGBIF1_RIM_RGB6 (2 << 0) + +#define ILI9320_RGBIF1_CLK_INT (0 << 4) +#define ILI9320_RGBIF1_CLK_RGBIF (1 << 4) +#define ILI9320_RGBIF1_CLK_VSYNC (2 << 4) + +#define ILI9320_RGBIF1_RM (1 << 8) + +#define ILI9320_RGBIF1_ENC_FRAMES(x) (((x) - 1)<< 13) + +#define ILI9320_RGBIF2_DPL (1 << 0) +#define ILI9320_RGBIF2_EPL (1 << 1) +#define ILI9320_RGBIF2_HSPL (1 << 3) +#define ILI9320_RGBIF2_VSPL (1 << 4) + + +#define ILI9320_POWER1_SLP (1 << 1) +#define ILI9320_POWER1_DSTB (1 << 2) +#define ILI9320_POWER1_AP(x) ((x) << 4) +#define ILI9320_POWER1_APE (1 << 7) +#define ILI9320_POWER1_BT(x) ((x) << 8) +#define ILI9320_POWER1_SAP (1 << 12) + + +#define ILI9320_POWER2_VC(x) ((x) << 0) +#define ILI9320_POWER2_DC0(x) ((x) << 4) +#define ILI9320_POWER2_DC1(x) ((x) << 8) + + +#define ILI9320_POWER3_VRH(x) ((x) << 0) +#define ILI9320_POWER3_PON (1 << 4) +#define ILI9320_POWER3_VCMR (1 << 8) + + +#define ILI9320_POWER4_VREOUT(x) ((x) << 8) + + +#define ILI9320_DRIVER2_SCNL(x) ((x) << 0) +#define ILI9320_DRIVER2_NL(x) ((x) << 8) +#define ILI9320_DRIVER2_GS (1 << 15) + + +#define ILI9320_BASEIMAGE_REV (1 << 0) +#define ILI9320_BASEIMAGE_VLE (1 << 1) +#define ILI9320_BASEIMAGE_NDL (1 << 2) + + +#define ILI9320_INTERFACE4_RTNE(x) (x) +#define ILI9320_INTERFACE4_DIVE(x) ((x) << 8) + +/* SPI interface definitions */ + +#define ILI9320_SPI_IDCODE (0x70) +#define ILI9320_SPI_ID(x) ((x) << 2) +#define ILI9320_SPI_READ (0x01) +#define ILI9320_SPI_WRITE (0x00) +#define ILI9320_SPI_DATA (0x02) +#define ILI9320_SPI_INDEX (0x00) + +/* platform data to pass configuration from lcd */ + +enum ili9320_suspend { + ILI9320_SUSPEND_OFF, + ILI9320_SUSPEND_DEEP, +}; + +struct ili9320_platdata { + unsigned short hsize; + unsigned short vsize; + + enum ili9320_suspend suspend; + + /* set the reset line, 0 = reset asserted, 1 = normal */ + void (*reset)(unsigned int val); + + unsigned short entry_mode; + unsigned short display2; + unsigned short display3; + unsigned short display4; + unsigned short rgb_if1; + unsigned short rgb_if2; + unsigned short interface2; + unsigned short interface3; + unsigned short interface4; + unsigned short interface5; + unsigned short interface6; +}; + diff --git a/include/video/imx-ipu-image-convert.h b/include/video/imx-ipu-image-convert.h new file mode 100644 index 000000000..3c71b8b94 --- /dev/null +++ b/include/video/imx-ipu-image-convert.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2012-2016 Mentor Graphics Inc. + * + * i.MX Queued image conversion support, with tiling and rotation. + */ +#ifndef __IMX_IPU_IMAGE_CONVERT_H__ +#define __IMX_IPU_IMAGE_CONVERT_H__ + +#include