/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_
#define ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_

/*
 *****************************************
 *   DCORE1_MME_CTRL_LO
 *   (Prototype: MME_CTRL_LO)
 *****************************************
 */

#define mmDCORE1_MME_CTRL_LO_ARCH_STATUS 0x42CB000

#define mmDCORE1_MME_CTRL_LO_CMD 0x42CB004

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x42CB148

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x42CB14C

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x42CB150

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x42CB154

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x42CB158

#define mmDCORE1_MME_CTRL_LO_ARCH_A_SS 0x42CB224

#define mmDCORE1_MME_CTRL_LO_ARCH_B_SS 0x42CB228

#define mmDCORE1_MME_CTRL_LO_ARCH_COUT_SS 0x42CB27C

#define mmDCORE1_MME_CTRL_LO_QM_STALL 0x42CB400

#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_LO 0x42CB404

#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_HI 0x42CB408

#define mmDCORE1_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x42CB40C

#define mmDCORE1_MME_CTRL_LO_REDUN 0x42CB410

#define mmDCORE1_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x42CB414

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x42CB418

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x42CB41C

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x42CB420

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x42CB424

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x42CB428

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x42CB42C

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x42CB430

#define mmDCORE1_MME_CTRL_LO_PCU_RL_DESC0 0x42CB434

#define mmDCORE1_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x42CB438

#define mmDCORE1_MME_CTRL_LO_PCU_RL_TH 0x42CB43C

#define mmDCORE1_MME_CTRL_LO_PCU_RL_MIN 0x42CB440

#define mmDCORE1_MME_CTRL_LO_PCU_RL_CTRL_EN 0x42CB444

#define mmDCORE1_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x42CB448

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x42CB44C

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x42CB450

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x42CB454

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x42CB458

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_F8 0x42CB45C

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x42CB460

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x42CB464

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x42CB468

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x42CB46C

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x42CB470

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x42CB474

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x42CB478

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x42CB47C

#define mmDCORE1_MME_CTRL_LO_PROT 0x42CB480

#define mmDCORE1_MME_CTRL_LO_EU 0x42CB484

#define mmDCORE1_MME_CTRL_LO_SBTE 0x42CB488

#define mmDCORE1_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x42CB48C

#define mmDCORE1_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x42CB490

#define mmDCORE1_MME_CTRL_LO_PCU_RL_SAT_SEC 0x42CB494

#define mmDCORE1_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x42CB498

#define mmDCORE1_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x42CB49C

#define mmDCORE1_MME_CTRL_LO_EU_ISOLATION_DIS 0x42CB4A0

#define mmDCORE1_MME_CTRL_LO_QM_SLV_CLK_EN 0x42CB4A4

#define mmDCORE1_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x42CB4A8

#define mmDCORE1_MME_CTRL_LO_AGU 0x42CB4AC

#define mmDCORE1_MME_CTRL_LO_QM 0x42CB4B0

#define mmDCORE1_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x42CB4B4

#define mmDCORE1_MME_CTRL_LO_INTR_CAUSE 0x42CB4B8

#define mmDCORE1_MME_CTRL_LO_INTR_MASK 0x42CB4BC

#define mmDCORE1_MME_CTRL_LO_INTR_CLEAR 0x42CB4C0

#define mmDCORE1_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x42CB4C4

#define mmDCORE1_MME_CTRL_LO_BIST 0x42CB4C8

#define mmDCORE1_MME_CTRL_LO_EU_RL_ENABLE 0x42CB4CC

#define mmDCORE1_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x42CB4D0

#define mmDCORE1_MME_CTRL_LO_EU_RL_CFG 0x42CB4D4

#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW0 0x42CB4D8

#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW1 0x42CB4DC

#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW2 0x42CB4E0

#define mmDCORE1_MME_CTRL_LO_PCU_DBG_DW3 0x42CB4E4

#define mmDCORE1_MME_CTRL_LO_PCU_DBG_WKL_ID 0x42CB4E8

#define mmDCORE1_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x42CB4EC

#endif /* ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_ */