/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ #define ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ /* ***************************************** * PDMA0_CORE_SPECIAL * (Prototype: SPECIAL_REGS) ***************************************** */ /* PDMA0_CORE_SPECIAL_GLBL_PRIV */ #define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_SHIFT 0 #define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_MASK 0xFFFFFFFF /* PDMA0_CORE_SPECIAL_MEM_GW_DATA */ #define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_MASK 0xFFFFFFFF /* PDMA0_CORE_SPECIAL_MEM_GW_REQ */ #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_MASK 0x3FFFFF #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_SHIFT 22 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_MASK 0x3FC00000 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_SHIFT 30 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_MASK 0x40000000 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_SHIFT 31 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_MASK 0x80000000 /* PDMA0_CORE_SPECIAL_MEM_NUMOF */ #define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_MASK 0xFF /* PDMA0_CORE_SPECIAL_MEM_ECC_SEL */ #define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_MASK 0xFF /* PDMA0_CORE_SPECIAL_MEM_ECC_CTL */ #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_MASK 0x1 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_SHIFT 1 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_MASK 0x2 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_SHIFT 2 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_MASK 0x4 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_SHIFT 3 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_MASK 0x8 /* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK */ #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_MASK 0x1 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_SHIFT 1 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_MASK 0x2 /* PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK */ #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_MASK 0x1 #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_SHIFT 1 #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_MASK 0x2 /* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS */ #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_MASK 0xFFFF #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_SHIFT 16 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_MASK 0x10000 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_SHIFT 17 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_MASK 0x20000 /* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR */ #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_MASK 0xFFFF /* PDMA0_CORE_SPECIAL_MEM_RM */ #define PDMA0_CORE_SPECIAL_MEM_RM_VAL_SHIFT 0 #define PDMA0_CORE_SPECIAL_MEM_RM_VAL_MASK 0x3FFFFFFF /* PDMA0_CORE_SPECIAL_GLBL_ERR_MASK */ #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_SHIFT 0 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_MASK 0x1 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_SHIFT 1 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_MASK 0x2 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_SHIFT 2 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_MASK 0x4 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_SHIFT 3 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_MASK 0x8 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_SHIFT 4 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_MASK 0x10 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_SHIFT 5 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_MASK 0x20 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_SHIFT 16 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_MASK 0x10000 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_SHIFT 17 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_MASK 0x20000 /* PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR */ #define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_SHIFT 0 #define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_MASK 0xFFFFFFFF /* PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE */ #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_SHIFT 0 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK 0x1 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_SHIFT 1 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK 0x2 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_SHIFT 2 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK 0x4 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_SHIFT 3 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK 0x8 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_SHIFT 4 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK 0x10 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_SHIFT 5 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK 0x20 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_SHIFT 16 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK 0x10000 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_SHIFT 17 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK 0x20000 /* PDMA0_CORE_SPECIAL_GLBL_SPARE */ #define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_SHIFT 0 #define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_MASK 0xFFFFFFFF /* PDMA0_CORE_SPECIAL_GLBL_SEC */ #define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_SHIFT 0 #define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_MASK 0xFFFFFFFF #endif /* ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ */