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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Audio SubSystem clock controller
maintainers:
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
All available clocks are defined as preprocessor macros in
include/dt-bindings/clock/exynos-audss-clk.h header.
properties:
compatible:
enum:
- samsung,exynos4210-audss-clock
- samsung,exynos5250-audss-clock
- samsung,exynos5410-audss-clock
- samsung,exynos5420-audss-clock
clocks:
minItems: 2
items:
- description:
Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
used if not specified.
- description:
Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
used if not specified.
- description:
Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
specified.
- description:
PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified.
- description:
External i2s clock, parent of mout_i2s. "cdclk0" is used if not
specified.
clock-names:
minItems: 2
items:
- const: pll_ref
- const: pll_in
- const: sclk_audio
- const: sclk_pcm_in
- const: cdclk
"#clock-cells":
const: 1
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- "#clock-cells"
- reg
additionalProperties: false
examples:
- |
clock-controller@3810000 {
compatible = "samsung,exynos5250-audss-clock";
reg = <0x03810000 0x0c>;
#clock-cells = <1>;
clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
};
|
