summaryrefslogtreecommitdiffstats
path: root/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json
blob: 6a6de8790f25fee3bfed7e05a42e3d097b7a27b9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
[
    {
        "BriefDescription": "Load misses in all DTLB levels that cause page walks",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
        "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "SampleAfterValue": "2000003",
        "UMask": "0x60"
    },
    {
        "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
        "SampleAfterValue": "2000003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
        "SampleAfterValue": "2000003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "100003",
        "UMask": "0xe"
    },
    {
        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
        "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles when PMH is busy with page walks",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
        "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Store misses in all DTLB levels that cause page walks",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
        "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
        "SampleAfterValue": "100003",
        "UMask": "0x60"
    },
    {
        "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
        "SampleAfterValue": "100003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "100003",
        "UMask": "0xe"
    },
    {
        "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
        "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles when PMH is busy with page walks",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
        "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycle count for an Extended Page table walk.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x4F",
        "EventName": "EPT.WALK_CYCLES",
        "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
        "SampleAfterValue": "2000003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xAE",
        "EventName": "ITLB.ITLB_FLUSH",
        "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Misses at all ITLB levels that cause page walks",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
        "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.STLB_HIT",
        "SampleAfterValue": "100003",
        "UMask": "0x60"
    },
    {
        "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.STLB_HIT_2M",
        "SampleAfterValue": "100003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K).",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.STLB_HIT_4K",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "100003",
        "UMask": "0xe"
    },
    {
        "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
        "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles when PMH is busy with page walks",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "Errata": "BDM69",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_DURATION",
        "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "Errata": "BDM69, BDM98",
        "EventCode": "0xBC",
        "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
        "SampleAfterValue": "2000003",
        "UMask": "0x11"
    },
    {
        "BriefDescription": "Number of DTLB page walker hits in the L2.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "Errata": "BDM69, BDM98",
        "EventCode": "0xBC",
        "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
        "SampleAfterValue": "2000003",
        "UMask": "0x12"
    },
    {
        "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "Errata": "BDM69, BDM98",
        "EventCode": "0xBC",
        "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
        "SampleAfterValue": "2000003",
        "UMask": "0x14"
    },
    {
        "BriefDescription": "Number of DTLB page walker hits in Memory.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "Errata": "BDM69, BDM98",
        "EventCode": "0xBC",
        "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
        "SampleAfterValue": "2000003",
        "UMask": "0x18"
    },
    {
        "BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "Errata": "BDM69, BDM98",
        "EventCode": "0xBC",
        "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
        "SampleAfterValue": "2000003",
        "UMask": "0x21"
    },
    {
        "BriefDescription": "Number of ITLB page walker hits in the L2.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "Errata": "BDM69, BDM98",
        "EventCode": "0xBC",
        "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
        "SampleAfterValue": "2000003",
        "UMask": "0x22"
    },
    {
        "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3",
        "Errata": "BDM69, BDM98",
        "EventCode": "0xBC",
        "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
        "SampleAfterValue": "2000003",
        "UMask": "0x24"
    },
    {
        "BriefDescription": "DTLB flush attempts of the thread-specific entries",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xBD",
        "EventName": "TLB_FLUSH.DTLB_THREAD",
        "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "STLB flush attempts",
        "Counter": "0,1,2,3",
        "CounterHTOff": "0,1,2,3,4,5,6,7",
        "EventCode": "0xBD",
        "EventName": "TLB_FLUSH.STLB_ANY",
        "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
        "SampleAfterValue": "100007",
        "UMask": "0x20"
    }
]