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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 14:30:35 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 14:30:35 +0000
commit378c18e5f024ac5a8aef4cb40d7c9aa9633d144c (patch)
tree44dfb6ca500d32cabd450649b322a42e70a30683 /tests/expected/lscpu/lscpu-s390-lpar-drawer
parentInitial commit. (diff)
downloadutil-linux-upstream.tar.xz
util-linux-upstream.zip
Adding upstream version 2.38.1.upstream/2.38.1upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
-rw-r--r--tests/expected/lscpu/lscpu-s390-lpar-drawer53
1 files changed, 53 insertions, 0 deletions
diff --git a/tests/expected/lscpu/lscpu-s390-lpar-drawer b/tests/expected/lscpu/lscpu-s390-lpar-drawer
new file mode 100644
index 0000000..467a76d
--- /dev/null
+++ b/tests/expected/lscpu/lscpu-s390-lpar-drawer
@@ -0,0 +1,53 @@
+CPU op-mode(s): 32-bit, 64-bit
+CPU(s): 8
+On-line CPU(s) list: 0-7
+Vendor ID: IBM/S390
+Model name: -
+Machine type: 2964
+Thread(s) per core: 1
+Core(s) per socket: 8
+Socket(s) per book: 3
+Book(s) per drawer: 2
+Drawer(s): 4
+CPU dynamic MHz: 5000
+CPU static MHz: 5000
+BogoMIPS: 20325.00
+Dispatching mode: horizontal
+Flags: esan3 zarch stfle msa ldisp eimm dfp edat etf3eh highgprs te vx sie
+Hypervisor: PR/SM
+Hypervisor vendor: IBM
+Virtualization type: full
+L1d cache: 1 MiB (8 instances)
+L1i cache: 768 KiB (8 instances)
+L2d cache: 16 MiB (8 instances)
+L2i cache: 16 MiB (8 instances)
+L3 cache: 64 MiB
+L4 cache: 480 MiB
+NUMA node(s): 1
+NUMA node0 CPU(s): 0-140
+
+# The following is the parsable format, which can be fed to other
+# programs. Each different item in every column has an unique ID
+# starting usually from zero.
+# CPU,Core,Socket,Node,,L1d,L1i,L2d,L2i
+0,0,0,0,,0,0,0,0
+1,1,0,0,,1,1,1,1
+2,2,1,0,,2,2,2,2
+3,3,1,0,,3,3,3,3
+4,4,1,0,,4,4,4,4
+5,5,1,0,,5,5,5,5
+6,6,1,0,,6,6,6,6
+7,7,1,0,,7,7,7,7
+
+# The following is the parsable format, which can be fed to other
+# programs. Each different item in every column has an unique ID
+# starting usually from zero.
+# CPU,Core,Socket,Node,,L1d,L1i,L2d,L2i
+0,0,2,0,,0,0,0,0
+1,1,2,0,,1,1,1,1
+2,2,3,0,,2,2,2,2
+3,3,3,0,,3,3,3,3
+4,4,3,0,,4,4,4,4
+5,5,3,0,,5,5,5,5
+6,6,3,0,,6,6,6,6
+7,7,3,0,,7,7,7,7