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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-06 01:02:30 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-06 01:02:30 +0000 |
| commit | 76cb841cb886eef6b3bee341a2266c76578724ad (patch) | |
| tree | f5892e5ba6cc11949952a6ce4ecbe6d516d6ce58 /arch/arm/boot/dts/r7s72100-rskrza1.dts | |
| parent | Initial commit. (diff) | |
| download | linux-76cb841cb886eef6b3bee341a2266c76578724ad.tar.xz linux-76cb841cb886eef6b3bee341a2266c76578724ad.zip | |
Adding upstream version 4.19.249.upstream/4.19.249
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm/boot/dts/r7s72100-rskrza1.dts')
| -rw-r--r-- | arch/arm/boot/dts/r7s72100-rskrza1.dts | 140 |
1 files changed, 140 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts new file mode 100644 index 000000000..8ee44a100 --- /dev/null +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/A1H RSK board + * + * Copyright (C) 2016 Renesas Electronics + */ + +/dts-v1/; +#include "r7s72100.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> + +/ { + model = "RSKRZA1"; + compatible = "renesas,rskrza1", "renesas,r7s72100"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@8000000 { + device_type = "memory"; + reg = <0x08000000 0x02000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led0 { + gpios = <&port7 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&extal_clk { + clock-frequency = <13330000>; +}; + +&usb_x1_clk { + clock-frequency = <48000000>; +}; + +&rtc_x1_clk { + clock-frequency = <32768>; +}; + +&pinctrl { + + /* Serial Console */ + scif2_pins: serial2 { + pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */ + <RZA1_PINMUX(3, 2, 4)>; /* RxD2 */ + }; + + /* Ethernet */ + ether_pins: ether { + /* Ethernet on Ports 1,2,3,5 */ + pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */ + <RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */ + <RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */ + <RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */ + <RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */ + <RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */ + <RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */ + <RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */ + <RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */ + <RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */ + <RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */ + <RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */ + <RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */ + <RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */ + <RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */ + <RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */ + <RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */ + <RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */ + }; + + /* SDHI ch1 on CN1 */ + sdhi1_pins: sdhi1 { + pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */ + <RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */ + <RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */ + <RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */ + <RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */ + <RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */ + <RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */ + <RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */ + }; +}; + +&mtu2 { + status = "okay"; +}; + +ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sdhi1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhi1_pins>; + bus-width = <4>; + status = "okay"; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + status = "okay"; +}; |