summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
blob: e9cb3ec5e50295ee1e047bf26eafb45861a002c3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
* Allwinner sunxi MMC controller

The highspeed MMC host controller on Allwinner SoCs provides an interface
for MMC, SD and SDIO types of memory cards.

Supported maximum speeds are the ones of the eMMC standard 4.5 as well
as the speed of SD standard 3.0.
Absolute maximum transfer rate is 200MB/s

Required properties:
 - compatible : should be one of:
   * "allwinner,sun4i-a10-mmc"
   * "allwinner,sun5i-a13-mmc"
   * "allwinner,sun7i-a20-mmc"
   * "allwinner,sun8i-a83t-emmc"
   * "allwinner,sun9i-a80-mmc"
   * "allwinner,sun50i-a64-emmc"
   * "allwinner,sun50i-a64-mmc"
   * "allwinner,sun50i-h6-emmc", "allwinner.sun50i-a64-emmc"
   * "allwinner,sun50i-h6-mmc", "allwinner.sun50i-a64-mmc"
 - reg : mmc controller base registers
 - clocks : a list with 4 phandle + clock specifier pairs
 - clock-names : must contain "ahb", "mmc", "output" and "sample"
 - interrupts : mmc controller interrupt

Optional properties:
 - resets : phandle + reset specifier pair
 - reset-names : must contain "ahb"
 - for cd, bus-width and additional generic mmc parameters
   please refer to mmc.txt within this directory

Examples:
	- Within .dtsi:
	mmc0: mmc@1c0f000 {
		compatible = "allwinner,sun5i-a13-mmc";
		reg = <0x01c0f000 0x1000>;
		clocks = <&ahb_gates 8>, <&mmc0_clk>, <&mmc0_output_clk>, <&mmc0_sample_clk>;
		clock-names = "ahb", "mod", "output", "sample";
		interrupts = <0 32 4>;
		status = "disabled";
	};

	- Within dts:
	mmc0: mmc@1c0f000 {
		pinctrl-names = "default", "default";
		pinctrl-0 = <&mmc0_pins_a>;
		pinctrl-1 = <&mmc0_cd_pin_reference_design>;
		bus-width = <4>;
		cd-gpios = <&pio 7 1 0>; /* PH1 */
		cd-inverted;
		status = "okay";
	};