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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-06 01:02:30 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-06 01:02:30 +0000 |
| commit | 76cb841cb886eef6b3bee341a2266c76578724ad (patch) | |
| tree | f5892e5ba6cc11949952a6ce4ecbe6d516d6ce58 /tools/perf/pmu-events/arch/x86/bonnell/frontend.json | |
| parent | Initial commit. (diff) | |
| download | linux-76cb841cb886eef6b3bee341a2266c76578724ad.tar.xz linux-76cb841cb886eef6b3bee341a2266c76578724ad.zip | |
Adding upstream version 4.19.249.upstream/4.19.249upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/bonnell/frontend.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/bonnell/frontend.json | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json new file mode 100644 index 000000000..935b7dcf0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json @@ -0,0 +1,83 @@ +[ + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200000", + "BriefDescription": "Instruction fetches." + }, + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "200000", + "BriefDescription": "Icache hit" + }, + { + "EventCode": "0x80", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200000", + "BriefDescription": "Icache miss" + }, + { + "EventCode": "0x86", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", + "SampleAfterValue": "2000000", + "BriefDescription": "Cycles during which instruction fetches are stalled." + }, + { + "EventCode": "0x87", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "DECODE_STALL.PFB_EMPTY", + "SampleAfterValue": "2000000", + "BriefDescription": "Decode stall due to PFB empty" + }, + { + "EventCode": "0x87", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "DECODE_STALL.IQ_FULL", + "SampleAfterValue": "2000000", + "BriefDescription": "Decode stall due to IQ full" + }, + { + "EventCode": "0xAA", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "MACRO_INSTS.NON_CISC_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "Non-CISC nacro instructions decoded" + }, + { + "EventCode": "0xAA", + "Counter": "0,1", + "UMask": "0x2", + "EventName": "MACRO_INSTS.CISC_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "CISC macro instructions decoded" + }, + { + "EventCode": "0xAA", + "Counter": "0,1", + "UMask": "0x3", + "EventName": "MACRO_INSTS.ALL_DECODED", + "SampleAfterValue": "2000000", + "BriefDescription": "All Instructions decoded" + }, + { + "EventCode": "0xA9", + "Counter": "0,1", + "UMask": "0x1", + "EventName": "UOPS.MS_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ", + "CounterMask": "1" + } +]
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