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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-06 01:02:30 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-06 01:02:30 +0000 |
| commit | 76cb841cb886eef6b3bee341a2266c76578724ad (patch) | |
| tree | f5892e5ba6cc11949952a6ce4ecbe6d516d6ce58 /tools/perf/pmu-events/arch/x86/haswellx/floating-point.json | |
| parent | Initial commit. (diff) | |
| download | linux-upstream.tar.xz linux-upstream.zip | |
Adding upstream version 4.19.249.upstream/4.19.249upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/haswellx/floating-point.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/haswellx/floating-point.json | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json new file mode 100644 index 000000000..bc08cc1f2 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json @@ -0,0 +1,83 @@ +[ + { + "EventCode": "0xC1", + "UMask": "0x8", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "Errata": "HSD56, HSM57", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "UMask": "0x10", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "Errata": "HSD56, HSM57", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC6", + "UMask": "0x7", + "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.", + "Counter": "0,1,2,3", + "EventName": "AVX_INSTS.ALL", + "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.", + "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x2", + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output values.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x4", + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "Number of X87 FP assists due to input values.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x8", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output values.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x10", + "BriefDescription": "Number of SIMD FP assists due to input values", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "Number of SIMD FP assists due to input values.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xCA", + "UMask": "0x1e", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "Counter": "0,1,2,3", + "EventName": "FP_ASSIST.ANY", + "CounterMask": "1", + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", + "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3" + } +]
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