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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-06 03:01:46 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-06 03:01:46 +0000 |
commit | f8fe689a81f906d1b91bb3220acde2a4ecb14c5b (patch) | |
tree | 26484e9d7e2c67806c2d1760196ff01aaa858e8c /src/VBox/Disassembler/testcase/tstAsmMovzx-1.asm | |
parent | Initial commit. (diff) | |
download | virtualbox-f8fe689a81f906d1b91bb3220acde2a4ecb14c5b.tar.xz virtualbox-f8fe689a81f906d1b91bb3220acde2a4ecb14c5b.zip |
Adding upstream version 6.0.4-dfsg.upstream/6.0.4-dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'src/VBox/Disassembler/testcase/tstAsmMovzx-1.asm')
-rw-r--r-- | src/VBox/Disassembler/testcase/tstAsmMovzx-1.asm | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/VBox/Disassembler/testcase/tstAsmMovzx-1.asm b/src/VBox/Disassembler/testcase/tstAsmMovzx-1.asm new file mode 100644 index 00000000..a48761e0 --- /dev/null +++ b/src/VBox/Disassembler/testcase/tstAsmMovzx-1.asm @@ -0,0 +1,39 @@ +; $Id: tstAsmMovzx-1.asm $ +;; @file +; Disassembly testcase - Valid movzx sequences and related instructions. +; +; This is a build test, that means it will be assembled, disassembled, +; then the disassembly output will be assembled and the new binary will +; compared with the original. +; + +; +; Copyright (C) 2008-2019 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + + BITS TEST_BITS + + movzx ax, al + movzx eax, al + movzx ax, [ebx] + movzx eax, byte [ebx] + movzx eax, word [ebx] +%if TEST_BITS != 64 + movzx ax, [bx+si+8] + movzx eax, byte [bx+si+8] + movzx eax, word [bx+si+8] +%else + movzx rax, al + movzx rax, ax + movzx rax, byte [rsi] + movzx rax, word [rsi] +%endif + |