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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-28 09:13:47 +0000 |
| commit | 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 (patch) | |
| tree | bcf648efac40ca6139842707f0eba5a4496a6dd2 /include/drivers/brcm | |
| parent | Initial commit. (diff) | |
| download | arm-trusted-firmware-102b0d2daa97dae68d3eed54d8fe37a9cc38a892.tar.xz arm-trusted-firmware-102b0d2daa97dae68d3eed54d8fe37a9cc38a892.zip | |
Adding upstream version 2.8.0+dfsg.upstream/2.8.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'include/drivers/brcm')
24 files changed, 8507 insertions, 0 deletions
diff --git a/include/drivers/brcm/chimp.h b/include/drivers/brcm/chimp.h new file mode 100644 index 0000000..02d528b --- /dev/null +++ b/include/drivers/brcm/chimp.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SR_CHIMP_H +#define SR_CHIMP_H + +#include <common/bl_common.h> +#include <common/debug.h> +#include <lib/mmio.h> + +#include <platform_def.h> + +#define CHIMP_WINDOW_SIZE 0x400000 +#define CHIMP_ERROR_OFFSET 28 +#define CHIMP_ERROR_MASK 0xf0000000 + +#ifndef EMULATION_SETUP +#define CHIMP_HANDSHAKE_TIMEOUT_MS 10000 +#else +/* + * 1hr timeout for test in emulator + * By doing this ChiMP is given a chance to boot + * fully from the QSPI + * (on Palladium this takes upto 50 min depending on QSPI clk) + */ + +#define CHIMP_HANDSHAKE_TIMEOUT_MS 3600000 +#endif + +#define CHIMP_BPE_MODE_ID_PATTERN (0x25000000) +#define CHIMP_BPE_MODE_ID_MASK (0x7f000000) +#define NIC_RESET_RELEASE_TIMEOUT_US (10) + +/* written by M0, used by ChiMP ROM */ +#define SR_IN_SMARTNIC_MODE_BIT 0 +/* written by M0, used by ChiMP ROM */ +#define SR_CHIMP_SECURE_BOOT_BIT 1 +/* cleared by AP, set by ChiMP BC2 code */ +#define SR_FLASH_ACCESS_DONE_BIT 2 + +#ifdef USE_CHIMP +void bcm_chimp_write(uintptr_t addr, uint32_t value); +uint32_t bcm_chimp_read(uintptr_t addr); +uint32_t bcm_chimp_read_ctrl(uint32_t offset); +void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits); +void bcm_chimp_setbits(uintptr_t addr, uint32_t bits); +int bcm_chimp_is_nic_mode(void); +void bcm_chimp_fru_prog_done(bool status); +int bcm_chimp_handshake_done(void); +int bcm_chimp_wait_handshake(void); +/* Fastboot-related*/ +int bcm_chimp_initiate_fastboot(int fastboot_type); +#else +static inline void bcm_chimp_write(uintptr_t addr, uint32_t value) +{ +} +static inline uint32_t bcm_chimp_read(uintptr_t addr) +{ + return 0; +} +static inline uint32_t bcm_chimp_read_ctrl(uint32_t offset) +{ + return 0; +} +static inline void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) +{ +} +static inline void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) +{ +} +static inline int bcm_chimp_is_nic_mode(void) +{ + return 0; +} +static inline void bcm_chimp_fru_prog_done(bool status) +{ +} +static inline int bcm_chimp_handshake_done(void) +{ + return 0; +} +static inline int bcm_chimp_wait_handshake(void) +{ + return 0; +} +static inline int bcm_chimp_initiate_fastboot(int fastboot_type) +{ + return 0; +} +#endif /* USE_CHIMP */ +#endif diff --git a/include/drivers/brcm/chimp_nv_defs.h b/include/drivers/brcm/chimp_nv_defs.h new file mode 100644 index 0000000..9be361f --- /dev/null +++ b/include/drivers/brcm/chimp_nv_defs.h @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BNXNVM_DEFS_H +#define BNXNVM_DEFS_H + +#if defined(__GNUC__) + #define PACKED_STRUCT __packed +#else /* non-GCC compiler */ + +#ifndef DOS_DRIVERS + #pragma pack(push) + #pragma pack(1) +#endif + #define PACKED_STRUCT +#endif + +typedef uint32_t u32_t; +typedef uint8_t u8_t; +typedef uint16_t u16_t; + +#define BNXNVM_DEFAULT_BLOCK_SIZE 4096 +#define BNXNVM_UNUSED_BYTE_VALUE 0xff + +#define NV_MAX_BLOCK_SIZE 16384 + +#define BITS_PER_BYTE (8) +#define SIZEOF_IN_BITS(x) (sizeof(x)*BITS_PER_BYTE) + +/************************/ +/* byte-swapping macros */ +/************************/ +#define BYTE_SWAP_16(x) \ + ((((u16_t)(x) & 0xff00) >> 8) | \ + (((u16_t)(x) & 0x00ff) << 8)) +#define BYTE_SWAP_32(x) \ + ((((u32_t)(x) & 0xff000000) >> 24) | \ + (((u32_t)(x) & 0x00ff0000) >> 8) | \ + (((u32_t)(x) & 0x0000ff00) << 8) | \ + (((u32_t)(x) & 0x000000ff) << 24)) + +/* auto-detect integer size */ +#define BYTE_SWAP_INT(x) \ + (SIZEOF_IN_BITS(x) == 16 ? BYTE_SWAP_16(x) : \ + SIZEOF_IN_BITS(x) == 32 ? BYTE_SWAP_32(x) : (x)) + +/********************************/ +/* Architecture-specific macros */ +/********************************/ +#ifdef __BIG_ENDIAN__ /* e.g. Motorola */ + + #define BE_INT16(x) (x) + #define BE_INT32(x) (x) + #define BE_INT(x) (x) + #define LE_INT16(x) BYTE_SWAP_16(x) + #define LE_INT32(x) BYTE_SWAP_32(x) + #define LE_INT(x) BYTE_SWAP_INT(x) + +#else /* Little Endian (e.g. Intel) */ + + #define LE_INT16(x) (x) + #define LE_INT32(x) (x) + #define LE_INT(x) (x) + #define BE_INT16(x) BYTE_SWAP_16(x) + #define BE_INT32(x) BYTE_SWAP_32(x) + #define BE_INT(x) BYTE_SWAP_INT(x) + +#endif + + +enum { + NV_OK = 0, + NV_NOT_NVRAM, + NV_BAD_MB, + NV_BAD_DIR_HEADER, + NV_BAD_DIR_ENTRY, + NV_FW_NOT_FOUND, +}; + +typedef struct { +#define BNXNVM_MASTER_BLOCK_SIG BE_INT32(0x424E5834) /*"BNX4"*/ + /* Signature*/ + u32_t sig; + /* Length of Master Block Header, in bytes [32] */ + u32_t length; + /* Block size, in bytes [4096] */ + u32_t block_size; + /* Byte-offset to Directory Block (translated) */ + u32_t directory_offset; + /* Byte-offset to Block Redirection Table (non-translated) */ + u32_t redirect_offset; + /* Size, in bytes of Reserved Blocks region (at end of NVRAM) */ + u32_t reserved_size; + /* + * Size of NVRAM (in bytes) - may be used to + * override auto-detected size + */ + u32_t nvram_size; + /* CRC-32 (IEEE 802.3 compatible) of the above */ + u32_t chksum; +} PACKED_STRUCT bnxnvm_master_block_header_t; + +typedef struct { +#define BNXNVM_DIRECTORY_BLOCK_SIG BE_INT32(0x44697230) /* "Dir0" */ + /* Signature */ + u32_t sig; + /* Length of Directory Header, in bytes [16] */ + u32_t length; + /* Number of Directory Entries */ + u32_t entries; + /* Length of each Directory Entry, in bytes [24] */ + u32_t entry_length; +} PACKED_STRUCT bnxnvm_directory_block_header_t; + +typedef struct { + /* Directory Entry Type (see enum bnxnvm_directory_type) */ + u16_t type; + /* Instance of this Directory Entry type (0-based) */ + u16_t ordinal; + /* + * Directory Entry Extension flags used to identify + * secondary instances of a type:ordinal combinations + */ + u16_t ext; + /* Directory Entry Attribute flags used to describe the item contents */ + u16_t attr; + /* Item location in NVRAM specified as offset (in bytes) */ + u32_t item_location; + /* + * Length of NVRAM item in bytes + * (including padding - multiple of block size) + */ + u32_t item_length; + /* Length of item data in bytes (excluding padding) */ + u32_t data_length; + /* + * CRC-32 (IEEE 802.3 compatible) of item data + * (excluding padding) (optional) + */ + u32_t data_chksum; +} PACKED_STRUCT bnxnvm_directory_entry_t; + +enum bnxnvm_version_format { + /* US-ASCII string (not necessarily null-terminated) */ + BNX_VERSION_FMT_ASCII = 0, + /* Each field 16-bits, displayed as unpadded decimal (e.g. "1.2.3.4") */ + BNX_VERSION_FMT_DEC = 1, + /* A single hexadecimal value, up to 64-bits (no dots) */ + BNX_VERSION_FMT_HEX = 2, + /* Multiple version values (three 8-bit version fields) */ + BNX_VERSION_FMT_MULTI = 3 +}; + +/* This structure definition must not change: */ +typedef struct { + u16_t flags; /* bit-flags (defaults to 0x0000) */ + u8_t version_format; /* enum bnxnvm_version_format */ + u8_t version_length; /* in bytes */ + u8_t version[16]; /* version value */ + u16_t dir_type; /* enum bnxnvm_directory_type */ + /* size of the entire trailer (to locate end of component data) */ + u16_t trailer_length; +#define BNXNVM_COMPONENT_TRAILER_SIG BE_INT32(0x54726c72) /* "Trlr" */ + u32_t sig; + u32_t chksum; /* CRC-32 of all bytes to this point */ +} PACKED_STRUCT bnxnvm_component_trailer_base_t; + +typedef struct { + /* + * new trailer members (e.g. digital signature) + * go here (insert at top): + */ + u8_t rsa_sig[256]; /* 2048-bit RSA-encrypted SHA-256 hash */ + bnxnvm_component_trailer_base_t base; +} PACKED_STRUCT bnxnvm_component_trailer_t; + +#define BNX_MAX_LEN_DIR_NAME 12 +#define BNX_MAX_LEN_DIR_DESC 50 +/********************************************************* + * NVRAM Directory Entry/Item Types, Names, and Descriptions + * + * If you see a name or description that needs improvement, + * please correct it or raise for discussion. + * When adding a new directory type, it would be appreciated + * if you also updated ../../libs/nvm/bnxt_nvm_str.c. + * DIR_NAME macros may contain up to 12 alpha-numeric + * US-ASCII characters only, camelCase is preferred for clarity. + * DIR_DESC macros may contain up to 50 US-ASCII characters + * providing a verbose description of the directory type. + */ +enum bnxnvm_directory_type { + /* 0x00 Unused directory entry, available for use */ + BNX_DIR_TYPE_UNUSED = 0, +#define BNX_DIR_NAME_UNUSED "unused" +#define BNX_DIR_DESC_UNUSED "Deleted directory entry, available for reuse" + /* 0x01 Package installation log */ + BNX_DIR_TYPE_PKG_LOG = 1, +#define BNX_DIR_NAME_PKG_LOG "pkgLog" +#define BNX_DIR_DESC_PKG_LOG "Package Installation Log" + BNX_DIR_TYPE_CHIMP_PATCH = 3, +#define BNX_DIR_NAME_CHIMP_PATCH "chimpPatch" +#define BNX_DIR_DESC_CHIMP_PATCH "ChiMP Patch Firmware" + /* 0x04 ChiMP firmware: Boot Code phase 1 */ + BNX_DIR_TYPE_BOOTCODE = 4, +#define BNX_DIR_NAME_BOOTCODE "chimpBoot" +#define BNX_DIR_DESC_BOOTCODE "Chip Management Processor Boot Firmware" + /* 0x05 VPD data block */ + BNX_DIR_TYPE_VPD = 5, +#define BNX_DIR_NAME_VPD "VPD" +#define BNX_DIR_DESC_VPD "Vital Product Data" + /* 0x06 Exp ROM MBA */ + BNX_DIR_TYPE_EXP_ROM_MBA = 6, +#define BNX_DIR_NAME_EXP_ROM_MBA "MBA" +#define BNX_DIR_DESC_EXP_ROM_MBA "Multiple Boot Agent Expansion ROM" + BNX_DIR_TYPE_AVS = 7, /* 0x07 AVS FW */ +#define BNX_DIR_NAME_AVS "AVS" +#define BNX_DIR_DESC_AVS "Adaptive Voltage Scaling Firmware" + BNX_DIR_TYPE_PCIE = 8, /* 0x08 PCIE FW */ +#define BNX_DIR_NAME_PCIE "PCIEucode" +#define BNX_DIR_DESC_PCIE "PCIe Microcode" + BNX_DIR_TYPE_PORT_MACRO = 9, /* 0x09 PORT MACRO FW */ +#define BNX_DIR_NAME_PORT_MACRO "portMacro" +#define BNX_DIR_DESC_PORT_MACRO "Port Macro Firmware" + BNX_DIR_TYPE_APE_FW = 10, /* 0x0A APE Firmware */ +#define BNX_DIR_NAME_APE_FW "apeFW" +#define BNX_DIR_DESC_APE_FW "Application Processing Engine Firmware" + /* 0x0B Patch firmware executed by APE ROM */ + BNX_DIR_TYPE_APE_PATCH = 11, +#define BNX_DIR_NAME_APE_PATCH "apePatch" +#define BNX_DIR_DESC_APE_PATCH "APE Patch Firmware" + BNX_DIR_TYPE_KONG_FW = 12, /* 0x0C Kong Firmware */ +#define BNX_DIR_NAME_KONG_FW "kongFW" +#define BNX_DIR_DESC_KONG_FW "Kong Firmware" + /* 0x0D Patch firmware executed by Kong ROM */ + BNX_DIR_TYPE_KONG_PATCH = 13, +#define BNX_DIR_NAME_KONG_PATCH "kongPatch" +#define BNX_DIR_DESC_KONG_PATCH "Kong Patch Firmware" + BNX_DIR_TYPE_BONO_FW = 14, /* 0x0E Bono Firmware */ +#define BNX_DIR_NAME_BONO_FW "bonoFW" +#define BNX_DIR_DESC_BONO_FW "Bono Firmware" + /* 0x0F Patch firmware executed by Bono ROM */ + BNX_DIR_TYPE_BONO_PATCH = 15, +#define BNX_DIR_NAME_BONO_PATCH "bonoPatch" +#define BNX_DIR_DESC_BONO_PATCH "Bono Patch Firmware" + BNX_DIR_TYPE_TANG_FW = 16, /* 0x10 Tang firmware */ +#define BNX_DIR_NAME_TANG_FW "tangFW" +#define BNX_DIR_DESC_TANG_FW "Tang Firmware" + /* 0x11 Patch firmware executed by Tang ROM */ + BNX_DIR_TYPE_TANG_PATCH = 17, +#define BNX_DIR_NAME_TANG_PATCH "tangPatch" +#define BNX_DIR_DESC_TANG_PATCH "Tang Patch Firmware" + /* 0x12 ChiMP firmware: Boot Code phase 2 (loaded by phase 1) */ + BNX_DIR_TYPE_BOOTCODE_2 = 18, +#define BNX_DIR_NAME_BOOTCODE_2 "chimpHWRM" +#define BNX_DIR_DESC_BOOTCODE_2 "ChiMP Hardware Resource Manager Firmware" + BNX_DIR_TYPE_CCM = 19, /* 0x13 CCM ROM binary */ +#define BNX_DIR_NAME_CCM "CCM" +#define BNX_DIR_DESC_CCM "Comprehensive Configuration Management" + /* 0x14 PCI-IDs, PCI-related configuration properties */ + BNX_DIR_TYPE_PCI_CFG = 20, +#define BNX_DIR_NAME_PCI_CFG "pciCFG" +#define BNX_DIR_DESC_PCI_CFG "PCIe Configuration Data" + + BNX_DIR_TYPE_TSCF_UCODE = 21, /* 0x15 TSCF micro-code */ +#define BNX_DIR_NAME_TSCF_UCODE "PHYucode" +#define BNX_DIR_DESC_TSCF_UCODE "Falcon PHY Microcode" + BNX_DIR_TYPE_ISCSI_BOOT = 22, /* 0x16 iSCSI Boot */ +#define BNX_DIR_NAME_ISCSI_BOOT "iSCSIboot" +#define BNX_DIR_DESC_ISCSI_BOOT "iSCSI Boot Software Initiator" + /* 0x18 iSCSI Boot IPV6 - ***DEPRECATED*** */ + BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, + /* 0x19 iSCSI Boot IPV4N6 - ***DEPRECATED*** */ + BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, + BNX_DIR_TYPE_ISCSI_BOOT_CFG = 26, /* 0x1a iSCSI Boot CFG v6 */ +#define BNX_DIR_NAME_ISCSI_BOOT_CFG "iSCSIcfg" +#define BNX_DIR_DESC_ISCSI_BOOT_CFG "iSCSI Boot Configuration Data" + BNX_DIR_TYPE_EXT_PHY = 27, /* 0x1b External PHY FW */ +#define BNX_DIR_NAME_EXT_PHY "extPHYfw" +#define BNX_DIR_DESC_EXT_PHY "External PHY Firmware" + BNX_DIR_TYPE_MODULES_PN = 28, /* 0x1c Modules PartNum list */ +#define BNX_DIR_NAME_MODULES_PN "modPartNums" +#define BNX_DIR_DESC_MODULES_PN "Optical Modules Part Number List" + BNX_DIR_TYPE_SHARED_CFG = 40, /* 0x28 shared configuration block */ +#define BNX_DIR_NAME_SHARED_CFG "sharedCFG" +#define BNX_DIR_DESC_SHARED_CFG "Shared Configuration Data" + BNX_DIR_TYPE_PORT_CFG = 41, /* 0x29 port configuration block */ +#define BNX_DIR_NAME_PORT_CFG "portCFG" +#define BNX_DIR_DESC_PORT_CFG "Port Configuration Data" + BNX_DIR_TYPE_FUNC_CFG = 42, /* 0x2A func configuration block */ +#define BNX_DIR_NAME_FUNC_CFG "funcCFG" +#define BNX_DIR_DESC_FUNC_CFG "Function Configuration Data" + + /* Management Firmware (TruManage) related dir entries*/ + /* 0x30 Management firmware configuration (see BMCFG library)*/ + BNX_DIR_TYPE_MGMT_CFG = 48, +#define BNX_DIR_NAME_MGMT_CFG "mgmtCFG" +#define BNX_DIR_DESC_MGMT_CFG "Out-of-band Management Configuration Data" + BNX_DIR_TYPE_MGMT_DATA = 49, /* 0x31 "Opaque Management Data" */ +#define BNX_DIR_NAME_MGMT_DATA "mgmtData" +#define BNX_DIR_DESC_MGMT_DATA "Out-of-band Management Data" + BNX_DIR_TYPE_MGMT_WEB_DATA = 50, /* 0x32 "Web GUI" file data */ +#define BNX_DIR_NAME_MGMT_WEB_DATA "webData" +#define BNX_DIR_DESC_MGMT_WEB_DATA "Out-of-band Management Web Data" + /* 0x33 "Web GUI" file metadata */ + BNX_DIR_TYPE_MGMT_WEB_META = 51, +#define BNX_DIR_NAME_MGMT_WEB_META "webMeta" +#define BNX_DIR_DESC_MGMT_WEB_META "Out-of-band Management Web Metadata" + /* 0x34 Management firmware Event Log (a.k.a. "SEL") */ + BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, +#define BNX_DIR_NAME_MGMT_EVENT_LOG "eventLog" +#define BNX_DIR_DESC_MGMT_EVENT_LOG "Out-of-band Management Event Log" + /* 0x35 Management firmware Audit Log */ + BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 +#define BNX_DIR_NAME_MGMT_AUDIT_LOG "auditLog" +#define BNX_DIR_DESC_MGMT_AUDIT_LOG "Out-of-band Management Audit Log" + +}; + +/* For backwards compatibility only, may be removed later */ +#define BNX_DIR_TYPE_ISCSI_BOOT_CFG6 BNX_DIR_TYPE_ISCSI_BOOT_CFG + +/* Firmware NVM items of "APE BIN" format are identified with + * the following macro: + */ +#define BNX_DIR_TYPE_IS_APE_BIN_FMT(type)\ + ((type) == BNX_DIR_TYPE_CHIMP_PATCH \ + || (type) == BNX_DIR_TYPE_BOOTCODE \ + || (type) == BNX_DIR_TYPE_BOOTCODE_2 \ + || (type) == BNX_DIR_TYPE_APE_FW \ + || (type) == BNX_DIR_TYPE_APE_PATCH \ + || (type) == BNX_DIR_TYPE_TANG_FW \ + || (type) == BNX_DIR_TYPE_TANG_PATCH \ + || (type) == BNX_DIR_TYPE_KONG_FW \ + || (type) == BNX_DIR_TYPE_KONG_PATCH \ + || (type) == BNX_DIR_TYPE_BONO_FW \ + || (type) == BNX_DIR_TYPE_BONO_PATCH \ + ) + +/* Other (non APE BIN) executable NVM items are identified with + * the following macro: + */ +#define BNX_DIR_TYPE_IS_OTHER_EXEC(type)\ + ((type) == BNX_DIR_TYPE_AVS \ + || (type) == BNX_DIR_TYPE_EXP_ROM_MBA \ + || (type) == BNX_DIR_TYPE_PCIE \ + || (type) == BNX_DIR_TYPE_TSCF_UCODE \ + || (type) == BNX_DIR_TYPE_EXT_PHY \ + || (type) == BNX_DIR_TYPE_CCM \ + || (type) == BNX_DIR_TYPE_ISCSI_BOOT \ + ) + +/* Executable NVM items (e.g. microcode, firmware, software) identified + * with the following macro + */ +#define BNX_DIR_TYPE_IS_EXECUTABLE(type) \ + (BNX_DIR_TYPE_IS_APE_BIN_FMT(type) \ + || BNX_DIR_TYPE_IS_OTHER_EXEC(type)) + +#define BNX_DIR_ORDINAL_FIRST 0 /* Ordinals are 0-based */ + +/* No extension flags for this directory entry */ +#define BNX_DIR_EXT_NONE 0 +/* Directory entry is inactive (not used, not hidden, + * not available for reuse) + */ +#define BNX_DIR_EXT_INACTIVE (1 << 0) +/* Directory content is a temporary staging location for + * updating the primary (non-update) directory entry contents + * (e.g. performing a secure firmware update) + */ +#define BNX_DIR_EXT_UPDATE (1 << 1) + +/* No attribute flags set for this directory entry */ +#define BNX_DIR_ATTR_NONE 0 +/* Directory entry checksum of contents is purposely incorrect */ +#define BNX_DIR_ATTR_NO_CHKSUM (1 << 0) +/* Directory contents are in the form of a property-stream + * (e.g. configuration properties) + */ +#define BNX_DIR_ATTR_PROP_STREAM (1 << 1) +/* Directory content (e.g. iSCSI boot) supports IPv4 */ +#define BNX_DIR_ATTR_IPv4 (1 << 2) +/* Directory content (e.g. iSCSI boot) supports IPv6 */ +#define BNX_DIR_ATTR_IPv6 (1 << 3) +/* Directory content includes standard NVM component trailer + * (bnxnvm_component_trailer_t) + */ +#define BNX_DIR_ATTR_TRAILER (1 << 4) + +/* Index of tab-delimited fields in each package log + * (BNX_DIR_TYPE_PKG_LOG) record (\n-terminated line): + */ +enum bnxnvm_pkglog_field_index { + /* Package installation date/time in ISO-8601 format */ + BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, + /* Installed package description (from package header) or "N/A" */ + BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, + /* Installed package version string (from package header) or "N/A" */ + BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, + /* Installed package creation/modification timestamp (ISO-8601) */ + BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, + /* Installed package checksum in hexadecimal (CRC-32) or "N/A" */ + BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, + /* Total number of packaged items applied in this installation */ + BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, + /* Hexadecimal bit-mask identifying which items were installed */ + BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 +}; + +#if !defined(__GNUC__) +#ifndef DOS_DRIVERS + #pragma pack(pop) /* original packing */ +#endif +#endif + +#endif /* Don't add anything after this line */ diff --git a/include/drivers/brcm/dmu.h b/include/drivers/brcm/dmu.h new file mode 100644 index 0000000..3a57bbd --- /dev/null +++ b/include/drivers/brcm/dmu.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DMU_H +#define DMU_H + +/* Clock field should be 2 bits only */ +#define CLKCONFIG_MASK 0x3 + +/* argument */ +struct DmuBlockEnable { + uint32_t sotp:1; + uint32_t pka_rng:1; + uint32_t crypto:1; + uint32_t spl:1; + uint32_t cdru_vgm:1; + uint32_t apbs_s0_idm:1; + uint32_t smau_s0_idm:1; +}; + +/* prototype */ +uint32_t bcm_dmu_block_enable(struct DmuBlockEnable dbe); +uint32_t bcm_dmu_block_disable(struct DmuBlockEnable dbe); +uint32_t bcm_set_ihost_pll_freq(uint32_t cluster_num, int ihost_pll_freq_sel); +uint32_t bcm_get_ihost_pll_freq(uint32_t cluster_num); + +#define PLL_FREQ_BYPASS 0x0 +#define PLL_FREQ_FULL 0x1 +#define PLL_FREQ_HALF 0x2 +#define PLL_FREQ_QRTR 0x3 + +#endif diff --git a/include/drivers/brcm/emmc/bcm_emmc.h b/include/drivers/brcm/emmc/bcm_emmc.h new file mode 100644 index 0000000..67f0602 --- /dev/null +++ b/include/drivers/brcm/emmc/bcm_emmc.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMMC_H +#define EMMC_H + +#include <stdint.h> + +#include <common/debug.h> + +#include <platform_def.h> + +#include "emmc_chal_types.h" +#include "emmc_chal_sd.h" +#include "emmc_csl_sdprot.h" +#include "emmc_csl_sdcmd.h" +#include "emmc_pboot_hal_memory_drv.h" + +/* ------------------------------------------------------------------- */ +#define EXT_CSD_SIZE 512 + +#ifdef PLAT_SD_MAX_READ_LENGTH +#define SD_MAX_READ_LENGTH PLAT_SD_MAX_READ_LENGTH +#ifdef USE_EMMC_LARGE_BLK_TRANSFER_LENGTH +#define SD_MAX_BLK_TRANSFER_LENGTH 0x10000000 +#else +#define SD_MAX_BLK_TRANSFER_LENGTH 0x1000 +#endif +#else +#define SD_MAX_READ_LENGTH EMMC_BLOCK_SIZE +#define SD_MAX_BLK_TRANSFER_LENGTH EMMC_BLOCK_SIZE +#endif + +struct emmc_global_buffer { + union { + uint8_t Ext_CSD_storage[EXT_CSD_SIZE]; + uint8_t tempbuf[SD_MAX_READ_LENGTH]; + } u; +}; + +struct emmc_global_vars { + struct sd_card_data cardData; + struct sd_handle sdHandle; + struct sd_dev sdDevice; + struct sd_card_info sdCard; + unsigned int init_done; +}; + +#define ICFG_SDIO0_CAP0__SLOT_TYPE_R 27 +#define ICFG_SDIO0_CAP0__INT_MODE_R 26 +#define ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R 25 +#define ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R 24 +#define ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R 23 +#define ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R 22 +#define ICFG_SDIO0_CAP0__SUSPEND_RESUME_R 21 +#define ICFG_SDIO0_CAP0__SDMA_R 20 +#define ICFG_SDIO0_CAP0__HIGH_SPEED_R 19 +#define ICFG_SDIO0_CAP0__ADMA2_R 18 +#define ICFG_SDIO0_CAP0__EXTENDED_MEDIA_R 17 +#define ICFG_SDIO0_CAP0__MAX_BLOCK_LEN_R 15 +#define ICFG_SDIO0_CAP0__BASE_CLK_FREQ_R 7 +#define ICFG_SDIO0_CAP0__TIMEOUT_UNIT_R 6 +#define ICFG_SDIO0_CAP0__TIMEOUT_CLK_FREQ_R 0 +#define ICFG_SDIO0_CAP1__SPI_BLOCK_MODE_R 22 +#define ICFG_SDIO0_CAP1__SPI_MODE_R 21 +#define ICFG_SDIO0_CAP1__CLK_MULT_R 13 +#define ICFG_SDIO0_CAP1__RETUNING_MODE_R 11 +#define ICFG_SDIO0_CAP1__TUNE_SDR50_R 10 +#define ICFG_SDIO0_CAP1__TIME_RETUNE_R 6 +#define ICFG_SDIO0_CAP1__DRIVER_D_R 5 +#define ICFG_SDIO0_CAP1__DRIVER_C_R 4 +#define ICFG_SDIO0_CAP1__DRIVER_A_R 3 +#define ICFG_SDIO0_CAP1__DDR50_R 2 +#define ICFG_SDIO0_CAP1__SDR104_R 1 +#define ICFG_SDIO0_CAP1__SDR50_R 0 + +#define SDIO0_CTRL_REGS_BASE_ADDR (SDIO0_EMMCSDXC_SYSADDR) +#define SDIO0_IDM_RESET_CTRL_ADDR (SDIO_IDM0_IDM_RESET_CONTROL) + +#define EMMC_CTRL_REGS_BASE_ADDR SDIO0_CTRL_REGS_BASE_ADDR +#define EMMC_IDM_RESET_CTRL_ADDR SDIO0_IDM_RESET_CTRL_ADDR +#define EMMC_IDM_IO_CTRL_DIRECT_ADDR SDIO_IDM0_IO_CONTROL_DIRECT + +extern struct emmc_global_buffer *emmc_global_buf_ptr; + +extern struct emmc_global_vars *emmc_global_vars_ptr; + +#define EMMC_CARD_DETECT_TIMEOUT_MS 1200 +#define EMMC_CMD_TIMEOUT_MS 200 +#define EMMC_BUSY_CMD_TIMEOUT_MS 200 +#define EMMC_CLOCK_SETTING_TIMEOUT_MS 100 +#define EMMC_WFE_RETRY 40000 +#define EMMC_WFE_RETRY_DELAY_US 10 + +#ifdef EMMC_DEBUG +#define EMMC_TRACE INFO +#else +#define EMMC_TRACE(...) +#endif + +#endif /* EMMC_H */ diff --git a/include/drivers/brcm/emmc/emmc_api.h b/include/drivers/brcm/emmc/emmc_api.h new file mode 100644 index 0000000..c4c2a58 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_api.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMMC_API_H +#define EMMC_API_H + +#include "bcm_emmc.h" +#include "emmc_pboot_hal_memory_drv.h" + +#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE +/* + * The erasable unit of the eMMC is the Erase Group + * Erase group is measured in write blocks which + * are the basic writable units of the Device + * EMMC_ERASE_GROUP_SIZE is the number of writeable + * units (each unit is 512 bytes) + */ + +/* Start address (sector) */ +#define EMMC_ERASE_START_BLOCK 0x0 +/* Number of blocks to be erased */ +#define EMMC_ERASE_BLOCK_COUNT 0x1 + +#define EMMC_ERASE_USER_AREA 0 +#define EMMC_ERASE_BOOT_PARTITION1 1 +#define EMMC_ERASE_BOOT_PARTITION2 2 + +/* eMMC partition to be erased */ +#define EMMC_ERASE_PARTITION EMMC_ERASE_USER_AREA +#endif + +uint32_t bcm_emmc_init(bool card_rdy_only); +void emmc_deinit(void); + +#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE +int emmc_erase(uintptr_t mem_addr, size_t num_of_blocks, uint32_t partition); +#endif + +uint32_t emmc_partition_select(uint32_t partition); +uint32_t emmc_read(uintptr_t mem_addr, uintptr_t storage_addr, + size_t storage_size, size_t bytes_to_read); +uint32_t emmc_write(uintptr_t mem_addr, uintptr_t data_addr, + size_t bytes_to_write); +#endif /* EMMC_API_H */ diff --git a/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h b/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h new file mode 100644 index 0000000..96c333d --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h @@ -0,0 +1,1116 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BRCM_RDB_SD4_EMMC_TOP_H +#define BRCM_RDB_SD4_EMMC_TOP_H + +#define SD4_EMMC_TOP_SYSADDR_OFFSET 0x00000000 +#define SD4_EMMC_TOP_SYSADDR_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_SYSADDR_TYPE uint32_t +#define SD4_EMMC_TOP_SYSADDR_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_SYSADDR_SYSADDR_SHIFT 0 +#define SD4_EMMC_TOP_SYSADDR_SYSADDR_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_BLOCK_OFFSET 0x00000004 +#define SD4_EMMC_TOP_BLOCK_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_BLOCK_TYPE uint32_t +#define SD4_EMMC_TOP_BLOCK_RESERVED_MASK 0x00008000 +#define SD4_EMMC_TOP_BLOCK_BCNT_SHIFT 16 +#define SD4_EMMC_TOP_BLOCK_BCNT_MASK 0xFFFF0000 +#define SD4_EMMC_TOP_BLOCK_HSBS_SHIFT 12 +#define SD4_EMMC_TOP_BLOCK_HSBS_MASK 0x00007000 +#define SD4_EMMC_TOP_BLOCK_TBS_SHIFT 0 +#define SD4_EMMC_TOP_BLOCK_TBS_MASK 0x00000FFF + +#define SD4_EMMC_TOP_ARG_OFFSET 0x00000008 +#define SD4_EMMC_TOP_ARG_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ARG_TYPE uint32_t +#define SD4_EMMC_TOP_ARG_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_ARG_ARG_SHIFT 0 +#define SD4_EMMC_TOP_ARG_ARG_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_CMD_OFFSET 0x0000000C +#define SD4_EMMC_TOP_CMD_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CMD_TYPE uint32_t +#define SD4_EMMC_TOP_CMD_RESERVED_MASK 0xC004FFC0 +#define SD4_EMMC_TOP_CMD_CIDX_SHIFT 24 +#define SD4_EMMC_TOP_CMD_CIDX_MASK 0x3F000000 +#define SD4_EMMC_TOP_CMD_CTYP_SHIFT 22 +#define SD4_EMMC_TOP_CMD_CTYP_MASK 0x00C00000 +#define SD4_EMMC_TOP_CMD_DPS_SHIFT 21 +#define SD4_EMMC_TOP_CMD_DPS_MASK 0x00200000 +#define SD4_EMMC_TOP_CMD_CCHK_EN_SHIFT 20 +#define SD4_EMMC_TOP_CMD_CCHK_EN_MASK 0x00100000 +#define SD4_EMMC_TOP_CMD_CRC_EN_SHIFT 19 +#define SD4_EMMC_TOP_CMD_CRC_EN_MASK 0x00080000 +#define SD4_EMMC_TOP_CMD_RTSEL_SHIFT 16 +#define SD4_EMMC_TOP_CMD_RTSEL_MASK 0x00030000 +#define SD4_EMMC_TOP_CMD_MSBS_SHIFT 5 +#define SD4_EMMC_TOP_CMD_MSBS_MASK 0x00000020 +#define SD4_EMMC_TOP_CMD_DTDS_SHIFT 4 +#define SD4_EMMC_TOP_CMD_DTDS_MASK 0x00000010 +#define SD4_EMMC_TOP_CMD_ACMDEN_SHIFT 2 +#define SD4_EMMC_TOP_CMD_ACMDEN_MASK 0x0000000C +#define SD4_EMMC_TOP_CMD_BCEN_SHIFT 1 +#define SD4_EMMC_TOP_CMD_BCEN_MASK 0x00000002 +#define SD4_EMMC_TOP_CMD_DMA_SHIFT 0 +#define SD4_EMMC_TOP_CMD_DMA_MASK 0x00000001 + +#define SD4_EMMC_TOP_CMD_SD4_OFFSET 0x0000000C +#define SD4_EMMC_TOP_CMD_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CMD_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CMD_SD4_RESERVED_MASK 0xC004FE00 +#define SD4_EMMC_TOP_CMD_SD4_CIDX_SHIFT 24 +#define SD4_EMMC_TOP_CMD_SD4_CIDX_MASK 0x3F000000 +#define SD4_EMMC_TOP_CMD_SD4_CTYP_SHIFT 22 +#define SD4_EMMC_TOP_CMD_SD4_CTYP_MASK 0x00C00000 +#define SD4_EMMC_TOP_CMD_SD4_DPS_SHIFT 21 +#define SD4_EMMC_TOP_CMD_SD4_DPS_MASK 0x00200000 +#define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_SHIFT 20 +#define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_MASK 0x00100000 +#define SD4_EMMC_TOP_CMD_SD4_CRC_EN_SHIFT 19 +#define SD4_EMMC_TOP_CMD_SD4_CRC_EN_MASK 0x00080000 +#define SD4_EMMC_TOP_CMD_SD4_RTSEL_SHIFT 16 +#define SD4_EMMC_TOP_CMD_SD4_RTSEL_MASK 0x00030000 +#define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_SHIFT 8 +#define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_MASK 0x00000100 +#define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_SHIFT 7 +#define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_MASK 0x00000080 +#define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_SHIFT 6 +#define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_MASK 0x00000040 +#define SD4_EMMC_TOP_CMD_SD4_MSBS_SHIFT 5 +#define SD4_EMMC_TOP_CMD_SD4_MSBS_MASK 0x00000020 +#define SD4_EMMC_TOP_CMD_SD4_DTDS_SHIFT 4 +#define SD4_EMMC_TOP_CMD_SD4_DTDS_MASK 0x00000010 +#define SD4_EMMC_TOP_CMD_SD4_ACMDEN_SHIFT 2 +#define SD4_EMMC_TOP_CMD_SD4_ACMDEN_MASK 0x0000000C +#define SD4_EMMC_TOP_CMD_SD4_BCEN_SHIFT 1 +#define SD4_EMMC_TOP_CMD_SD4_BCEN_MASK 0x00000002 +#define SD4_EMMC_TOP_CMD_SD4_DMA_SHIFT 0 +#define SD4_EMMC_TOP_CMD_SD4_DMA_MASK 0x00000001 + +#define SD4_EMMC_TOP_RESP0_OFFSET 0x00000010 +#define SD4_EMMC_TOP_RESP0_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_RESP0_TYPE uint32_t +#define SD4_EMMC_TOP_RESP0_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_RESP0_RESP0_SHIFT 0 +#define SD4_EMMC_TOP_RESP0_RESP0_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_RESP2_OFFSET 0x00000014 +#define SD4_EMMC_TOP_RESP2_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_RESP2_TYPE uint32_t +#define SD4_EMMC_TOP_RESP2_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_RESP2_RESP2_SHIFT 0 +#define SD4_EMMC_TOP_RESP2_RESP2_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_RESP4_OFFSET 0x00000018 +#define SD4_EMMC_TOP_RESP4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_RESP4_TYPE uint32_t +#define SD4_EMMC_TOP_RESP4_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_RESP4_RESP4_SHIFT 0 +#define SD4_EMMC_TOP_RESP4_RESP4_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_RESP6_OFFSET 0x0000001C +#define SD4_EMMC_TOP_RESP6_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_RESP6_TYPE uint32_t +#define SD4_EMMC_TOP_RESP6_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_RESP6_RESP6_SHIFT 0 +#define SD4_EMMC_TOP_RESP6_RESP6_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_BUFDAT_OFFSET 0x00000020 +#define SD4_EMMC_TOP_BUFDAT_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_BUFDAT_TYPE uint32_t +#define SD4_EMMC_TOP_BUFDAT_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_BUFDAT_BUFDAT_SHIFT 0 +#define SD4_EMMC_TOP_BUFDAT_BUFDAT_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_PSTATE_OFFSET 0x00000024 +#define SD4_EMMC_TOP_PSTATE_DEFAULT 0x1FFC0000 +#define SD4_EMMC_TOP_PSTATE_TYPE uint32_t +#define SD4_EMMC_TOP_PSTATE_RESERVED_MASK 0xE000F0F0 +#define SD4_EMMC_TOP_PSTATE_DLS7_4_SHIFT 25 +#define SD4_EMMC_TOP_PSTATE_DLS7_4_MASK 0x1E000000 +#define SD4_EMMC_TOP_PSTATE_CLSL_SHIFT 24 +#define SD4_EMMC_TOP_PSTATE_CLSL_MASK 0x01000000 +#define SD4_EMMC_TOP_PSTATE_DLS3_0_SHIFT 20 +#define SD4_EMMC_TOP_PSTATE_DLS3_0_MASK 0x00F00000 +#define SD4_EMMC_TOP_PSTATE_WPSL_SHIFT 19 +#define SD4_EMMC_TOP_PSTATE_WPSL_MASK 0x00080000 +#define SD4_EMMC_TOP_PSTATE_CDPL_SHIFT 18 +#define SD4_EMMC_TOP_PSTATE_CDPL_MASK 0x00040000 +#define SD4_EMMC_TOP_PSTATE_CSS_SHIFT 17 +#define SD4_EMMC_TOP_PSTATE_CSS_MASK 0x00020000 +#define SD4_EMMC_TOP_PSTATE_CINS_SHIFT 16 +#define SD4_EMMC_TOP_PSTATE_CINS_MASK 0x00010000 +#define SD4_EMMC_TOP_PSTATE_BREN_SHIFT 11 +#define SD4_EMMC_TOP_PSTATE_BREN_MASK 0x00000800 +#define SD4_EMMC_TOP_PSTATE_BWEN_SHIFT 10 +#define SD4_EMMC_TOP_PSTATE_BWEN_MASK 0x00000400 +#define SD4_EMMC_TOP_PSTATE_RXACT_SHIFT 9 +#define SD4_EMMC_TOP_PSTATE_RXACT_MASK 0x00000200 +#define SD4_EMMC_TOP_PSTATE_WXACT_SHIFT 8 +#define SD4_EMMC_TOP_PSTATE_WXACT_MASK 0x00000100 +#define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_SHIFT 3 +#define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_MASK 0x00000008 +#define SD4_EMMC_TOP_PSTATE_DATACT_SHIFT 2 +#define SD4_EMMC_TOP_PSTATE_DATACT_MASK 0x00000004 +#define SD4_EMMC_TOP_PSTATE_DATINH_SHIFT 1 +#define SD4_EMMC_TOP_PSTATE_DATINH_MASK 0x00000002 +#define SD4_EMMC_TOP_PSTATE_CMDINH_SHIFT 0 +#define SD4_EMMC_TOP_PSTATE_CMDINH_MASK 0x00000001 + +#define SD4_EMMC_TOP_PSTATE_SD4_OFFSET 0x00000024 +#define SD4_EMMC_TOP_PSTATE_SD4_DEFAULT 0x01FC00F0 +#define SD4_EMMC_TOP_PSTATE_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_PSTATE_SD4_RESERVED_MASK 0x1E00F000 +#define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_SHIFT 31 +#define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_MASK 0x80000000 +#define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_SHIFT 30 +#define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_MASK 0x40000000 +#define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_SHIFT 29 +#define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_MASK 0x20000000 +#define SD4_EMMC_TOP_PSTATE_SD4_CLSL_SHIFT 24 +#define SD4_EMMC_TOP_PSTATE_SD4_CLSL_MASK 0x01000000 +#define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_SHIFT 20 +#define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_MASK 0x00F00000 +#define SD4_EMMC_TOP_PSTATE_SD4_WPSL_SHIFT 19 +#define SD4_EMMC_TOP_PSTATE_SD4_WPSL_MASK 0x00080000 +#define SD4_EMMC_TOP_PSTATE_SD4_CDPL_SHIFT 18 +#define SD4_EMMC_TOP_PSTATE_SD4_CDPL_MASK 0x00040000 +#define SD4_EMMC_TOP_PSTATE_SD4_CSS_SHIFT 17 +#define SD4_EMMC_TOP_PSTATE_SD4_CSS_MASK 0x00020000 +#define SD4_EMMC_TOP_PSTATE_SD4_CINS_SHIFT 16 +#define SD4_EMMC_TOP_PSTATE_SD4_CINS_MASK 0x00010000 +#define SD4_EMMC_TOP_PSTATE_SD4_BREN_SHIFT 11 +#define SD4_EMMC_TOP_PSTATE_SD4_BREN_MASK 0x00000800 +#define SD4_EMMC_TOP_PSTATE_SD4_BWEN_SHIFT 10 +#define SD4_EMMC_TOP_PSTATE_SD4_BWEN_MASK 0x00000400 +#define SD4_EMMC_TOP_PSTATE_SD4_RXACT_SHIFT 9 +#define SD4_EMMC_TOP_PSTATE_SD4_RXACT_MASK 0x00000200 +#define SD4_EMMC_TOP_PSTATE_SD4_WXACT_SHIFT 8 +#define SD4_EMMC_TOP_PSTATE_SD4_WXACT_MASK 0x00000100 +#define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_SHIFT 4 +#define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_MASK 0x000000F0 +#define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_SHIFT 3 +#define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_MASK 0x00000008 +#define SD4_EMMC_TOP_PSTATE_SD4_DATACT_SHIFT 2 +#define SD4_EMMC_TOP_PSTATE_SD4_DATACT_MASK 0x00000004 +#define SD4_EMMC_TOP_PSTATE_SD4_DATINH_SHIFT 1 +#define SD4_EMMC_TOP_PSTATE_SD4_DATINH_MASK 0x00000002 +#define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_SHIFT 0 +#define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_MASK 0x00000001 + +#define SD4_EMMC_TOP_CTRL_OFFSET 0x00000028 +#define SD4_EMMC_TOP_CTRL_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CTRL_TYPE uint32_t +#define SD4_EMMC_TOP_CTRL_RESERVED_MASK 0xF800E000 +#define SD4_EMMC_TOP_CTRL_WAKENRMV_SHIFT 26 +#define SD4_EMMC_TOP_CTRL_WAKENRMV_MASK 0x04000000 +#define SD4_EMMC_TOP_CTRL_WAKENINS_SHIFT 25 +#define SD4_EMMC_TOP_CTRL_WAKENINS_MASK 0x02000000 +#define SD4_EMMC_TOP_CTRL_WAKENIRQ_SHIFT 24 +#define SD4_EMMC_TOP_CTRL_WAKENIRQ_MASK 0x01000000 +#define SD4_EMMC_TOP_CTRL_BOOTACK_SHIFT 23 +#define SD4_EMMC_TOP_CTRL_BOOTACK_MASK 0x00800000 +#define SD4_EMMC_TOP_CTRL_ATLBOOTEN_SHIFT 22 +#define SD4_EMMC_TOP_CTRL_ATLBOOTEN_MASK 0x00400000 +#define SD4_EMMC_TOP_CTRL_BOOTEN_SHIFT 21 +#define SD4_EMMC_TOP_CTRL_BOOTEN_MASK 0x00200000 +#define SD4_EMMC_TOP_CTRL_SPIMODE_SHIFT 20 +#define SD4_EMMC_TOP_CTRL_SPIMODE_MASK 0x00100000 +#define SD4_EMMC_TOP_CTRL_BLKIRQ_SHIFT 19 +#define SD4_EMMC_TOP_CTRL_BLKIRQ_MASK 0x00080000 +#define SD4_EMMC_TOP_CTRL_RDWTCRTL_SHIFT 18 +#define SD4_EMMC_TOP_CTRL_RDWTCRTL_MASK 0x00040000 +#define SD4_EMMC_TOP_CTRL_CONTREQ_SHIFT 17 +#define SD4_EMMC_TOP_CTRL_CONTREQ_MASK 0x00020000 +#define SD4_EMMC_TOP_CTRL_BLKSTPREQ_SHIFT 16 +#define SD4_EMMC_TOP_CTRL_BLKSTPREQ_MASK 0x00010000 +#define SD4_EMMC_TOP_CTRL_HRESET_SHIFT 12 +#define SD4_EMMC_TOP_CTRL_HRESET_MASK 0x00001000 +#define SD4_EMMC_TOP_CTRL_SDVSELVDD1_SHIFT 9 +#define SD4_EMMC_TOP_CTRL_SDVSELVDD1_MASK 0x00000E00 +#define SD4_EMMC_TOP_CTRL_SDPWR_SHIFT 8 +#define SD4_EMMC_TOP_CTRL_SDPWR_MASK 0x00000100 +#define SD4_EMMC_TOP_CTRL_CDSD_SHIFT 7 +#define SD4_EMMC_TOP_CTRL_CDSD_MASK 0x00000080 +#define SD4_EMMC_TOP_CTRL_CDTL_SHIFT 6 +#define SD4_EMMC_TOP_CTRL_CDTL_MASK 0x00000040 +#define SD4_EMMC_TOP_CTRL_SDB_SHIFT 5 +#define SD4_EMMC_TOP_CTRL_SDB_MASK 0x00000020 +#define SD4_EMMC_TOP_CTRL_DMASEL_SHIFT 3 +#define SD4_EMMC_TOP_CTRL_DMASEL_MASK 0x00000018 +#define SD4_EMMC_TOP_CTRL_HSEN_SHIFT 2 +#define SD4_EMMC_TOP_CTRL_HSEN_MASK 0x00000004 +#define SD4_EMMC_TOP_CTRL_DXTW_SHIFT 1 +#define SD4_EMMC_TOP_CTRL_DXTW_MASK 0x00000002 +#define SD4_EMMC_TOP_CTRL_LEDCTL_SHIFT 0 +#define SD4_EMMC_TOP_CTRL_LEDCTL_MASK 0x00000001 + +#define SD4_EMMC_TOP_CTRL_SD4_OFFSET 0x00000028 +#define SD4_EMMC_TOP_CTRL_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CTRL_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CTRL_SD4_RESERVED_MASK 0xF8F00000 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_SHIFT 26 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_MASK 0x04000000 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_SHIFT 25 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_MASK 0x02000000 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_SHIFT 24 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_MASK 0x01000000 +#define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_SHIFT 19 +#define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_MASK 0x00080000 +#define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_SHIFT 18 +#define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_MASK 0x00040000 +#define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_SHIFT 17 +#define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_MASK 0x00020000 +#define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_SHIFT 16 +#define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_MASK 0x00010000 +#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_SHIFT 13 +#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_MASK 0x0000E000 +#define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_SHIFT 12 +#define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_MASK 0x00001000 +#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_SHIFT 9 +#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_MASK 0x00000E00 +#define SD4_EMMC_TOP_CTRL_SD4_SDPWR_SHIFT 8 +#define SD4_EMMC_TOP_CTRL_SD4_SDPWR_MASK 0x00000100 +#define SD4_EMMC_TOP_CTRL_SD4_CDSD_SHIFT 7 +#define SD4_EMMC_TOP_CTRL_SD4_CDSD_MASK 0x00000080 +#define SD4_EMMC_TOP_CTRL_SD4_CDTL_SHIFT 6 +#define SD4_EMMC_TOP_CTRL_SD4_CDTL_MASK 0x00000040 +#define SD4_EMMC_TOP_CTRL_SD4_SDB_SHIFT 5 +#define SD4_EMMC_TOP_CTRL_SD4_SDB_MASK 0x00000020 +#define SD4_EMMC_TOP_CTRL_SD4_DMASEL_SHIFT 3 +#define SD4_EMMC_TOP_CTRL_SD4_DMASEL_MASK 0x00000018 +#define SD4_EMMC_TOP_CTRL_SD4_HSEN_SHIFT 2 +#define SD4_EMMC_TOP_CTRL_SD4_HSEN_MASK 0x00000004 +#define SD4_EMMC_TOP_CTRL_SD4_DXTW_SHIFT 1 +#define SD4_EMMC_TOP_CTRL_SD4_DXTW_MASK 0x00000002 +#define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_SHIFT 0 +#define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_MASK 0x00000001 + +#define SD4_EMMC_TOP_CTRL1_OFFSET 0x0000002C +#define SD4_EMMC_TOP_CTRL1_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CTRL1_TYPE uint32_t +#define SD4_EMMC_TOP_CTRL1_RESERVED_MASK 0xF8F00018 +#define SD4_EMMC_TOP_CTRL1_DATRST_SHIFT 26 +#define SD4_EMMC_TOP_CTRL1_DATRST_MASK 0x04000000 +#define SD4_EMMC_TOP_CTRL1_CMDRST_SHIFT 25 +#define SD4_EMMC_TOP_CTRL1_CMDRST_MASK 0x02000000 +#define SD4_EMMC_TOP_CTRL1_RST_SHIFT 24 +#define SD4_EMMC_TOP_CTRL1_RST_MASK 0x01000000 +#define SD4_EMMC_TOP_CTRL1_DTCNT_SHIFT 16 +#define SD4_EMMC_TOP_CTRL1_DTCNT_MASK 0x000F0000 +#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_SHIFT 8 +#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_MASK 0x0000FF00 +#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_SHIFT 6 +#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_MASK 0x000000C0 +#define SD4_EMMC_TOP_CTRL1_CLKGENSEL_SHIFT 5 +#define SD4_EMMC_TOP_CTRL1_CLKGENSEL_MASK 0x00000020 +#define SD4_EMMC_TOP_CTRL1_SDCLKEN_SHIFT 2 +#define SD4_EMMC_TOP_CTRL1_SDCLKEN_MASK 0x00000004 +#define SD4_EMMC_TOP_CTRL1_ICLKSTB_SHIFT 1 +#define SD4_EMMC_TOP_CTRL1_ICLKSTB_MASK 0x00000002 +#define SD4_EMMC_TOP_CTRL1_ICLKEN_SHIFT 0 +#define SD4_EMMC_TOP_CTRL1_ICLKEN_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTR_OFFSET 0x00000030 +#define SD4_EMMC_TOP_INTR_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTR_TYPE uint32_t +#define SD4_EMMC_TOP_INTR_RESERVED_MASK 0xEC000000 +#define SD4_EMMC_TOP_INTR_TRESPERR_SHIFT 28 +#define SD4_EMMC_TOP_INTR_TRESPERR_MASK 0x10000000 +#define SD4_EMMC_TOP_INTR_ADMAERR_SHIFT 25 +#define SD4_EMMC_TOP_INTR_ADMAERR_MASK 0x02000000 +#define SD4_EMMC_TOP_INTR_CMDERROR_SHIFT 24 +#define SD4_EMMC_TOP_INTR_CMDERROR_MASK 0x01000000 +#define SD4_EMMC_TOP_INTR_IERR_SHIFT 23 +#define SD4_EMMC_TOP_INTR_IERR_MASK 0x00800000 +#define SD4_EMMC_TOP_INTR_DEBERR_SHIFT 22 +#define SD4_EMMC_TOP_INTR_DEBERR_MASK 0x00400000 +#define SD4_EMMC_TOP_INTR_DCRCERR_SHIFT 21 +#define SD4_EMMC_TOP_INTR_DCRCERR_MASK 0x00200000 +#define SD4_EMMC_TOP_INTR_DTOERR_SHIFT 20 +#define SD4_EMMC_TOP_INTR_DTOERR_MASK 0x00100000 +#define SD4_EMMC_TOP_INTR_CMDIDXERR_SHIFT 19 +#define SD4_EMMC_TOP_INTR_CMDIDXERR_MASK 0x00080000 +#define SD4_EMMC_TOP_INTR_CEBERR_SHIFT 18 +#define SD4_EMMC_TOP_INTR_CEBERR_MASK 0x00040000 +#define SD4_EMMC_TOP_INTR_CCRCERR_SHIFT 17 +#define SD4_EMMC_TOP_INTR_CCRCERR_MASK 0x00020000 +#define SD4_EMMC_TOP_INTR_CTOERR_SHIFT 16 +#define SD4_EMMC_TOP_INTR_CTOERR_MASK 0x00010000 +#define SD4_EMMC_TOP_INTR_ERRIRQ_SHIFT 15 +#define SD4_EMMC_TOP_INTR_ERRIRQ_MASK 0x00008000 +#define SD4_EMMC_TOP_INTR_BTIRQ_SHIFT 14 +#define SD4_EMMC_TOP_INTR_BTIRQ_MASK 0x00004000 +#define SD4_EMMC_TOP_INTR_BTACKRX_SHIFT 13 +#define SD4_EMMC_TOP_INTR_BTACKRX_MASK 0x00002000 +#define SD4_EMMC_TOP_INTR_RETUNE_EVENT_SHIFT 12 +#define SD4_EMMC_TOP_INTR_RETUNE_EVENT_MASK 0x00001000 +#define SD4_EMMC_TOP_INTR_INT_C_SHIFT 11 +#define SD4_EMMC_TOP_INTR_INT_C_MASK 0x00000800 +#define SD4_EMMC_TOP_INTR_INT_B_SHIFT 10 +#define SD4_EMMC_TOP_INTR_INT_B_MASK 0x00000400 +#define SD4_EMMC_TOP_INTR_INT_A_SHIFT 9 +#define SD4_EMMC_TOP_INTR_INT_A_MASK 0x00000200 +#define SD4_EMMC_TOP_INTR_CRDIRQ_SHIFT 8 +#define SD4_EMMC_TOP_INTR_CRDIRQ_MASK 0x00000100 +#define SD4_EMMC_TOP_INTR_CRDRMV_SHIFT 7 +#define SD4_EMMC_TOP_INTR_CRDRMV_MASK 0x00000080 +#define SD4_EMMC_TOP_INTR_CRDINS_SHIFT 6 +#define SD4_EMMC_TOP_INTR_CRDINS_MASK 0x00000040 +#define SD4_EMMC_TOP_INTR_BRRDY_SHIFT 5 +#define SD4_EMMC_TOP_INTR_BRRDY_MASK 0x00000020 +#define SD4_EMMC_TOP_INTR_BWRDY_SHIFT 4 +#define SD4_EMMC_TOP_INTR_BWRDY_MASK 0x00000010 +#define SD4_EMMC_TOP_INTR_DMAIRQ_SHIFT 3 +#define SD4_EMMC_TOP_INTR_DMAIRQ_MASK 0x00000008 +#define SD4_EMMC_TOP_INTR_BLKENT_SHIFT 2 +#define SD4_EMMC_TOP_INTR_BLKENT_MASK 0x00000004 +#define SD4_EMMC_TOP_INTR_TXDONE_SHIFT 1 +#define SD4_EMMC_TOP_INTR_TXDONE_MASK 0x00000002 +#define SD4_EMMC_TOP_INTR_CMDDONE_SHIFT 0 +#define SD4_EMMC_TOP_INTR_CMDDONE_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTR_SD4_OFFSET 0x00000030 +#define SD4_EMMC_TOP_INTR_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTR_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_INTR_SD4_RESERVED_MASK 0xF0006000 +#define SD4_EMMC_TOP_INTR_SD4_TRESPERR_SHIFT 27 +#define SD4_EMMC_TOP_INTR_SD4_TRESPERR_MASK 0x08000000 +#define SD4_EMMC_TOP_INTR_SD4_TUNEERR_SHIFT 26 +#define SD4_EMMC_TOP_INTR_SD4_TUNEERR_MASK 0x04000000 +#define SD4_EMMC_TOP_INTR_SD4_ADMAERR_SHIFT 25 +#define SD4_EMMC_TOP_INTR_SD4_ADMAERR_MASK 0x02000000 +#define SD4_EMMC_TOP_INTR_SD4_CMDERROR_SHIFT 24 +#define SD4_EMMC_TOP_INTR_SD4_CMDERROR_MASK 0x01000000 +#define SD4_EMMC_TOP_INTR_SD4_IERR_SHIFT 23 +#define SD4_EMMC_TOP_INTR_SD4_IERR_MASK 0x00800000 +#define SD4_EMMC_TOP_INTR_SD4_DEBERR_SHIFT 22 +#define SD4_EMMC_TOP_INTR_SD4_DEBERR_MASK 0x00400000 +#define SD4_EMMC_TOP_INTR_SD4_DCRCERR_SHIFT 21 +#define SD4_EMMC_TOP_INTR_SD4_DCRCERR_MASK 0x00200000 +#define SD4_EMMC_TOP_INTR_SD4_DTOERR_SHIFT 20 +#define SD4_EMMC_TOP_INTR_SD4_DTOERR_MASK 0x00100000 +#define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_SHIFT 19 +#define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_MASK 0x00080000 +#define SD4_EMMC_TOP_INTR_SD4_CEBERR_SHIFT 18 +#define SD4_EMMC_TOP_INTR_SD4_CEBERR_MASK 0x00040000 +#define SD4_EMMC_TOP_INTR_SD4_CCRCERR_SHIFT 17 +#define SD4_EMMC_TOP_INTR_SD4_CCRCERR_MASK 0x00020000 +#define SD4_EMMC_TOP_INTR_SD4_CTOERR_SHIFT 16 +#define SD4_EMMC_TOP_INTR_SD4_CTOERR_MASK 0x00010000 +#define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_SHIFT 15 +#define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_MASK 0x00008000 +#define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_SHIFT 12 +#define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_MASK 0x00001000 +#define SD4_EMMC_TOP_INTR_SD4_INT_C_SHIFT 11 +#define SD4_EMMC_TOP_INTR_SD4_INT_C_MASK 0x00000800 +#define SD4_EMMC_TOP_INTR_SD4_INT_B_SHIFT 10 +#define SD4_EMMC_TOP_INTR_SD4_INT_B_MASK 0x00000400 +#define SD4_EMMC_TOP_INTR_SD4_INT_A_SHIFT 9 +#define SD4_EMMC_TOP_INTR_SD4_INT_A_MASK 0x00000200 +#define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_SHIFT 8 +#define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_MASK 0x00000100 +#define SD4_EMMC_TOP_INTR_SD4_CRDRMV_SHIFT 7 +#define SD4_EMMC_TOP_INTR_SD4_CRDRMV_MASK 0x00000080 +#define SD4_EMMC_TOP_INTR_SD4_CRDINS_SHIFT 6 +#define SD4_EMMC_TOP_INTR_SD4_CRDINS_MASK 0x00000040 +#define SD4_EMMC_TOP_INTR_SD4_BRRDY_SHIFT 5 +#define SD4_EMMC_TOP_INTR_SD4_BRRDY_MASK 0x00000020 +#define SD4_EMMC_TOP_INTR_SD4_BWRDY_SHIFT 4 +#define SD4_EMMC_TOP_INTR_SD4_BWRDY_MASK 0x00000010 +#define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_SHIFT 3 +#define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_MASK 0x00000008 +#define SD4_EMMC_TOP_INTR_SD4_BLKENT_SHIFT 2 +#define SD4_EMMC_TOP_INTR_SD4_BLKENT_MASK 0x00000004 +#define SD4_EMMC_TOP_INTR_SD4_TXDONE_SHIFT 1 +#define SD4_EMMC_TOP_INTR_SD4_TXDONE_MASK 0x00000002 +#define SD4_EMMC_TOP_INTR_SD4_CMDDONE_SHIFT 0 +#define SD4_EMMC_TOP_INTR_SD4_CMDDONE_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTREN1_OFFSET 0x00000034 +#define SD4_EMMC_TOP_INTREN1_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTREN1_TYPE uint32_t +#define SD4_EMMC_TOP_INTREN1_RESERVED_MASK 0xEC000000 +#define SD4_EMMC_TOP_INTREN1_TRESPERREN_SHIFT 28 +#define SD4_EMMC_TOP_INTREN1_TRESPERREN_MASK 0x10000000 +#define SD4_EMMC_TOP_INTREN1_ADMAEREN_SHIFT 25 +#define SD4_EMMC_TOP_INTREN1_ADMAEREN_MASK 0x02000000 +#define SD4_EMMC_TOP_INTREN1_CMDERREN_SHIFT 24 +#define SD4_EMMC_TOP_INTREN1_CMDERREN_MASK 0x01000000 +#define SD4_EMMC_TOP_INTREN1_ILIMERREN_SHIFT 23 +#define SD4_EMMC_TOP_INTREN1_ILIMERREN_MASK 0x00800000 +#define SD4_EMMC_TOP_INTREN1_DEBERREN_SHIFT 22 +#define SD4_EMMC_TOP_INTREN1_DEBERREN_MASK 0x00400000 +#define SD4_EMMC_TOP_INTREN1_DCRCERREN_SHIFT 21 +#define SD4_EMMC_TOP_INTREN1_DCRCERREN_MASK 0x00200000 +#define SD4_EMMC_TOP_INTREN1_DTOERREN_SHIFT 20 +#define SD4_EMMC_TOP_INTREN1_DTOERREN_MASK 0x00100000 +#define SD4_EMMC_TOP_INTREN1_CIDXERREN_SHIFT 19 +#define SD4_EMMC_TOP_INTREN1_CIDXERREN_MASK 0x00080000 +#define SD4_EMMC_TOP_INTREN1_CEBERREN_SHIFT 18 +#define SD4_EMMC_TOP_INTREN1_CEBERREN_MASK 0x00040000 +#define SD4_EMMC_TOP_INTREN1_CMDCRCEN_SHIFT 17 +#define SD4_EMMC_TOP_INTREN1_CMDCRCEN_MASK 0x00020000 +#define SD4_EMMC_TOP_INTREN1_CMDTOEN_SHIFT 16 +#define SD4_EMMC_TOP_INTREN1_CMDTOEN_MASK 0x00010000 +#define SD4_EMMC_TOP_INTREN1_FIXZ_SHIFT 15 +#define SD4_EMMC_TOP_INTREN1_FIXZ_MASK 0x00008000 +#define SD4_EMMC_TOP_INTREN1_BTIRQEN_SHIFT 14 +#define SD4_EMMC_TOP_INTREN1_BTIRQEN_MASK 0x00004000 +#define SD4_EMMC_TOP_INTREN1_BTACKRXEN_SHIFT 13 +#define SD4_EMMC_TOP_INTREN1_BTACKRXEN_MASK 0x00002000 +#define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_SHIFT 12 +#define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_MASK 0x00001000 +#define SD4_EMMC_TOP_INTREN1_INT_C_EN_SHIFT 11 +#define SD4_EMMC_TOP_INTREN1_INT_C_EN_MASK 0x00000800 +#define SD4_EMMC_TOP_INTREN1_INT_B_EN_SHIFT 10 +#define SD4_EMMC_TOP_INTREN1_INT_B_EN_MASK 0x00000400 +#define SD4_EMMC_TOP_INTREN1_INT_A_EN_SHIFT 9 +#define SD4_EMMC_TOP_INTREN1_INT_A_EN_MASK 0x00000200 +#define SD4_EMMC_TOP_INTREN1_CIRQEN_SHIFT 8 +#define SD4_EMMC_TOP_INTREN1_CIRQEN_MASK 0x00000100 +#define SD4_EMMC_TOP_INTREN1_CRDRMVEN_SHIFT 7 +#define SD4_EMMC_TOP_INTREN1_CRDRMVEN_MASK 0x00000080 +#define SD4_EMMC_TOP_INTREN1_CRDINSEN_SHIFT 6 +#define SD4_EMMC_TOP_INTREN1_CRDINSEN_MASK 0x00000040 +#define SD4_EMMC_TOP_INTREN1_BUFRREN_SHIFT 5 +#define SD4_EMMC_TOP_INTREN1_BUFRREN_MASK 0x00000020 +#define SD4_EMMC_TOP_INTREN1_BUFWREN_SHIFT 4 +#define SD4_EMMC_TOP_INTREN1_BUFWREN_MASK 0x00000010 +#define SD4_EMMC_TOP_INTREN1_DMAIRQEN_SHIFT 3 +#define SD4_EMMC_TOP_INTREN1_DMAIRQEN_MASK 0x00000008 +#define SD4_EMMC_TOP_INTREN1_BLKEN_SHIFT 2 +#define SD4_EMMC_TOP_INTREN1_BLKEN_MASK 0x00000004 +#define SD4_EMMC_TOP_INTREN1_TXDONEEN_SHIFT 1 +#define SD4_EMMC_TOP_INTREN1_TXDONEEN_MASK 0x00000002 +#define SD4_EMMC_TOP_INTREN1_CMDDONEEN_SHIFT 0 +#define SD4_EMMC_TOP_INTREN1_CMDDONEEN_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTREN1_SD4_OFFSET 0x00000034 +#define SD4_EMMC_TOP_INTREN1_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTREN1_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_INTREN1_SD4_RESERVED_MASK 0x00006000 +#define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_SHIFT 28 +#define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_MASK 0xF0000000 +#define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_SHIFT 27 +#define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_MASK 0x08000000 +#define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_SHIFT 26 +#define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_MASK 0x04000000 +#define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_SHIFT 25 +#define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_MASK 0x02000000 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_SHIFT 24 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_MASK 0x01000000 +#define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_SHIFT 23 +#define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_MASK 0x00800000 +#define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_SHIFT 22 +#define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_MASK 0x00400000 +#define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_SHIFT 21 +#define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_MASK 0x00200000 +#define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_SHIFT 20 +#define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_MASK 0x00100000 +#define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_SHIFT 19 +#define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_MASK 0x00080000 +#define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_SHIFT 18 +#define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_MASK 0x00040000 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_SHIFT 17 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_MASK 0x00020000 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_SHIFT 16 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_MASK 0x00010000 +#define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_SHIFT 15 +#define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_MASK 0x00008000 +#define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_SHIFT 12 +#define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_MASK 0x00001000 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_SHIFT 11 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_MASK 0x00000800 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_SHIFT 10 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_MASK 0x00000400 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_SHIFT 9 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_MASK 0x00000200 +#define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_SHIFT 8 +#define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_MASK 0x00000100 +#define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_SHIFT 7 +#define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_MASK 0x00000080 +#define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_SHIFT 6 +#define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_MASK 0x00000040 +#define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_SHIFT 5 +#define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_MASK 0x00000020 +#define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_SHIFT 4 +#define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_MASK 0x00000010 +#define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_SHIFT 3 +#define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_MASK 0x00000008 +#define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_SHIFT 2 +#define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_MASK 0x00000004 +#define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_SHIFT 1 +#define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_MASK 0x00000002 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_SHIFT 0 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTREN2_OFFSET 0x00000038 +#define SD4_EMMC_TOP_INTREN2_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTREN2_TYPE uint32_t +#define SD4_EMMC_TOP_INTREN2_RESERVED_MASK 0xEC000000 +#define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_SHIFT 28 +#define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_MASK 0x10000000 +#define SD4_EMMC_TOP_INTREN2_ADMASIGEN_SHIFT 25 +#define SD4_EMMC_TOP_INTREN2_ADMASIGEN_MASK 0x02000000 +#define SD4_EMMC_TOP_INTREN2_CMDSIGEN_SHIFT 24 +#define SD4_EMMC_TOP_INTREN2_CMDSIGEN_MASK 0x01000000 +#define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_SHIFT 23 +#define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_MASK 0x00800000 +#define SD4_EMMC_TOP_INTREN2_DEBSIGEN_SHIFT 22 +#define SD4_EMMC_TOP_INTREN2_DEBSIGEN_MASK 0x00400000 +#define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_SHIFT 21 +#define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_MASK 0x00200000 +#define SD4_EMMC_TOP_INTREN2_DTOSIGEN_SHIFT 20 +#define SD4_EMMC_TOP_INTREN2_DTOSIGEN_MASK 0x00100000 +#define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_SHIFT 19 +#define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_MASK 0x00080000 +#define SD4_EMMC_TOP_INTREN2_CEBSIGEN_SHIFT 18 +#define SD4_EMMC_TOP_INTREN2_CEBSIGEN_MASK 0x00040000 +#define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_SHIFT 17 +#define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_MASK 0x00020000 +#define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_SHIFT 16 +#define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_MASK 0x00010000 +#define SD4_EMMC_TOP_INTREN2_FIXZERO_SHIFT 15 +#define SD4_EMMC_TOP_INTREN2_FIXZERO_MASK 0x00008000 +#define SD4_EMMC_TOP_INTREN2_BTIRQSEN_SHIFT 14 +#define SD4_EMMC_TOP_INTREN2_BTIRQSEN_MASK 0x00004000 +#define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_SHIFT 13 +#define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_MASK 0x00002000 +#define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_SHIFT 12 +#define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_MASK 0x00001000 +#define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_SHIFT 11 +#define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_MASK 0x00000800 +#define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_SHIFT 10 +#define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_MASK 0x00000400 +#define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_SHIFT 9 +#define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_MASK 0x00000200 +#define SD4_EMMC_TOP_INTREN2_CRDIRQEN_SHIFT 8 +#define SD4_EMMC_TOP_INTREN2_CRDIRQEN_MASK 0x00000100 +#define SD4_EMMC_TOP_INTREN2_CRDRVMEN_SHIFT 7 +#define SD4_EMMC_TOP_INTREN2_CRDRVMEN_MASK 0x00000080 +#define SD4_EMMC_TOP_INTREN2_CRDINSEN_SHIFT 6 +#define SD4_EMMC_TOP_INTREN2_CRDINSEN_MASK 0x00000040 +#define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_SHIFT 5 +#define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_MASK 0x00000020 +#define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_SHIFT 4 +#define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_MASK 0x00000010 +#define SD4_EMMC_TOP_INTREN2_DMAIRQEN_SHIFT 3 +#define SD4_EMMC_TOP_INTREN2_DMAIRQEN_MASK 0x00000008 +#define SD4_EMMC_TOP_INTREN2_BLKGAPEN_SHIFT 2 +#define SD4_EMMC_TOP_INTREN2_BLKGAPEN_MASK 0x00000004 +#define SD4_EMMC_TOP_INTREN2_TXDONE_SHIFT 1 +#define SD4_EMMC_TOP_INTREN2_TXDONE_MASK 0x00000002 +#define SD4_EMMC_TOP_INTREN2_CMDDONE_SHIFT 0 +#define SD4_EMMC_TOP_INTREN2_CMDDONE_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTREN2_SD4_OFFSET 0x00000038 +#define SD4_EMMC_TOP_INTREN2_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTREN2_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_INTREN2_SD4_RESERVED_MASK 0xF0006000 +#define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_SHIFT 27 +#define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_MASK 0x08000000 +#define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_SHIFT 26 +#define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_MASK 0x04000000 +#define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_SHIFT 25 +#define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_MASK 0x02000000 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_SHIFT 24 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_MASK 0x01000000 +#define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_SHIFT 23 +#define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_MASK 0x00800000 +#define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_SHIFT 22 +#define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_MASK 0x00400000 +#define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_SHIFT 21 +#define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_MASK 0x00200000 +#define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_SHIFT 20 +#define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_MASK 0x00100000 +#define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_SHIFT 19 +#define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_MASK 0x00080000 +#define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_SHIFT 18 +#define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_MASK 0x00040000 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_SHIFT 17 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_MASK 0x00020000 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_SHIFT 16 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_MASK 0x00010000 +#define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_SHIFT 15 +#define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_MASK 0x00008000 +#define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_SHIFT 12 +#define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_MASK 0x00001000 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_SHIFT 11 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_MASK 0x00000800 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_SHIFT 10 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_MASK 0x00000400 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_SHIFT 9 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_MASK 0x00000200 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_SHIFT 8 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_MASK 0x00000100 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_SHIFT 7 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_MASK 0x00000080 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_SHIFT 6 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_MASK 0x00000040 +#define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_SHIFT 5 +#define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_MASK 0x00000020 +#define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_SHIFT 4 +#define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_MASK 0x00000010 +#define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_SHIFT 3 +#define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_MASK 0x00000008 +#define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_SHIFT 2 +#define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_MASK 0x00000004 +#define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_SHIFT 1 +#define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_MASK 0x00000002 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_SHIFT 0 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_MASK 0x00000001 + +#define SD4_EMMC_TOP_ERRSTAT_OFFSET 0x0000003C +#define SD4_EMMC_TOP_ERRSTAT_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ERRSTAT_TYPE uint32_t +#define SD4_EMMC_TOP_ERRSTAT_RESERVED_MASK 0x3F00FF60 +#define SD4_EMMC_TOP_ERRSTAT_PRESETEN_SHIFT 31 +#define SD4_EMMC_TOP_ERRSTAT_PRESETEN_MASK 0x80000000 +#define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_SHIFT 30 +#define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_MASK 0x40000000 +#define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_SHIFT 23 +#define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_MASK 0x00800000 +#define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_SHIFT 22 +#define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_MASK 0x00400000 +#define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_SHIFT 20 +#define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_MASK 0x00300000 +#define SD4_EMMC_TOP_ERRSTAT_EN1P8V_SHIFT 19 +#define SD4_EMMC_TOP_ERRSTAT_EN1P8V_MASK 0x00080000 +#define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_SHIFT 16 +#define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_MASK 0x00070000 +#define SD4_EMMC_TOP_ERRSTAT_NOCMD_SHIFT 7 +#define SD4_EMMC_TOP_ERRSTAT_NOCMD_MASK 0x00000080 +#define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_SHIFT 4 +#define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_MASK 0x00000010 +#define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_SHIFT 3 +#define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_MASK 0x00000008 +#define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_SHIFT 2 +#define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_MASK 0x00000004 +#define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_SHIFT 1 +#define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_MASK 0x00000002 +#define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_SHIFT 0 +#define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_MASK 0x00000001 + +#define SD4_EMMC_TOP_ERRSTAT_SD4_OFFSET 0x0000003C +#define SD4_EMMC_TOP_ERRSTAT_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_ERRSTAT_SD4_RESERVED_MASK 0x0E00FF40 +#define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_SHIFT 31 +#define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_MASK 0x80000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_SHIFT 30 +#define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_MASK 0x40000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_SHIFT 29 +#define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_MASK 0x20000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_SHIFT 28 +#define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_MASK 0x10000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_SHIFT 24 +#define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_MASK 0x01000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_SHIFT 23 +#define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_MASK 0x00800000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_SHIFT 22 +#define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_MASK 0x00400000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_SHIFT 20 +#define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_MASK 0x00300000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_SHIFT 19 +#define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_MASK 0x00080000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_SHIFT 16 +#define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_MASK 0x00070000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_SHIFT 7 +#define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_MASK 0x00000080 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_SHIFT 5 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_MASK 0x00000020 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_SHIFT 4 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_MASK 0x00000010 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_SHIFT 3 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_MASK 0x00000008 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_SHIFT 2 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_MASK 0x00000004 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_SHIFT 1 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_MASK 0x00000002 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_SHIFT 0 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_MASK 0x00000001 + +#define SD4_EMMC_TOP_CAPABILITIES1_OFFSET 0x00000040 +#define SD4_EMMC_TOP_CAPABILITIES1_DEFAULT 0x17EFD0B0 +#define SD4_EMMC_TOP_CAPABILITIES1_TYPE uint32_t +#define SD4_EMMC_TOP_CAPABILITIES1_RESERVED_MASK 0x08100040 +#define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_SHIFT 30 +#define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_MASK 0xC0000000 +#define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_SHIFT 29 +#define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_MASK 0x20000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_SHIFT 28 +#define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_MASK 0x10000000 +#define SD4_EMMC_TOP_CAPABILITIES1_V18_SHIFT 26 +#define SD4_EMMC_TOP_CAPABILITIES1_V18_MASK 0x04000000 +#define SD4_EMMC_TOP_CAPABILITIES1_V3_SHIFT 25 +#define SD4_EMMC_TOP_CAPABILITIES1_V3_MASK 0x02000000 +#define SD4_EMMC_TOP_CAPABILITIES1_V33_SHIFT 24 +#define SD4_EMMC_TOP_CAPABILITIES1_V33_MASK 0x01000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_SHIFT 23 +#define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_MASK 0x00800000 +#define SD4_EMMC_TOP_CAPABILITIES1_SDMA_SHIFT 22 +#define SD4_EMMC_TOP_CAPABILITIES1_SDMA_MASK 0x00400000 +#define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_SHIFT 21 +#define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_MASK 0x00200000 +#define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_SHIFT 19 +#define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_MASK 0x00080000 +#define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_SHIFT 18 +#define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_MASK 0x00040000 +#define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_SHIFT 16 +#define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_MASK 0x00030000 +#define SD4_EMMC_TOP_CAPABILITIES1_BCLK_SHIFT 8 +#define SD4_EMMC_TOP_CAPABILITIES1_BCLK_MASK 0x0000FF00 +#define SD4_EMMC_TOP_CAPABILITIES1_TOUT_SHIFT 7 +#define SD4_EMMC_TOP_CAPABILITIES1_TOUT_MASK 0x00000080 +#define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_SHIFT 0 +#define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_MASK 0x0000003F + +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_OFFSET 0x00000040 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_DEFAULT 0x10E934B4 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_RESERVED_MASK 0x08100040 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_SHIFT 30 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_MASK 0xC0000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_SHIFT 29 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_MASK 0x20000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_SHIFT 28 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_MASK 0x10000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_SHIFT 26 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_MASK 0x04000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_SHIFT 25 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_MASK 0x02000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_SHIFT 24 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_MASK 0x01000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_SHIFT 23 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_MASK 0x00800000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_SHIFT 22 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_MASK 0x00400000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_SHIFT 21 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_MASK 0x00200000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_SHIFT 19 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_MASK 0x00080000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_SHIFT 18 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_MASK 0x00040000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_SHIFT 16 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_MASK 0x00030000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_SHIFT 8 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_MASK 0x0000FF00 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_SHIFT 7 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_MASK 0x00000080 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_SHIFT 0 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_MASK 0x0000003F + +#define SD4_EMMC_TOP_CAPABILITIES2_OFFSET 0x00000044 +#define SD4_EMMC_TOP_CAPABILITIES2_DEFAULT 0x03002177 +#define SD4_EMMC_TOP_CAPABILITIES2_TYPE uint32_t +#define SD4_EMMC_TOP_CAPABILITIES2_RESERVED_MASK 0xFC001088 +#define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_SHIFT 25 +#define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_MASK 0x02000000 +#define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_SHIFT 24 +#define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_MASK 0x01000000 +#define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_SHIFT 16 +#define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_MASK 0x00FF0000 +#define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_SHIFT 14 +#define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_MASK 0x0000C000 +#define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_SHIFT 13 +#define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_MASK 0x00002000 +#define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_SHIFT 8 +#define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_MASK 0x00000F00 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_SHIFT 6 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_MASK 0x00000040 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_SHIFT 5 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_MASK 0x00000020 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_SHIFT 4 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_MASK 0x00000010 +#define SD4_EMMC_TOP_CAPABILITIES2_DDR50_SHIFT 2 +#define SD4_EMMC_TOP_CAPABILITIES2_DDR50_MASK 0x00000004 +#define SD4_EMMC_TOP_CAPABILITIES2_SDR104_SHIFT 1 +#define SD4_EMMC_TOP_CAPABILITIES2_SDR104_MASK 0x00000002 +#define SD4_EMMC_TOP_CAPABILITIES2_SDR50_SHIFT 0 +#define SD4_EMMC_TOP_CAPABILITIES2_SDR50_MASK 0x00000001 + +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_OFFSET 0x00000044 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DEFAULT 0x10000064 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RESERVED_MASK 0xE7001080 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_SHIFT 28 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_MASK 0x10000000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_SHIFT 27 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_MASK 0x08000000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_SHIFT 16 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_MASK 0x00FF0000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_SHIFT 14 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_MASK 0x0000C000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_SHIFT 13 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_MASK 0x00002000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_SHIFT 8 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_MASK 0x00000F00 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_SHIFT 6 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_MASK 0x00000040 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_SHIFT 5 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_MASK 0x00000020 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_SHIFT 4 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_MASK 0x00000010 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_SHIFT 3 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_MASK 0x00000008 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_SHIFT 2 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_MASK 0x00000004 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_SHIFT 1 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_MASK 0x00000002 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_SHIFT 0 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_MASK 0x00000001 + +#define SD4_EMMC_TOP_MAX_A1_OFFSET 0x00000048 +#define SD4_EMMC_TOP_MAX_A1_DEFAULT 0x00000001 +#define SD4_EMMC_TOP_MAX_A1_TYPE uint32_t +#define SD4_EMMC_TOP_MAX_A1_RESERVED_MASK 0xFF000000 +#define SD4_EMMC_TOP_MAX_A1_MAXA18_SHIFT 16 +#define SD4_EMMC_TOP_MAX_A1_MAXA18_MASK 0x00FF0000 +#define SD4_EMMC_TOP_MAX_A1_MAXA30_SHIFT 8 +#define SD4_EMMC_TOP_MAX_A1_MAXA30_MASK 0x0000FF00 +#define SD4_EMMC_TOP_MAX_A1_MAXA33_SHIFT 0 +#define SD4_EMMC_TOP_MAX_A1_MAXA33_MASK 0x000000FF + +#define SD4_EMMC_TOP_MAX_A2_OFFSET 0x0000004C +#define SD4_EMMC_TOP_MAX_A2_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_MAX_A2_TYPE uint32_t +#define SD4_EMMC_TOP_MAX_A2_RESERVED_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_MAX_A2_SD4_OFFSET 0x0000004C +#define SD4_EMMC_TOP_MAX_A2_SD4_DEFAULT 0x00000001 +#define SD4_EMMC_TOP_MAX_A2_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_MAX_A2_SD4_RESERVED_MASK 0xFFFFFF00 +#define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_SHIFT 0 +#define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_MASK 0x000000FF + +#define SD4_EMMC_TOP_CMDENTSTAT_OFFSET 0x00000050 +#define SD4_EMMC_TOP_CMDENTSTAT_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CMDENTSTAT_TYPE uint32_t +#define SD4_EMMC_TOP_CMDENTSTAT_RESERVED_MASK 0x2C00FF60 +#define SD4_EMMC_TOP_CMDENTSTAT_VSES_SHIFT 30 +#define SD4_EMMC_TOP_CMDENTSTAT_VSES_MASK 0xC0000000 +#define SD4_EMMC_TOP_CMDENTSTAT_TRERR_SHIFT 28 +#define SD4_EMMC_TOP_CMDENTSTAT_TRERR_MASK 0x10000000 +#define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_SHIFT 25 +#define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_MASK 0x02000000 +#define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_SHIFT 24 +#define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_MASK 0x01000000 +#define SD4_EMMC_TOP_CMDENTSTAT_ILERR_SHIFT 23 +#define SD4_EMMC_TOP_CMDENTSTAT_ILERR_MASK 0x00800000 +#define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_SHIFT 22 +#define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_MASK 0x00400000 +#define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_SHIFT 21 +#define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_MASK 0x00200000 +#define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_SHIFT 20 +#define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_MASK 0x00100000 +#define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_SHIFT 19 +#define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_MASK 0x00080000 +#define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_SHIFT 18 +#define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_MASK 0x00040000 +#define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_SHIFT 17 +#define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_MASK 0x00020000 +#define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_SHIFT 16 +#define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_MASK 0x00010000 +#define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_SHIFT 7 +#define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_MASK 0x00000080 +#define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_SHIFT 4 +#define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_MASK 0x00000010 +#define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_SHIFT 3 +#define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_MASK 0x00000008 +#define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_SHIFT 2 +#define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_MASK 0x00000004 +#define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_SHIFT 1 +#define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_MASK 0x00000002 +#define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_SHIFT 0 +#define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_MASK 0x00000001 + +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_OFFSET 0x00000050 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESERVED_MASK 0x0000FF40 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_SHIFT 28 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_MASK 0xF0000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_SHIFT 27 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_MASK 0x08000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_SHIFT 26 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_MASK 0x04000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_SHIFT 25 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_MASK 0x02000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_SHIFT 24 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_MASK 0x01000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_SHIFT 23 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_MASK 0x00800000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_SHIFT 22 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_MASK 0x00400000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_SHIFT 21 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_MASK 0x00200000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_SHIFT 20 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_MASK 0x00100000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_SHIFT 19 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_MASK 0x00080000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_SHIFT 18 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_MASK 0x00040000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_SHIFT 17 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_MASK 0x00020000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_SHIFT 16 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_MASK 0x00010000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_SHIFT 7 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_MASK 0x00000080 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_SHIFT 5 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_MASK 0x00000020 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_SHIFT 4 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_MASK 0x00000010 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_SHIFT 3 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_MASK 0x00000008 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_SHIFT 2 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_MASK 0x00000004 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_SHIFT 1 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_MASK 0x00000002 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_SHIFT 0 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_MASK 0x00000001 + +#define SD4_EMMC_TOP_ADMAERR_OFFSET 0x00000054 +#define SD4_EMMC_TOP_ADMAERR_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ADMAERR_TYPE uint32_t +#define SD4_EMMC_TOP_ADMAERR_RESERVED_MASK 0xFFFFFFF8 +#define SD4_EMMC_TOP_ADMAERR_ADMALERR_SHIFT 2 +#define SD4_EMMC_TOP_ADMAERR_ADMALERR_MASK 0x00000004 +#define SD4_EMMC_TOP_ADMAERR_ADMAERR_SHIFT 0 +#define SD4_EMMC_TOP_ADMAERR_ADMAERR_MASK 0x00000003 + +#define SD4_EMMC_TOP_ADMAADDR0_OFFSET 0x00000058 +#define SD4_EMMC_TOP_ADMAADDR0_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ADMAADDR0_TYPE uint32_t +#define SD4_EMMC_TOP_ADMAADDR0_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_SHIFT 0 +#define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_ADMAADDR1_OFFSET 0x0000005C +#define SD4_EMMC_TOP_ADMAADDR1_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ADMAADDR1_TYPE uint32_t +#define SD4_EMMC_TOP_ADMAADDR1_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_SHIFT 0 +#define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_PRESETVAL1_OFFSET 0x00000060 +#define SD4_EMMC_TOP_PRESETVAL1_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_PRESETVAL1_TYPE uint32_t +#define SD4_EMMC_TOP_PRESETVAL1_RESERVED_MASK 0x38003800 +#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_SHIFT 30 +#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_MASK 0xC0000000 +#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_SHIFT 26 +#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_MASK 0x04000000 +#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_SHIFT 16 +#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_MASK 0x03FF0000 +#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_SHIFT 14 +#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_MASK 0x0000C000 +#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_SHIFT 10 +#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_MASK 0x00000400 +#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_SHIFT 0 +#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_MASK 0x000003FF + +#define SD4_EMMC_TOP_PRESETVAL2_OFFSET 0x00000064 +#define SD4_EMMC_TOP_PRESETVAL2_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_PRESETVAL2_TYPE uint32_t +#define SD4_EMMC_TOP_PRESETVAL2_RESERVED_MASK 0x38003800 +#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_SHIFT 30 +#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_MASK 0xC0000000 +#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_SHIFT 26 +#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_MASK 0x04000000 +#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_SHIFT 16 +#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_MASK 0x03FF0000 +#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_SHIFT 14 +#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_MASK 0x0000C000 +#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_SHIFT 10 +#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_MASK 0x00000400 +#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_SHIFT 0 +#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_MASK 0x000003FF + +#define SD4_EMMC_TOP_PRESETVAL3_OFFSET 0x00000068 +#define SD4_EMMC_TOP_PRESETVAL3_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_PRESETVAL3_TYPE uint32_t +#define SD4_EMMC_TOP_PRESETVAL3_RESERVED_MASK 0x38003800 +#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_SHIFT 30 +#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_MASK 0xC0000000 +#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_SHIFT 26 +#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_MASK 0x04000000 +#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_SHIFT 16 +#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_MASK 0x03FF0000 +#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_SHIFT 14 +#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_MASK 0x0000C000 +#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_SHIFT 10 +#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_MASK 0x00000400 +#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_SHIFT 0 +#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_MASK 0x000003FF + +#define SD4_EMMC_TOP_PRESETVAL4_OFFSET 0x0000006C +#define SD4_EMMC_TOP_PRESETVAL4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_PRESETVAL4_TYPE uint32_t +#define SD4_EMMC_TOP_PRESETVAL4_RESERVED_MASK 0x38003800 +#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_SHIFT 30 +#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_MASK 0xC0000000 +#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_SHIFT 26 +#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_MASK 0x04000000 +#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_SHIFT 16 +#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_MASK 0x03FF0000 +#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_SHIFT 14 +#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_MASK 0x0000C000 +#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_SHIFT 10 +#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_MASK 0x00000400 +#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_SHIFT 0 +#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_MASK 0x000003FF + +#define SD4_EMMC_TOP_BOOTTIMEOUT_OFFSET 0x00000070 +#define SD4_EMMC_TOP_BOOTTIMEOUT_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_BOOTTIMEOUT_TYPE uint32_t +#define SD4_EMMC_TOP_BOOTTIMEOUT_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_SHIFT 0 +#define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_DBGSEL_OFFSET 0x00000074 +#define SD4_EMMC_TOP_DBGSEL_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_DBGSEL_TYPE uint32_t +#define SD4_EMMC_TOP_DBGSEL_RESERVED_MASK 0xFFFFFFFE +#define SD4_EMMC_TOP_DBGSEL_DBGSEL_SHIFT 0 +#define SD4_EMMC_TOP_DBGSEL_DBGSEL_MASK 0x00000001 + +#define SD4_EMMC_TOP_UHS2_PRESETVAL_OFFSET 0x00000074 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_TYPE uint32_t +#define SD4_EMMC_TOP_UHS2_PRESETVAL_RESERVED_MASK 0xFFFF3800 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_SHIFT 14 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_MASK 0x0000C000 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_SHIFT 10 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_MASK 0x00000400 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_SHIFT 0 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_MASK 0x000003FF + +#define SD4_EMMC_TOP_HCVERSIRQ_OFFSET 0x000000FC +#define SD4_EMMC_TOP_HCVERSIRQ_DEFAULT 0x10020000 +#define SD4_EMMC_TOP_HCVERSIRQ_TYPE uint32_t +#define SD4_EMMC_TOP_HCVERSIRQ_RESERVED_MASK 0x0000FF00 +#define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_SHIFT 24 +#define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_MASK 0xFF000000 +#define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_SHIFT 16 +#define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_MASK 0x00FF0000 +#define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_SHIFT 0 +#define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_MASK 0x000000FF + +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_OFFSET 0x000000FC +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_DEFAULT 0x01030000 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_RESERVED_MASK 0x0000FF00 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_SHIFT 24 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_MASK 0xFF000000 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_SHIFT 16 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_MASK 0x00FF0000 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_SHIFT 0 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_MASK 0x000000FF + +#endif /* BRCM_RDB_SD4_EMMC_TOP_H */ diff --git a/include/drivers/brcm/emmc/emmc_chal_sd.h b/include/drivers/brcm/emmc/emmc_chal_sd.h new file mode 100644 index 0000000..8d223f9 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_chal_sd.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CHAL_SD_H +#define CHAL_SD_H + +#include <stddef.h> + +#define BASE_CLK_FREQ (200 * 1000 * 1000) +#define INIT_CLK_FREQ (400 * 1000) + +#define SD_ERROR_RECOVERABLE 0 +#define SD_ERROR_NON_RECOVERABLE 1 + +#define SD_OK 0 +#define SD_FAIL (-1) +#define SD_INVALID_HANDLE (-2) +#define SD_CEATA_INIT_ERROR (-3) +#define SD_RESET_ERROR (-4) +#define SD_CARD_INIT_ERROR (-5) +#define SD_INV_DATA_WIDTH (-6) +#define SD_SET_BUS_WIDTH_ERROR (-7) +#define SD_DMA_NOT_SUPPORT (-8) +#define SD_SDIO_READ_ERROR (-9) +#define SD_SDIO_WRITE_ERROR (-10) +#define SD_WRITE_ERROR (-11) +#define SD_READ_ERROR (-12) +#define SD_READ_SIZE_ERROR (-13) +#define SD_RW_ADDRESS_ERROR (-14) +#define SD_XFER_ADDRESS_ERROR (-15) +#define SD_DATA_XFER_ADDR_ERROR (-16) +#define SD_DATA_XFER_ERROR (-17) +#define SD_WRITE_SIZE_ERROR (-18) +#define SD_CMD_STATUS_UPDATE_ERR (-19) +#define SD_CMD12_ERROR (-20) +#define SD_CMD_DATA_ERROR (-21) +#define SD_CMD_TIMEOUT (-22) +#define SD_CMD_NO_RESPONSE (-22) +#define SD_CMD_ABORT_ERROR (-23) +#define SD_CMD_INVALID (-24) +#define SD_CMD_RESUME_ERROR (-25) +#define SD_CMD_ERR_INVALID_RESPONSE (-26) +#define SD_WAIT_TIMEOUT (-27) +#define SD_READ_TIMEOUT (-28) +#define SD_CEATA_REST_ERROR (-29) +#define SD_INIT_CAED_FAILED (-30) +#define SD_ERROR_CLOCK_OFFLIMIT (-31) +#define SD_INV_SLOT (-32) + +#define SD_NOR_INTERRUPTS 0x000000FF +#define SD_ERR_INTERRUPTS 0x03FF0000 +#define SD_CMD_ERROR_INT 0x010F0000 +#define SD_DAT_ERROR_INT 0x02F00000 +#define SD_DAT_TIMEOUT 0x00100000 + +/* Operation modes */ +#define SD_PIO_MODE 0 +#define SD_INT_MODE 1 + +/* Support both ADMA and SDMA (for version 2.0 and above) */ +#define SD_DMA_OFF 0 +#define SD_DMA_SDMA 1 +#define SD_DMA_ADMA 2 + +#define SD_NORMAL_SPEED 0 +#define SD_HIGH_SPEED 1 + +#define SD_XFER_CARD_TO_HOST 3 +#define SD_XFER_HOST_TO_CARD 4 + +#define SD_CARD_DETECT_AUTO 0 +#define SD_CARD_DETECT_SD 1 +#define SD_CARD_DETECT_SDIO 2 +#define SD_CARD_DETECT_MMC 3 +#define SD_CARD_DETECT_CEATA 4 + +#define SD_ABORT_SYNC_MODE 0 +#define SD_ABORT_ASYNC_MODE 1 + +#define SD_CMD_ERROR_FLAGS (0x18F << 16) +#define SD_DATA_ERROR_FLAGS (0x70 << 16) +#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F) + +#define SD_CARD_STATUS_ERROR 0x10000000 +#define SD_CMD_MISSING 0x80000000 +#define SD_ERROR_INT 0x8000 + +#define SD_TRAN_HIGH_SPEED 0x32 +#define SD_CARD_HIGH_CAPACITY 0x40000000 +#define SD_CARD_POWER_UP_STATUS 0x80000000 + +#define SD_HOST_CORE_TIMEOUT 0x0E + +/* SD CARD and Host Controllers bus width */ +#define SD_BUS_DATA_WIDTH_1BIT 0x00 +#define SD_BUS_DATA_WIDTH_4BIT 0x02 +#define SD_BUS_DATA_WIDTH_8BIT 0x20 + +/* dma boundary settings */ +#define SD_DMA_BOUNDARY_4K 0 +#define SD_DMA_BOUNDARY_8K (1 << 12) +#define SD_DMA_BOUNDARY_16K (2 << 12) +#define SD_DMA_BOUNDARY_32K (3 << 12) +#define SD_DMA_BOUNDARY_64K (4 << 12) +#define SD_DMA_BOUNDARY_128K (5 << 12) +#define SD_DMA_BOUNDARY_256K (6 << 12) +#define SD_DMA_BOUNDARY_512K (7 << 12) + +#define SD_CMDR_CMD_NORMAL 0x00000000 +#define SD_CMDR_CMD_SUSPEND 0x00400000 +#define SD_CMDR_CMD_RESUME 0x00800000 +#define SD_CMDR_CMD_ABORT 0x00c00000 + +#define SD_CMDR_RSP_TYPE_NONE 0x0 +#define SD_CMDR_RSP_TYPE_R2 0x1 +#define SD_CMDR_RSP_TYPE_R3_4 0x2 +#define SD_CMDR_RSP_TYPE_R1_5_6 0x2 +#define SD_CMDR_RSP_TYPE_R1b_5b 0x3 +#define SD_CMDR_RSP_TYPE_S 16 + +struct sd_ctrl_info { + uint32_t blkReg; /* current block register cache value */ + uint32_t cmdReg; /* current command register cache value */ + uint32_t argReg; /* current argument register cache value */ + uint32_t cmdIndex; /* current command index */ + uint32_t cmdStatus; /* current command status, cmd/data compelete */ + uint16_t rca; /* relative card address */ + uint32_t ocr; /* operation codition */ + uint32_t eventList; /* events list */ + uint32_t blkGapEnable; + + uint32_t capability; /* controller's capbilities */ + uint32_t maxCurrent; /* maximum current supported */ + uint32_t present; /* if card is inserted or removed */ + uint32_t version; /* SD spec version 1.0 or 2.0 */ + uint32_t vendor; /* vendor number */ + + uintptr_t sdRegBaseAddr; /* sdio control registers */ + uintptr_t hostRegBaseAddr; /* SD Host control registers */ +}; + +struct sd_cfg { + uint32_t mode; /* interrupt or polling */ + uint32_t dma; /* dma enabled or disabled */ + uint32_t retryLimit; /* command retry limit */ + uint32_t speedMode; /* speed mode, 0 standard, 1 high speed */ + uint32_t voltage; /* voltage level */ + uint32_t blockSize; /* access block size (512 for HC card) */ + uint32_t dmaBoundary; /* dma address boundary */ + uint32_t detSignal; /* card det signal src, for test purpose only */ + uint32_t rdWaiting; + uint32_t wakeupOut; + uint32_t wakeupIn; + uint32_t wakeupInt; + uint32_t wfe_retry; + uint32_t gapInt; + uint32_t readWait; + uint32_t led; +}; + +struct sd_dev { + struct sd_cfg cfg; /* SD configuration */ + struct sd_ctrl_info ctrl; /* SD info */ +}; + +int32_t chal_sd_start(CHAL_HANDLE *sdHandle, uint32_t mode, + uint32_t sdBase, uint32_t hostBase); +int32_t chal_sd_config(CHAL_HANDLE *sdHandle, uint32_t speed, + uint32_t retry, uint32_t boundary, + uint32_t blkSize, uint32_t dma); +int32_t chal_sd_stop(void); +int32_t chal_sd_set_dma(CHAL_HANDLE *sdHandle, uint32_t mode); +uintptr_t chal_sd_get_dma_addr(CHAL_HANDLE *handle); +int32_t chal_sd_config_bus_width(CHAL_HANDLE *sdHandle, int32_t width); +int32_t chal_sd_send_cmd(CHAL_HANDLE *sdHandle, uint32_t cmdIndex, + uint32_t arg, uint32_t options); +int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sdHandle, uintptr_t address); +int32_t chal_sd_set_clock(CHAL_HANDLE *sdHandle, + uint32_t div_ctrl_setting, uint32_t on); +uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq); +int32_t chal_sd_setup_xfer(CHAL_HANDLE *sdHandle, uint8_t *data, + uint32_t length, int32_t dir); +int32_t chal_sd_write_buffer(CHAL_HANDLE *sdHandle, uint32_t length, + uint8_t *data); +int32_t chal_sd_read_buffer(CHAL_HANDLE *sdHandle, uint32_t length, + uint8_t *data); +int32_t chal_sd_reset_line(CHAL_HANDLE *sdHandle, uint32_t line); +int32_t chal_sd_get_response(CHAL_HANDLE *sdHandle, uint32_t *resp); +int32_t chal_sd_clear_pending_irq(CHAL_HANDLE *sdHandle); +int32_t chal_sd_get_irq_status(CHAL_HANDLE *sdHandle); +int32_t chal_sd_clear_irq(CHAL_HANDLE *sdHandle, uint32_t mask); +uint32_t chal_sd_get_present_status(CHAL_HANDLE *sdHandle); +int32_t chal_sd_get_atuo12_error(CHAL_HANDLE *sdHandle); +void chal_sd_set_speed(CHAL_HANDLE *sdHandle, uint32_t speed); +int32_t chal_sd_check_cap(CHAL_HANDLE *sdHandle, uint32_t cap); +void chal_sd_set_irq_signal(CHAL_HANDLE *sdHandle, uint32_t mask, + uint32_t state); +void chal_sd_dump_fifo(CHAL_HANDLE *sdHandle); +#endif /* CHAL_SD_H */ diff --git a/include/drivers/brcm/emmc/emmc_chal_types.h b/include/drivers/brcm/emmc/emmc_chal_types.h new file mode 100644 index 0000000..9563273 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_chal_types.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef CHAL_TYPES_H +#define CHAL_TYPES_H + +#include <stdint.h> + +// +// Generic cHAL handler +// +#ifndef CHAL_HANDLE + typedef void *CHAL_HANDLE; ///< void pointer (32 bits wide) +#endif + +#endif /* _CHAL_TYPES_H_ */ diff --git a/include/drivers/brcm/emmc/emmc_csl_sd.h b/include/drivers/brcm/emmc/emmc_csl_sd.h new file mode 100644 index 0000000..52b8bc8 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_csl_sd.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CSL_SD_H +#define CSL_SD_H + +#define SD_CLOCK_BASE 104000000 +#define SD_CLOCK_52MHZ 52000000 +#define SD_CLOCK_26MHZ 26000000 +#define SD_CLOCK_17MHZ 17330000 +#define SD_CLOCK_13MHZ 13000000 +#define SD_CLOCK_10MHZ 10000000 +#define SD_CLOCK_9MHZ 9000000 +#define SD_CLOCK_7MHZ 7000000 +#define SD_CLOCK_5MHZ 5000000 +#define SD_CLOCK_1MHZ 1000000 +#define SD_CLOCK_400KHZ 400000 + +#define SD_DRIVE_STRENGTH_MASK 0x38000000 +#if defined(_BCM213x1_) || defined(_BCM21551_) || defined(_ATHENA_) +#define SD_DRIVE_STRENGTH 0x28000000 +#elif defined(_BCM2153_) +#define SD_DRIVE_STRENGTH 0x38000000 +#else +#define SD_DRIVE_STRENGTH 0x00000000 +#endif + +#define SD_NUM_HOST 2 + +#define SD_CARD_UNLOCK 0 +#define SD_CARD_LOCK 0x4 +#define SD_CARD_CLEAR_PWD 0x2 +#define SD_CARD_SET_PWD 0x1 +#define SD_CARD_ERASE_PWD 0x8 + +#define SD_CARD_LOCK_STATUS 0x02000000 +#define SD_CARD_UNLOCK_STATUS 0x01000000 + +#define SD_CMD_ERROR_FLAGS (0x18F << 16) +#define SD_DATA_ERROR_FLAGS (0x70 << 16) +#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F) +#define SD_CARD_STATUS_ERROR 0x10000000 +#define SD_CMD_MISSING 0x80000000 + +#define SD_TRAN_HIGH_SPEED 0x32 +#define SD_CARD_HIGH_CAPACITY 0x40000000 +#define SD_CARD_POWER_UP_STATUS 0x80000000 + +struct sd_dev_info { + uint32_t mode; /* interrupt or polling */ + uint32_t dma; /* dma enabled or disabled */ + uint32_t voltage; /* voltage level */ + uint32_t slot; /* if the HC is locatd at slot 0 or slot 1 */ + uint32_t version; /* 1.0 or 2.0 */ + uint32_t curSystemAddr; /* system address */ + uint32_t dataWidth; /* data width for the controller */ + uint32_t clock; /* clock rate */ + uint32_t status; /* if device is active on transfer or not */ +}; + +void data_xfer_setup(struct sd_handle *handle, uint8_t *data, + uint32_t length, int dir); +int reset_card(struct sd_handle *handle); +int reset_host_ctrl(struct sd_handle *handle); +int init_card(struct sd_handle *handle, int detection); +int init_mmc_card(struct sd_handle *handle); +int write_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer); +int read_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer); +int select_blk_sz(struct sd_handle *handle, uint16_t size); +int check_error(struct sd_handle *handle, uint32_t ints); + +int process_data_xfer(struct sd_handle *handle, uint8_t *buffer, + uint32_t addr, uint32_t length, int dir); +int read_block(struct sd_handle *handle, uint8_t *dst, uint32_t addr, + uint32_t len); +#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE +int erase_card(struct sd_handle *handle, uint32_t addr, uint32_t blocks); +#endif +int write_block(struct sd_handle *handle, uint8_t *src, uint32_t addr, + uint32_t len); +int process_cmd_response(struct sd_handle *handle, uint32_t cmdIndex, + uint32_t rsp0, uint32_t rsp1, uint32_t rsp2, + uint32_t rsp3, struct sd_resp *resp); +int32_t set_config(struct sd_handle *handle, uint32_t speed, + uint32_t retry, uint32_t dma, uint32_t dmaBound, + uint32_t blkSize, uint32_t wfe_retry); + +uint32_t wait_for_event(struct sd_handle *handle, uint32_t mask, + uint32_t retry); +int set_boot_config(struct sd_handle *handle, uint32_t config); + +int mmc_cmd1(struct sd_handle *handle); +#endif /* CSL_SD_H */ diff --git a/include/drivers/brcm/emmc/emmc_csl_sdcmd.h b/include/drivers/brcm/emmc/emmc_csl_sdcmd.h new file mode 100644 index 0000000..425603f --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_csl_sdcmd.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CSL_SD_CMD_H +#define CSL_SD_CMD_H + +#define SD_CMD_OK 0 +#define SD_CMD_ERROR -1 + +#define SD_CMD_ERR_NO_IO_FUNC 5 +#define SD_CMD_ERR_INVALID_PARAMETER 6 +#define SD_CMD_ERR_R1_ILLEGAL_COMMAND 7 +#define SD_CMD_ERR_R1_COM_CRC_ERROR 8 +#define SD_CMD_ERR_R1_FUNC_NUM_ERROR 9 +#define SD_CMD_ERR_R1_ADDRESS_ERROR 10 +#define SD_CMD_ERR_R1_PARAMETER_ERROR 11 +#define SD_CMD_ERR_DATA_ERROR_TOKEN 12 +#define SD_CMD_ERR_DATA_NOT_ACCEPTED 13 +#define SD_CMD7_ARG_RCA_SHIFT 16 + +#define SD_CARD_STATUS_PENDING 0x01 +#define SD_CARD_STATUS_BUFFER_OVERFLOW 0x01 +#define SD_CARD_STATUS_DEVICE_BUSY 0x02 +#define SD_CARD_STATUS_UNSUCCESSFUL 0x03 +#define SD_CARD_STATUS_NOT_IMPLEMENTED 0x04 +#define SD_CARD_STATUS_ACCESS_VIOLATION 0x05 +#define SD_CARD_STATUS_INVALID_HANDLE 0x06 +#define SD_CARD_STATUS_INVALID_PARAMETER 0x07 +#define SD_CARD_STATUS_NO_SUCH_DEVICE 0x08 +#define SD_CARD_STATUS_INVALID_DEVICE_REQUEST 0x09 +#define SD_CARD_STATUS_NO_MEMORY 0x0A +#define SD_CARD_STATUS_BUS_DRIVER_NOT_READY 0x0B +#define SD_CARD_STATUS_DATA_ERROR 0x0C +#define SD_CARD_STATUS_CRC_ERROR 0x0D +#define SD_CARD_STATUS_INSUFFICIENT_RESOURCES 0x0E +#define SD_CARD_STATUS_DEVICE_NOT_CONNECTED 0x10 +#define SD_CARD_STATUS_DEVICE_REMOVED 0x11 +#define SD_CARD_STATUS_DEVICE_NOT_RESPONDING 0x12 +#define SD_CARD_STATUS_CANCELED 0x13 +#define SD_CARD_STATUS_RESPONSE_TIMEOUT 0x14 +#define SD_CARD_STATUS_DATA_TIMEOUT 0x15 +#define SD_CARD_STATUS_DEVICE_RESPONSE_ERROR 0x16 +#define SD_CARD_STATUS_DEVICE_UNSUPPORTED 0x17 + +/* Response structure */ +struct sd_r2_resp { + uint32_t rsp4; /* 127:96 */ + uint32_t rsp3; /* 95:64 */ + uint32_t rsp2; /* 63:32 */ + uint32_t rsp1; /* 31:0 */ +}; + +struct sd_r3_resp { + uint32_t ocr; +}; + +struct sd_r4_resp { + uint8_t cardReady; + uint8_t funcs; + uint8_t memPresent; + uint32_t ocr; +}; + +struct sd_r5_resp { + uint8_t data; +}; + +struct sd_r6_resp { + uint16_t rca; + uint16_t cardStatus; +}; + +struct sd_r7_resp { + uint16_t rca; +}; + +struct sd_resp { + uint8_t r1; + uint32_t cardStatus; + uint32_t rawData[4]; + union { + struct sd_r2_resp r2; + struct sd_r3_resp r3; + struct sd_r4_resp r4; + struct sd_r5_resp r5; + struct sd_r6_resp r6; + struct sd_r7_resp r7; + } data; +}; + +struct sd_card_info { + uint32_t type; /* card type SD, MMC or SDIO */ + uint64_t size; /* card size */ + uint32_t speed; /* card speed */ + uint32_t voltage; /* voltage supported */ + uint32_t mId; /* manufacturer ID */ + uint32_t oId; /* OEM ID */ + uint32_t classes; /* card class */ + uint32_t name1; /* product name part 1 */ + uint32_t name2; /* product name part 2 */ + uint32_t revision; /* revison */ + uint32_t sn; /* serial number */ + uint32_t numIoFuns; /* total I/O function number */ + uint32_t maxRdBlkLen; /* max read block length */ + uint32_t maxWtBlkLen; /* max write block length */ + uint32_t blkMode; /* sdio card block mode support */ + uint32_t f0Cis; /* sdio card block mode support */ + uint32_t f1Cis; /* sdio card block mode support */ + + uint8_t partRead; /* partial block read allowed */ + uint8_t partWrite; /* partial block write allowed */ + uint8_t dsr; /* card DSR */ + uint8_t rdCurMin; /* min current for read */ + uint8_t rdCurMax; /* max current for read */ + uint8_t wtCurMin; /* min current for write */ + uint8_t wtCurMax; /* max current for write */ + uint8_t erase; /* erase enable */ + uint8_t eraseSecSize; /* erase sector size */ + uint8_t proGrpSize; /* write protection group size */ + uint8_t protect; /* permanent write protection or not */ + uint8_t tmpProt; /* temp write protection or not */ + uint8_t wtSpeed; /* write speed relatively to read */ + uint8_t version; /* card version 0:1.0 - 1.01, 1:1.10, 2:2.0 */ + uint8_t eraseState; /* if the data will be 0 or 1 after erase */ + uint8_t bus; /* data with supported */ + uint8_t security; /* security support 0, 2:1.01 3:2.0 */ + uint8_t format; /* file format */ + uint8_t fileGrp; /* file group */ + char pwd[20]; /* password */ +}; + +struct sd_handle { + struct sd_dev *device; + struct sd_card_info *card; +}; + +int sd_cmd0(struct sd_handle *handle); +int sd_cmd1(struct sd_handle *handle, uint32_t initOcr, uint32_t *ocr); +int sd_cmd2(struct sd_handle *handle); +int sd_cmd3(struct sd_handle *handle); +int sd_cmd7(struct sd_handle *handle, uint32_t rca); +int sd_cmd9(struct sd_handle *handle, struct sd_card_data *card); +int sd_cmd13(struct sd_handle *handle, uint32_t *status); +int sd_cmd16(struct sd_handle *handle, uint32_t blockLen); +int sd_cmd17(struct sd_handle *handle, + uint32_t addr, uint32_t len, uint8_t *buffer); +int sd_cmd18(struct sd_handle *handle, + uint32_t addr, uint32_t len, uint8_t *buffer); +#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE +int sd_cmd24(struct sd_handle *handle, + uint32_t addr, uint32_t len, uint8_t *buffer); +int sd_cmd25(struct sd_handle *handle, + uint32_t addr, uint32_t len, uint8_t *buffer); +#endif +#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE +int sd_cmd35(struct sd_handle *handle, uint32_t start); +int sd_cmd36(struct sd_handle *handle, uint32_t end); +int sd_cmd38(struct sd_handle *handle); +#endif +int mmc_cmd6(struct sd_handle *handle, uint32_t argument); +int mmc_cmd8(struct sd_handle *handle, uint8_t *extCsdReg); + +int send_cmd(struct sd_handle *handle, uint32_t cmdIndex, + uint32_t argument, uint32_t options, struct sd_resp *resp); +#endif /* CSL_SD_CMD_H */ diff --git a/include/drivers/brcm/emmc/emmc_csl_sdprot.h b/include/drivers/brcm/emmc/emmc_csl_sdprot.h new file mode 100644 index 0000000..597e1e0 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_csl_sdprot.h @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CSL_SD_PROT_H +#define CSL_SD_PROT_H + +#define SD_CARD_UNKNOWN 0 /* bad type or unrecognized */ +#define SD_CARD_SD 1 /* IO only card */ +#define SD_CARD_SDIO 2 /* memory only card */ +#define SD_CARD_COMBO 3 /* IO and memory combo card */ +#define SD_CARD_MMC 4 /* memory only card */ +#define SD_CARD_CEATA 5 /* IO and memory combo card */ + +#define SD_IO_FIXED_ADDRESS 0 /* fix Address */ +#define SD_IO_INCREMENT_ADDRESS 1 + +#define SD_HIGH_CAPACITY_CARD 0x40000000 + +#define MMC_CMD_IDLE_RESET_ARG 0xF0F0F0F0 + +/* Supported operating voltages are 3.2-3.3 and 3.3-3.4 */ +#define MMC_OCR_OP_VOLT 0x00300000 +/* Enable sector access mode */ +#define MMC_OCR_SECTOR_ACCESS_MODE 0x40000000 + +/* command index */ +#define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ +#define SD_CMD_SEND_OPCOND 1 +#define SD_CMD_ALL_SEND_CID 2 +#define SD_CMD_MMC_SET_RCA 3 +#define SD_CMD_MMC_SET_DSR 4 +#define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ +#define SD_ACMD_SET_BUS_WIDTH 6 +#define SD_CMD_SWITCH_FUNC 6 +#define SD_CMD_SELECT_DESELECT_CARD 7 +#define SD_CMD_READ_EXT_CSD 8 +#define SD_CMD_SEND_CSD 9 +#define SD_CMD_SEND_CID 10 +#define SD_CMD_STOP_TRANSMISSION 12 +#define SD_CMD_SEND_STATUS 13 +#define SD_ACMD_SD_STATUS 13 +#define SD_CMD_GO_INACTIVE_STATE 15 +#define SD_CMD_SET_BLOCKLEN 16 +#define SD_CMD_READ_SINGLE_BLOCK 17 +#define SD_CMD_READ_MULTIPLE_BLOCK 18 +#define SD_CMD_WRITE_BLOCK 24 +#define SD_CMD_WRITE_MULTIPLE_BLOCK 25 +#define SD_CMD_PROGRAM_CSD 27 +#define SD_CMD_SET_WRITE_PROT 28 +#define SD_CMD_CLR_WRITE_PROT 29 +#define SD_CMD_SEND_WRITE_PROT 30 +#define SD_CMD_ERASE_WR_BLK_START 32 +#define SD_CMD_ERASE_WR_BLK_END 33 +#define SD_CMD_ERASE_GROUP_START 35 +#define SD_CMD_ERASE_GROUP_END 36 +#define SD_CMD_ERASE 38 +#define SD_CMD_LOCK_UNLOCK 42 +#define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ +#define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ +#define SD_CMD_APP_CMD 55 +#define SD_CMD_GEN_CMD 56 +#define SD_CMD_READ_OCR 58 +#define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ +#define SD_ACMD_SEND_NUM_WR_BLOCKS 22 +#define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 +#define SD_ACMD_SD_SEND_OP_COND 41 +#define SD_ACMD_SET_CLR_CARD_DETECT 42 +#define SD_ACMD_SEND_SCR 51 + +/* response parameters */ +#define SD_RSP_NO_NONE 0 +#define SD_RSP_NO_1 1 +#define SD_RSP_NO_2 2 +#define SD_RSP_NO_3 3 +#define SD_RSP_NO_4 4 +#define SD_RSP_NO_5 5 +#define SD_RSP_NO_6 6 + +/* Modified R6 response (to CMD3) */ +#define SD_RSP_MR6_COM_CRC_ERROR 0x8000 +#define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 +#define SD_RSP_MR6_ERROR 0x2000 + +/* Modified R1 in R4 Response (to CMD5) */ +#define SD_RSP_MR1_SBIT 0x80 +#define SD_RSP_MR1_PARAMETER_ERROR 0x40 +#define SD_RSP_MR1_RFU5 0x20 +#define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 +#define SD_RSP_MR1_COM_CRC_ERROR 0x80 +#define SD_RSP_MR1_ILLEGAL_COMMAND 0x40 +#define SD_RSP_MR1_RFU1 0x20 +#define SD_RSP_MR1_IDLE_STATE 0x01 + +/* R5 response (to CMD52 and CMD53) */ +#define SD_RSP_R5_COM_CRC_ERROR 0x80 +#define SD_RSP_R5_ILLEGAL_COMMAND 0x40 +#define SD_RSP_R5_IO_CURRENTSTATE1 0x20 +#define SD_RSP_R5_IO_CURRENTSTATE0 0x10 +#define SD_RSP_R5_ERROR 0x80 +#define SD_RSP_R5_RFU 0x40 +#define SD_RSP_R5_FUNC_NUM_ERROR 0x20 +#define SD_RSP_R5_OUT_OF_RANGE 0x01 + +/* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ +#define SD_OP_READ 0 /* Read_Write */ +#define SD_OP_WRITE 1 /* Read_Write */ + +#define SD_RW_NORMAL 0 /* no RAW */ +#define SD_RW_RAW 1 /* RAW */ + +#define SD_BYTE_MODE 0 /* Byte Mode */ +#define SD_BLOCK_MODE 1 /* BlockMode */ + +#define SD_FIXED_ADDRESS 0 /* fix Address */ +#define SD_INCREMENT_ADDRESS 1 /* IncrementAddress */ + +#define SD_CMD5_ARG_IO_OCR_MASK 0x00FFFFFF +#define SD_CMD5_ARG_IO_OCR_SHIFT 0 +#define SD_CMD55_ARG_RCA_SHIFT 16 +#define SD_CMD59_ARG_CRC_OPTION_MASK 0x01 +#define SD_CMD59_ARG_CRC_OPTION_SHIFT 0 + +/* SD_CMD_IO_RW_DIRECT Argument */ +#define SdioIoRWDirectArg(rw, raw, func, addr, data) \ + (((rw & 1) << 31) | ((func & 0x7) << 28) | \ + ((raw & 1) << 27) | ((addr & 0x1FFFF) << 9) | \ + (data & 0xFF)) + +/* build SD_CMD_IO_RW_EXTENDED Argument */ +#define SdioIoRWExtArg(rw, blk, func, addr, inc_addr, count) \ + (((rw & 1) << 31) | ((func & 0x7) << 28) | \ + ((blk & 1) << 27) | ((inc_addr & 1) << 26) | \ + ((addr & 0x1FFFF) << 9) | (count & 0x1FF)) + +/* + * The Common I/O area shall be implemented on all SDIO cards and + * is accessed the the host via I/O reads and writes to function 0, + * the registers within the CIA are provided to enable/disable + * the operationo fthe i/o funciton. + */ + +/* cccr_sdio_rev */ +#define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ +#define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ + +/* sd_rev */ +#define SDIO_REV_PHY_MASK 0x0f /* SD format version number */ +#define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ +#define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ +#define SDIO_INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ +#define SDIO_INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ +#define SDIO_INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ +#define SDIO_IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ +#define SDIO_IO_ABORT_FUNC_MASK 0x07 /* abort selection: function x */ +#define SDIO_BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ +#define SDIO_BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ +#define SDIO_BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ +#define SDIO_BUS_DATA_WIDTH_MASK 0x03 /* bus width mask */ +#define SDIO_BUS_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ +#define SDIO_BUS_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ + +/* capability */ +#define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ +#define SDIO_CAP_LSC 0x40 /* low speed card */ +#define SDIO_CAP_E4MI 0x20 /* enable int between block in 4-bit mode */ +#define SDIO_CAP_S4MI 0x10 /* support int between block in 4-bit mode */ +#define SDIO_CAP_SBS 0x08 /* support suspend/resume */ +#define SDIO_CAP_SRW 0x04 /* support read wait */ +#define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ +#define SDIO_CAP_SDC 0x01 /* Support Direct cmd during multi-uint8 transfer */ + +/* CIA FBR1 registers */ +#define SDIO_FUNC1_INFO 0x100 /* basic info for function 1 */ +#define SDIO_FUNC1_EXT 0x101 /* extension of standard I/O device */ +#define SDIO_CIS_FUNC1_BASE_LOW 0x109 /* function 1 cis address bit 0-7 */ +#define SDIO_CIS_FUNC1_BASE_MID 0x10A /* function 1 cis address bit 8-15 */ +#define SDIO_CIS_FUNC1_BASE_HIGH 0x10B /* function 1 cis address bit 16 */ +#define SDIO_CSA_BASE_LOW 0x10C /* CSA base address uint8_t 0 */ +#define SDIO_CSA_BASE_MID 0x10D /* CSA base address uint8_t 1 */ +#define SDIO_CSA_BASE_HIGH 0x10E /* CSA base address uint8_t 2 */ +#define SDIO_CSA_DATA_OFFSET 0x10F /* CSA data register */ +#define SDIO_IO_BLK_SIZE_LOW 0x110 /* I/O block size uint8_t 0 */ +#define SDIO_IO_BLK_SIZE_HIGH 0x111 /* I/O block size uint8_t 1 */ + +/* SD_SDIO_FUNC1_INFO bits */ +#define SDIO_FUNC1_INFO_DIC 0x0f /* device interface code */ +#define SDIO_FUNC1_INFO_CSA 0x40 /* CSA support flag */ +#define SDIO_FUNC1_INFO_CSA_EN 0x80 /* CSA enabled */ + +/* SD_SDIO_FUNC1_EXT bits */ +#define SDIO_FUNC1_EXT_SHP 0x03 /* support high power */ +#define SDIO_FUNC1_EXT_EHP 0x04 /* enable high power */ + +/* devctr */ +/* I/O device interface code */ +#define SDIO_DEVCTR_DEVINTER 0x0f +/* support CSA */ +#define SDIO_DEVCTR_CSA_SUP 0x40 +/* enable CSA */ +#define SDIO_DEVCTR_CSA_EN 0x80 + +/* ext_dev */ +/* supports high-power mask */ +#define SDIO_HIGHPWR_SUPPORT_M 0x3 +/* enable high power */ +#define SDIO_HIGHPWR_EN 0x4 +/* standard power function(up to 200mA */ +#define SDIO_HP_STD 0 +/* need high power to operate */ +#define SDIO_HP_REQUIRED 0x2 +/* can work with standard power, but prefer high power */ +#define SDIO_HP_DESIRED 0x3 + +/* misc define */ +/* macro to calculate fbr register base */ +#define FBR_REG_BASE(n) (n*0x100) +#define SDIO_FUNC_0 0 +#define SDIO_FUNC_1 1 +#define SDIO_FUNC_2 2 +#define SDIO_FUNC_3 3 +#define SDIO_FUNC_4 4 +#define SDIO_FUNC_5 5 +#define SDIO_FUNC_6 6 +#define SDIO_FUNC_7 7 + +/* maximum block size for block mode operation */ +#define SDIO_MAX_BLOCK_SIZE 2048 +/* minimum block size for block mode operation */ +#define SDIO_MIN_BLOCK_SIZE 1 + +/* Card registers: status bit position */ +#define SDIO_STATUS_OUTOFRANGE 31 +#define SDIO_STATUS_COMCRCERROR 23 +#define SDIO_STATUS_ILLEGALCOMMAND 22 +#define SDIO_STATUS_ERROR 19 +#define SDIO_STATUS_IOCURRENTSTATE3 12 +#define SDIO_STATUS_IOCURRENTSTATE2 11 +#define SDIO_STATUS_IOCURRENTSTATE1 10 +#define SDIO_STATUS_IOCURRENTSTATE0 9 +#define SDIO_STATUS_FUN_NUM_ERROR 4 + +#define GET_SDIOCARD_STATUS(x) ((x >> 9) & 0x0f) +#define SDIO_STATUS_STATE_IDLE 0 +#define SDIO_STATUS_STATE_READY 1 +#define SDIO_STATUS_STATE_IDENT 2 +#define SDIO_STATUS_STATE_STBY 3 +#define SDIO_STATUS_STATE_TRAN 4 +#define SDIO_STATUS_STATE_DATA 5 +#define SDIO_STATUS_STATE_RCV 6 +#define SDIO_STATUS_STATE_PRG 7 +#define SDIO_STATUS_STATE_DIS 8 + +/* sprom */ +#define SBSDIO_SPROM_CS 0x10000 /* command and status */ +#define SBSDIO_SPROM_INFO 0x10001 /* info register */ +#define SBSDIO_SPROM_DATA_LOW 0x10002 /* indirect access data uint8_t 0 */ +#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* indirect access data uint8_t 1 */ +#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* indirect access addr uint8_t 0 */ +#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* indirect access addr uint8_t 0 */ +#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu data output */ +#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu enable */ +#define SBSDIO_WATERMARK 0x10008 /* retired in rev 7 */ +#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */ + +#define SBSDIO_SPROM_IDLE 0 +#define SBSDIO_SPROM_WRITE 1 +#define SBSDIO_SPROM_READ 2 +#define SBSDIO_SPROM_WEN 4 +#define SBSDIO_SPROM_WDS 7 +#define SBSDIO_SPROM_DONE 8 + +/* SBSDIO_SPROM_INFO */ +#define SBSDIO_SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */ +#define SBSDIO_SROM_BLANK 0x04 /* depreciated in corerev 6 */ +#define SBSDIO_SROM_OTP 0x80 /* OTP present */ + +/* SBSDIO_CHIP_CTRL */ +/* or'd with onchip xtal_pu, 1: power on oscillator */ +#define SBSDIO_CHIP_CTRL_XTAL 0x01 + +/* SBSDIO_WATERMARK */ +/* number of bytes minus 1 for sd device to wait before sending data to host */ +#define SBSDIO_WATERMARK_MASK 0x3f + +/* SBSDIO_DEVICE_CTL */ +/* 1: device will assert busy signal when receiving CMD53 */ +#define SBSDIO_DEVCTL_SETBUSY 0x01 +/* 1: assertion of sdio interrupt is synchronous to the sdio clock */ +#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 + +/* function 1 OCP space */ +/* sb offset addr is <= 15 bits, 32k */ +#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF +#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 +/* sdsdio function 1 OCP space has 16/32 bit section */ +#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 + +/* direct(mapped) cis space */ +/* MAPPED common CIS address */ +#define SBSDIO_CIS_BASE_COMMON 0x1000 +/* function 0(common) cis size in bytes */ +#define SBSDIO_CIS_FUNC0_LIMIT 0x020 +/* funciton 1 cis size in bytes */ +#define SBSDIO_CIS_SIZE_LIMIT 0x200 +/* cis offset addr is < 17 bits */ +#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF +/* manfid tuple length, include tuple, link bytes */ +#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 + +/* indirect cis access (in sprom) */ +/* 8 control bytes first, CIS starts from 8th uint8_t */ +#define SBSDIO_SPROM_CIS_OFFSET 0x8 +/* sdio uint8_t mode: maximum length of one data comamnd */ +#define SBSDIO_BYTEMODE_DATALEN_MAX 64 +/* 4317 supports less */ +#define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52 +/* sdio core function one address mask */ +#define SBSDIO_CORE_ADDR_MASK 0x1FFFF + +/* CEATA defines */ +#define CEATA_EXT_CSDBLOCK_SIZE 512 +#define CEATA_FAST_IO 39 +#define CEATA_MULTIPLE_REGISTER_RW 60 +#define CEATA_MULTIPLE_BLOCK_RW 61 + +/* defines CE ATA task file registers */ +#define CEATA_SCT_CNT_EXP_REG 0x02 +#define CEATA_LBA_LOW_EXP_REG 0x03 +#define CEATA_LBA_MID_EXP_REG 0x04 +#define CEATA_LBA_HIGH_EXP_REG 0x05 +#define CEATA_CNTRL_REG 0x06 +#define CEATA_FEATURE_REG 0x09 /* write */ +#define CEATA_ERROR_REG 0x09 /* read */ +#define CEATA_SCT_CNT_REG 0x0A +#define CEATA_LBA_LOW_REG 0x0B +#define CEATA_LBA_MID_REG 0x0C +#define CEATA_LBA_HIGH_REG 0x0D +#define CEATA_DEV_HEAD_REG 0x0E +#define CEATA_STA_REG 0x0F /* read */ +#define CEATA_CMD_REG 0x0F /* write */ + +/* defines CEATA control and status registers for ce ata client driver */ +#define CEATA_SCR_TEMPC_REG 0x80 +#define CEATA_SCR_TEMPMAXP_REG 0x84 +#define CEATA_TEMPMINP_REG 0x88 +#define CEATA_SCR_STATUS_REG 0x8C +#define CEATA_SCR_REALLOCSA_REG 0x90 +#define CEATA_SCR_ERETRACTSA_REG 0x94 +#define CEATA_SCR_CAPABILITIES_REG 0x98 +#define CEATA_SCR_CONTROL_REG 0xC0 + +/* defines for SCR capabilities register bits for ce ata client driver */ +#define CEATA_SCR_CAP_512 0x00000001 +#define CEATA_SCR_CAP_1K 0x00000002 +#define CEATA_SCR_CAP_4K 0x00000004 + +/* defines CE ATA Control reg bits for ce ata client driver */ +#define CEATA_CNTRL_ENABLE_INTR 0x00 +#define CEATA_CNTRL_DISABLE_INTR 0x02 +#define CEATA_CNTRL_SRST 0x04 +#define CEATA_CNTRL_RSRST 0x00 + +/* define CE ATA Status reg bits for ce ata client driver */ +#define CEATA_STA_ERROR_BIT 0x01 +#define CEATA_STA_OVR_BIT 0x02 +#define CEATA_STA_SPT_BIT 0x04 +#define CEATA_STA_DRQ_BIT 0x08 +#define CEATA_STA_DRDY_BIT 0x40 +#define CEATA_STA_BSY_BIT 0x80 + +/* define CE ATA Error reg bits for ce ata client driver */ +#define CEATA_ERROR_ABORTED_BIT 0x04 +#define CEATA_ERROR_IDNF_BIT 0x10 +#define CEATA_ERROR_UNCORRECTABLE_BIT 0x40 +#define CEATA_ERROR_ICRC_BIT 0x80 + +/* define CE ATA Commands for ce ata client driver */ +#define CEATA_CMD_IDENTIFY_DEVICE 0xEC +#define CEATA_CMD_READ_DMA_EXT 0x25 +#define CEATA_CMD_WRITE_DMA_EXT 0x35 +#define CEATA_CMD_STANDBY_IMMEDIATE 0xE0 +#define CEATA_CMD_FLUSH_CACHE_EXT 0xEA + +struct csd_mmc { + uint32_t padding:8; + uint32_t structure:2; + uint32_t csdSpecVer:4; + uint32_t reserved1:2; + uint32_t taac:8; + uint32_t nsac:8; + uint32_t speed:8; + uint32_t classes:12; + uint32_t rdBlkLen:4; + uint32_t rdBlkPartial:1; + uint32_t wrBlkMisalign:1; + uint32_t rdBlkMisalign:1; + uint32_t dsr:1; + uint32_t reserved2:2; + uint32_t size:12; + uint32_t vddRdCurrMin:3; + uint32_t vddRdCurrMax:3; + uint32_t vddWrCurrMin:3; + uint32_t vddWrCurrMax:3; + uint32_t devSizeMulti:3; + uint32_t eraseGrpSize:5; + uint32_t eraseGrpSizeMulti:5; + uint32_t wrProtGroupSize:5; + uint32_t wrProtGroupEnable:1; + uint32_t manuDefEcc:2; + uint32_t wrSpeedFactor:3; + uint32_t wrBlkLen:4; + uint32_t wrBlkPartial:1; + uint32_t reserved5:4; + uint32_t protAppl:1; + uint32_t fileFormatGrp:1; + uint32_t copyFlag:1; + uint32_t permWrProt:1; + uint32_t tmpWrProt:1; + uint32_t fileFormat:2; + uint32_t eccCode:2; +}; + +/* CSD register*/ +union sd_csd { + uint32_t csd[4]; + struct csd_mmc mmc; +}; + +struct sd_card_data { + union sd_csd csd; +}; +#endif /* CSL_SD_PROT_H */ diff --git a/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h b/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h new file mode 100644 index 0000000..8e61b51 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PBOOT_HAL_MEMORY_EMMC_DRV_H +#define PBOOT_HAL_MEMORY_EMMC_DRV_H + +#include <drivers/delay_timer.h> + +#include "emmc_chal_types.h" +#include "emmc_chal_sd.h" +#include "emmc_csl_sdprot.h" +#include "emmc_csl_sdcmd.h" +#include "emmc_csl_sd.h" +#include "emmc_brcm_rdb_sd4_top.h" + +#define CLK_SDIO_DIV_52MHZ 0x0 +#define SYSCFG_IOCR4_PAD_10MA 0x38000000 + +#define SDCLK_CNT_PER_MS 52000 +#define BOOT_ACK_TIMEOUT (50 * SDCLK_CNT_PER_MS) +#define BOOT_DATA_TIMEOUT (1000 * SDCLK_CNT_PER_MS) + +#define EMMC_BOOT_OK 0 +#define EMMC_BOOT_ERROR 1 +#define EMMC_BOOT_TIMEOUT 2 +#define EMMC_BOOT_INVALIDIMAGE 3 +#define EMMC_BOOT_NO_CARD 4 + +#define EMMC_USER_AREA 0 +#define EMMC_BOOT_PARTITION1 1 +#define EMMC_BOOT_PARTITION2 2 +#define EMMC_USE_CURRENT_PARTITION 3 + +#define EMMC_BOOT_PARTITION_SIZE (128*1024) +#define EMMC_BLOCK_SIZE 512 +#define EMMC_DMA_SIZE (4*1024) + +/* + * EMMC4.3 definitions + * Table 6 EXT_CSD access mode + * Access + * Bits Access Name Operation + * 00 Command Set The command set is changed according to the Cmd Set field of + * the argument + * 01 Set Bits The bits in the pointed uint8_t are set, + * according to the 1 bits in the Value field. + * 10 Clear Bits The bits in the pointed uint8_t are cleared, + * according to the 1 bits in the Value field. + * 11 Write Byte The Value field is written into the pointed uint8_t. + */ + +#define SDIO_HW_EMMC_EXT_CSD_WRITE_BYTE 0X03000000 + +/* Boot bus width1 BOOT_BUS_WIDTH 1 R/W [177] */ +#define SDIO_HW_EMMC_EXT_CSD_BOOT_BUS_WIDTH_OFFSET 0X00B10000 + +/* Boot configuration BOOT_CONFIG 1 R/W [179] */ +#define SDIO_HW_EMMC_EXT_CSD_BOOT_CONFIG_OFFSET 0X00B30000 + +/* Bus width mode BUS_WIDTH 1 WO [183] */ +#define SDIO_HW_EMMC_EXT_CSD_BUS_WIDTH_OFFSET 0X00B70000 + +/* + * Bit 6: BOOT_ACK (non-volatile) + * 0x0 : No boot acknowledge sent (default) + * 0x1 : Boot acknowledge sent during boot operation + * Bit[5:3] : BOOT_PARTITION_ENABLE (non-volatile) + * User selects boot data that will be sent to master + * 0x0 : Device not boot enabled (default) + * 0x1 : Boot partition 1 enabled for boot + * 0x2 : Boot partition 2 enabled for boot + * 0x3-0x6 : Reserved + * 0x7 : User area enabled for boot + * Bit[2:0] : BOOT_PARTITION_ACCESS + * User selects boot partition for read and write operation + * 0x0 : No access to boot partition (default) + * 0x1 : R/W boot partition 1 + * 0x2 : R/W boot partition 2 + * 0x3-0x7 : Reserved + */ + +#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT1 0X00000100 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT2 0X00000200 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_USER 0X00000000 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT1 0X00004800 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT2 0X00005000 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_USER 0X00007800 + +#define SD_US_DELAY(x) udelay(x) + +#endif diff --git a/include/drivers/brcm/fru.h b/include/drivers/brcm/fru.h new file mode 100644 index 0000000..ee863b4 --- /dev/null +++ b/include/drivers/brcm/fru.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FRU_H +#define FRU_H + +#include <stdbool.h> +#include <stdint.h> + +/* max string length */ +#define FRU_MAX_STR_LEN 32 + +/* max number of DDR channels */ +#define BCM_MAX_NR_DDR 3 + +/* max supported FRU table size */ +#define BCM_MAX_FRU_LEN 512 + +/* FRU table starting offset */ +#define BCM_FRU_TBL_OFFSET 0x300000 + +/* FRU time constants */ +#define MINS_PER_DAY 1440 +#define MINS_PER_HOUR 60 +#define FRU_YEAR_START 1996 +#define FRU_MONTH_START 1 +#define FRU_DAY_START 1 +#define MONTHS_PER_YEAR 12 + +/* + * FRU areas based on the spec + */ +enum fru_area_name { + FRU_AREA_INTERNAL = 0, + FRU_AREA_CHASSIS_INFO, + FRU_AREA_BOARD_INFO, + FRU_AREA_PRODUCT_INFO, + FRU_AREA_MRECORD_INFO, + FRU_MAX_NR_AREAS +}; + +/* + * FRU area information + * + * @use: indicate this area is being used + * @version: format version + * @offset: offset of this area from the beginning of the FRU table + * @len: total length of the area + */ +struct fru_area_info { + bool use; + uint8_t version; + unsigned int offset; + unsigned int len; +}; + +/* + * DDR MCB information + * + * @idx: DDR channel index + * @size_mb: DDR size of this channel in MB + * @ref_id: DDR MCB reference ID + */ +struct ddr_mcb { + unsigned int idx; + unsigned int size_mb; + uint32_t ref_id; +}; + +/* + * DDR information + * + * @ddr_info: array that contains MCB related info for each channel + */ +struct ddr_info { + struct ddr_mcb mcb[BCM_MAX_NR_DDR]; +}; + +/* + * FRU board area information + * + * @lang: Language code + * @mfg_date: Manufacturing date + * @manufacturer: Manufacturer + * @product_name: Product name + * @serial_number: Serial number + * @part_number: Part number + * @file_id: FRU file ID + */ +struct fru_board_info { + unsigned char lang; + unsigned int mfg_date; + unsigned char manufacturer[FRU_MAX_STR_LEN]; + unsigned char product_name[FRU_MAX_STR_LEN]; + unsigned char serial_number[FRU_MAX_STR_LEN]; + unsigned char part_number[FRU_MAX_STR_LEN]; + unsigned char file_id[FRU_MAX_STR_LEN]; +}; + +/* + * FRU manufacture date in human readable format + */ +struct fru_time { + unsigned int min; + unsigned int hour; + unsigned int day; + unsigned int month; + unsigned int year; +}; + +#ifdef USE_FRU +int fru_validate(uint8_t *data, struct fru_area_info *fru_area); +int fru_parse_ddr(uint8_t *data, struct fru_area_info *area, + struct ddr_info *ddr); +int fru_parse_board(uint8_t *data, struct fru_area_info *area, + struct fru_board_info *board); +void fru_format_time(unsigned int min, struct fru_time *tm); +#else +static inline int fru_validate(uint8_t *data, struct fru_area_info *fru_area) +{ + return -1; +} + +static inline int fru_parse_ddr(uint8_t *data, struct fru_area_info *area, + struct ddr_info *ddr) +{ + return -1; +} + +static inline int fru_parse_board(uint8_t *data, struct fru_area_info *area, + struct fru_board_info *board) +{ + return -1; +} + +static inline void fru_format_time(unsigned int min, struct fru_time *tm) +{ +} +#endif /* USE_FRU */ + +#endif /* FRU_H */ diff --git a/include/drivers/brcm/i2c/i2c.h b/include/drivers/brcm/i2c/i2c.h new file mode 100644 index 0000000..24d42e2 --- /dev/null +++ b/include/drivers/brcm/i2c/i2c.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2016 - 2021, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef I2C_H +#define I2C_H + +#include <stdint.h> + +#define I2C_SPEED_100KHz 100000 +#define I2C_SPEED_400KHz 400000 +#define I2C_SPEED_DEFAULT I2C_SPEED_100KHz + +/* + * Function Name: i2c_probe + * + * Description: + * This function probes the I2C bus for the existence of the specified + * device. + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_probe(uint32_t bus_id, uint8_t devaddr); + +/* + * Function Name: i2c_init + * + * Description: + * This function initializes the SMBUS. + * + * Parameters: + * bus_id - I2C bus ID + * speed - I2C bus speed in Hz + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_init(uint32_t bus_id, int speed); + +/* + * Function Name: i2c_set_bus_speed + * + * Description: + * This function configures the SMBUS speed + * + * Parameters: + * bus_id - I2C bus ID + * speed - I2C bus speed in Hz + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_set_bus_speed(uint32_t bus_id, uint32_t speed); + +/* + * Function Name: i2c_get_bus_speed + * + * Description: + * This function returns the SMBUS speed. + * + * Parameters: + * bus_id - I2C bus ID + * + * Return: + * Bus speed in Hz, 0 on failure + */ +uint32_t i2c_get_bus_speed(uint32_t bus_id); + +/* + * Function Name: i2c_recv_byte + * + * Description: + * This function reads I2C data from a device without specifying + * a command regsiter. + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * value - Data Read + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value); + +/* + * Function Name: i2c_send_byte + * + * Description: + * This function send I2C data to a device without specifying + * a command regsiter. + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * value - Data Send + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_send_byte(uint32_t bus_id, uint8_t devaddr, uint8_t value); + +/* + * Function Name: i2c_read + * + * Description: + * This function reads I2C data from a device with a designated + * command register + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * addr - Register Offset + * alen - Address Length, 1 for byte, 2 for word (not supported) + * buffer - Data Buffer + * len - Data Length in bytes + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_read(uint32_t bus_id, + uint8_t devaddr, + uint32_t addr, + int alen, + uint8_t *buffer, + int len); + +/* + * Function Name: i2c_write + * + * Description: + * This function write I2C data to a device with a designated + * command register + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * addr - Register Offset + * alen - Address Length, 1 for byte, 2 for word (not supported) + * buffer - Data Buffer + * len - Data Length in bytes + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_write(uint32_t bus_id, + uint8_t devaddr, + uint32_t addr, + int alen, + uint8_t *buffer, + int len); + + +#endif /* I2C_H */ diff --git a/include/drivers/brcm/i2c/i2c_regs.h b/include/drivers/brcm/i2c/i2c_regs.h new file mode 100644 index 0000000..74ea824 --- /dev/null +++ b/include/drivers/brcm/i2c/i2c_regs.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2016 - 2021, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef I2C_REGS +#define I2C_REGS + +/* SMBUS Config register */ +#define SMB_CFG_REG 0x0U + +#define SMB_CFG_RST_MASK 0x80000000U +#define SMB_CFG_RST_SHIFT 31U + +#define SMB_CFG_SMBEN_MASK 0x40000000U +#define SMB_CFG_SMBEN_SHIFT 30U + +#define SMB_CFG_BITBANGEN_MASK 0x20000000U +#define SMB_CFG_BITBANGEN_SHIFT 29U + +#define SMB_CFG_EN_NIC_SMBADDR0_MASK 0x10000000U +#define SMB_CFG_EN_NIC_SMBADDR0_SHIFT 28U + +#define SMB_CFG_PROMISCMODE_MASK 0x08000000U +#define SMB_CFG_PROMISCMODE_SHIFT 27U + +#define SMB_CFG_TSTMPCNTEN_MASK 0x04000000U +#define SMB_CFG_TSTMPCNTEN_SHIFT 26U + +#define SMB_CFG_MSTRRTRYCNT_MASK 0x000F0000U +#define SMB_CFG_MSTRRTRYCNT_SHIFT 16U + +/* SMBUS Timing config register */ +#define SMB_TIMGCFG_REG 0x4U + +#define SMB_TIMGCFG_MODE400_MASK 0x80000000U +#define SMB_TIMGCFG_MODE400_SHIFT 31U + +#define SMB_TIMGCFG_RNDSLVSTR_MASK 0x7F000000U +#define SMB_TIMGCFG_RNDSLVSTR_SHIFT 24U + +#define SMB_TIMGCFG_PERSLVSTR_MASK 0x00FF0000U +#define SMB_TIMGCFG_PERSLVSTR_SHIFT 16U + +#define SMB_TIMGCFG_IDLTIME_MASK 0x0000FF00U +#define SMB_TIMGCFG_IDLTIME_SHIFT 8U + +/* SMBUS Slave address register */ +#define SMB_ADDR_REG 0x8U + +#define SMB_EN_NIC_SMBADDR3_MASK 0x80000000U +#define SMB_EN_NIC_SMBADDR3_SHIFT 31U + +#define SMB_NIC_SMBADDR3_MASK 0x7F000000U +#define SMB_NIC_SMBADDR3_SHIFT 24U + +#define SMB_EN_NIC_SMBADDR2_MASK 0x00800000U +#define SMB_EN_NIC_SMBADDR2_SHIFT 23U + +#define SMB_NIC_SMBADDR2_MASK 0x007F0000U +#define SMB_NIC_SMBADDR2_SHIFT 16U + +#define SMB_EN_NIC_SMBADDR1_MASK 0x00008000U +#define SMB_EN_NIC_SMBADDR1_SHIFT 15U + +#define SMB_NIC_SMBADDR1_MASK 0x00007F00U +#define SMB_NIC_SMBADDR1_SHIFT 8U + +#define SMB_EN_NIC_SMBADDR0_MASK 0x00000080U +#define SMB_EN_NIC_SMBADDR0_SHIFT 7U + +#define SMB_NIC_SMBADDR0_MASK 0x0000007FU +#define SMB_NIC_SMBADDR0_SHIFT 0U + +/* SMBUS Master FIFO control register */ +#define SMB_MSTRFIFOCTL_REG 0xCU + +#define SMB_MSTRRXFIFOFLSH_MASK 0x80000000U +#define SMB_MSTRRXFIFOFLSH_SHIFT 31U + +#define SMB_MSTRTXFIFOFLSH_MASK 0x40000000U +#define SMB_MSTRTXFIFOFLSH_SHIFT 30U + +#define SMB_MSTRRXPKTCNT_MASK 0x007F0000U +#define SMB_MSTRRXPKTCNT_SHIFT 16U + +#define SMB_MSTRRXFIFOTHR_MASK 0x00003F00U +#define SMB_MSTRRXFIFOTHR_SHIFT 8U + +/* SMBUS Slave FIFO control register */ +#define SMB_SLVFIFOCTL_REG 0x10U + +#define SMB_SLVRXFIFOFLSH_MASK 0x80000000U +#define SMB_SLVRXFIFOFLSH_SHIFT 31U + +#define SMB_SLVTXFIFOFLSH_MASK 0x40000000U +#define SMB_SLVTXFIFOFLSH_SHIFT 30U + +#define SMB_SLVRXPKTCNT_MASK 0x007F0000U +#define SMB_SLVRXPKTCNT_SHIFT 16U + +#define SMB_SLVRXFIFOTHR_MASK 0x00003F00U +#define SMB_SLVRXFIFOTHR_SHIFT 8U + +/* SMBUS Bit-bang mode control register */ +#define SMB_BITBANGCTL_REG 0x14U + +#define SMB_SMBCLKIN_MASK 0x80000000U +#define SMB_SMBCLKIN_SHIFT 31U + +#define SMB_SMBCLKOUTEN_MASK 0x40000000U +#define SMB_SMBCLKOUTEN_SHIFT 30U + +#define SMB_SMBDATAIN_MASK 0x20000000U +#define SMB_SMBDATAIN_SHIFT 29U + +#define SMB_SMBDATAOUTEN_MASK 0x10000000U +#define SMB_SMBDATAOUTEN_SHIFT 28U + +/* SMBUS Master command register */ +#define SMB_MSTRCMD_REG 0x30U + +#define SMB_MSTRSTARTBUSYCMD_MASK 0x80000000U +#define SMB_MSTRSTARTBUSYCMD_SHIFT 31U + +#define SMB_MSTRABORT_MASK 0x40000000U +#define SMB_MSTRABORT_SHIFT 30U + +#define SMB_MSTRSTS_MASK 0x0E000000U +#define SMB_MSTRSTS_SHIFT 25U + +#define SMB_MSTRSMBUSPROTO_MASK 0x00001E00U +#define SMB_MSTRSMBUSPROTO_SHIFT 9U + +#define SMB_MSTRPEC_MASK 0x00000100U +#define SMB_MSTRPEC_SHIFT 8U + +#define SMB_MSTRRDBYTECNT_MASK 0x000000FFU +#define SMB_MSTRRDBYTECNT_SHIFT 0U + +/* SMBUS Slave command register */ +#define SMB_SLVCMD_REG 0x34U + +#define SMB_SLVSTARTBUSYCMD_MASK 0x80000000U +#define SMB_SLVSTARTBUSYCMD_SHIFT 31U + +#define SMB_SLVABORT_MASK 0x40000000U +#define SMB_SLVABORT_SHIFT 30U + +#define SMB_SLVSTS_MASK 0x03800000U +#define SMB_SLVSTS_SHIFT 23U + +#define SMB_SLVPEC_MASK 0x00000100U +#define SMB_SLVPEC_SHIFT 8U + +/* SMBUS Event enable register */ +#define SMB_EVTEN_REG 0x38U + +#define SMB_MSTRRXFIFOFULLEN_MASK 0x80000000U +#define SMB_MSTRRXFIFOFULLEN_SHIFT 31U + +#define SMB_MSTRRXFIFOTHRHITEN_MASK 0x40000000U +#define SMB_MSTRRXFIFOTHRHITEN_SHIFT 30U + +#define SMB_MSTRRXEVTEN_MASK 0x20000000U +#define SMB_MSTRRXEVTEN_SHIFT 29U + +#define SMB_MSTRSTARTBUSYEN_MASK 0x10000000U +#define SMB_MSTRSTARTBUSYEN_SHIFT 28U + +#define SMB_MSTRTXUNDEN_MASK 0x08000000U +#define SMB_MSTRTXUNDEN_SHIFT 27U + +#define SMB_SLVRXFIFOFULLEN_MASK 0x04000000U +#define SMB_SLVRXFIFOFULLEN_SHIFT 26U + +#define SMB_SLVRXFIFOTHRHITEN_MASK 0x02000000U +#define SMB_SLVRXFIFOTHRHITEN_SHIFT 25U + +#define SMB_SLVRXEVTEN_MASK 0x01000000U +#define SMB_SLVRXEVTEN_SHIFT 24U + +#define SMB_SLVSTARTBUSYEN_MASK 0x00800000U +#define SMB_SLVSTARTBUSYEN_SHIFT 23U + +#define SMB_SLVTXUNDEN_MASK 0x00400000U +#define SMB_SLVTXUNDEN_SHIFT 22U + +#define SMB_SLVRDEVTEN_MASK 0x00200000U +#define SMB_SLVRDEVTEN_SHIFT 21U + +/* SMBUS Event status register */ +#define SMB_EVTSTS_REG 0x3CU + +#define SMB_MSTRRXFIFOFULLSTS_MASK 0x80000000U +#define SMB_MSTRRXFIFOFULLSTS_SHIFT 31U + +#define SMB_MSTRRXFIFOTHRHITSTS_MASK 0x40000000U +#define SMB_MSTRRXFIFOTHRHITSTS_SHIFT 30U + +#define SMB_MSTRRXEVTSTS_MASK 0x20000000U +#define SMB_MSTRRXEVTSTS_SHIFT 29U + +#define SMB_MSTRSTARTBUSYSTS_MASK 0x10000000U +#define SMB_MSTRSTARTBUSYSTS_SHIFT 28U + +#define SMB_MSTRTXUNDSTS_MASK 0x08000000U +#define SMB_MSTRTXUNDSTS_SHIFT 27U + +#define SMB_SLVRXFIFOFULLSTS_MASK 0x04000000U +#define SMB_SLVRXFIFOFULLSTS_SHIFT 26U + +#define SMB_SLVRXFIFOTHRHITSTS_MASK 0x02000000U +#define SMB_SLVRXFIFOTHRHITSTS_SHIFT 25U + +#define SMB_SLVRXEVTSTS_MASK 0x01000000U +#define SMB_SLVRXEVTSTS_SHIFT 24U + +#define SMB_SLVSTARTBUSYSTS_MASK 0x00800000U +#define SMB_SLVSTARTBUSYSTS_SHIFT 23U + +#define SMB_SLVTXUNDSTS_MASK 0x00400000U +#define SMB_SLVTXUNDSTS_SHIFT 22U + +#define SMB_SLVRDEVTSTS_MASK 0x00200000U +#define SMB_SLVRDEVTSTS_SHIFT 21U + +/* SMBUS Master data write register */ +#define SMB_MSTRDATAWR_REG 0x40U + +#define SMB_MSTRWRSTS_MASK 0x80000000U +#define SMB_MSTRWRSTS_SHIFT 31U + +#define SMB_MSTRWRDATA_MASK 0x000000FFU +#define SMB_MSTRWRDATA_SHIFT 0U + +/* SMBUS Master data read register */ +#define SMB_MSTRDATARD_REG 0x44U + +#define SMB_MSTRRDSTS_MASK 0xC0000000U +#define SMB_MSTRRDSTS_SHIFT 30U + +#define SMB_MSTRRDPECERR_MASK 0x20000000U +#define SMB_MSTRRDPECERR_SHIFT 29U + +#define SMB_MSTRRDDATA_MASK 0x000000FFU +#define SMB_MSTRRDDATA_SHIFT 0U + +/* SMBUS Slave data write register */ +#define SMB_SLVDATAWR_REG 0x48U + +#define SMB_SLVWRSTS_MASK 0x80000000U +#define SMB_SLVWRSTS_SHIFT 31U + +#define SMB_SLVWRDATA_MASK 0x000000FFU +#define SMB_SLVWRDATA_SHIFT 0U + +/* SMBUS Slave data read register */ +#define SMB_SLVDATARD_REG 0x4CU + +#define SMB_SLVRDSTS_MASK 0xC0000000U +#define SMB_SLVRDSTS_SHIFT 30U + +#define SMB_SLVRDERRSTS_MASK 0x30000000U +#define SMB_SLVRDERRSTS_SHIFT 28U + +#define SMB_SLVRDDATA_MASK 0x000000FFU +#define SMB_SLVRDDATA_SHIFT 0U + +#endif /* I2C_REGS */ diff --git a/include/drivers/brcm/iproc_gpio.h b/include/drivers/brcm/iproc_gpio.h new file mode 100644 index 0000000..be971f6 --- /dev/null +++ b/include/drivers/brcm/iproc_gpio.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IPROC_GPIO_H +#define IPROC_GPIO_H + +#ifdef USE_GPIO +void iproc_gpio_init(uintptr_t base, int nr_gpios, uintptr_t pinmux_base, + uintptr_t pinconf_base); +#else +static void iproc_gpio_init(uintptr_t base, int nr_gpios, uintptr_t pinmux_base, + uintptr_t pinconf_base) +{ +} +#endif /* IPROC_GPIO */ + +#endif /* IPROC_GPIO_H */ diff --git a/include/drivers/brcm/mdio/mdio.h b/include/drivers/brcm/mdio/mdio.h new file mode 100644 index 0000000..b27c7b3 --- /dev/null +++ b/include/drivers/brcm/mdio/mdio.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2016 - 2021, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MDIO_H +#define MDIO_H + +#define CMIC_MIIM_PARAM (PLAT_CMIC_MIIM_BASE + 0x23cU) +#define MDIO_PARAM_MIIM_CYCLE 29U +#define MDIO_PARAM_INTERNAL_SEL 25U +#define MDIO_PARAM_BUSID 22U +#define MDIO_PARAM_BUSID_MASK 0x7U +#define MDIO_PARAM_C45_SEL 21U +#define MDIO_PARAM_PHYID 16U +#define MDIO_PARAM_PHYID_MASK 0x1FU +#define MDIO_PARAM_DATA 0U +#define MDIO_PARAM_DATA_MASK 0xFFFFU +#define CMIC_MIIM_READ_DATA (PLAT_CMIC_MIIM_BASE + 0x240U) +#define MDIO_READ_DATA_MASK 0xffffU +#define CMIC_MIIM_ADDRESS (PLAT_CMIC_MIIM_BASE + 0x244U) +#define CMIC_MIIM_CTRL (PLAT_CMIC_MIIM_BASE + 0x248U) +#define MDIO_CTRL_WRITE_OP 0x1U +#define MDIO_CTRL_READ_OP 0x2U +#define CMIC_MIIM_STAT (PLAT_CMIC_MIIM_BASE + 0x24cU) +#define MDIO_STAT_DONE 1U + +int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val); +int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg); +#endif /* MDIO_H */ diff --git a/include/drivers/brcm/ocotp.h b/include/drivers/brcm/ocotp.h new file mode 100644 index 0000000..830b3e4 --- /dev/null +++ b/include/drivers/brcm/ocotp.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef OCOTP_H +#define OCOTP_H + +#include <stdint.h> + +struct otpc_map { + /* in words. */ + uint32_t otpc_row_size; + /* 128 bit row / 4 words support. */ + uint16_t data_r_offset[4]; + /* 128 bit row / 4 words support. */ + uint16_t data_w_offset[4]; + int word_size; + int stride; +}; + +int bcm_otpc_init(struct otpc_map *map); +int bcm_otpc_read(unsigned int offset, void *val, uint32_t bytes, + uint32_t ecc_flag); + +#endif /* OCOTP_H */ diff --git a/include/drivers/brcm/scp.h b/include/drivers/brcm/scp.h new file mode 100644 index 0000000..7806314 --- /dev/null +++ b/include/drivers/brcm/scp.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_H +#define SCP_H + +#include <stdint.h> + +int download_scp_patch(void *image, unsigned int image_size); + +#endif /* SCP_H */ diff --git a/include/drivers/brcm/sf.h b/include/drivers/brcm/sf.h new file mode 100644 index 0000000..c32cbeb --- /dev/null +++ b/include/drivers/brcm/sf.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SF_H +#define SF_H + +#include <stdint.h> +#include <stddef.h> + +#ifdef SPI_DEBUG +#define SPI_DEBUG(fmt, ...) INFO(fmt, ##__VA_ARGS__) +#else +#define SPI_DEBUG(fmt, ...) +#endif + +#define SPI_FLASH_MAX_ID_LEN 6 + +#define CMD_WRSR 0x01 /* Write status register */ +#define CMD_PAGE_PROGRAM 0x02 +#define CMD_READ_NORMAL 0x03 +#define CMD_RDSR 0x05 +#define CMD_WRITE_ENABLE 0x06 +#define CMD_RDFSR 0x70 +#define CMD_READ_ID 0x9f +#define CMD_ERASE_4K 0x20 +#define CMD_ERASE_64K 0xd8 +#define ERASE_SIZE_64K (64 * 1024) + +/* Common status */ +#define STATUS_WIP BIT(0) + +struct spi_flash { + struct spi_slave *spi; + uint32_t size; + uint32_t page_size; + uint32_t sector_size; + uint32_t erase_size; + uint8_t erase_cmd; + uint8_t read_cmd; + uint8_t write_cmd; + uint8_t flags; +}; + +struct spi_flash_info { + const char *name; + + /* + * This array stores the ID bytes. + * The first three bytes are the JEDIC ID. + * JEDEC ID zero means "no ID" (mostly older chips). + */ + uint8_t id[SPI_FLASH_MAX_ID_LEN]; + uint8_t id_len; + + uint32_t sector_size; + uint32_t n_sectors; + uint16_t page_size; + + uint8_t flags; +}; + +/* Enum list - Full read commands */ +enum spi_read_cmds { + ARRAY_SLOW = BIT(0), + ARRAY_FAST = BIT(1), + DUAL_OUTPUT_FAST = BIT(2), + DUAL_IO_FAST = BIT(3), + QUAD_OUTPUT_FAST = BIT(4), + QUAD_IO_FAST = BIT(5), +}; + +/* sf param flags */ +enum spi_param_flag { + SECT_4K = BIT(0), + SECT_32K = BIT(1), + E_FSR = BIT(2), + SST_BP = BIT(3), + SST_WP = BIT(4), + WR_QPP = BIT(5), +}; + +int spi_flash_cmd_read(const uint8_t *cmd, size_t cmd_len, + void *data, size_t data_len); +int spi_flash_cmd(uint8_t cmd, void *response, size_t len); +int spi_flash_cmd_write(const uint8_t *cmd, size_t cmd_len, + const void *data, size_t data_len); +#endif diff --git a/include/drivers/brcm/sotp.h b/include/drivers/brcm/sotp.h new file mode 100644 index 0000000..a93d687 --- /dev/null +++ b/include/drivers/brcm/sotp.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2016-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOTP_H +#define SOTP_H + +#include <stddef.h> +#include <stdint.h> + +#include <platform_sotp.h> + +#define SOTP_ROW_NO_ECC 0 +#define SOTP_ROW_ECC 1 + +#define SOTP_STATUS_1 (SOTP_REGS_OTP_BASE + 0x001c) +#define SOTP_FAIL_BITS 0x18000000000 +#define SOTP_ECC_ERR_DETECT 0x8000000000000000 + +#define SOTP_REGS_SOTP_CHIP_STATES (SOTP_REGS_OTP_BASE + 0x0028) +#define SOTP_REGS_OTP_WR_LOCK (SOTP_REGS_OTP_BASE + 0x0038) + +#define SOTP_CHIP_STATES_MANU_DEBUG_MASK (1 << 8) +#define SOTP_DEVICE_SECURE_CFG0_OTP_ERASED_MASK (3 << 16) +#define SOTP_REGS_SOTP_CHIP_STATES_OTP_ERASED_MASK (1 << 16) + +#define SOTP_DEVICE_SECURE_CFG0_CID_MASK (3 << 2) +#define SOTP_DEVICE_SECURE_CFG0_AB_MASK (3 << 6) +#define SOTP_DEVICE_SECURE_CFG0_DEV_MASK (3 << 8) + +#define SOTP_BOOT_SOURCE_SHIFT 8 +/* bits 14 and 15 */ +#define SOTP_BOOT_SOURCE_ENABLE_MASK (0xC0 << SOTP_BOOT_SOURCE_SHIFT) +/* bits 8 to 13 */ +#define SOTP_BOOT_SOURCE_BITS0 (0x03 << SOTP_BOOT_SOURCE_SHIFT) +#define SOTP_BOOT_SOURCE_BITS1 (0x0C << SOTP_BOOT_SOURCE_SHIFT) +#define SOTP_BOOT_SOURCE_BITS2 (0x30 << SOTP_BOOT_SOURCE_SHIFT) +#define SOTP_BOOT_SOURCE_MASK (0x3F << SOTP_BOOT_SOURCE_SHIFT) + +#define SOTP_ATF_CFG_ROW_ID SOTP_DEVICE_SECURE_CFG2_ROW +/* bits 28 and 29 */ +#define SOTP_SBL_MASK (3 << 28) +/* bits 30 and 31 */ +#define SOTP_ATF_NVCOUNTER_ENABLE_MASK ((uint64_t)3 << 30) +/* bits 32 and 33 */ +#define SOTP_ATF_WATCHDOG_ENABLE_MASK ((uint64_t)3 << 32) +/* bits 34 and 35 */ +#define SOTP_ATF_PLL_ON ((uint64_t)3 << 34) +/* bits 36 and 37 */ +#define SOTP_ATF_RESET_RETRY ((uint64_t)3 << 36) +/* bits 38 to 40 */ +#define SOTP_ATF_LOG_LEVEL_SHIFT 38 +#define SOTP_ATF_LOG_LEVEL ((uint64_t)7 << SOTP_ATF_LOG_LEVEL_SHIFT) + +#define SOTP_ATF2_CFG_ROW_ID SOTP_DEVICE_SECURE_CFG3_ROW +/* bits 16 and 17 */ +#define SOTP_ROMKEY_MASK (3 << 16) +/* bits 18 and 19 */ +#define SOTP_EC_EN_MASK (3 << 18) + +#define SOTP_ENC_DEV_TYPE_AB_DEV ((uint64_t)0x19999800000) +#define SOTP_ENC_DEV_TYPE_MASK ((uint64_t)0x1ffff800000) + +uint64_t sotp_mem_read(uint32_t offset, uint32_t sotp_add_ecc); +void sotp_mem_write(uint32_t addr, uint32_t sotp_add_ecc, uint64_t wdata); +int sotp_read_key(uint8_t *key, size_t keysize, int start_row, int end_row); +int sotp_key_erased(void); +uint32_t sotp_redundancy_reduction(uint32_t sotp_row_data); +#endif diff --git a/include/drivers/brcm/spi.h b/include/drivers/brcm/spi.h new file mode 100644 index 0000000..9d92d8c --- /dev/null +++ b/include/drivers/brcm/spi.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPI_H +#define SPI_H + +#include <stdint.h> + +#define SPI_XFER_BEGIN (1 << 0) /* Assert CS before transfer */ +#define SPI_XFER_END (1 << 1) /* De-assert CS after transfer */ +#define SPI_XFER_QUAD (1 << 2) + +int spi_init(void); +int spi_claim_bus(void); +void spi_release_bus(void); +int spi_xfer(uint32_t bitlen, const void *dout, void *din, uint32_t flags); + +#endif /* _SPI_H_ */ diff --git a/include/drivers/brcm/spi_flash.h b/include/drivers/brcm/spi_flash.h new file mode 100644 index 0000000..bbaaa50 --- /dev/null +++ b/include/drivers/brcm/spi_flash.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPI_FLASH_H +#define SPI_FLASH_H + +#include <sf.h> + +int spi_flash_probe(struct spi_flash *flash); +int spi_flash_erase(struct spi_flash *flash, uint32_t offset, uint32_t len); +int spi_flash_write(struct spi_flash *flash, uint32_t offset, + uint32_t len, void *buf); +int spi_flash_read(struct spi_flash *flash, uint32_t offset, + uint32_t len, void *data); +#endif /* _SPI_FLASH_H_ */ diff --git a/include/drivers/brcm/usbh_xhci_regs.h b/include/drivers/brcm/usbh_xhci_regs.h new file mode 100644 index 0000000..93dec7b --- /dev/null +++ b/include/drivers/brcm/usbh_xhci_regs.h @@ -0,0 +1,4809 @@ +/* + * Copyright (c) 2017 - 2021, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef USBH_XHCI_REGS_H +#define USBH_XHCI_REGS_H + +#include <lib/mmio.h> +#include <platform_def.h> + +#define XHCI_LEN (8096U) + +#define XHC_CPLIVER_OFFSET 0x000U +#define XHC_SPARAMS1_OFFSET 0x004U +#define XHC_SPARAMS2_OFFSET 0x008U +#define XHC_SPARAMS3_OFFSET 0x00cU +#define XHC_CPARAMS1_OFFSET 0x010U +#define XHC_DBOFF_OFFSET 0x014U +#define XHC_RTOFF_OFFSET 0x018U +#define XHC_CPARAMS2_OFFSET 0x01cU +#define XHC_USBCMD_OFFSET 0x020U +#define XHC_USBSTS_OFFSET 0x024U +#define XHC_PAGESIZE_OFFSET 0x028U +#define XHC_DNCTRL_OFFSET 0x034U +#define XHC_CRCRL_OFFSET 0x038U +#define XHC_CRCRH_OFFSET 0x03cU +#define XHC_DCBAAPL_OFFSET 0x050U +#define XHC_DCBAAPH_OFFSET 0x054U +#define XHC_CONFIG_OFFSET 0x058U +#define XHC_PORTSC1_OFFSET 0x420U +#define XHC_PORTPM1_OFFSET 0x424U +#define XHC_PORTLC1_OFFSET 0x428U +#define XHC_PORTSC2_OFFSET 0x430U +#define XHC_PORTPM2_OFFSET 0x434U +#define XHC_PORTLC2_OFFSET 0x43cU +#define XHC_PORTSC3_OFFSET 0x440U +#define XHC_PORTPM3_OFFSET 0x444U +#define XHC_PORTLI3_OFFSET 0x44cU +#define XHC_MFINDEX_OFFSET 0x4a0U +#define XHC_IMAN0_OFFSET 0x4c0U +#define XHC_IMOD0_OFFSET 0x4c4U +#define XHC_ERSTSZ0_OFFSET 0x4c8U +#define XHC_ERSTBAL0_OFFSET 0x4d0U +#define XHC_ERSTBAH0_OFFSET 0x4d4U +#define XHC_ERDPL0_OFFSET 0x4d8U +#define XHC_ERDPH0_OFFSET 0x4dcU +#define XHC_IMAN1_OFFSET 0x4e0U +#define XHC_IMOD1_OFFSET 0x4e4U +#define XHC_ERSTSZ1_OFFSET 0x4e8U +#define XHC_ERSTBAL1_OFFSET 0x4f0U +#define XHC_ERSTBAH1_OFFSET 0x4f4U +#define XHC_ERDPL1_OFFSET 0x4f8U +#define XHC_ERDPH1_OFFSET 0x4fcU +#define XHC_DBLCMD_OFFSET 0x8c0U +#define XHC_DBLDVX1_OFFSET 0x8c4U +#define XHC_DBLDVX2_OFFSET 0x8c8U +#define XHC_DBLDVX3_OFFSET 0x8ccU +#define XHC_DBLDVX4_OFFSET 0x8d0U +#define XHC_DBLDVX5_OFFSET 0x8d4U +#define XHC_DBLDVX6_OFFSET 0x8d8U +#define XHC_DBLDVX7_OFFSET 0x8dcU +#define XHC_DBLDVX8_OFFSET 0x8e0U +#define XHC_DBLDVX9_OFFSET 0x8e4U +#define XHC_DBLDVX10_OFFSET 0x8e8U +#define XHC_DBLDVX11_OFFSET 0x8ecU +#define XHC_DBLDVX12_OFFSET 0x8f0U +#define XHC_DBLDVX13_OFFSET 0x8f4U +#define XHC_DBLDVX14_OFFSET 0x8f8U +#define XHC_DBLDVX15_OFFSET 0x8fcU +#define XHC_DBLDVX16_OFFSET 0x900U +#define XHC_ECHSPT3_OFFSET 0x940U +#define XHC_PNSTR3_OFFSET 0x944U +#define XHC_PSUM3_OFFSET 0x948U +#define XHC_PTSLTYP3_OFFSET 0x94cU +#define XHC_ECHSPT2_OFFSET 0x950U +#define XHC_PNSTR2_OFFSET 0x954U +#define XHC_PSUM2_OFFSET 0x958U +#define XHC_PTSLTYP2_OFFSET 0x95cU +#define XHC_ECHRSVP_OFFSET 0x960U +#define XHC_ECHRSVI_OFFSET 0x968U +#define XHC_ECHRSVM_OFFSET 0xae8U +#define XHC_ECHRSVD_OFFSET 0xaf8U +#define XHC_ECHRSVO_OFFSET 0xb38U +#define XHC_ECHCTT_OFFSET 0xbf0U +#define XHC_CTTMTS0_OFFSET 0xbf8U +#define XHC_CTTMTS1_OFFSET 0xbfcU +#define XHC_ECHBIU_OFFSET 0xc00U +#define XHC_BIUSPC_OFFSET 0xc04U +#define XHC_AXIWRA_OFFSET 0xc08U +#define XHC_AXIRDA_OFFSET 0xc0cU +#define XHC_AXILPM_OFFSET 0xc10U +#define XHC_AXIQOS_OFFSET 0xc14U +#define XHC_ECHCSR_OFFSET 0xc20U +#define XHC_CSRSPC_OFFSET 0xc24U +#define XHC_ECHAIU_OFFSET 0xc30U +#define XHC_AIUDMA_OFFSET 0xc34U +#define XHC_AIUFLA_OFFSET 0xc38U +#define XHC_AIUCFG_OFFSET 0xc3cU +#define XHC_ECHFSC_OFFSET 0xc40U +#define XHC_FSCPOC_OFFSET 0xc54U +#define XHC_FSCGOC_OFFSET 0xc58U +#define XHC_FSCNOC_OFFSET 0xc5cU +#define XHC_FSCAIC_OFFSET 0xc60U +#define XHC_FSCPIC_OFFSET 0xc64U +#define XHC_FSCGIC_OFFSET 0xc68U +#define XHC_FSCNIC_OFFSET 0xc6cU +#define XHC_ECHPRT_OFFSET 0xc70U +#define XHC_PRTHSC_OFFSET 0xc78U +#define XHC_PRTHSR_OFFSET 0xc7cU +#define XHC_ECHRHS_OFFSET 0xc80U +#define XHC_RHSDES_OFFSET 0xc84U +#define XHC_RHSHSC0_OFFSET 0xc90U +#define XHC_RHSHSR0_OFFSET 0xc94U +#define XHC_RHSHSC1_OFFSET 0xc98U +#define XHC_RHSHSR1_OFFSET 0xc9cU +#define XHC_RHSHSC2_OFFSET 0xca0U +#define XHC_RHSHSR2_OFFSET 0xca4U +#define XHC_RHSHSC3_OFFSET 0xca8U +#define XHC_RHSHSR3_OFFSET 0xcacU +#define XHC_ECHSSP_OFFSET 0xcb0U +#define XHC_SSPVER_OFFSET 0xcb4U +#define XHC_SSPMGN_OFFSET 0xcb8U +#define XHC_ECHFSC2_OFFSET 0xcc0U +#define XHC_FSC2POC_OFFSET 0xcd4U +#define XHC_FSC2GOC_OFFSET 0xcd8U +#define XHC_FSC2NOC_OFFSET 0xcdcU +#define XHC_FSC2AIC_OFFSET 0xce0U +#define XHC_FSC2PIC_OFFSET 0xce4U +#define XHC_FSC2GIC_OFFSET 0xce8U +#define XHC_FSC2NIC_OFFSET 0xcecU +#define XHC_ECHPRT2_OFFSET 0xcf0U +#define XHC_PRT2HSC_OFFSET 0xcf8U +#define XHC_PRT2HSR_OFFSET 0xcfcU +#define XHC_ECHRH2_OFFSET 0xd00U +#define XHC_RH2DES_OFFSET 0xd04U +#define XHC_RH2HSC0_OFFSET 0xd10U +#define XHC_RH2HSR0_OFFSET 0xd14U +#define XHC_RH2HSC1_OFFSET 0xd18U +#define XHC_RH2HSR1_OFFSET 0xd1cU +#define XHC_RH2HSC2_OFFSET 0xd20U +#define XHC_RH2HSR2_OFFSET 0xd24U +#define XHC_RH2HSC3_OFFSET 0xd28U +#define XHC_RH2HSR3_OFFSET 0xd2cU +#define XHC_ECHU2P_OFFSET 0xd30U +#define XHC_U2PVER_OFFSET 0xd34U +#define XHC_U2PMGN_OFFSET 0xd38U +#define XHC_ECHRSV2_OFFSET 0xd40U +#define XHC_ECHIRA_OFFSET 0xf90U +#define XHC_IRAADR_OFFSET 0xf98U +#define XHC_IRADAT_OFFSET 0xf9cU +#define XHC_ECHHST_OFFSET 0xfa0U +#define XHC_HSTDBG_OFFSET 0xfa4U +#define XHC_HSTNPL_OFFSET 0xfa8U +#define XHC_HSTNPH_OFFSET 0xfacU +#define XHC_ECHRBV_OFFSET 0xfb0U +#define XHC_RBVPDT_OFFSET 0xfb4U +#define XHC_RBVMGN_OFFSET 0xfbcU + +#define XHC_CPLIVER_BASE 0x000U +#define XHC_CPLIVER__IVH_L 31U +#define XHC_CPLIVER__IVH_R 24U +#define XHC_CPLIVER__IVH_WIDTH 8U +#define XHC_CPLIVER__IVH_RESETVALUE 0x01U +#define XHC_CPLIVER__IVL_L 23U +#define XHC_CPLIVER__IVL_R 16U +#define XHC_CPLIVER__IVL_WIDTH 8U +#define XHC_CPLIVER__IVL_RESETVALUE 0x10U +#define XHC_CPLIVER__reserved_L 15U +#define XHC_CPLIVER__reserved_R 8U +#define XHC_CPLIVER__reserved_WIDTH 8U +#define XHC_CPLIVER__reserved_RESETVALUE 0x00U +#define XHC_CPLIVER__CPL_L 7U +#define XHC_CPLIVER__CPL_R 0U +#define XHC_CPLIVER__CPL_WIDTH 8U +#define XHC_CPLIVER__CPL_RESETVALUE 0x00U +#define XHC_CPLIVER_WIDTH 32U +#define XHC_CPLIVER__WIDTH 32U +#define XHC_CPLIVER_ALL_L 31U +#define XHC_CPLIVER_ALL_R 0U +#define XHC_CPLIVER__ALL_L 31U +#define XHC_CPLIVER__ALL_R 0U +#define XHC_CPLIVER_DATAMASK 0xffffffffU +#define XHC_CPLIVER_RDWRMASK 0x00000000U +#define XHC_CPLIVER_RESETVALUE 0x01100000U + +#define XHC_SPARAMS1_OFFSET 0x004U +#define XHC_SPARAMS1_BASE 0x004U +#define XHC_SPARAMS1__NPTS_L 31U +#define XHC_SPARAMS1__NPTS_R 24U +#define XHC_SPARAMS1__NPTS_WIDTH 8U +#define XHC_SPARAMS1__NPTS_RESETVALUE 0x00U +#define XHC_SPARAMS1__reserved_L 23U +#define XHC_SPARAMS1__reserved_R 19U +#define XHC_SPARAMS1__reserved_WIDTH 5U +#define XHC_SPARAMS1__reserved_RESETVALUE 0x0U +#define XHC_SPARAMS1__MITS_L 18U +#define XHC_SPARAMS1__MITS_R 8U +#define XHC_SPARAMS1__MITS_WIDTH 11U +#define XHC_SPARAMS1__MITS_RESETVALUE 0x1U +#define XHC_SPARAMS1__MSLS_L 7U +#define XHC_SPARAMS1__MSLS_R 0U +#define XHC_SPARAMS1__MSLS_WIDTH 8U +#define XHC_SPARAMS1__MSLS_RESETVALUE 0x00U +#define XHC_SPARAMS1_WIDTH 32U +#define XHC_SPARAMS1__WIDTH 32U +#define XHC_SPARAMS1_ALL_L 31U +#define XHC_SPARAMS1_ALL_R 0U +#define XHC_SPARAMS1__ALL_L 31U +#define XHC_SPARAMS1__ALL_R 0U +#define XHC_SPARAMS1_DATAMASK 0xffffffffU +#define XHC_SPARAMS1_RDWRMASK 0x00000000U +#define XHC_SPARAMS1_RESETVALUE 0x00000100U + +#define XHC_SPARAMS2_OFFSET 0x008U +#define XHC_SPARAMS2_BASE 0x008U +#define XHC_SPARAMS2__MSPBSL_L 31U +#define XHC_SPARAMS2__MSPBSL_R 27U +#define XHC_SPARAMS2__MSPBSL_WIDTH 5U +#define XHC_SPARAMS2__MSPBSL_RESETVALUE 0x0U +#define XHC_SPARAMS2__SPR 26U +#define XHC_SPARAMS2__SPR_L 26U +#define XHC_SPARAMS2__SPR_R 26U +#define XHC_SPARAMS2__SPR_WIDTH 1U +#define XHC_SPARAMS2__SPR_RESETVALUE 0x1U +#define XHC_SPARAMS2__MSPBSH_L 25U +#define XHC_SPARAMS2__MSPBSH_R 21U +#define XHC_SPARAMS2__MSPBSH_WIDTH 5U +#define XHC_SPARAMS2__MSPBSH_RESETVALUE 0x0U +#define XHC_SPARAMS2__reserved_L 20U +#define XHC_SPARAMS2__reserved_R 8U +#define XHC_SPARAMS2__reserved_WIDTH 13U +#define XHC_SPARAMS2__reserved_RESETVALUE 0x0U +#define XHC_SPARAMS2__MERST_L 7U +#define XHC_SPARAMS2__MERST_R 4U +#define XHC_SPARAMS2__MERST_WIDTH 4U +#define XHC_SPARAMS2__MERST_RESETVALUE 0x0U +#define XHC_SPARAMS2__IST_L 3U +#define XHC_SPARAMS2__IST_R 0U +#define XHC_SPARAMS2__IST_WIDTH 4U +#define XHC_SPARAMS2__IST_RESETVALUE 0x0U +#define XHC_SPARAMS2_WIDTH 32U +#define XHC_SPARAMS2__WIDTH 32U +#define XHC_SPARAMS2_ALL_L 31U +#define XHC_SPARAMS2_ALL_R 0U +#define XHC_SPARAMS2__ALL_L 31U +#define XHC_SPARAMS2__ALL_R 0U +#define XHC_SPARAMS2_DATAMASK 0xffffffffU +#define XHC_SPARAMS2_RDWRMASK 0x00000000U +#define XHC_SPARAMS2_RESETVALUE 0x04000000U + +#define XHC_SPARAMS3_OFFSET 0x00cU +#define XHC_SPARAMS3_BASE 0x00cU +#define XHC_SPARAMS3__U2L_L 31U +#define XHC_SPARAMS3__U2L_R 16U +#define XHC_SPARAMS3__U2L_WIDTH 16U +#define XHC_SPARAMS3__U2L_RESETVALUE 0x0000U +#define XHC_SPARAMS3__reserved_L 15U +#define XHC_SPARAMS3__reserved_R 8U +#define XHC_SPARAMS3__reserved_WIDTH 8U +#define XHC_SPARAMS3__reserved_RESETVALUE 0x00U +#define XHC_SPARAMS3__U1L_L 7U +#define XHC_SPARAMS3__U1L_R 0U +#define XHC_SPARAMS3__U1L_WIDTH 8U +#define XHC_SPARAMS3__U1L_RESETVALUE 0x00U +#define XHC_SPARAMS3_WIDTH 32U +#define XHC_SPARAMS3__WIDTH 32U +#define XHC_SPARAMS3_ALL_L 31U +#define XHC_SPARAMS3_ALL_R 0U +#define XHC_SPARAMS3__ALL_L 31U +#define XHC_SPARAMS3__ALL_R 0U +#define XHC_SPARAMS3_DATAMASK 0xffffffffU +#define XHC_SPARAMS3_RDWRMASK 0x00000000U +#define XHC_SPARAMS3_RESETVALUE 0x00000000U + +#define XHC_CPARAMS1_OFFSET 0x010U +#define XHC_CPARAMS1_BASE 0x010U +#define XHC_CPARAMS1__XECP_L 31U +#define XHC_CPARAMS1__XECP_R 16U +#define XHC_CPARAMS1__XECP_WIDTH 16U +#define XHC_CPARAMS1__XECP_RESETVALUE 0x0000U +#define XHC_CPARAMS1__MPSA_L 15U +#define XHC_CPARAMS1__MPSA_R 12U +#define XHC_CPARAMS1__MPSA_WIDTH 4U +#define XHC_CPARAMS1__MPSA_RESETVALUE 0x0U +#define XHC_CPARAMS1__CFC 11U +#define XHC_CPARAMS1__CFC_L 11U +#define XHC_CPARAMS1__CFC_R 11U +#define XHC_CPARAMS1__CFC_WIDTH 1U +#define XHC_CPARAMS1__CFC_RESETVALUE 0x0U +#define XHC_CPARAMS1__SEC 10U +#define XHC_CPARAMS1__SEC_L 10U +#define XHC_CPARAMS1__SEC_R 10U +#define XHC_CPARAMS1__SEC_WIDTH 1U +#define XHC_CPARAMS1__SEC_RESETVALUE 0x0U +#define XHC_CPARAMS1__SPC 9U +#define XHC_CPARAMS1__SPC_L 9U +#define XHC_CPARAMS1__SPC_R 9U +#define XHC_CPARAMS1__SPC_WIDTH 1U +#define XHC_CPARAMS1__SPC_RESETVALUE 0x0U +#define XHC_CPARAMS1__PAE 8U +#define XHC_CPARAMS1__PAE_L 8U +#define XHC_CPARAMS1__PAE_R 8U +#define XHC_CPARAMS1__PAE_WIDTH 1U +#define XHC_CPARAMS1__PAE_RESETVALUE 0x1U +#define XHC_CPARAMS1__NSS 7U +#define XHC_CPARAMS1__NSS_L 7U +#define XHC_CPARAMS1__NSS_R 7U +#define XHC_CPARAMS1__NSS_WIDTH 1U +#define XHC_CPARAMS1__NSS_RESETVALUE 0x0U +#define XHC_CPARAMS1__LTC 6U +#define XHC_CPARAMS1__LTC_L 6U +#define XHC_CPARAMS1__LTC_R 6U +#define XHC_CPARAMS1__LTC_WIDTH 1U +#define XHC_CPARAMS1__LTC_RESETVALUE 0x1U +#define XHC_CPARAMS1__LRC 5U +#define XHC_CPARAMS1__LRC_L 5U +#define XHC_CPARAMS1__LRC_R 5U +#define XHC_CPARAMS1__LRC_WIDTH 1U +#define XHC_CPARAMS1__LRC_RESETVALUE 0x0U +#define XHC_CPARAMS1__PIND 4U +#define XHC_CPARAMS1__PIND_L 4U +#define XHC_CPARAMS1__PIND_R 4U +#define XHC_CPARAMS1__PIND_WIDTH 1U +#define XHC_CPARAMS1__PIND_RESETVALUE 0x0U + +#define XHC_CPARAMS1__PPC_L 3U +#define XHC_CPARAMS1__PPC_R 3U +#define XHC_CPARAMS1__PPC_WIDTH 1U +#define XHC_CPARAMS1__PPC_RESETVALUE 0x0U +#define XHC_CPARAMS1__CSZ 2U +#define XHC_CPARAMS1__CSZ_L 2U +#define XHC_CPARAMS1__CSZ_R 2U +#define XHC_CPARAMS1__CSZ_WIDTH 1U +#define XHC_CPARAMS1__CSZ_RESETVALUE 0x1U +#define XHC_CPARAMS1__BNC 1U +#define XHC_CPARAMS1__BNC_L 1U +#define XHC_CPARAMS1__BNC_R 1U +#define XHC_CPARAMS1__BNC_WIDTH 1U +#define XHC_CPARAMS1__BNC_RESETVALUE 0x0U +#define XHC_CPARAMS1__AC64 0U +#define XHC_CPARAMS1__AC64_L 0U +#define XHC_CPARAMS1__AC64_R 0U +#define XHC_CPARAMS1__AC64_WIDTH 1U +#define XHC_CPARAMS1__AC64_RESETVALUE 0x0U +#define XHC_CPARAMS1_WIDTH 32U +#define XHC_CPARAMS1__WIDTH 32U +#define XHC_CPARAMS1_ALL_L 31U +#define XHC_CPARAMS1_ALL_R 0U +#define XHC_CPARAMS1__ALL_L 31U +#define XHC_CPARAMS1__ALL_R 0U +#define XHC_CPARAMS1_DATAMASK 0xffffffffU +#define XHC_CPARAMS1_RDWRMASK 0x00000000U +#define XHC_CPARAMS1_RESETVALUE 0x00000144U + +#define XHC_DBOFF_OFFSET 0x014U +#define XHC_DBOFF_BASE 0x014U +#define XHC_DBOFF__DBO_L 15U +#define XHC_DBOFF__DBO_R 2U +#define XHC_DBOFF__DBO_WIDTH 14U +#define XHC_DBOFF__DBO_RESETVALUE 0x0U +#define XHC_DBOFF__reserved_L 1U +#define XHC_DBOFF__reserved_R 0U +#define XHC_DBOFF__reserved_WIDTH 2U +#define XHC_DBOFF__reserved_RESETVALUE 0x0U +#define XHC_DBOFF__RESERVED_L 31U +#define XHC_DBOFF__RESERVED_R 16U +#define XHC_DBOFF_WIDTH 16U +#define XHC_DBOFF__WIDTH 16U +#define XHC_DBOFF_ALL_L 15U +#define XHC_DBOFF_ALL_R 0U +#define XHC_DBOFF__ALL_L 15U +#define XHC_DBOFF__ALL_R 0U +#define XHC_DBOFF_DATAMASK 0x0000ffffU +#define XHC_DBOFF_RDWRMASK 0xffff0000U +#define XHC_DBOFF_RESETVALUE 0x0000U + +#define XHC_RTOFF_OFFSET 0x018U +#define XHC_RTOFF_BASE 0x018U +#define XHC_RTOFF__RTO_L 15U +#define XHC_RTOFF__RTO_R 5U +#define XHC_RTOFF__RTO_WIDTH 11U +#define XHC_RTOFF__RTO_RESETVALUE 0x0U +#define XHC_RTOFF__reserved_L 4U +#define XHC_RTOFF__reserved_R 0U +#define XHC_RTOFF__reserved_WIDTH 5U +#define XHC_RTOFF__reserved_RESETVALUE 0x0U +#define XHC_RTOFF__RESERVED_L 31U +#define XHC_RTOFF__RESERVED_R 16U +#define XHC_RTOFF_WIDTH 16U +#define XHC_RTOFF__WIDTH 16U +#define XHC_RTOFF_ALL_L 15U +#define XHC_RTOFF_ALL_R 0U +#define XHC_RTOFF__ALL_L 15U +#define XHC_RTOFF__ALL_R 0U +#define XHC_RTOFF_DATAMASK 0x0000ffffU +#define XHC_RTOFF_RDWRMASK 0xffff0000U +#define XHC_RTOFF_RESETVALUE 0x0000U + +#define XHC_CPARAMS2_OFFSET 0x01cU +#define XHC_CPARAMS2_BASE 0x01cU +#define XHC_CPARAMS2__reserved_L 31U +#define XHC_CPARAMS2__reserved_R 6U +#define XHC_CPARAMS2__reserved_WIDTH 26U +#define XHC_CPARAMS2__reserved_RESETVALUE 0x0U +#define XHC_CPARAMS2__CIC 5U +#define XHC_CPARAMS2__CIC_L 5U +#define XHC_CPARAMS2__CIC_R 5U +#define XHC_CPARAMS2__CIC_WIDTH 1U +#define XHC_CPARAMS2__CIC_RESETVALUE 0x0U +#define XHC_CPARAMS2__LEC 4U +#define XHC_CPARAMS2__LEC_L 4U +#define XHC_CPARAMS2__LEC_R 4U +#define XHC_CPARAMS2__LEC_WIDTH 1U +#define XHC_CPARAMS2__LEC_RESETVALUE 0x0U +#define XHC_CPARAMS2__CTC 3U +#define XHC_CPARAMS2__CTC_L 3U +#define XHC_CPARAMS2__CTC_R 3U +#define XHC_CPARAMS2__CTC_WIDTH 1U +#define XHC_CPARAMS2__CTC_RESETVALUE 0x0U +#define XHC_CPARAMS2__FSC 2U +#define XHC_CPARAMS2__FSC_L 2U +#define XHC_CPARAMS2__FSC_R 2U +#define XHC_CPARAMS2__FSC_WIDTH 1U +#define XHC_CPARAMS2__FSC_RESETVALUE 0x0U +#define XHC_CPARAMS2__CMC 1U +#define XHC_CPARAMS2__CMC_L 1U +#define XHC_CPARAMS2__CMC_R 1U +#define XHC_CPARAMS2__CMC_WIDTH 1U +#define XHC_CPARAMS2__CMC_RESETVALUE 0x0U +#define XHC_CPARAMS2__U3C 0U +#define XHC_CPARAMS2__U3C_L 0U +#define XHC_CPARAMS2__U3C_R 0U +#define XHC_CPARAMS2__U3C_WIDTH 1U +#define XHC_CPARAMS2__U3C_RESETVALUE 0x0U +#define XHC_CPARAMS2_WIDTH 32U +#define XHC_CPARAMS2__WIDTH 32U +#define XHC_CPARAMS2_ALL_L 31U +#define XHC_CPARAMS2_ALL_R 0U +#define XHC_CPARAMS2__ALL_L 31U +#define XHC_CPARAMS2__ALL_R 0U +#define XHC_CPARAMS2_DATAMASK 0xffffffffU +#define XHC_CPARAMS2_RDWRMASK 0x00000000U +#define XHC_CPARAMS2_RESETVALUE 0x00000000U + +#define XHC_USBCMD_OFFSET 0x020U +#define XHC_USBCMD_BASE 0x020U +#define XHC_USBCMD__CME 13U +#define XHC_USBCMD__CME_L 13U +#define XHC_USBCMD__CME_R 13U +#define XHC_USBCMD__CME_WIDTH 1U +#define XHC_USBCMD__CME_RESETVALUE 0x0U +#define XHC_USBCMD__SPE 12U +#define XHC_USBCMD__SPE_L 12U +#define XHC_USBCMD__SPE_R 12U +#define XHC_USBCMD__SPE_WIDTH 1U +#define XHC_USBCMD__SPE_RESETVALUE 0x0U +#define XHC_USBCMD__EU3S 11U +#define XHC_USBCMD__EU3S_L 11U +#define XHC_USBCMD__EU3S_R 11U +#define XHC_USBCMD__EU3S_WIDTH 1U +#define XHC_USBCMD__EU3S_RESETVALUE 0x0U +#define XHC_USBCMD__EWE 10U +#define XHC_USBCMD__EWE_L 10U +#define XHC_USBCMD__EWE_R 10U +#define XHC_USBCMD__EWE_WIDTH 1U +#define XHC_USBCMD__EWE_RESETVALUE 0x0U +#define XHC_USBCMD__CRS 9U +#define XHC_USBCMD__CRS_L 9U +#define XHC_USBCMD__CRS_R 9U +#define XHC_USBCMD__CRS_WIDTH 1U +#define XHC_USBCMD__CRS_RESETVALUE 0x0U +#define XHC_USBCMD__CSS 8U +#define XHC_USBCMD__CSS_L 8U +#define XHC_USBCMD__CSS_R 8U +#define XHC_USBCMD__CSS_WIDTH 1U +#define XHC_USBCMD__CSS_RESETVALUE 0x0U +#define XHC_USBCMD__LRST 7U +#define XHC_USBCMD__LRST_L 7U +#define XHC_USBCMD__LRST_R 7U +#define XHC_USBCMD__LRST_WIDTH 1U +#define XHC_USBCMD__LRST_RESETVALUE 0x0U +#define XHC_USBCMD__reserved_L 6U +#define XHC_USBCMD__reserved_R 4U +#define XHC_USBCMD__reserved_WIDTH 3U +#define XHC_USBCMD__reserved_RESETVALUE 0x0U +#define XHC_USBCMD__HSEE 3U +#define XHC_USBCMD__HSEE_L 3U +#define XHC_USBCMD__HSEE_R 3U +#define XHC_USBCMD__HSEE_WIDTH 1U +#define XHC_USBCMD__HSEE_RESETVALUE 0x0U +#define XHC_USBCMD__INTE 2U +#define XHC_USBCMD__INTE_L 2U +#define XHC_USBCMD__INTE_R 2U +#define XHC_USBCMD__INTE_WIDTH 1U +#define XHC_USBCMD__INTE_RESETVALUE 0x0U +#define XHC_USBCMD__RST 1U +#define XHC_USBCMD__RST_L 1U +#define XHC_USBCMD__RST_R 1U +#define XHC_USBCMD__RST_WIDTH 1U +#define XHC_USBCMD__RST_RESETVALUE 0x0U +#define XHC_USBCMD__RS 0U +#define XHC_USBCMD__RS_L 0U +#define XHC_USBCMD__RS_R 0U +#define XHC_USBCMD__RS_WIDTH 1U +#define XHC_USBCMD__RS_RESETVALUE 0x0U +#define XHC_USBCMD__RESERVED_L 31U +#define XHC_USBCMD__RESERVED_R 14U +#define XHC_USBCMD_WIDTH 14U +#define XHC_USBCMD__WIDTH 14U +#define XHC_USBCMD_ALL_L 13U +#define XHC_USBCMD_ALL_R 0U +#define XHC_USBCMD__ALL_L 13U +#define XHC_USBCMD__ALL_R 0U +#define XHC_USBCMD_DATAMASK 0x00003fffU +#define XHC_USBCMD_RDWRMASK 0xffffc000U +#define XHC_USBCMD_RESETVALUE 0x0000U + +#define XHC_USBSTS_OFFSET 0x024U +#define XHC_USBSTS_BASE 0x024U +#define XHC_USBSTS__CE 12U +#define XHC_USBSTS__CE_L 12U +#define XHC_USBSTS__CE_R 12U +#define XHC_USBSTS__CE_WIDTH 1U +#define XHC_USBSTS__CE_RESETVALUE 0x0U +#define XHC_USBSTS__CNR 11U +#define XHC_USBSTS__CNR_L 11U +#define XHC_USBSTS__CNR_R 11U +#define XHC_USBSTS__CNR_WIDTH 1U +#define XHC_USBSTS__CNR_RESETVALUE 0x1U + +#define XHC_USBSTS__SRE 10U +#define XHC_USBSTS__SRE_L 10U +#define XHC_USBSTS__SRE_R 10U +#define XHC_USBSTS__SRE_WIDTH 1U +#define XHC_USBSTS__SRE_RESETVALUE 0x0U +#define XHC_USBSTS__RSS 9U +#define XHC_USBSTS__RSS_L 9U +#define XHC_USBSTS__RSS_R 9U +#define XHC_USBSTS__RSS_WIDTH 1U +#define XHC_USBSTS__RSS_RESETVALUE 0x0U +#define XHC_USBSTS__SSS 8U +#define XHC_USBSTS__SSS_L 8U +#define XHC_USBSTS__SSS_R 8U +#define XHC_USBSTS__SSS_WIDTH 1U +#define XHC_USBSTS__SSS_RESETVALUE 0x0U +#define XHC_USBSTS__PCD 4U +#define XHC_USBSTS__PCD_L 4U +#define XHC_USBSTS__PCD_R 4U +#define XHC_USBSTS__PCD_WIDTH 1U +#define XHC_USBSTS__PCD_RESETVALUE 0x0U +#define XHC_USBSTS__EINT 3U +#define XHC_USBSTS__EINT_L 3U +#define XHC_USBSTS__EINT_R 3U +#define XHC_USBSTS__EINT_WIDTH 1U +#define XHC_USBSTS__EINT_RESETVALUE 0x0U +#define XHC_USBSTS__HSE 2U +#define XHC_USBSTS__HSE_L 2U +#define XHC_USBSTS__HSE_R 2U +#define XHC_USBSTS__HSE_WIDTH 1U +#define XHC_USBSTS__HSE_RESETVALUE 0x0U +#define XHC_USBSTS__reserved 1U +#define XHC_USBSTS__reserved_L 1U +#define XHC_USBSTS__reserved_R 1U +#define XHC_USBSTS__reserved_WIDTH 1U +#define XHC_USBSTS__reserved_RESETVALUE 0x0U + +#define XHC_USBSTS__CH_L 0U +#define XHC_USBSTS__CH_R 0U +#define XHC_USBSTS__CH_WIDTH 1U +#define XHC_USBSTS__CH_RESETVALUE 0x1U +#define XHC_USBSTS__RESERVED_L 31U +#define XHC_USBSTS__RESERVED_R 13U +#define XHC_USBSTS_WIDTH 13U +#define XHC_USBSTS__WIDTH 13U +#define XHC_USBSTS_ALL_L 12U +#define XHC_USBSTS_ALL_R 0U +#define XHC_USBSTS__ALL_L 12U +#define XHC_USBSTS__ALL_R 0U +#define XHC_USBSTS_DATAMASK 0x00001f1fU +#define XHC_USBSTS_RDWRMASK 0xffffe0e0U +#define XHC_USBSTS_RESETVALUE 0x0801U + +#define XHC_PAGESIZE_OFFSET 0x028U +#define XHC_PAGESIZE_BASE 0x028U +#define XHC_PAGESIZE__reserved_L 31U +#define XHC_PAGESIZE__reserved_R 16U +#define XHC_PAGESIZE__reserved_WIDTH 16U +#define XHC_PAGESIZE__reserved_RESETVALUE 0x0000U +#define XHC_PAGESIZE__PS_L 15U +#define XHC_PAGESIZE__PS_R 0U +#define XHC_PAGESIZE__PS_WIDTH 16U +#define XHC_PAGESIZE__PS_RESETVALUE 0x0000U +#define XHC_PAGESIZE_WIDTH 32U +#define XHC_PAGESIZE__WIDTH 32U +#define XHC_PAGESIZE_ALL_L 31U +#define XHC_PAGESIZE_ALL_R 0U +#define XHC_PAGESIZE__ALL_L 31U +#define XHC_PAGESIZE__ALL_R 0U +#define XHC_PAGESIZE_DATAMASK 0xffffffffU +#define XHC_PAGESIZE_RDWRMASK 0x00000000U +#define XHC_PAGESIZE_RESETVALUE 0x00000000U + +#define XHC_DNCTRL_OFFSET 0x034U +#define XHC_DNCTRL_BASE 0x034U +#define XHC_DNCTRL__reserved_L 31U +#define XHC_DNCTRL__reserved_R 16U +#define XHC_DNCTRL__reserved_WIDTH 16U +#define XHC_DNCTRL__reserved_RESETVALUE 0x0000U +#define XHC_DNCTRL__DNE_L 15U +#define XHC_DNCTRL__DNE_R 0U +#define XHC_DNCTRL__DNE_WIDTH 16U +#define XHC_DNCTRL__DNE_RESETVALUE 0x0000U +#define XHC_DNCTRL_WIDTH 32U +#define XHC_DNCTRL__WIDTH 32U +#define XHC_DNCTRL_ALL_L 31U +#define XHC_DNCTRL_ALL_R 0U +#define XHC_DNCTRL__ALL_L 31U +#define XHC_DNCTRL__ALL_R 0U +#define XHC_DNCTRL_DATAMASK 0xffffffffU +#define XHC_DNCTRL_RDWRMASK 0x00000000U +#define XHC_DNCTRL_RESETVALUE 0x00000000U + +#define XHC_CRCRL_OFFSET 0x038U +#define XHC_CRCRL_BASE 0x038U +#define XHC_CRCRL__CRPL_L 31U +#define XHC_CRCRL__CRPL_R 6U +#define XHC_CRCRL__CRPL_WIDTH 26U +#define XHC_CRCRL__CRPL_RESETVALUE 0x0U +#define XHC_CRCRL__reserved_L 5U +#define XHC_CRCRL__reserved_R 4U +#define XHC_CRCRL__reserved_WIDTH 2U +#define XHC_CRCRL__reserved_RESETVALUE 0x0U +#define XHC_CRCRL__CRR 3U +#define XHC_CRCRL__CRR_L 3U +#define XHC_CRCRL__CRR_R 3U +#define XHC_CRCRL__CRR_WIDTH 1U +#define XHC_CRCRL__CRR_RESETVALUE 0x0U +#define XHC_CRCRL__CA 2U +#define XHC_CRCRL__CA_L 2U +#define XHC_CRCRL__CA_R 2U +#define XHC_CRCRL__CA_WIDTH 1U +#define XHC_CRCRL__CA_RESETVALUE 0x0U +#define XHC_CRCRL__CS 1U +#define XHC_CRCRL__CS_L 1U +#define XHC_CRCRL__CS_R 1U +#define XHC_CRCRL__CS_WIDTH 1U +#define XHC_CRCRL__CS_RESETVALUE 0x0U +#define XHC_CRCRL__RCS 0U +#define XHC_CRCRL__RCS_L 0U +#define XHC_CRCRL__RCS_R 0U +#define XHC_CRCRL__RCS_WIDTH 1U +#define XHC_CRCRL__RCS_RESETVALUE 0x0U +#define XHC_CRCRL_WIDTH 32U +#define XHC_CRCRL__WIDTH 32U +#define XHC_CRCRL_ALL_L 31U +#define XHC_CRCRL_ALL_R 0U +#define XHC_CRCRL__ALL_L 31U +#define XHC_CRCRL__ALL_R 0U +#define XHC_CRCRL_DATAMASK 0xffffffffU +#define XHC_CRCRL_RDWRMASK 0x00000000U +#define XHC_CRCRL_RESETVALUE 0x00000000U + +#define XHC_CRCRH_OFFSET 0x03cU +#define XHC_CRCRH_BASE 0x03cU +#define XHC_CRCRH__CRPH_L 31U +#define XHC_CRCRH__CRPH_R 0U +#define XHC_CRCRH__CRPH_WIDTH 32U +#define XHC_CRCRH__CRPH_RESETVALUE 0x00000000U +#define XHC_CRCRH_WIDTH 32U +#define XHC_CRCRH__WIDTH 32U +#define XHC_CRCRH_ALL_L 31U +#define XHC_CRCRH_ALL_R 0U +#define XHC_CRCRH__ALL_L 31U +#define XHC_CRCRH__ALL_R 0U +#define XHC_CRCRH_DATAMASK 0xffffffffU +#define XHC_CRCRH_RDWRMASK 0x00000000U +#define XHC_CRCRH_RESETVALUE 0x00000000U + +#define XHC_DCBAAPL_OFFSET 0x050U +#define XHC_DCBAAPL_BASE 0x050U +#define XHC_DCBAAPL__DCAL_L 31U +#define XHC_DCBAAPL__DCAL_R 6U +#define XHC_DCBAAPL__DCAL_WIDTH 26U +#define XHC_DCBAAPL__DCAL_RESETVALUE 0x0U + +#define XHC_DCBAAPL__reserved_L 5U +#define XHC_DCBAAPL__reserved_R 0U +#define XHC_DCBAAPL__reserved_WIDTH 6U +#define XHC_DCBAAPL__reserved_RESETVALUE 0x0U +#define XHC_DCBAAPL_WIDTH 32U +#define XHC_DCBAAPL__WIDTH 32U +#define XHC_DCBAAPL_ALL_L 31U +#define XHC_DCBAAPL_ALL_R 0U +#define XHC_DCBAAPL__ALL_L 31U +#define XHC_DCBAAPL__ALL_R 0U +#define XHC_DCBAAPL_DATAMASK 0xffffffffU +#define XHC_DCBAAPL_RDWRMASK 0x00000000U +#define XHC_DCBAAPL_RESETVALUE 0x00000000U + +#define XHC_DCBAAPH_OFFSET 0x054U +#define XHC_DCBAAPH_BASE 0x054U +#define XHC_DCBAAPH__DCAH_L 31U +#define XHC_DCBAAPH__DCAH_R 0U +#define XHC_DCBAAPH__DCAH_WIDTH 32U +#define XHC_DCBAAPH__DCAH_RESETVALUE 0x00000000U +#define XHC_DCBAAPH_WIDTH 32U +#define XHC_DCBAAPH__WIDTH 32U +#define XHC_DCBAAPH_ALL_L 31U +#define XHC_DCBAAPH_ALL_R 0U +#define XHC_DCBAAPH__ALL_L 31U +#define XHC_DCBAAPH__ALL_R 0U +#define XHC_DCBAAPH_DATAMASK 0xffffffffU +#define XHC_DCBAAPH_RDWRMASK 0x00000000U +#define XHC_DCBAAPH_RESETVALUE 0x00000000U + +#define XHC_CONFIG_OFFSET 0x058U +#define XHC_CONFIG_BASE 0x058U +#define XHC_CONFIG__reserved_L 31U +#define XHC_CONFIG__reserved_R 10U +#define XHC_CONFIG__reserved_WIDTH 22U +#define XHC_CONFIG__reserved_RESETVALUE 0x0U +#define XHC_CONFIG__CIE 9U +#define XHC_CONFIG__CIE_L 9U +#define XHC_CONFIG__CIE_R 9U +#define XHC_CONFIG__CIE_WIDTH 1U +#define XHC_CONFIG__CIE_RESETVALUE 0x0U +#define XHC_CONFIG__U3E 8U +#define XHC_CONFIG__U3E_L 8U +#define XHC_CONFIG__U3E_R 8U +#define XHC_CONFIG__U3E_WIDTH 1U +#define XHC_CONFIG__U3E_RESETVALUE 0x0U +#define XHC_CONFIG__MSE_L 7U +#define XHC_CONFIG__MSE_R 0U +#define XHC_CONFIG__MSE_WIDTH 8U +#define XHC_CONFIG__MSE_RESETVALUE 0x00U +#define XHC_CONFIG_WIDTH 32U +#define XHC_CONFIG__WIDTH 32U +#define XHC_CONFIG_ALL_L 31U +#define XHC_CONFIG_ALL_R 0U +#define XHC_CONFIG__ALL_L 31U +#define XHC_CONFIG__ALL_R 0U +#define XHC_CONFIG_DATAMASK 0xffffffffU +#define XHC_CONFIG_RDWRMASK 0x00000000U +#define XHC_CONFIG_RESETVALUE 0x00000000U + +#define XHC_PORTSC1_OFFSET 0x420U +#define XHC_PORTSC1_BASE 0x420U + +#define XHC_PORTSC1__WPR_L 31U +#define XHC_PORTSC1__WPR_R 31U +#define XHC_PORTSC1__WPR_WIDTH 1U +#define XHC_PORTSC1__WPR_RESETVALUE 0x0U + +#define XHC_PORTSC1__DNR_L 30U +#define XHC_PORTSC1__DNR_R 30U +#define XHC_PORTSC1__DNR_WIDTH 1U +#define XHC_PORTSC1__DNR_RESETVALUE 0x0U + +#define XHC_PORTSC1__WOE_L 27U +#define XHC_PORTSC1__WOE_R 27U +#define XHC_PORTSC1__WOE_WIDTH 1U +#define XHC_PORTSC1__WOE_RESETVALUE 0x0U + +#define XHC_PORTSC1__WDE_L 26U +#define XHC_PORTSC1__WDE_R 26U +#define XHC_PORTSC1__WDE_WIDTH 1U +#define XHC_PORTSC1__WDE_RESETVALUE 0x0U + +#define XHC_PORTSC1__WCE_L 25U +#define XHC_PORTSC1__WCE_R 25U +#define XHC_PORTSC1__WCE_WIDTH 1U +#define XHC_PORTSC1__WCE_RESETVALUE 0x0U + +#define XHC_PORTSC1__CAS_L 24U +#define XHC_PORTSC1__CAS_R 24U +#define XHC_PORTSC1__CAS_WIDTH 1U +#define XHC_PORTSC1__CAS_RESETVALUE 0x0U + +#define XHC_PORTSC1__CEC_L 23U +#define XHC_PORTSC1__CEC_R 23U +#define XHC_PORTSC1__CEC_WIDTH 1U +#define XHC_PORTSC1__CEC_RESETVALUE 0x0U + +#define XHC_PORTSC1__PLC_L 22U +#define XHC_PORTSC1__PLC_R 22U +#define XHC_PORTSC1__PLC_WIDTH 1U +#define XHC_PORTSC1__PLC_RESETVALUE 0x0U + +#define XHC_PORTSC1__PRC_L 21U +#define XHC_PORTSC1__PRC_R 21U +#define XHC_PORTSC1__PRC_WIDTH 1U +#define XHC_PORTSC1__PRC_RESETVALUE 0x0U + +#define XHC_PORTSC1__OCC_L 20U +#define XHC_PORTSC1__OCC_R 20U +#define XHC_PORTSC1__OCC_WIDTH 1U +#define XHC_PORTSC1__OCC_RESETVALUE 0x0U + +#define XHC_PORTSC1__WRC_L 19U +#define XHC_PORTSC1__WRC_R 19U +#define XHC_PORTSC1__WRC_WIDTH 1U +#define XHC_PORTSC1__WRC_RESETVALUE 0x0U + +#define XHC_PORTSC1__PEC_L 18U +#define XHC_PORTSC1__PEC_R 18U +#define XHC_PORTSC1__PEC_WIDTH 1U +#define XHC_PORTSC1__PEC_RESETVALUE 0x0U + +#define XHC_PORTSC1__CSC_L 17U +#define XHC_PORTSC1__CSC_R 17U +#define XHC_PORTSC1__CSC_WIDTH 1U +#define XHC_PORTSC1__CSC_RESETVALUE 0x0U + +#define XHC_PORTSC1__LWS_L 16U +#define XHC_PORTSC1__LWS_R 16U +#define XHC_PORTSC1__LWS_WIDTH 1U +#define XHC_PORTSC1__LWS_RESETVALUE 0x0U +#define XHC_PORTSC1__PIC_L 15U +#define XHC_PORTSC1__PIC_R 14U +#define XHC_PORTSC1__PIC_WIDTH 2U +#define XHC_PORTSC1__PIC_RESETVALUE 0x0U +#define XHC_PORTSC1__PS_L 13U +#define XHC_PORTSC1__PS_R 10U +#define XHC_PORTSC1__PS_WIDTH 4U +#define XHC_PORTSC1__PS_RESETVALUE 0x0U + +#define XHC_PORTSC1__PP_L 9U +#define XHC_PORTSC1__PP_R 9U +#define XHC_PORTSC1__PP_WIDTH 1U +#define XHC_PORTSC1__PP_RESETVALUE 0x0U +#define XHC_PORTSC1__PLS_L 8U +#define XHC_PORTSC1__PLS_R 5U +#define XHC_PORTSC1__PLS_WIDTH 4U +#define XHC_PORTSC1__PLS_RESETVALUE 0x5U + +#define XHC_PORTSC1__PRST_L 4U +#define XHC_PORTSC1__PRST_R 4U +#define XHC_PORTSC1__PRST_WIDTH 1U +#define XHC_PORTSC1__PRST_RESETVALUE 0x0U + +#define XHC_PORTSC1__OCA_L 3U +#define XHC_PORTSC1__OCA_R 3U +#define XHC_PORTSC1__OCA_WIDTH 1U +#define XHC_PORTSC1__OCA_RESETVALUE 0x0U +#define XHC_PORTSC1__reserved 2U +#define XHC_PORTSC1__reserved_L 2U +#define XHC_PORTSC1__reserved_R 2U +#define XHC_PORTSC1__reserved_WIDTH 1U +#define XHC_PORTSC1__reserved_RESETVALUE 0x0U + +#define XHC_PORTSC1__PED_L 1U +#define XHC_PORTSC1__PED_R 1U +#define XHC_PORTSC1__PED_WIDTH 1U +#define XHC_PORTSC1__PED_RESETVALUE 0x0U + +#define XHC_PORTSC1__CCS_L 0U +#define XHC_PORTSC1__CCS_R 0U +#define XHC_PORTSC1__CCS_WIDTH 1U +#define XHC_PORTSC1__CCS_RESETVALUE 0x0U +#define XHC_PORTSC1__RESERVED_L 29U +#define XHC_PORTSC1__RESERVED_R 28U +#define XHC_PORTSC1_WIDTH 32U +#define XHC_PORTSC1__WIDTH 32U +#define XHC_PORTSC1_ALL_L 31U +#define XHC_PORTSC1_ALL_R 0U +#define XHC_PORTSC1__ALL_L 31U +#define XHC_PORTSC1__ALL_R 0U +#define XHC_PORTSC1_DATAMASK 0xcfffffffU +#define XHC_PORTSC1_RDWRMASK 0x30000000U +#define XHC_PORTSC1_RESETVALUE 0x000000a0U + +#define XHC_PORTPM1_OFFSET 0x424U +#define XHC_PORTPM1_BASE 0x424U +#define XHC_PORTPM1__reserved_L 31U +#define XHC_PORTPM1__reserved_R 17U +#define XHC_PORTPM1__reserved_WIDTH 15U +#define XHC_PORTPM1__reserved_RESETVALUE 0x0U +#define XHC_PORTPM1__FLA 16U +#define XHC_PORTPM1__FLA_L 16U +#define XHC_PORTPM1__FLA_R 16U +#define XHC_PORTPM1__FLA_WIDTH 1U +#define XHC_PORTPM1__FLA_RESETVALUE 0x0U +#define XHC_PORTPM1__U2T_L 15U +#define XHC_PORTPM1__U2T_R 8U +#define XHC_PORTPM1__U2T_WIDTH 8U +#define XHC_PORTPM1__U2T_RESETVALUE 0x00U +#define XHC_PORTPM1__U1T_L 7U +#define XHC_PORTPM1__U1T_R 0U +#define XHC_PORTPM1__U1T_WIDTH 8U +#define XHC_PORTPM1__U1T_RESETVALUE 0x00U +#define XHC_PORTPM1_WIDTH 32U +#define XHC_PORTPM1__WIDTH 32U +#define XHC_PORTPM1_ALL_L 31U +#define XHC_PORTPM1_ALL_R 0U +#define XHC_PORTPM1__ALL_L 31U +#define XHC_PORTPM1__ALL_R 0U +#define XHC_PORTPM1_DATAMASK 0xffffffffU +#define XHC_PORTPM1_RDWRMASK 0x00000000U +#define XHC_PORTPM1_RESETVALUE 0x00000000U + +#define XHC_PORTLC1_OFFSET 0x428U +#define XHC_PORTLC1_BASE 0x428U +#define XHC_PORTLC1__reserved_L 31U +#define XHC_PORTLC1__reserved_R 0U +#define XHC_PORTLC1__reserved_WIDTH 32U +#define XHC_PORTLC1__reserved_RESETVALUE 0x00000000U +#define XHC_PORTLC1_WIDTH 32U +#define XHC_PORTLC1__WIDTH 32U +#define XHC_PORTLC1_ALL_L 31U +#define XHC_PORTLC1_ALL_R 0U +#define XHC_PORTLC1__ALL_L 31U +#define XHC_PORTLC1__ALL_R 0U +#define XHC_PORTLC1_DATAMASK 0xffffffffU +#define XHC_PORTLC1_RDWRMASK 0x00000000U +#define XHC_PORTLC1_RESETVALUE 0x00000000U + +#define XHC_PORTSC2_OFFSET 0x430U +#define XHC_PORTSC2_BASE 0x430U +#define XHC_PORTSC2__WPR 31U +#define XHC_PORTSC2__WPR_L 31U +#define XHC_PORTSC2__WPR_R 31U +#define XHC_PORTSC2__WPR_WIDTH 1U +#define XHC_PORTSC2__WPR_RESETVALUE 0x0U +#define XHC_PORTSC2__DNR 30U +#define XHC_PORTSC2__DNR_L 30U +#define XHC_PORTSC2__DNR_R 30U +#define XHC_PORTSC2__DNR_WIDTH 1U +#define XHC_PORTSC2__DNR_RESETVALUE 0x0U +#define XHC_PORTSC2__WOE 27U +#define XHC_PORTSC2__WOE_L 27U +#define XHC_PORTSC2__WOE_R 27U +#define XHC_PORTSC2__WOE_WIDTH 1U +#define XHC_PORTSC2__WOE_RESETVALUE 0x0U +#define XHC_PORTSC2__WDE 26U +#define XHC_PORTSC2__WDE_L 26U +#define XHC_PORTSC2__WDE_R 26U +#define XHC_PORTSC2__WDE_WIDTH 1U +#define XHC_PORTSC2__WDE_RESETVALUE 0x0U +#define XHC_PORTSC2__WCE 25U +#define XHC_PORTSC2__WCE_L 25U +#define XHC_PORTSC2__WCE_R 25U +#define XHC_PORTSC2__WCE_WIDTH 1U +#define XHC_PORTSC2__WCE_RESETVALUE 0x0U +#define XHC_PORTSC2__CAS 24U +#define XHC_PORTSC2__CAS_L 24U +#define XHC_PORTSC2__CAS_R 24U +#define XHC_PORTSC2__CAS_WIDTH 1U +#define XHC_PORTSC2__CAS_RESETVALUE 0x0U +#define XHC_PORTSC2__CEC 23U +#define XHC_PORTSC2__CEC_L 23U +#define XHC_PORTSC2__CEC_R 23U +#define XHC_PORTSC2__CEC_WIDTH 1U +#define XHC_PORTSC2__CEC_RESETVALUE 0x0U +#define XHC_PORTSC2__PLC 22U +#define XHC_PORTSC2__PLC_L 22U +#define XHC_PORTSC2__PLC_R 22U +#define XHC_PORTSC2__PLC_WIDTH 1U +#define XHC_PORTSC2__PLC_RESETVALUE 0x0U +#define XHC_PORTSC2__PRC 21U +#define XHC_PORTSC2__PRC_L 21U +#define XHC_PORTSC2__PRC_R 21U +#define XHC_PORTSC2__PRC_WIDTH 1U +#define XHC_PORTSC2__PRC_RESETVALUE 0x0U +#define XHC_PORTSC2__OCC 20U +#define XHC_PORTSC2__OCC_L 20U +#define XHC_PORTSC2__OCC_R 20U +#define XHC_PORTSC2__OCC_WIDTH 1U +#define XHC_PORTSC2__OCC_RESETVALUE 0x0U +#define XHC_PORTSC2__WRC 19U +#define XHC_PORTSC2__WRC_L 19U +#define XHC_PORTSC2__WRC_R 19U +#define XHC_PORTSC2__WRC_WIDTH 1U +#define XHC_PORTSC2__WRC_RESETVALUE 0x0U +#define XHC_PORTSC2__PEC 18U +#define XHC_PORTSC2__PEC_L 18U +#define XHC_PORTSC2__PEC_R 18U +#define XHC_PORTSC2__PEC_WIDTH 1U +#define XHC_PORTSC2__PEC_RESETVALUE 0x0U +#define XHC_PORTSC2__CSC 17U +#define XHC_PORTSC2__CSC_L 17U +#define XHC_PORTSC2__CSC_R 17U +#define XHC_PORTSC2__CSC_WIDTH 1U +#define XHC_PORTSC2__CSC_RESETVALUE 0x0U +#define XHC_PORTSC2__LWS 16U +#define XHC_PORTSC2__LWS_L 16U +#define XHC_PORTSC2__LWS_R 16U +#define XHC_PORTSC2__LWS_WIDTH 1U +#define XHC_PORTSC2__LWS_RESETVALUE 0x0U +#define XHC_PORTSC2__PIC_L 15U +#define XHC_PORTSC2__PIC_R 14U +#define XHC_PORTSC2__PIC_WIDTH 2U +#define XHC_PORTSC2__PIC_RESETVALUE 0x0U +#define XHC_PORTSC2__PS_L 13U +#define XHC_PORTSC2__PS_R 10U +#define XHC_PORTSC2__PS_WIDTH 4U +#define XHC_PORTSC2__PS_RESETVALUE 0x0U +#define XHC_PORTSC2__PP 9U +#define XHC_PORTSC2__PP_L 9U +#define XHC_PORTSC2__PP_R 9U +#define XHC_PORTSC2__PP_WIDTH 1U +#define XHC_PORTSC2__PP_RESETVALUE 0x0U +#define XHC_PORTSC2__PLS_L 8U +#define XHC_PORTSC2__PLS_R 5U +#define XHC_PORTSC2__PLS_WIDTH 4U +#define XHC_PORTSC2__PLS_RESETVALUE 0x5U + +#define XHC_PORTSC2__PRST_L 4U +#define XHC_PORTSC2__PRST_R 4U +#define XHC_PORTSC2__PRST_WIDTH 1U +#define XHC_PORTSC2__PRST_RESETVALUE 0x0U +#define XHC_PORTSC2__OCA 3U +#define XHC_PORTSC2__OCA_L 3U +#define XHC_PORTSC2__OCA_R 3U +#define XHC_PORTSC2__OCA_WIDTH 1U +#define XHC_PORTSC2__OCA_RESETVALUE 0x0U +#define XHC_PORTSC2__reserved 2U +#define XHC_PORTSC2__reserved_L 2U +#define XHC_PORTSC2__reserved_R 2U +#define XHC_PORTSC2__reserved_WIDTH 1U +#define XHC_PORTSC2__reserved_RESETVALUE 0x0U +#define XHC_PORTSC2__PED 1U +#define XHC_PORTSC2__PED_L 1U +#define XHC_PORTSC2__PED_R 1U +#define XHC_PORTSC2__PED_WIDTH 1U +#define XHC_PORTSC2__PED_RESETVALUE 0x0U +#define XHC_PORTSC2__CCS 0U +#define XHC_PORTSC2__CCS_L 0U +#define XHC_PORTSC2__CCS_R 0U +#define XHC_PORTSC2__CCS_WIDTH 1U +#define XHC_PORTSC2__CCS_RESETVALUE 0x0U +#define XHC_PORTSC2__RESERVED_L 29U +#define XHC_PORTSC2__RESERVED_R 28U +#define XHC_PORTSC2_WIDTH 32U +#define XHC_PORTSC2__WIDTH 32U +#define XHC_PORTSC2_ALL_L 31U +#define XHC_PORTSC2_ALL_R 0U +#define XHC_PORTSC2__ALL_L 31U +#define XHC_PORTSC2__ALL_R 0U +#define XHC_PORTSC2_DATAMASK 0xcfffffffU +#define XHC_PORTSC2_RDWRMASK 0x30000000U +#define XHC_PORTSC2_RESETVALUE 0x000000a0U + +#define XHC_PORTPM2_OFFSET 0x434U +#define XHC_PORTPM2_BASE 0x434U +#define XHC_PORTPM2__PTC_L 31U +#define XHC_PORTPM2__PTC_R 28U +#define XHC_PORTPM2__PTC_WIDTH 4U +#define XHC_PORTPM2__PTC_RESETVALUE 0x0U +#define XHC_PORTPM2__reserved_L 27U +#define XHC_PORTPM2__reserved_R 17U +#define XHC_PORTPM2__reserved_WIDTH 11U +#define XHC_PORTPM2__reserved_RESETVALUE 0x0U +#define XHC_PORTPM2__HLE 16U +#define XHC_PORTPM2__HLE_L 16U +#define XHC_PORTPM2__HLE_R 16U +#define XHC_PORTPM2__HLE_WIDTH 1U +#define XHC_PORTPM2__HLE_RESETVALUE 0x0U +#define XHC_PORTPM2__L1DS_L 15U +#define XHC_PORTPM2__L1DS_R 8U +#define XHC_PORTPM2__L1DS_WIDTH 8U +#define XHC_PORTPM2__L1DS_RESETVALUE 0x00U +#define XHC_PORTPM2__BESL_L 7U +#define XHC_PORTPM2__BESL_R 4U +#define XHC_PORTPM2__BESL_WIDTH 4U +#define XHC_PORTPM2__BESL_RESETVALUE 0x0U +#define XHC_PORTPM2__RWE 3U +#define XHC_PORTPM2__RWE_L 3U +#define XHC_PORTPM2__RWE_R 3U +#define XHC_PORTPM2__RWE_WIDTH 1U +#define XHC_PORTPM2__RWE_RESETVALUE 0x0U +#define XHC_PORTPM2__L1S_L 2U +#define XHC_PORTPM2__L1S_R 0U +#define XHC_PORTPM2__L1S_WIDTH 3U +#define XHC_PORTPM2__L1S_RESETVALUE 0x0U +#define XHC_PORTPM2_WIDTH 32U +#define XHC_PORTPM2__WIDTH 32U +#define XHC_PORTPM2_ALL_L 31U +#define XHC_PORTPM2_ALL_R 0U +#define XHC_PORTPM2__ALL_L 31U +#define XHC_PORTPM2__ALL_R 0U +#define XHC_PORTPM2_DATAMASK 0xffffffffU +#define XHC_PORTPM2_RDWRMASK 0x00000000U +#define XHC_PORTPM2_RESETVALUE 0x00000000U + +#define XHC_PORTLC2_OFFSET 0x43cU +#define XHC_PORTLC2_BASE 0x43cU +#define XHC_PORTLC2__reserved_L 31U +#define XHC_PORTLC2__reserved_R 14U +#define XHC_PORTLC2__reserved_WIDTH 18U +#define XHC_PORTLC2__reserved_RESETVALUE 0x0U +#define XHC_PORTLC2__BESLD_L 13U +#define XHC_PORTLC2__BESLD_R 10U +#define XHC_PORTLC2__BESLD_WIDTH 4U +#define XHC_PORTLC2__BESLD_RESETVALUE 0x0U +#define XHC_PORTLC2__L1T_L 9U +#define XHC_PORTLC2__L1T_R 2U +#define XHC_PORTLC2__L1T_WIDTH 8U +#define XHC_PORTLC2__L1T_RESETVALUE 0x00U +#define XHC_PORTLC2__HIRDM_L 1U +#define XHC_PORTLC2__HIRDM_R 0U +#define XHC_PORTLC2__HIRDM_WIDTH 2U +#define XHC_PORTLC2__HIRDM_RESETVALUE 0x0U +#define XHC_PORTLC2_WIDTH 32U +#define XHC_PORTLC2__WIDTH 32U +#define XHC_PORTLC2_ALL_L 31U +#define XHC_PORTLC2_ALL_R 0U +#define XHC_PORTLC2__ALL_L 31U +#define XHC_PORTLC2__ALL_R 0U +#define XHC_PORTLC2_DATAMASK 0xffffffffU +#define XHC_PORTLC2_RDWRMASK 0x00000000U +#define XHC_PORTLC2_RESETVALUE 0x00000000U + +#define XHC_PORTSC3_OFFSET 0x440U +#define XHC_PORTSC3_BASE 0x440U +#define XHC_PORTSC3__WPR 31U +#define XHC_PORTSC3__WPR_L 31U +#define XHC_PORTSC3__WPR_R 31U +#define XHC_PORTSC3__WPR_WIDTH 1U +#define XHC_PORTSC3__WPR_RESETVALUE 0x0U +#define XHC_PORTSC3__DNR 30U +#define XHC_PORTSC3__DNR_L 30U +#define XHC_PORTSC3__DNR_R 30U +#define XHC_PORTSC3__DNR_WIDTH 1U +#define XHC_PORTSC3__DNR_RESETVALUE 0x0U +#define XHC_PORTSC3__WOE 27U +#define XHC_PORTSC3__WOE_L 27U +#define XHC_PORTSC3__WOE_R 27U +#define XHC_PORTSC3__WOE_WIDTH 1U +#define XHC_PORTSC3__WOE_RESETVALUE 0x0U +#define XHC_PORTSC3__WDE 26U +#define XHC_PORTSC3__WDE_L 26U +#define XHC_PORTSC3__WDE_R 26U +#define XHC_PORTSC3__WDE_WIDTH 1U +#define XHC_PORTSC3__WDE_RESETVALUE 0x0U +#define XHC_PORTSC3__WCE 25U +#define XHC_PORTSC3__WCE_L 25U +#define XHC_PORTSC3__WCE_R 25U +#define XHC_PORTSC3__WCE_WIDTH 1U +#define XHC_PORTSC3__WCE_RESETVALUE 0x0U +#define XHC_PORTSC3__CAS 24U +#define XHC_PORTSC3__CAS_L 24U +#define XHC_PORTSC3__CAS_R 24U +#define XHC_PORTSC3__CAS_WIDTH 1U +#define XHC_PORTSC3__CAS_RESETVALUE 0x0U +#define XHC_PORTSC3__CEC 23U +#define XHC_PORTSC3__CEC_L 23U +#define XHC_PORTSC3__CEC_R 23U +#define XHC_PORTSC3__CEC_WIDTH 1U +#define XHC_PORTSC3__CEC_RESETVALUE 0x0U +#define XHC_PORTSC3__PLC 22U +#define XHC_PORTSC3__PLC_L 22U +#define XHC_PORTSC3__PLC_R 22U +#define XHC_PORTSC3__PLC_WIDTH 1U +#define XHC_PORTSC3__PLC_RESETVALUE 0x0U +#define XHC_PORTSC3__PRC 21U +#define XHC_PORTSC3__PRC_L 21U +#define XHC_PORTSC3__PRC_R 21U +#define XHC_PORTSC3__PRC_WIDTH 1U +#define XHC_PORTSC3__PRC_RESETVALUE 0x0U +#define XHC_PORTSC3__OCC 20U +#define XHC_PORTSC3__OCC_L 20U +#define XHC_PORTSC3__OCC_R 20U +#define XHC_PORTSC3__OCC_WIDTH 1U +#define XHC_PORTSC3__OCC_RESETVALUE 0x0U +#define XHC_PORTSC3__WRC 19U +#define XHC_PORTSC3__WRC_L 19U +#define XHC_PORTSC3__WRC_R 19U +#define XHC_PORTSC3__WRC_WIDTH 1U +#define XHC_PORTSC3__WRC_RESETVALUE 0x0U +#define XHC_PORTSC3__PEC 18U +#define XHC_PORTSC3__PEC_L 18U +#define XHC_PORTSC3__PEC_R 18U +#define XHC_PORTSC3__PEC_WIDTH 1U +#define XHC_PORTSC3__PEC_RESETVALUE 0x0U +#define XHC_PORTSC3__CSC 17U +#define XHC_PORTSC3__CSC_L 17U +#define XHC_PORTSC3__CSC_R 17U +#define XHC_PORTSC3__CSC_WIDTH 1U +#define XHC_PORTSC3__CSC_RESETVALUE 0x0U +#define XHC_PORTSC3__LWS 16U +#define XHC_PORTSC3__LWS_L 16U +#define XHC_PORTSC3__LWS_R 16U +#define XHC_PORTSC3__LWS_WIDTH 1U +#define XHC_PORTSC3__LWS_RESETVALUE 0x0U +#define XHC_PORTSC3__PIC_L 15U +#define XHC_PORTSC3__PIC_R 14U +#define XHC_PORTSC3__PIC_WIDTH 2U +#define XHC_PORTSC3__PIC_RESETVALUE 0x0U +#define XHC_PORTSC3__PS_L 13U +#define XHC_PORTSC3__PS_R 10U +#define XHC_PORTSC3__PS_WIDTH 4U +#define XHC_PORTSC3__PS_RESETVALUE 0x0U +#define XHC_PORTSC3__PP 9U +#define XHC_PORTSC3__PP_L 9U +#define XHC_PORTSC3__PP_R 9U +#define XHC_PORTSC3__PP_WIDTH 1U +#define XHC_PORTSC3__PP_RESETVALUE 0x0U +#define XHC_PORTSC3__PLS_L 8U +#define XHC_PORTSC3__PLS_R 5U +#define XHC_PORTSC3__PLS_WIDTH 4U +#define XHC_PORTSC3__PLS_RESETVALUE 0x5U +#define XHC_PORTSC3__PR 4U +#define XHC_PORTSC3__PR_L 4U +#define XHC_PORTSC3__PR_R 4U +#define XHC_PORTSC3__PR_WIDTH 1U +#define XHC_PORTSC3__PR_RESETVALUE 0x0U +#define XHC_PORTSC3__OCA 3U +#define XHC_PORTSC3__OCA_L 3U +#define XHC_PORTSC3__OCA_R 3U +#define XHC_PORTSC3__OCA_WIDTH 1U +#define XHC_PORTSC3__OCA_RESETVALUE 0x0U +#define XHC_PORTSC3__reserved 2U +#define XHC_PORTSC3__reserved_L 2U +#define XHC_PORTSC3__reserved_R 2U +#define XHC_PORTSC3__reserved_WIDTH 1U +#define XHC_PORTSC3__reserved_RESETVALUE 0x0U +#define XHC_PORTSC3__PED 1U +#define XHC_PORTSC3__PED_L 1U +#define XHC_PORTSC3__PED_R 1U +#define XHC_PORTSC3__PED_WIDTH 1U +#define XHC_PORTSC3__PED_RESETVALUE 0x0U +#define XHC_PORTSC3__CCS 0U +#define XHC_PORTSC3__CCS_L 0U +#define XHC_PORTSC3__CCS_R 0U +#define XHC_PORTSC3__CCS_WIDTH 1U +#define XHC_PORTSC3__CCS_RESETVALUE 0x0U +#define XHC_PORTSC3__RESERVED_L 29U +#define XHC_PORTSC3__RESERVED_R 28U +#define XHC_PORTSC3_WIDTH 32U +#define XHC_PORTSC3__WIDTH 32U +#define XHC_PORTSC3_ALL_L 31U +#define XHC_PORTSC3_ALL_R 0U +#define XHC_PORTSC3__ALL_L 31U +#define XHC_PORTSC3__ALL_R 0U +#define XHC_PORTSC3_DATAMASK 0xcfffffffU +#define XHC_PORTSC3_RDWRMASK 0x30000000U +#define XHC_PORTSC3_RESETVALUE 0x000000a0U + +#define XHC_PORTPM3_OFFSET 0x444U +#define XHC_PORTPM3_BASE 0x444U +#define XHC_PORTPM3__PTC_L 31U +#define XHC_PORTPM3__PTC_R 28U +#define XHC_PORTPM3__PTC_WIDTH 4U +#define XHC_PORTPM3__PTC_RESETVALUE 0x0U +#define XHC_PORTPM3__reserved_L 27U +#define XHC_PORTPM3__reserved_R 17U +#define XHC_PORTPM3__reserved_WIDTH 11U +#define XHC_PORTPM3__reserved_RESETVALUE 0x0U +#define XHC_PORTPM3__HLE 16U +#define XHC_PORTPM3__HLE_L 16U +#define XHC_PORTPM3__HLE_R 16U +#define XHC_PORTPM3__HLE_WIDTH 1U +#define XHC_PORTPM3__HLE_RESETVALUE 0x0U +#define XHC_PORTPM3__L1DS_L 15U +#define XHC_PORTPM3__L1DS_R 8U +#define XHC_PORTPM3__L1DS_WIDTH 8U +#define XHC_PORTPM3__L1DS_RESETVALUE 0x00U +#define XHC_PORTPM3__BESL_L 7U +#define XHC_PORTPM3__BESL_R 4U +#define XHC_PORTPM3__BESL_WIDTH 4U +#define XHC_PORTPM3__BESL_RESETVALUE 0x0U +#define XHC_PORTPM3__RWE 3U +#define XHC_PORTPM3__RWE_L 3U +#define XHC_PORTPM3__RWE_R 3U +#define XHC_PORTPM3__RWE_WIDTH 1U +#define XHC_PORTPM3__RWE_RESETVALUE 0x0U +#define XHC_PORTPM3__L1S_L 2U +#define XHC_PORTPM3__L1S_R 0U +#define XHC_PORTPM3__L1S_WIDTH 3U +#define XHC_PORTPM3__L1S_RESETVALUE 0x0U +#define XHC_PORTPM3_WIDTH 32U +#define XHC_PORTPM3__WIDTH 32U +#define XHC_PORTPM3_ALL_L 31U +#define XHC_PORTPM3_ALL_R 0U +#define XHC_PORTPM3__ALL_L 31U +#define XHC_PORTPM3__ALL_R 0U +#define XHC_PORTPM3_DATAMASK 0xffffffffU +#define XHC_PORTPM3_RDWRMASK 0x00000000U +#define XHC_PORTPM3_RESETVALUE 0x00000000U + +#define XHC_PORTLI3_OFFSET 0x44cU +#define XHC_PORTLI3_BASE 0x44cU +#define XHC_PORTLI3__reserved_L 31U +#define XHC_PORTLI3__reserved_R 0U +#define XHC_PORTLI3__reserved_WIDTH 32U +#define XHC_PORTLI3__reserved_RESETVALUE 0x00000000U +#define XHC_PORTLI3_WIDTH 32U +#define XHC_PORTLI3__WIDTH 32U +#define XHC_PORTLI3_ALL_L 31U +#define XHC_PORTLI3_ALL_R 0U +#define XHC_PORTLI3__ALL_L 31U +#define XHC_PORTLI3__ALL_R 0U +#define XHC_PORTLI3_DATAMASK 0xffffffffU +#define XHC_PORTLI3_RDWRMASK 0x00000000U +#define XHC_PORTLI3_RESETVALUE 0x00000000U + +#define XHC_MFINDEX_OFFSET 0x4a0U +#define XHC_MFINDEX_BASE 0x4a0U +#define XHC_MFINDEX__reserved_L 31U +#define XHC_MFINDEX__reserved_R 14U +#define XHC_MFINDEX__reserved_WIDTH 18U +#define XHC_MFINDEX__reserved_RESETVALUE 0x0U +#define XHC_MFINDEX__MFI_L 13U +#define XHC_MFINDEX__MFI_R 0U +#define XHC_MFINDEX__MFI_WIDTH 14U +#define XHC_MFINDEX__MFI_RESETVALUE 0x0U +#define XHC_MFINDEX_WIDTH 32U +#define XHC_MFINDEX__WIDTH 32U +#define XHC_MFINDEX_ALL_L 31U +#define XHC_MFINDEX_ALL_R 0U +#define XHC_MFINDEX__ALL_L 31U +#define XHC_MFINDEX__ALL_R 0U +#define XHC_MFINDEX_DATAMASK 0xffffffffU +#define XHC_MFINDEX_RDWRMASK 0x00000000U +#define XHC_MFINDEX_RESETVALUE 0x00000000U + +#define XHC_IMAN0_OFFSET 0x4c0U +#define XHC_IMAN0_BASE 0x4c0U +#define XHC_IMAN0__reserved_L 31U +#define XHC_IMAN0__reserved_R 2U +#define XHC_IMAN0__reserved_WIDTH 30U +#define XHC_IMAN0__reserved_RESETVALUE 0x0U +#define XHC_IMAN0__IE 1U +#define XHC_IMAN0__IE_L 1U +#define XHC_IMAN0__IE_R 1U +#define XHC_IMAN0__IE_WIDTH 1U +#define XHC_IMAN0__IE_RESETVALUE 0x0U +#define XHC_IMAN0__IP 0U +#define XHC_IMAN0__IP_L 0U +#define XHC_IMAN0__IP_R 0U +#define XHC_IMAN0__IP_WIDTH 1U +#define XHC_IMAN0__IP_RESETVALUE 0x0U +#define XHC_IMAN0_WIDTH 32U +#define XHC_IMAN0__WIDTH 32U +#define XHC_IMAN0_ALL_L 31U +#define XHC_IMAN0_ALL_R 0U +#define XHC_IMAN0__ALL_L 31U +#define XHC_IMAN0__ALL_R 0U +#define XHC_IMAN0_DATAMASK 0xffffffffU +#define XHC_IMAN0_RDWRMASK 0x00000000U +#define XHC_IMAN0_RESETVALUE 0x00000000U + +#define XHC_IMOD0_OFFSET 0x4c4U +#define XHC_IMOD0_BASE 0x4c4U +#define XHC_IMOD0__IMODC_L 31U +#define XHC_IMOD0__IMODC_R 16U +#define XHC_IMOD0__IMODC_WIDTH 16U +#define XHC_IMOD0__IMODC_RESETVALUE 0x0000U +#define XHC_IMOD0__IMODI_L 15U +#define XHC_IMOD0__IMODI_R 0U +#define XHC_IMOD0__IMODI_WIDTH 16U +#define XHC_IMOD0__IMODI_RESETVALUE 0x4000U +#define XHC_IMOD0_WIDTH 32U +#define XHC_IMOD0__WIDTH 32U +#define XHC_IMOD0_ALL_L 31U +#define XHC_IMOD0_ALL_R 0U +#define XHC_IMOD0__ALL_L 31U +#define XHC_IMOD0__ALL_R 0U +#define XHC_IMOD0_DATAMASK 0xffffffffU +#define XHC_IMOD0_RDWRMASK 0x00000000U +#define XHC_IMOD0_RESETVALUE 0x00004000U + +#define XHC_ERSTSZ0_OFFSET 0x4c8U +#define XHC_ERSTSZ0_BASE 0x4c8U +#define XHC_ERSTSZ0__reserved_L 31U +#define XHC_ERSTSZ0__reserved_R 16U +#define XHC_ERSTSZ0__reserved_WIDTH 16U +#define XHC_ERSTSZ0__reserved_RESETVALUE 0x0000U +#define XHC_ERSTSZ0__TSZ_L 15U +#define XHC_ERSTSZ0__TSZ_R 0U +#define XHC_ERSTSZ0__TSZ_WIDTH 16U +#define XHC_ERSTSZ0__TSZ_RESETVALUE 0x0000U +#define XHC_ERSTSZ0_WIDTH 32U +#define XHC_ERSTSZ0__WIDTH 32U +#define XHC_ERSTSZ0_ALL_L 31U +#define XHC_ERSTSZ0_ALL_R 0U +#define XHC_ERSTSZ0__ALL_L 31U +#define XHC_ERSTSZ0__ALL_R 0U +#define XHC_ERSTSZ0_DATAMASK 0xffffffffU +#define XHC_ERSTSZ0_RDWRMASK 0x00000000U +#define XHC_ERSTSZ0_RESETVALUE 0x00000000U + +#define XHC_ERSTBAL0_OFFSET 0x4d0U +#define XHC_ERSTBAL0_BASE 0x4d0U +#define XHC_ERSTBAL0__BAL_L 31U +#define XHC_ERSTBAL0__BAL_R 4U +#define XHC_ERSTBAL0__BAL_WIDTH 28U +#define XHC_ERSTBAL0__BAL_RESETVALUE 0x0000000U +#define XHC_ERSTBAL0__reserved_L 3U +#define XHC_ERSTBAL0__reserved_R 0U +#define XHC_ERSTBAL0__reserved_WIDTH 4U +#define XHC_ERSTBAL0__reserved_RESETVALUE 0x0U +#define XHC_ERSTBAL0_WIDTH 32U +#define XHC_ERSTBAL0__WIDTH 32U +#define XHC_ERSTBAL0_ALL_L 31U +#define XHC_ERSTBAL0_ALL_R 0U +#define XHC_ERSTBAL0__ALL_L 31U +#define XHC_ERSTBAL0__ALL_R 0U +#define XHC_ERSTBAL0_DATAMASK 0xffffffffU +#define XHC_ERSTBAL0_RDWRMASK 0x00000000U +#define XHC_ERSTBAL0_RESETVALUE 0x00000000U + +#define XHC_ERSTBAH0_OFFSET 0x4d4U +#define XHC_ERSTBAH0_BASE 0x4d4U +#define XHC_ERSTBAH0__BAH_L 31U +#define XHC_ERSTBAH0__BAH_R 0U +#define XHC_ERSTBAH0__BAH_WIDTH 32U +#define XHC_ERSTBAH0__BAH_RESETVALUE 0x00000000U +#define XHC_ERSTBAH0_WIDTH 32U +#define XHC_ERSTBAH0__WIDTH 32U +#define XHC_ERSTBAH0_ALL_L 31U +#define XHC_ERSTBAH0_ALL_R 0U +#define XHC_ERSTBAH0__ALL_L 31U +#define XHC_ERSTBAH0__ALL_R 0U +#define XHC_ERSTBAH0_DATAMASK 0xffffffffU +#define XHC_ERSTBAH0_RDWRMASK 0x00000000U +#define XHC_ERSTBAH0_RESETVALUE 0x00000000U + +#define XHC_ERDPL0_OFFSET 0x4d8U +#define XHC_ERDPL0_BASE 0x4d8U +#define XHC_ERDPL0__DPL_L 31U +#define XHC_ERDPL0__DPL_R 4U +#define XHC_ERDPL0__DPL_WIDTH 28U +#define XHC_ERDPL0__DPL_RESETVALUE 0x0000000U +#define XHC_ERDPL0__EHB 3U +#define XHC_ERDPL0__EHB_L 3U +#define XHC_ERDPL0__EHB_R 3U +#define XHC_ERDPL0__EHB_WIDTH 1U +#define XHC_ERDPL0__EHB_RESETVALUE 0x0U +#define XHC_ERDPL0__DESI_L 2U +#define XHC_ERDPL0__DESI_R 0U +#define XHC_ERDPL0__DESI_WIDTH 3U +#define XHC_ERDPL0__DESI_RESETVALUE 0x0U +#define XHC_ERDPL0_WIDTH 32U +#define XHC_ERDPL0__WIDTH 32U +#define XHC_ERDPL0_ALL_L 31U +#define XHC_ERDPL0_ALL_R 0U +#define XHC_ERDPL0__ALL_L 31U +#define XHC_ERDPL0__ALL_R 0U +#define XHC_ERDPL0_DATAMASK 0xffffffffU +#define XHC_ERDPL0_RDWRMASK 0x00000000U +#define XHC_ERDPL0_RESETVALUE 0x00000000U + +#define XHC_ERDPH0_OFFSET 0x4dcU +#define XHC_ERDPH0_BASE 0x4dcU +#define XHC_ERDPH0__DPH_L 31U +#define XHC_ERDPH0__DPH_R 0U +#define XHC_ERDPH0__DPH_WIDTH 32U +#define XHC_ERDPH0__DPH_RESETVALUE 0x00000000U +#define XHC_ERDPH0_WIDTH 32U +#define XHC_ERDPH0__WIDTH 32U +#define XHC_ERDPH0_ALL_L 31U +#define XHC_ERDPH0_ALL_R 0U +#define XHC_ERDPH0__ALL_L 31U +#define XHC_ERDPH0__ALL_R 0U +#define XHC_ERDPH0_DATAMASK 0xffffffffU +#define XHC_ERDPH0_RDWRMASK 0x00000000U +#define XHC_ERDPH0_RESETVALUE 0x00000000U + +#define XHC_IMAN1_OFFSET 0x4e0U +#define XHC_IMAN1_BASE 0x4e0U +#define XHC_IMAN1__reserved_L 31U +#define XHC_IMAN1__reserved_R 2U +#define XHC_IMAN1__reserved_WIDTH 30U +#define XHC_IMAN1__reserved_RESETVALUE 0x0U +#define XHC_IMAN1__IE 1U +#define XHC_IMAN1__IE_L 1U +#define XHC_IMAN1__IE_R 1U +#define XHC_IMAN1__IE_WIDTH 1U +#define XHC_IMAN1__IE_RESETVALUE 0x0U +#define XHC_IMAN1__IP 0U +#define XHC_IMAN1__IP_L 0U +#define XHC_IMAN1__IP_R 0U +#define XHC_IMAN1__IP_WIDTH 1U +#define XHC_IMAN1__IP_RESETVALUE 0x0U +#define XHC_IMAN1_WIDTH 32U +#define XHC_IMAN1__WIDTH 32U +#define XHC_IMAN1_ALL_L 31U +#define XHC_IMAN1_ALL_R 0U +#define XHC_IMAN1__ALL_L 31U +#define XHC_IMAN1__ALL_R 0U +#define XHC_IMAN1_DATAMASK 0xffffffffU +#define XHC_IMAN1_RDWRMASK 0x00000000U +#define XHC_IMAN1_RESETVALUE 0x00000000U + +#define XHC_IMOD1_OFFSET 0x4e4U +#define XHC_IMOD1_BASE 0x4e4U +#define XHC_IMOD1__IMODC_L 31U +#define XHC_IMOD1__IMODC_R 16U +#define XHC_IMOD1__IMODC_WIDTH 16U +#define XHC_IMOD1__IMODC_RESETVALUE 0x0000U +#define XHC_IMOD1__IMODI_L 15U +#define XHC_IMOD1__IMODI_R 0U +#define XHC_IMOD1__IMODI_WIDTH 16U +#define XHC_IMOD1__IMODI_RESETVALUE 0x4000U +#define XHC_IMOD1_WIDTH 32U +#define XHC_IMOD1__WIDTH 32U +#define XHC_IMOD1_ALL_L 31U +#define XHC_IMOD1_ALL_R 0U +#define XHC_IMOD1__ALL_L 31U +#define XHC_IMOD1__ALL_R 0U +#define XHC_IMOD1_DATAMASK 0xffffffffU +#define XHC_IMOD1_RDWRMASK 0x00000000U +#define XHC_IMOD1_RESETVALUE 0x00004000U + +#define XHC_ERSTSZ1_OFFSET 0x4e8U +#define XHC_ERSTSZ1_BASE 0x4e8U +#define XHC_ERSTSZ1__reserved_L 31U +#define XHC_ERSTSZ1__reserved_R 16U +#define XHC_ERSTSZ1__reserved_WIDTH 16U +#define XHC_ERSTSZ1__reserved_RESETVALUE 0x0000U +#define XHC_ERSTSZ1__TSZ_L 15U +#define XHC_ERSTSZ1__TSZ_R 0U +#define XHC_ERSTSZ1__TSZ_WIDTH 16U +#define XHC_ERSTSZ1__TSZ_RESETVALUE 0x0000U +#define XHC_ERSTSZ1_WIDTH 32U +#define XHC_ERSTSZ1__WIDTH 32U +#define XHC_ERSTSZ1_ALL_L 31U +#define XHC_ERSTSZ1_ALL_R 0U +#define XHC_ERSTSZ1__ALL_L 31U +#define XHC_ERSTSZ1__ALL_R 0U +#define XHC_ERSTSZ1_DATAMASK 0xffffffffU +#define XHC_ERSTSZ1_RDWRMASK 0x00000000U +#define XHC_ERSTSZ1_RESETVALUE 0x00000000U + +#define XHC_ERSTBAL1_OFFSET 0x4f0U +#define XHC_ERSTBAL1_BASE 0x4f0U +#define XHC_ERSTBAL1__BAL_L 31U +#define XHC_ERSTBAL1__BAL_R 4U +#define XHC_ERSTBAL1__BAL_WIDTH 28U +#define XHC_ERSTBAL1__BAL_RESETVALUE 0x0000000U +#define XHC_ERSTBAL1__reserved_L 3U +#define XHC_ERSTBAL1__reserved_R 0U +#define XHC_ERSTBAL1__reserved_WIDTH 4U +#define XHC_ERSTBAL1__reserved_RESETVALUE 0x0U +#define XHC_ERSTBAL1_WIDTH 32U +#define XHC_ERSTBAL1__WIDTH 32U +#define XHC_ERSTBAL1_ALL_L 31U +#define XHC_ERSTBAL1_ALL_R 0U +#define XHC_ERSTBAL1__ALL_L 31U +#define XHC_ERSTBAL1__ALL_R 0U +#define XHC_ERSTBAL1_DATAMASK 0xffffffffU +#define XHC_ERSTBAL1_RDWRMASK 0x00000000U +#define XHC_ERSTBAL1_RESETVALUE 0x00000000U + +#define XHC_ERSTBAH1_OFFSET 0x4f4U +#define XHC_ERSTBAH1_BASE 0x4f4U +#define XHC_ERSTBAH1__BAH_L 31U +#define XHC_ERSTBAH1__BAH_R 0U +#define XHC_ERSTBAH1__BAH_WIDTH 32U +#define XHC_ERSTBAH1__BAH_RESETVALUE 0x00000000U +#define XHC_ERSTBAH1_WIDTH 32U +#define XHC_ERSTBAH1__WIDTH 32U +#define XHC_ERSTBAH1_ALL_L 31U +#define XHC_ERSTBAH1_ALL_R 0U +#define XHC_ERSTBAH1__ALL_L 31U +#define XHC_ERSTBAH1__ALL_R 0U +#define XHC_ERSTBAH1_DATAMASK 0xffffffffU +#define XHC_ERSTBAH1_RDWRMASK 0x00000000U +#define XHC_ERSTBAH1_RESETVALUE 0x00000000U + +#define XHC_ERDPL1_OFFSET 0x4f8U +#define XHC_ERDPL1_BASE 0x4f8U +#define XHC_ERDPL1__DPL_L 31U +#define XHC_ERDPL1__DPL_R 4U +#define XHC_ERDPL1__DPL_WIDTH 28U +#define XHC_ERDPL1__DPL_RESETVALUE 0x0000000U +#define XHC_ERDPL1__EHB 3U +#define XHC_ERDPL1__EHB_L 3U +#define XHC_ERDPL1__EHB_R 3U +#define XHC_ERDPL1__EHB_WIDTH 1U +#define XHC_ERDPL1__EHB_RESETVALUE 0x0U +#define XHC_ERDPL1__DESI_L 2U +#define XHC_ERDPL1__DESI_R 0U +#define XHC_ERDPL1__DESI_WIDTH 3U +#define XHC_ERDPL1__DESI_RESETVALUE 0x0U +#define XHC_ERDPL1_WIDTH 32U +#define XHC_ERDPL1__WIDTH 32U +#define XHC_ERDPL1_ALL_L 31U +#define XHC_ERDPL1_ALL_R 0U +#define XHC_ERDPL1__ALL_L 31U +#define XHC_ERDPL1__ALL_R 0U +#define XHC_ERDPL1_DATAMASK 0xffffffffU +#define XHC_ERDPL1_RDWRMASK 0x00000000U +#define XHC_ERDPL1_RESETVALUE 0x00000000U + +#define XHC_ERDPH1_OFFSET 0x4fcU +#define XHC_ERDPH1_BASE 0x4fcU +#define XHC_ERDPH1__DPH_L 31U +#define XHC_ERDPH1__DPH_R 0U +#define XHC_ERDPH1__DPH_WIDTH 32U +#define XHC_ERDPH1__DPH_RESETVALUE 0x00000000U +#define XHC_ERDPH1_WIDTH 32U +#define XHC_ERDPH1__WIDTH 32U +#define XHC_ERDPH1_ALL_L 31U +#define XHC_ERDPH1_ALL_R 0U +#define XHC_ERDPH1__ALL_L 31U +#define XHC_ERDPH1__ALL_R 0U +#define XHC_ERDPH1_DATAMASK 0xffffffffU +#define XHC_ERDPH1_RDWRMASK 0x00000000U +#define XHC_ERDPH1_RESETVALUE 0x00000000U + +#define XHC_DBLCMD_OFFSET 0x8c0U +#define XHC_DBLCMD_BASE 0x8c0U +#define XHC_DBLCMD__SID_L 31U +#define XHC_DBLCMD__SID_R 16U +#define XHC_DBLCMD__SID_WIDTH 16U +#define XHC_DBLCMD__SID_RESETVALUE 0x0000U +#define XHC_DBLCMD__reserved_L 15U +#define XHC_DBLCMD__reserved_R 8U +#define XHC_DBLCMD__reserved_WIDTH 8U +#define XHC_DBLCMD__reserved_RESETVALUE 0x00U +#define XHC_DBLCMD__TGT_L 7U +#define XHC_DBLCMD__TGT_R 0U +#define XHC_DBLCMD__TGT_WIDTH 8U +#define XHC_DBLCMD__TGT_RESETVALUE 0x00U +#define XHC_DBLCMD_WIDTH 32U +#define XHC_DBLCMD__WIDTH 32U +#define XHC_DBLCMD_ALL_L 31U +#define XHC_DBLCMD_ALL_R 0U +#define XHC_DBLCMD__ALL_L 31U +#define XHC_DBLCMD__ALL_R 0U +#define XHC_DBLCMD_DATAMASK 0xffffffffU +#define XHC_DBLCMD_RDWRMASK 0x00000000U +#define XHC_DBLCMD_RESETVALUE 0x00000000U + +#define XHC_DBLDVX1_OFFSET 0x8c4U +#define XHC_DBLDVX1_BASE 0x8c4U +#define XHC_DBLDVX1__SID_L 31U +#define XHC_DBLDVX1__SID_R 16U +#define XHC_DBLDVX1__SID_WIDTH 16U +#define XHC_DBLDVX1__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX1__reserved_L 15U +#define XHC_DBLDVX1__reserved_R 8U +#define XHC_DBLDVX1__reserved_WIDTH 8U +#define XHC_DBLDVX1__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX1__TGT_L 7U +#define XHC_DBLDVX1__TGT_R 0U +#define XHC_DBLDVX1__TGT_WIDTH 8U +#define XHC_DBLDVX1__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX1_WIDTH 32U +#define XHC_DBLDVX1__WIDTH 32U +#define XHC_DBLDVX1_ALL_L 31U +#define XHC_DBLDVX1_ALL_R 0U +#define XHC_DBLDVX1__ALL_L 31U +#define XHC_DBLDVX1__ALL_R 0U +#define XHC_DBLDVX1_DATAMASK 0xffffffffU +#define XHC_DBLDVX1_RDWRMASK 0x00000000U +#define XHC_DBLDVX1_RESETVALUE 0x00000000U + +#define XHC_DBLDVX2_OFFSET 0x8c8U +#define XHC_DBLDVX2_BASE 0x8c8U +#define XHC_DBLDVX2__SID_L 31U +#define XHC_DBLDVX2__SID_R 16U +#define XHC_DBLDVX2__SID_WIDTH 16U +#define XHC_DBLDVX2__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX2__reserved_L 15U +#define XHC_DBLDVX2__reserved_R 8U +#define XHC_DBLDVX2__reserved_WIDTH 8U +#define XHC_DBLDVX2__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX2__TGT_L 7U +#define XHC_DBLDVX2__TGT_R 0U +#define XHC_DBLDVX2__TGT_WIDTH 8U +#define XHC_DBLDVX2__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX2_WIDTH 32U +#define XHC_DBLDVX2__WIDTH 32U +#define XHC_DBLDVX2_ALL_L 31U +#define XHC_DBLDVX2_ALL_R 0U +#define XHC_DBLDVX2__ALL_L 31U +#define XHC_DBLDVX2__ALL_R 0U +#define XHC_DBLDVX2_DATAMASK 0xffffffffU +#define XHC_DBLDVX2_RDWRMASK 0x00000000U +#define XHC_DBLDVX2_RESETVALUE 0x00000000U + +#define XHC_DBLDVX3_OFFSET 0x8ccU +#define XHC_DBLDVX3_BASE 0x8ccU +#define XHC_DBLDVX3__SID_L 31U +#define XHC_DBLDVX3__SID_R 16U +#define XHC_DBLDVX3__SID_WIDTH 16U +#define XHC_DBLDVX3__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX3__reserved_L 15U +#define XHC_DBLDVX3__reserved_R 8U +#define XHC_DBLDVX3__reserved_WIDTH 8U +#define XHC_DBLDVX3__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX3__TGT_L 7U +#define XHC_DBLDVX3__TGT_R 0U +#define XHC_DBLDVX3__TGT_WIDTH 8U +#define XHC_DBLDVX3__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX3_WIDTH 32U +#define XHC_DBLDVX3__WIDTH 32U +#define XHC_DBLDVX3_ALL_L 31U +#define XHC_DBLDVX3_ALL_R 0U +#define XHC_DBLDVX3__ALL_L 31U +#define XHC_DBLDVX3__ALL_R 0U +#define XHC_DBLDVX3_DATAMASK 0xffffffffU +#define XHC_DBLDVX3_RDWRMASK 0x00000000U +#define XHC_DBLDVX3_RESETVALUE 0x00000000U + +#define XHC_DBLDVX4_OFFSET 0x8d0U +#define XHC_DBLDVX4_BASE 0x8d0U +#define XHC_DBLDVX4__SID_L 31U +#define XHC_DBLDVX4__SID_R 16U +#define XHC_DBLDVX4__SID_WIDTH 16U +#define XHC_DBLDVX4__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX4__reserved_L 15U +#define XHC_DBLDVX4__reserved_R 8U +#define XHC_DBLDVX4__reserved_WIDTH 8U +#define XHC_DBLDVX4__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX4__TGT_L 7U +#define XHC_DBLDVX4__TGT_R 0U +#define XHC_DBLDVX4__TGT_WIDTH 8U +#define XHC_DBLDVX4__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX4_WIDTH 32U +#define XHC_DBLDVX4__WIDTH 32U +#define XHC_DBLDVX4_ALL_L 31U +#define XHC_DBLDVX4_ALL_R 0U +#define XHC_DBLDVX4__ALL_L 31U +#define XHC_DBLDVX4__ALL_R 0U +#define XHC_DBLDVX4_DATAMASK 0xffffffffU +#define XHC_DBLDVX4_RDWRMASK 0x00000000U +#define XHC_DBLDVX4_RESETVALUE 0x00000000U + +#define XHC_DBLDVX5_OFFSET 0x8d4U +#define XHC_DBLDVX5_BASE 0x8d4U +#define XHC_DBLDVX5__SID_L 31U +#define XHC_DBLDVX5__SID_R 16U +#define XHC_DBLDVX5__SID_WIDTH 16U +#define XHC_DBLDVX5__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX5__reserved_L 15U +#define XHC_DBLDVX5__reserved_R 8U +#define XHC_DBLDVX5__reserved_WIDTH 8U +#define XHC_DBLDVX5__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX5__TGT_L 7U +#define XHC_DBLDVX5__TGT_R 0U +#define XHC_DBLDVX5__TGT_WIDTH 8U +#define XHC_DBLDVX5__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX5_WIDTH 32U +#define XHC_DBLDVX5__WIDTH 32U +#define XHC_DBLDVX5_ALL_L 31U +#define XHC_DBLDVX5_ALL_R 0U +#define XHC_DBLDVX5__ALL_L 31U +#define XHC_DBLDVX5__ALL_R 0U +#define XHC_DBLDVX5_DATAMASK 0xffffffffU +#define XHC_DBLDVX5_RDWRMASK 0x00000000U +#define XHC_DBLDVX5_RESETVALUE 0x00000000U + +#define XHC_DBLDVX6_OFFSET 0x8d8U +#define XHC_DBLDVX6_BASE 0x8d8U +#define XHC_DBLDVX6__SID_L 31U +#define XHC_DBLDVX6__SID_R 16U +#define XHC_DBLDVX6__SID_WIDTH 16U +#define XHC_DBLDVX6__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX6__reserved_L 15U +#define XHC_DBLDVX6__reserved_R 8U +#define XHC_DBLDVX6__reserved_WIDTH 8U +#define XHC_DBLDVX6__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX6__TGT_L 7U +#define XHC_DBLDVX6__TGT_R 0U +#define XHC_DBLDVX6__TGT_WIDTH 8U +#define XHC_DBLDVX6__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX6_WIDTH 32U +#define XHC_DBLDVX6__WIDTH 32U +#define XHC_DBLDVX6_ALL_L 31U +#define XHC_DBLDVX6_ALL_R 0U +#define XHC_DBLDVX6__ALL_L 31U +#define XHC_DBLDVX6__ALL_R 0U +#define XHC_DBLDVX6_DATAMASK 0xffffffffU +#define XHC_DBLDVX6_RDWRMASK 0x00000000U +#define XHC_DBLDVX6_RESETVALUE 0x00000000U + +#define XHC_DBLDVX7_OFFSET 0x8dcU +#define XHC_DBLDVX7_BASE 0x8dcU +#define XHC_DBLDVX7__SID_L 31U +#define XHC_DBLDVX7__SID_R 16U +#define XHC_DBLDVX7__SID_WIDTH 16U +#define XHC_DBLDVX7__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX7__reserved_L 15U +#define XHC_DBLDVX7__reserved_R 8U +#define XHC_DBLDVX7__reserved_WIDTH 8U +#define XHC_DBLDVX7__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX7__TGT_L 7U +#define XHC_DBLDVX7__TGT_R 0U +#define XHC_DBLDVX7__TGT_WIDTH 8U +#define XHC_DBLDVX7__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX7_WIDTH 32U +#define XHC_DBLDVX7__WIDTH 32U +#define XHC_DBLDVX7_ALL_L 31U +#define XHC_DBLDVX7_ALL_R 0U +#define XHC_DBLDVX7__ALL_L 31U +#define XHC_DBLDVX7__ALL_R 0U +#define XHC_DBLDVX7_DATAMASK 0xffffffffU +#define XHC_DBLDVX7_RDWRMASK 0x00000000U +#define XHC_DBLDVX7_RESETVALUE 0x00000000U + +#define XHC_DBLDVX8_OFFSET 0x8e0U +#define XHC_DBLDVX8_BASE 0x8e0U +#define XHC_DBLDVX8__SID_L 31U +#define XHC_DBLDVX8__SID_R 16U +#define XHC_DBLDVX8__SID_WIDTH 16U +#define XHC_DBLDVX8__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX8__reserved_L 15U +#define XHC_DBLDVX8__reserved_R 8U +#define XHC_DBLDVX8__reserved_WIDTH 8U +#define XHC_DBLDVX8__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX8__TGT_L 7U +#define XHC_DBLDVX8__TGT_R 0U +#define XHC_DBLDVX8__TGT_WIDTH 8U +#define XHC_DBLDVX8__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX8_WIDTH 32U +#define XHC_DBLDVX8__WIDTH 32U +#define XHC_DBLDVX8_ALL_L 31U +#define XHC_DBLDVX8_ALL_R 0U +#define XHC_DBLDVX8__ALL_L 31U +#define XHC_DBLDVX8__ALL_R 0U +#define XHC_DBLDVX8_DATAMASK 0xffffffffU +#define XHC_DBLDVX8_RDWRMASK 0x00000000U +#define XHC_DBLDVX8_RESETVALUE 0x00000000U + +#define XHC_DBLDVX9_OFFSET 0x8e4U +#define XHC_DBLDVX9_BASE 0x8e4U +#define XHC_DBLDVX9__SID_L 31U +#define XHC_DBLDVX9__SID_R 16U +#define XHC_DBLDVX9__SID_WIDTH 16U +#define XHC_DBLDVX9__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX9__reserved_L 15U +#define XHC_DBLDVX9__reserved_R 8U +#define XHC_DBLDVX9__reserved_WIDTH 8U +#define XHC_DBLDVX9__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX9__TGT_L 7U +#define XHC_DBLDVX9__TGT_R 0U +#define XHC_DBLDVX9__TGT_WIDTH 8U +#define XHC_DBLDVX9__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX9_WIDTH 32U +#define XHC_DBLDVX9__WIDTH 32U +#define XHC_DBLDVX9_ALL_L 31U +#define XHC_DBLDVX9_ALL_R 0U +#define XHC_DBLDVX9__ALL_L 31U +#define XHC_DBLDVX9__ALL_R 0U +#define XHC_DBLDVX9_DATAMASK 0xffffffffU +#define XHC_DBLDVX9_RDWRMASK 0x00000000U +#define XHC_DBLDVX9_RESETVALUE 0x00000000U + +#define XHC_DBLDVX10_OFFSET 0x8e8U +#define XHC_DBLDVX10_BASE 0x8e8U +#define XHC_DBLDVX10__SID_L 31U +#define XHC_DBLDVX10__SID_R 16U +#define XHC_DBLDVX10__SID_WIDTH 16U +#define XHC_DBLDVX10__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX10__reserved_L 15U +#define XHC_DBLDVX10__reserved_R 8U +#define XHC_DBLDVX10__reserved_WIDTH 8U +#define XHC_DBLDVX10__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX10__TGT_L 7U +#define XHC_DBLDVX10__TGT_R 0U +#define XHC_DBLDVX10__TGT_WIDTH 8U +#define XHC_DBLDVX10__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX10_WIDTH 32U +#define XHC_DBLDVX10__WIDTH 32U +#define XHC_DBLDVX10_ALL_L 31U +#define XHC_DBLDVX10_ALL_R 0U +#define XHC_DBLDVX10__ALL_L 31U +#define XHC_DBLDVX10__ALL_R 0U +#define XHC_DBLDVX10_DATAMASK 0xffffffffU +#define XHC_DBLDVX10_RDWRMASK 0x00000000U +#define XHC_DBLDVX10_RESETVALUE 0x00000000U + +#define XHC_DBLDVX11_OFFSET 0x8ecU +#define XHC_DBLDVX11_BASE 0x8ecU +#define XHC_DBLDVX11__SID_L 31U +#define XHC_DBLDVX11__SID_R 16U +#define XHC_DBLDVX11__SID_WIDTH 16U +#define XHC_DBLDVX11__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX11__reserved_L 15U +#define XHC_DBLDVX11__reserved_R 8U +#define XHC_DBLDVX11__reserved_WIDTH 8U +#define XHC_DBLDVX11__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX11__TGT_L 7U +#define XHC_DBLDVX11__TGT_R 0U +#define XHC_DBLDVX11__TGT_WIDTH 8U +#define XHC_DBLDVX11__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX11_WIDTH 32U +#define XHC_DBLDVX11__WIDTH 32U +#define XHC_DBLDVX11_ALL_L 31U +#define XHC_DBLDVX11_ALL_R 0U +#define XHC_DBLDVX11__ALL_L 31U +#define XHC_DBLDVX11__ALL_R 0U +#define XHC_DBLDVX11_DATAMASK 0xffffffffU +#define XHC_DBLDVX11_RDWRMASK 0x00000000U +#define XHC_DBLDVX11_RESETVALUE 0x00000000U + +#define XHC_DBLDVX12_OFFSET 0x8f0U +#define XHC_DBLDVX12_BASE 0x8f0U +#define XHC_DBLDVX12__SID_L 31U +#define XHC_DBLDVX12__SID_R 16U +#define XHC_DBLDVX12__SID_WIDTH 16U +#define XHC_DBLDVX12__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX12__reserved_L 15U +#define XHC_DBLDVX12__reserved_R 8U +#define XHC_DBLDVX12__reserved_WIDTH 8U +#define XHC_DBLDVX12__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX12__TGT_L 7U +#define XHC_DBLDVX12__TGT_R 0U +#define XHC_DBLDVX12__TGT_WIDTH 8U +#define XHC_DBLDVX12__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX12_WIDTH 32U +#define XHC_DBLDVX12__WIDTH 32U +#define XHC_DBLDVX12_ALL_L 31U +#define XHC_DBLDVX12_ALL_R 0U +#define XHC_DBLDVX12__ALL_L 31U +#define XHC_DBLDVX12__ALL_R 0U +#define XHC_DBLDVX12_DATAMASK 0xffffffffU +#define XHC_DBLDVX12_RDWRMASK 0x00000000U +#define XHC_DBLDVX12_RESETVALUE 0x00000000U + +#define XHC_DBLDVX13_OFFSET 0x8f4U +#define XHC_DBLDVX13_BASE 0x8f4U +#define XHC_DBLDVX13__SID_L 31U +#define XHC_DBLDVX13__SID_R 16U +#define XHC_DBLDVX13__SID_WIDTH 16U +#define XHC_DBLDVX13__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX13__reserved_L 15U +#define XHC_DBLDVX13__reserved_R 8U +#define XHC_DBLDVX13__reserved_WIDTH 8U +#define XHC_DBLDVX13__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX13__TGT_L 7U +#define XHC_DBLDVX13__TGT_R 0U +#define XHC_DBLDVX13__TGT_WIDTH 8U +#define XHC_DBLDVX13__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX13_WIDTH 32U +#define XHC_DBLDVX13__WIDTH 32U +#define XHC_DBLDVX13_ALL_L 31U +#define XHC_DBLDVX13_ALL_R 0U +#define XHC_DBLDVX13__ALL_L 31U +#define XHC_DBLDVX13__ALL_R 0U +#define XHC_DBLDVX13_DATAMASK 0xffffffffU +#define XHC_DBLDVX13_RDWRMASK 0x00000000U +#define XHC_DBLDVX13_RESETVALUE 0x00000000U + +#define XHC_DBLDVX14_OFFSET 0x8f8U +#define XHC_DBLDVX14_BASE 0x8f8U +#define XHC_DBLDVX14__SID_L 31U +#define XHC_DBLDVX14__SID_R 16U +#define XHC_DBLDVX14__SID_WIDTH 16U +#define XHC_DBLDVX14__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX14__reserved_L 15U +#define XHC_DBLDVX14__reserved_R 8U +#define XHC_DBLDVX14__reserved_WIDTH 8U +#define XHC_DBLDVX14__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX14__TGT_L 7U +#define XHC_DBLDVX14__TGT_R 0U +#define XHC_DBLDVX14__TGT_WIDTH 8U +#define XHC_DBLDVX14__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX14_WIDTH 32U +#define XHC_DBLDVX14__WIDTH 32U +#define XHC_DBLDVX14_ALL_L 31U +#define XHC_DBLDVX14_ALL_R 0U +#define XHC_DBLDVX14__ALL_L 31U +#define XHC_DBLDVX14__ALL_R 0U +#define XHC_DBLDVX14_DATAMASK 0xffffffffU +#define XHC_DBLDVX14_RDWRMASK 0x00000000U +#define XHC_DBLDVX14_RESETVALUE 0x00000000U + +#define XHC_DBLDVX15_OFFSET 0x8fcU +#define XHC_DBLDVX15_BASE 0x8fcU +#define XHC_DBLDVX15__SID_L 31U +#define XHC_DBLDVX15__SID_R 16U +#define XHC_DBLDVX15__SID_WIDTH 16U +#define XHC_DBLDVX15__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX15__reserved_L 15U +#define XHC_DBLDVX15__reserved_R 8U +#define XHC_DBLDVX15__reserved_WIDTH 8U +#define XHC_DBLDVX15__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX15__TGT_L 7U +#define XHC_DBLDVX15__TGT_R 0U +#define XHC_DBLDVX15__TGT_WIDTH 8U +#define XHC_DBLDVX15__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX15_WIDTH 32U +#define XHC_DBLDVX15__WIDTH 32U +#define XHC_DBLDVX15_ALL_L 31U +#define XHC_DBLDVX15_ALL_R 0U +#define XHC_DBLDVX15__ALL_L 31U +#define XHC_DBLDVX15__ALL_R 0U +#define XHC_DBLDVX15_DATAMASK 0xffffffffU +#define XHC_DBLDVX15_RDWRMASK 0x00000000U +#define XHC_DBLDVX15_RESETVALUE 0x00000000U + +#define XHC_DBLDVX16_OFFSET 0x900U +#define XHC_DBLDVX16_BASE 0x900U +#define XHC_DBLDVX16__SID_L 31U +#define XHC_DBLDVX16__SID_R 16U +#define XHC_DBLDVX16__SID_WIDTH 16U +#define XHC_DBLDVX16__SID_RESETVALUE 0x0000U +#define XHC_DBLDVX16__reserved_L 15U +#define XHC_DBLDVX16__reserved_R 8U +#define XHC_DBLDVX16__reserved_WIDTH 8U +#define XHC_DBLDVX16__reserved_RESETVALUE 0x00U +#define XHC_DBLDVX16__TGT_L 7U +#define XHC_DBLDVX16__TGT_R 0U +#define XHC_DBLDVX16__TGT_WIDTH 8U +#define XHC_DBLDVX16__TGT_RESETVALUE 0x00U +#define XHC_DBLDVX16_WIDTH 32U +#define XHC_DBLDVX16__WIDTH 32U +#define XHC_DBLDVX16_ALL_L 31U +#define XHC_DBLDVX16_ALL_R 0U +#define XHC_DBLDVX16__ALL_L 31U +#define XHC_DBLDVX16__ALL_R 0U +#define XHC_DBLDVX16_DATAMASK 0xffffffffU +#define XHC_DBLDVX16_RDWRMASK 0x00000000U +#define XHC_DBLDVX16_RESETVALUE 0x00000000U + +#define XHC_ECHSPT3_OFFSET 0x940U +#define XHC_ECHSPT3_BASE 0x940U +#define XHC_ECHSPT3__RMAJ_L 31U +#define XHC_ECHSPT3__RMAJ_R 24U +#define XHC_ECHSPT3__RMAJ_WIDTH 8U +#define XHC_ECHSPT3__RMAJ_RESETVALUE 0x00U +#define XHC_ECHSPT3__RMIN_L 23U +#define XHC_ECHSPT3__RMIN_R 16U +#define XHC_ECHSPT3__RMIN_WIDTH 8U +#define XHC_ECHSPT3__RMIN_RESETVALUE 0x00U +#define XHC_ECHSPT3__NCP_L 15U +#define XHC_ECHSPT3__NCP_R 8U +#define XHC_ECHSPT3__NCP_WIDTH 8U +#define XHC_ECHSPT3__NCP_RESETVALUE 0x00U +#define XHC_ECHSPT3__CID_L 7U +#define XHC_ECHSPT3__CID_R 0U +#define XHC_ECHSPT3__CID_WIDTH 8U +#define XHC_ECHSPT3__CID_RESETVALUE 0x02U +#define XHC_ECHSPT3_WIDTH 32U +#define XHC_ECHSPT3__WIDTH 32U +#define XHC_ECHSPT3_ALL_L 31U +#define XHC_ECHSPT3_ALL_R 0U +#define XHC_ECHSPT3__ALL_L 31U +#define XHC_ECHSPT3__ALL_R 0U +#define XHC_ECHSPT3_DATAMASK 0xffffffffU +#define XHC_ECHSPT3_RDWRMASK 0x00000000U +#define XHC_ECHSPT3_RESETVALUE 0x00000002U + +#define XHC_PNSTR3_OFFSET 0x944U +#define XHC_PNSTR3_BASE 0x944U +#define XHC_PNSTR3__STR_L 31U +#define XHC_PNSTR3__STR_R 0U +#define XHC_PNSTR3__STR_WIDTH 32U +#define XHC_PNSTR3__STR_RESETVALUE 0x20425355U +#define XHC_PNSTR3_WIDTH 32U +#define XHC_PNSTR3__WIDTH 32U +#define XHC_PNSTR3_ALL_L 31U +#define XHC_PNSTR3_ALL_R 0U +#define XHC_PNSTR3__ALL_L 31U +#define XHC_PNSTR3__ALL_R 0U +#define XHC_PNSTR3_DATAMASK 0xffffffffU +#define XHC_PNSTR3_RDWRMASK 0x00000000U +#define XHC_PNSTR3_RESETVALUE 0x20425355U + +#define XHC_PSUM3_OFFSET 0x948U +#define XHC_PSUM3_BASE 0x948U +#define XHC_PSUM3__PSIC_L 31U +#define XHC_PSUM3__PSIC_R 28U +#define XHC_PSUM3__PSIC_WIDTH 4U +#define XHC_PSUM3__PSIC_RESETVALUE 0x0U +#define XHC_PSUM3__MHD_L 27U +#define XHC_PSUM3__MHD_R 25U +#define XHC_PSUM3__MHD_WIDTH 3U +#define XHC_PSUM3__MHD_RESETVALUE 0x0U +#define XHC_PSUM3__BLC 20U +#define XHC_PSUM3__BLC_L 20U +#define XHC_PSUM3__BLC_R 20U +#define XHC_PSUM3__BLC_WIDTH 1U +#define XHC_PSUM3__BLC_RESETVALUE 0x0U +#define XHC_PSUM3__HLC 19U +#define XHC_PSUM3__HLC_L 19U +#define XHC_PSUM3__HLC_R 19U +#define XHC_PSUM3__HLC_WIDTH 1U +#define XHC_PSUM3__HLC_RESETVALUE 0x1U +#define XHC_PSUM3__IHI 18U +#define XHC_PSUM3__IHI_L 18U +#define XHC_PSUM3__IHI_R 18U +#define XHC_PSUM3__IHI_WIDTH 1U +#define XHC_PSUM3__IHI_RESETVALUE 0x0U +#define XHC_PSUM3__HSO 17U +#define XHC_PSUM3__HSO_L 17U +#define XHC_PSUM3__HSO_R 17U +#define XHC_PSUM3__HSO_WIDTH 1U +#define XHC_PSUM3__HSO_RESETVALUE 0x0U +#define XHC_PSUM3__reserved 16U +#define XHC_PSUM3__reserved_L 16U +#define XHC_PSUM3__reserved_R 16U +#define XHC_PSUM3__reserved_WIDTH 1U +#define XHC_PSUM3__reserved_RESETVALUE 0x0U +#define XHC_PSUM3__CPC_L 15U +#define XHC_PSUM3__CPC_R 8U +#define XHC_PSUM3__CPC_WIDTH 8U +#define XHC_PSUM3__CPC_RESETVALUE 0x00U +#define XHC_PSUM3__CPO_L 7U +#define XHC_PSUM3__CPO_R 0U +#define XHC_PSUM3__CPO_WIDTH 8U +#define XHC_PSUM3__CPO_RESETVALUE 0x00U +#define XHC_PSUM3__RESERVED_L 24U +#define XHC_PSUM3__RESERVED_R 21U +#define XHC_PSUM3_WIDTH 32U +#define XHC_PSUM3__WIDTH 32U +#define XHC_PSUM3_ALL_L 31U +#define XHC_PSUM3_ALL_R 0U +#define XHC_PSUM3__ALL_L 31U +#define XHC_PSUM3__ALL_R 0U +#define XHC_PSUM3_DATAMASK 0xfe1fffffU +#define XHC_PSUM3_RDWRMASK 0x01e00000U +#define XHC_PSUM3_RESETVALUE 0x00080000U + +#define XHC_PTSLTYP3_OFFSET 0x94cU +#define XHC_PTSLTYP3_BASE 0x94cU +#define XHC_PTSLTYP3__reserved_L 31U +#define XHC_PTSLTYP3__reserved_R 5U +#define XHC_PTSLTYP3__reserved_WIDTH 27U +#define XHC_PTSLTYP3__reserved_RESETVALUE 0x0U +#define XHC_PTSLTYP3__PST_L 4U +#define XHC_PTSLTYP3__PST_R 0U +#define XHC_PTSLTYP3__PST_WIDTH 5U +#define XHC_PTSLTYP3__PST_RESETVALUE 0x0U +#define XHC_PTSLTYP3_WIDTH 32U +#define XHC_PTSLTYP3__WIDTH 32U +#define XHC_PTSLTYP3_ALL_L 31U +#define XHC_PTSLTYP3_ALL_R 0U +#define XHC_PTSLTYP3__ALL_L 31U +#define XHC_PTSLTYP3__ALL_R 0U +#define XHC_PTSLTYP3_DATAMASK 0xffffffffU +#define XHC_PTSLTYP3_RDWRMASK 0x00000000U +#define XHC_PTSLTYP3_RESETVALUE 0x00000000U + +#define XHC_ECHSPT2_OFFSET 0x950U +#define XHC_ECHSPT2_BASE 0x950U +#define XHC_ECHSPT2__RMAJ_L 31U +#define XHC_ECHSPT2__RMAJ_R 24U +#define XHC_ECHSPT2__RMAJ_WIDTH 8U +#define XHC_ECHSPT2__RMAJ_RESETVALUE 0x00U +#define XHC_ECHSPT2__RMIN_L 23U +#define XHC_ECHSPT2__RMIN_R 16U +#define XHC_ECHSPT2__RMIN_WIDTH 8U +#define XHC_ECHSPT2__RMIN_RESETVALUE 0x00U +#define XHC_ECHSPT2__NCP_L 15U +#define XHC_ECHSPT2__NCP_R 8U +#define XHC_ECHSPT2__NCP_WIDTH 8U +#define XHC_ECHSPT2__NCP_RESETVALUE 0x00U +#define XHC_ECHSPT2__CID_L 7U +#define XHC_ECHSPT2__CID_R 0U +#define XHC_ECHSPT2__CID_WIDTH 8U +#define XHC_ECHSPT2__CID_RESETVALUE 0x02U +#define XHC_ECHSPT2_WIDTH 32U +#define XHC_ECHSPT2__WIDTH 32U +#define XHC_ECHSPT2_ALL_L 31U +#define XHC_ECHSPT2_ALL_R 0U +#define XHC_ECHSPT2__ALL_L 31U +#define XHC_ECHSPT2__ALL_R 0U +#define XHC_ECHSPT2_DATAMASK 0xffffffffU +#define XHC_ECHSPT2_RDWRMASK 0x00000000U +#define XHC_ECHSPT2_RESETVALUE 0x00000002U + +#define XHC_PNSTR2_OFFSET 0x954U +#define XHC_PNSTR2_BASE 0x954U +#define XHC_PNSTR2__STR_L 31U +#define XHC_PNSTR2__STR_R 0U +#define XHC_PNSTR2__STR_WIDTH 32U +#define XHC_PNSTR2__STR_RESETVALUE 0x20425355U +#define XHC_PNSTR2_WIDTH 32U +#define XHC_PNSTR2__WIDTH 32U +#define XHC_PNSTR2_ALL_L 31U +#define XHC_PNSTR2_ALL_R 0U +#define XHC_PNSTR2__ALL_L 31U +#define XHC_PNSTR2__ALL_R 0U +#define XHC_PNSTR2_DATAMASK 0xffffffffU +#define XHC_PNSTR2_RDWRMASK 0x00000000U +#define XHC_PNSTR2_RESETVALUE 0x20425355U + +#define XHC_PSUM2_OFFSET 0x958U +#define XHC_PSUM2_BASE 0x958U +#define XHC_PSUM2__PSIC_L 31U +#define XHC_PSUM2__PSIC_R 28U +#define XHC_PSUM2__PSIC_WIDTH 4U +#define XHC_PSUM2__PSIC_RESETVALUE 0x0U +#define XHC_PSUM2__MHD_L 27U +#define XHC_PSUM2__MHD_R 25U +#define XHC_PSUM2__MHD_WIDTH 3U +#define XHC_PSUM2__MHD_RESETVALUE 0x0U +#define XHC_PSUM2__BLC 20U +#define XHC_PSUM2__BLC_L 20U +#define XHC_PSUM2__BLC_R 20U +#define XHC_PSUM2__BLC_WIDTH 1U +#define XHC_PSUM2__BLC_RESETVALUE 0x0U +#define XHC_PSUM2__HLC 19U +#define XHC_PSUM2__HLC_L 19U +#define XHC_PSUM2__HLC_R 19U +#define XHC_PSUM2__HLC_WIDTH 1U +#define XHC_PSUM2__HLC_RESETVALUE 0x1U +#define XHC_PSUM2__IHI 18U +#define XHC_PSUM2__IHI_L 18U +#define XHC_PSUM2__IHI_R 18U +#define XHC_PSUM2__IHI_WIDTH 1U +#define XHC_PSUM2__IHI_RESETVALUE 0x0U +#define XHC_PSUM2__HSO 17U +#define XHC_PSUM2__HSO_L 17U +#define XHC_PSUM2__HSO_R 17U +#define XHC_PSUM2__HSO_WIDTH 1U +#define XHC_PSUM2__HSO_RESETVALUE 0x0U +#define XHC_PSUM2__reserved 16U +#define XHC_PSUM2__reserved_L 16U +#define XHC_PSUM2__reserved_R 16U +#define XHC_PSUM2__reserved_WIDTH 1U +#define XHC_PSUM2__reserved_RESETVALUE 0x0U +#define XHC_PSUM2__CPC_L 15U +#define XHC_PSUM2__CPC_R 8U +#define XHC_PSUM2__CPC_WIDTH 8U +#define XHC_PSUM2__CPC_RESETVALUE 0x00U +#define XHC_PSUM2__CPO_L 7U +#define XHC_PSUM2__CPO_R 0U +#define XHC_PSUM2__CPO_WIDTH 8U +#define XHC_PSUM2__CPO_RESETVALUE 0x00U +#define XHC_PSUM2__RESERVED_L 24U +#define XHC_PSUM2__RESERVED_R 21U +#define XHC_PSUM2_WIDTH 32U +#define XHC_PSUM2__WIDTH 32U +#define XHC_PSUM2_ALL_L 31U +#define XHC_PSUM2_ALL_R 0U +#define XHC_PSUM2__ALL_L 31U +#define XHC_PSUM2__ALL_R 0U +#define XHC_PSUM2_DATAMASK 0xfe1fffffU +#define XHC_PSUM2_RDWRMASK 0x01e00000U +#define XHC_PSUM2_RESETVALUE 0x00080000U + +#define XHC_PTSLTYP2_OFFSET 0x95cU +#define XHC_PTSLTYP2_BASE 0x95cU +#define XHC_PTSLTYP2__reserved_L 31U +#define XHC_PTSLTYP2__reserved_R 5U +#define XHC_PTSLTYP2__reserved_WIDTH 27U +#define XHC_PTSLTYP2__reserved_RESETVALUE 0x0U +#define XHC_PTSLTYP2__PST_L 4U +#define XHC_PTSLTYP2__PST_R 0U +#define XHC_PTSLTYP2__PST_WIDTH 5U +#define XHC_PTSLTYP2__PST_RESETVALUE 0x0U +#define XHC_PTSLTYP2_WIDTH 32U +#define XHC_PTSLTYP2__WIDTH 32U +#define XHC_PTSLTYP2_ALL_L 31U +#define XHC_PTSLTYP2_ALL_R 0U +#define XHC_PTSLTYP2__ALL_L 31U +#define XHC_PTSLTYP2__ALL_R 0U +#define XHC_PTSLTYP2_DATAMASK 0xffffffffU +#define XHC_PTSLTYP2_RDWRMASK 0x00000000U +#define XHC_PTSLTYP2_RESETVALUE 0x00000000U + +#define XHC_ECHRSVP_OFFSET 0x960U +#define XHC_ECHRSVP_BASE 0x960U +#define XHC_ECHRSVP__reserved_L 31U +#define XHC_ECHRSVP__reserved_R 16U +#define XHC_ECHRSVP__reserved_WIDTH 16U +#define XHC_ECHRSVP__reserved_RESETVALUE 0x0000U +#define XHC_ECHRSVP__NCP_L 15U +#define XHC_ECHRSVP__NCP_R 8U +#define XHC_ECHRSVP__NCP_WIDTH 8U +#define XHC_ECHRSVP__NCP_RESETVALUE 0x00U +#define XHC_ECHRSVP__CID_L 7U +#define XHC_ECHRSVP__CID_R 0U +#define XHC_ECHRSVP__CID_WIDTH 8U +#define XHC_ECHRSVP__CID_RESETVALUE 0xffU +#define XHC_ECHRSVP_WIDTH 32U +#define XHC_ECHRSVP__WIDTH 32U +#define XHC_ECHRSVP_ALL_L 31U +#define XHC_ECHRSVP_ALL_R 0U +#define XHC_ECHRSVP__ALL_L 31U +#define XHC_ECHRSVP__ALL_R 0U +#define XHC_ECHRSVP_DATAMASK 0xffffffffU +#define XHC_ECHRSVP_RDWRMASK 0x00000000U +#define XHC_ECHRSVP_RESETVALUE 0x000000ffU + +#define XHC_ECHRSVI_OFFSET 0x968U +#define XHC_ECHRSVI_BASE 0x968U +#define XHC_ECHRSVI__reserved_L 31U +#define XHC_ECHRSVI__reserved_R 16U +#define XHC_ECHRSVI__reserved_WIDTH 16U +#define XHC_ECHRSVI__reserved_RESETVALUE 0x0000U +#define XHC_ECHRSVI__NCP_L 15U +#define XHC_ECHRSVI__NCP_R 8U +#define XHC_ECHRSVI__NCP_WIDTH 8U +#define XHC_ECHRSVI__NCP_RESETVALUE 0x00U +#define XHC_ECHRSVI__CID_L 7U +#define XHC_ECHRSVI__CID_R 0U +#define XHC_ECHRSVI__CID_WIDTH 8U +#define XHC_ECHRSVI__CID_RESETVALUE 0xffU +#define XHC_ECHRSVI_WIDTH 32U +#define XHC_ECHRSVI__WIDTH 32U +#define XHC_ECHRSVI_ALL_L 31U +#define XHC_ECHRSVI_ALL_R 0U +#define XHC_ECHRSVI__ALL_L 31U +#define XHC_ECHRSVI__ALL_R 0U +#define XHC_ECHRSVI_DATAMASK 0xffffffffU +#define XHC_ECHRSVI_RDWRMASK 0x00000000U +#define XHC_ECHRSVI_RESETVALUE 0x000000ffU + +#define XHC_ECHRSVM_OFFSET 0xae8U +#define XHC_ECHRSVM_BASE 0xae8U +#define XHC_ECHRSVM__reserved_L 31U +#define XHC_ECHRSVM__reserved_R 16U +#define XHC_ECHRSVM__reserved_WIDTH 16U +#define XHC_ECHRSVM__reserved_RESETVALUE 0x0000U +#define XHC_ECHRSVM__NCP_L 15U +#define XHC_ECHRSVM__NCP_R 8U +#define XHC_ECHRSVM__NCP_WIDTH 8U +#define XHC_ECHRSVM__NCP_RESETVALUE 0x00U +#define XHC_ECHRSVM__CID_L 7U +#define XHC_ECHRSVM__CID_R 0U +#define XHC_ECHRSVM__CID_WIDTH 8U +#define XHC_ECHRSVM__CID_RESETVALUE 0xffU +#define XHC_ECHRSVM_WIDTH 32U +#define XHC_ECHRSVM__WIDTH 32U +#define XHC_ECHRSVM_ALL_L 31U +#define XHC_ECHRSVM_ALL_R 0U +#define XHC_ECHRSVM__ALL_L 31U +#define XHC_ECHRSVM__ALL_R 0U +#define XHC_ECHRSVM_DATAMASK 0xffffffffU +#define XHC_ECHRSVM_RDWRMASK 0x00000000U +#define XHC_ECHRSVM_RESETVALUE 0x000000ffU + +#define XHC_ECHRSVD_OFFSET 0xaf8U +#define XHC_ECHRSVD_BASE 0xaf8U +#define XHC_ECHRSVD__reserved_L 31U +#define XHC_ECHRSVD__reserved_R 16U +#define XHC_ECHRSVD__reserved_WIDTH 16U +#define XHC_ECHRSVD__reserved_RESETVALUE 0x0000U +#define XHC_ECHRSVD__NCP_L 15U +#define XHC_ECHRSVD__NCP_R 8U +#define XHC_ECHRSVD__NCP_WIDTH 8U +#define XHC_ECHRSVD__NCP_RESETVALUE 0x00U +#define XHC_ECHRSVD__CID_L 7U +#define XHC_ECHRSVD__CID_R 0U +#define XHC_ECHRSVD__CID_WIDTH 8U +#define XHC_ECHRSVD__CID_RESETVALUE 0xffU +#define XHC_ECHRSVD_WIDTH 32U +#define XHC_ECHRSVD__WIDTH 32U +#define XHC_ECHRSVD_ALL_L 31U +#define XHC_ECHRSVD_ALL_R 0U +#define XHC_ECHRSVD__ALL_L 31U +#define XHC_ECHRSVD__ALL_R 0U +#define XHC_ECHRSVD_DATAMASK 0xffffffffU +#define XHC_ECHRSVD_RDWRMASK 0x00000000U +#define XHC_ECHRSVD_RESETVALUE 0x000000ffU + +#define XHC_ECHRSVO_OFFSET 0xb38U +#define XHC_ECHRSVO_BASE 0xb38U +#define XHC_ECHRSVO__reserved_L 31U +#define XHC_ECHRSVO__reserved_R 16U +#define XHC_ECHRSVO__reserved_WIDTH 16U +#define XHC_ECHRSVO__reserved_RESETVALUE 0x0000U +#define XHC_ECHRSVO__NCP_L 15U +#define XHC_ECHRSVO__NCP_R 8U +#define XHC_ECHRSVO__NCP_WIDTH 8U +#define XHC_ECHRSVO__NCP_RESETVALUE 0x00U +#define XHC_ECHRSVO__CID_L 7U +#define XHC_ECHRSVO__CID_R 0U +#define XHC_ECHRSVO__CID_WIDTH 8U +#define XHC_ECHRSVO__CID_RESETVALUE 0xffU +#define XHC_ECHRSVO_WIDTH 32U +#define XHC_ECHRSVO__WIDTH 32U +#define XHC_ECHRSVO_ALL_L 31U +#define XHC_ECHRSVO_ALL_R 0U +#define XHC_ECHRSVO__ALL_L 31U +#define XHC_ECHRSVO__ALL_R 0U +#define XHC_ECHRSVO_DATAMASK 0xffffffffU +#define XHC_ECHRSVO_RDWRMASK 0x00000000U +#define XHC_ECHRSVO_RESETVALUE 0x000000ffU + +#define XHC_ECHCTT_OFFSET 0xbf0U +#define XHC_ECHCTT_BASE 0xbf0U +#define XHC_ECHCTT__reserved_L 31U +#define XHC_ECHCTT__reserved_R 16U +#define XHC_ECHCTT__reserved_WIDTH 16U +#define XHC_ECHCTT__reserved_RESETVALUE 0x0000U +#define XHC_ECHCTT__NCP_L 15U +#define XHC_ECHCTT__NCP_R 8U +#define XHC_ECHCTT__NCP_WIDTH 8U +#define XHC_ECHCTT__NCP_RESETVALUE 0x04U +#define XHC_ECHCTT__CID_L 7U +#define XHC_ECHCTT__CID_R 0U +#define XHC_ECHCTT__CID_WIDTH 8U +#define XHC_ECHCTT__CID_RESETVALUE 0xe0U +#define XHC_ECHCTT_WIDTH 32U +#define XHC_ECHCTT__WIDTH 32U +#define XHC_ECHCTT_ALL_L 31U +#define XHC_ECHCTT_ALL_R 0U +#define XHC_ECHCTT__ALL_L 31U +#define XHC_ECHCTT__ALL_R 0U +#define XHC_ECHCTT_DATAMASK 0xffffffffU +#define XHC_ECHCTT_RDWRMASK 0x00000000U +#define XHC_ECHCTT_RESETVALUE 0x000004e0U + +#define XHC_CTTMTS0_OFFSET 0xbf8U +#define XHC_CTTMTS0_BASE 0xbf8U +#define XHC_CTTMTS0__DCM 31U +#define XHC_CTTMTS0__DCM_L 31U +#define XHC_CTTMTS0__DCM_R 31U +#define XHC_CTTMTS0__DCM_WIDTH 1U +#define XHC_CTTMTS0__DCM_RESETVALUE 0x0U +#define XHC_CTTMTS0__reserved_L 30U +#define XHC_CTTMTS0__reserved_R 10U +#define XHC_CTTMTS0__reserved_WIDTH 21U +#define XHC_CTTMTS0__reserved_RESETVALUE 0x0U +#define XHC_CTTMTS0__SLA_L 9U +#define XHC_CTTMTS0__SLA_R 0U +#define XHC_CTTMTS0__SLA_WIDTH 10U +#define XHC_CTTMTS0__SLA_RESETVALUE 0x0U +#define XHC_CTTMTS0_WIDTH 32U +#define XHC_CTTMTS0__WIDTH 32U +#define XHC_CTTMTS0_ALL_L 31U +#define XHC_CTTMTS0_ALL_R 0U +#define XHC_CTTMTS0__ALL_L 31U +#define XHC_CTTMTS0__ALL_R 0U +#define XHC_CTTMTS0_DATAMASK 0xffffffffU +#define XHC_CTTMTS0_RDWRMASK 0x00000000U +#define XHC_CTTMTS0_RESETVALUE 0x00000000U + +#define XHC_CTTMTS1_OFFSET 0xbfcU +#define XHC_CTTMTS1_BASE 0xbfcU +#define XHC_CTTMTS1__TXF_L 25U +#define XHC_CTTMTS1__TXF_R 16U +#define XHC_CTTMTS1__TXF_WIDTH 10U +#define XHC_CTTMTS1__TXF_RESETVALUE 0x0U +#define XHC_CTTMTS1__reserved_L 15U +#define XHC_CTTMTS1__reserved_R 10U +#define XHC_CTTMTS1__reserved_WIDTH 6U +#define XHC_CTTMTS1__reserved_RESETVALUE 0x0U +#define XHC_CTTMTS1__RXF_L 9U +#define XHC_CTTMTS1__RXF_R 0U +#define XHC_CTTMTS1__RXF_WIDTH 10U +#define XHC_CTTMTS1__RXF_RESETVALUE 0x0U +#define XHC_CTTMTS1__RESERVED_L 31U +#define XHC_CTTMTS1__RESERVED_R 26U +#define XHC_CTTMTS1_WIDTH 26U +#define XHC_CTTMTS1__WIDTH 26U +#define XHC_CTTMTS1_ALL_L 25U +#define XHC_CTTMTS1_ALL_R 0U +#define XHC_CTTMTS1__ALL_L 25U +#define XHC_CTTMTS1__ALL_R 0U +#define XHC_CTTMTS1_DATAMASK 0x03ffffffU +#define XHC_CTTMTS1_RDWRMASK 0xfc000000U +#define XHC_CTTMTS1_RESETVALUE 0x0000000U + +#define XHC_ECHBIU_OFFSET 0xc00U +#define XHC_ECHBIU_BASE 0xc00U +#define XHC_ECHBIU__CLK_L 31U +#define XHC_ECHBIU__CLK_R 21U +#define XHC_ECHBIU__CLK_WIDTH 11U +#define XHC_ECHBIU__CLK_RESETVALUE 0x0U +#define XHC_ECHBIU__reserved_L 20U +#define XHC_ECHBIU__reserved_R 19U +#define XHC_ECHBIU__reserved_WIDTH 2U +#define XHC_ECHBIU__reserved_RESETVALUE 0x0U +#define XHC_ECHBIU__WID_L 18U +#define XHC_ECHBIU__WID_R 16U +#define XHC_ECHBIU__WID_WIDTH 3U +#define XHC_ECHBIU__WID_RESETVALUE 0x0U +#define XHC_ECHBIU__NCP_L 15U +#define XHC_ECHBIU__NCP_R 8U +#define XHC_ECHBIU__NCP_WIDTH 8U +#define XHC_ECHBIU__NCP_RESETVALUE 0x08U +#define XHC_ECHBIU__CID_L 7U +#define XHC_ECHBIU__CID_R 0U +#define XHC_ECHBIU__CID_WIDTH 8U +#define XHC_ECHBIU__CID_RESETVALUE 0xc0U +#define XHC_ECHBIU_WIDTH 32U +#define XHC_ECHBIU__WIDTH 32U +#define XHC_ECHBIU_ALL_L 31U +#define XHC_ECHBIU_ALL_R 0U +#define XHC_ECHBIU__ALL_L 31U +#define XHC_ECHBIU__ALL_R 0U +#define XHC_ECHBIU_DATAMASK 0xffffffffU +#define XHC_ECHBIU_RDWRMASK 0x00000000U +#define XHC_ECHBIU_RESETVALUE 0x000008c0U + +#define XHC_BIUSPC_OFFSET 0xc04U +#define XHC_BIUSPC_BASE 0xc04U +#define XHC_BIUSPC__MAJ_L 31U +#define XHC_BIUSPC__MAJ_R 28U +#define XHC_BIUSPC__MAJ_WIDTH 4U +#define XHC_BIUSPC__MAJ_RESETVALUE 0x0U +#define XHC_BIUSPC__MIN_L 27U +#define XHC_BIUSPC__MIN_R 24U +#define XHC_BIUSPC__MIN_WIDTH 4U +#define XHC_BIUSPC__MIN_RESETVALUE 0x0U +#define XHC_BIUSPC__RLS_L 23U +#define XHC_BIUSPC__RLS_R 20U +#define XHC_BIUSPC__RLS_WIDTH 4U +#define XHC_BIUSPC__RLS_RESETVALUE 0x0U +#define XHC_BIUSPC__reserved_L 19U +#define XHC_BIUSPC__reserved_R 4U +#define XHC_BIUSPC__reserved_WIDTH 16U +#define XHC_BIUSPC__reserved_RESETVALUE 0x0000U +#define XHC_BIUSPC__SPI_L 3U +#define XHC_BIUSPC__SPI_R 2U +#define XHC_BIUSPC__SPI_WIDTH 2U +#define XHC_BIUSPC__SPI_RESETVALUE 0x3U +#define XHC_BIUSPC__TYP_L 1U +#define XHC_BIUSPC__TYP_R 0U +#define XHC_BIUSPC__TYP_WIDTH 2U +#define XHC_BIUSPC__TYP_RESETVALUE 0x0U +#define XHC_BIUSPC_WIDTH 32U +#define XHC_BIUSPC__WIDTH 32U +#define XHC_BIUSPC_ALL_L 31U +#define XHC_BIUSPC_ALL_R 0U +#define XHC_BIUSPC__ALL_L 31U +#define XHC_BIUSPC__ALL_R 0U +#define XHC_BIUSPC_DATAMASK 0xffffffffU +#define XHC_BIUSPC_RDWRMASK 0x00000000U +#define XHC_BIUSPC_RESETVALUE 0x0000000cU + +#define XHC_AXIWRA_OFFSET 0xc08U +#define XHC_AXIWRA_BASE 0xc08U +#define XHC_AXIWRA__WTS_L 31U +#define XHC_AXIWRA__WTS_R 28U +#define XHC_AXIWRA__WTS_WIDTH 4U +#define XHC_AXIWRA__WTS_RESETVALUE 0x2U +#define XHC_AXIWRA__WUA_L 24U +#define XHC_AXIWRA__WUA_R 16U +#define XHC_AXIWRA__WUA_WIDTH 9U +#define XHC_AXIWRA__WUA_RESETVALUE 0x0U +#define XHC_AXIWRA__reserved_L 15U +#define XHC_AXIWRA__reserved_R 10U +#define XHC_AXIWRA__reserved_WIDTH 6U +#define XHC_AXIWRA__reserved_RESETVALUE 0x0U +#define XHC_AXIWRA__BYP 9U +#define XHC_AXIWRA__BYP_L 9U +#define XHC_AXIWRA__BYP_R 9U +#define XHC_AXIWRA__BYP_WIDTH 1U +#define XHC_AXIWRA__BYP_RESETVALUE 0x0U +#define XHC_AXIWRA__WSA_L 8U +#define XHC_AXIWRA__WSA_R 0U +#define XHC_AXIWRA__WSA_WIDTH 9U +#define XHC_AXIWRA__WSA_RESETVALUE 0x0U +#define XHC_AXIWRA__RESERVED_L 27U +#define XHC_AXIWRA__RESERVED_R 25U +#define XHC_AXIWRA_WIDTH 32U +#define XHC_AXIWRA__WIDTH 32U +#define XHC_AXIWRA_ALL_L 31U +#define XHC_AXIWRA_ALL_R 0U +#define XHC_AXIWRA__ALL_L 31U +#define XHC_AXIWRA__ALL_R 0U +#define XHC_AXIWRA_DATAMASK 0xf1ffffffU +#define XHC_AXIWRA_RDWRMASK 0x0e000000U +#define XHC_AXIWRA_RESETVALUE 0x20000000U + +#define XHC_AXIRDA_OFFSET 0xc0cU +#define XHC_AXIRDA_BASE 0xc0cU +#define XHC_AXIRDA__RTS_L 31U +#define XHC_AXIRDA__RTS_R 28U +#define XHC_AXIRDA__RTS_WIDTH 4U +#define XHC_AXIRDA__RTS_RESETVALUE 0x2U +#define XHC_AXIRDA__RFPC 27U +#define XHC_AXIRDA__RFPC_L 27U +#define XHC_AXIRDA__RFPC_R 27U +#define XHC_AXIRDA__RFPC_WIDTH 1U +#define XHC_AXIRDA__RFPC_RESETVALUE 0x0U +#define XHC_AXIRDA__RUA_L 24U +#define XHC_AXIRDA__RUA_R 16U +#define XHC_AXIRDA__RUA_WIDTH 9U +#define XHC_AXIRDA__RUA_RESETVALUE 0x0U +#define XHC_AXIRDA__reserved_L 15U +#define XHC_AXIRDA__reserved_R 9U +#define XHC_AXIRDA__reserved_WIDTH 7U +#define XHC_AXIRDA__reserved_RESETVALUE 0x0U +#define XHC_AXIRDA__RSA_L 8U +#define XHC_AXIRDA__RSA_R 0U +#define XHC_AXIRDA__RSA_WIDTH 9U +#define XHC_AXIRDA__RSA_RESETVALUE 0x0U +#define XHC_AXIRDA__RESERVED_L 26U +#define XHC_AXIRDA__RESERVED_R 25U +#define XHC_AXIRDA_WIDTH 32U +#define XHC_AXIRDA__WIDTH 32U +#define XHC_AXIRDA_ALL_L 31U +#define XHC_AXIRDA_ALL_R 0U +#define XHC_AXIRDA__ALL_L 31U +#define XHC_AXIRDA__ALL_R 0U +#define XHC_AXIRDA_DATAMASK 0xf9ffffffU +#define XHC_AXIRDA_RDWRMASK 0x06000000U +#define XHC_AXIRDA_RESETVALUE 0x20000000U + +#define XHC_AXILPM_OFFSET 0xc10U +#define XHC_AXILPM_BASE 0xc10U +#define XHC_AXILPM__ENB 31U +#define XHC_AXILPM__ENB_L 31U +#define XHC_AXILPM__ENB_R 31U +#define XHC_AXILPM__ENB_WIDTH 1U +#define XHC_AXILPM__ENB_RESETVALUE 0x0U +#define XHC_AXILPM__reserved_L 30U +#define XHC_AXILPM__reserved_R 3U +#define XHC_AXILPM__reserved_WIDTH 28U +#define XHC_AXILPM__reserved_RESETVALUE 0x0000000U +#define XHC_AXILPM__ITT_L 2U +#define XHC_AXILPM__ITT_R 0U +#define XHC_AXILPM__ITT_WIDTH 3U +#define XHC_AXILPM__ITT_RESETVALUE 0x0U +#define XHC_AXILPM_WIDTH 32U +#define XHC_AXILPM__WIDTH 32U +#define XHC_AXILPM_ALL_L 31U +#define XHC_AXILPM_ALL_R 0U +#define XHC_AXILPM__ALL_L 31U +#define XHC_AXILPM__ALL_R 0U +#define XHC_AXILPM_DATAMASK 0xffffffffU +#define XHC_AXILPM_RDWRMASK 0x00000000U +#define XHC_AXILPM_RESETVALUE 0x00000000U + +#define XHC_AXIQOS_OFFSET 0xc14U +#define XHC_AXIQOS_BASE 0xc14U +#define XHC_AXIQOS__WQOS3_L 31U +#define XHC_AXIQOS__WQOS3_R 28U +#define XHC_AXIQOS__WQOS3_WIDTH 4U +#define XHC_AXIQOS__WQOS3_RESETVALUE 0x0U +#define XHC_AXIQOS__WQOS2_L 27U +#define XHC_AXIQOS__WQOS2_R 24U +#define XHC_AXIQOS__WQOS2_WIDTH 4U +#define XHC_AXIQOS__WQOS2_RESETVALUE 0x0U +#define XHC_AXIQOS__WQOS1_L 23U +#define XHC_AXIQOS__WQOS1_R 20U +#define XHC_AXIQOS__WQOS1_WIDTH 4U +#define XHC_AXIQOS__WQOS1_RESETVALUE 0x0U +#define XHC_AXIQOS__WQOS0_L 19U +#define XHC_AXIQOS__WQOS0_R 16U +#define XHC_AXIQOS__WQOS0_WIDTH 4U +#define XHC_AXIQOS__WQOS0_RESETVALUE 0x0U +#define XHC_AXIQOS__RQOS3_L 15U +#define XHC_AXIQOS__RQOS3_R 12U +#define XHC_AXIQOS__RQOS3_WIDTH 4U +#define XHC_AXIQOS__RQOS3_RESETVALUE 0x0U +#define XHC_AXIQOS__RQOS2_L 11U +#define XHC_AXIQOS__RQOS2_R 8U +#define XHC_AXIQOS__RQOS2_WIDTH 4U +#define XHC_AXIQOS__RQOS2_RESETVALUE 0x0U +#define XHC_AXIQOS__RQOS1_L 7U +#define XHC_AXIQOS__RQOS1_R 4U +#define XHC_AXIQOS__RQOS1_WIDTH 4U +#define XHC_AXIQOS__RQOS1_RESETVALUE 0x0U +#define XHC_AXIQOS__RQOS0_L 3U +#define XHC_AXIQOS__RQOS0_R 0U +#define XHC_AXIQOS__RQOS0_WIDTH 4U +#define XHC_AXIQOS__RQOS0_RESETVALUE 0x0U +#define XHC_AXIQOS_WIDTH 32U +#define XHC_AXIQOS__WIDTH 32U +#define XHC_AXIQOS_ALL_L 31U +#define XHC_AXIQOS_ALL_R 0U +#define XHC_AXIQOS__ALL_L 31U +#define XHC_AXIQOS__ALL_R 0U +#define XHC_AXIQOS_DATAMASK 0xffffffffU +#define XHC_AXIQOS_RDWRMASK 0x00000000U +#define XHC_AXIQOS_RESETVALUE 0x00000000U + +#define XHC_ECHCSR_OFFSET 0xc20U +#define XHC_ECHCSR_BASE 0xc20U +#define XHC_ECHCSR__CLK_L 31U +#define XHC_ECHCSR__CLK_R 21U +#define XHC_ECHCSR__CLK_WIDTH 11U +#define XHC_ECHCSR__CLK_RESETVALUE 0x0U +#define XHC_ECHCSR__reserved_L 20U +#define XHC_ECHCSR__reserved_R 19U +#define XHC_ECHCSR__reserved_WIDTH 2U +#define XHC_ECHCSR__reserved_RESETVALUE 0x0U +#define XHC_ECHCSR__WID_L 18U +#define XHC_ECHCSR__WID_R 16U +#define XHC_ECHCSR__WID_WIDTH 3U +#define XHC_ECHCSR__WID_RESETVALUE 0x0U +#define XHC_ECHCSR__NCP_L 15U +#define XHC_ECHCSR__NCP_R 8U +#define XHC_ECHCSR__NCP_WIDTH 8U +#define XHC_ECHCSR__NCP_RESETVALUE 0x04U +#define XHC_ECHCSR__CID_L 7U +#define XHC_ECHCSR__CID_R 0U +#define XHC_ECHCSR__CID_WIDTH 8U +#define XHC_ECHCSR__CID_RESETVALUE 0xc1U +#define XHC_ECHCSR_WIDTH 32U +#define XHC_ECHCSR__WIDTH 32U +#define XHC_ECHCSR_ALL_L 31U +#define XHC_ECHCSR_ALL_R 0U +#define XHC_ECHCSR__ALL_L 31U +#define XHC_ECHCSR__ALL_R 0U +#define XHC_ECHCSR_DATAMASK 0xffffffffU +#define XHC_ECHCSR_RDWRMASK 0x00000000U +#define XHC_ECHCSR_RESETVALUE 0x000004c1U + +#define XHC_CSRSPC_OFFSET 0xc24U +#define XHC_CSRSPC_BASE 0xc24U +#define XHC_CSRSPC__MAJ_L 31U +#define XHC_CSRSPC__MAJ_R 28U +#define XHC_CSRSPC__MAJ_WIDTH 4U +#define XHC_CSRSPC__MAJ_RESETVALUE 0x0U +#define XHC_CSRSPC__MIN_L 27U +#define XHC_CSRSPC__MIN_R 24U +#define XHC_CSRSPC__MIN_WIDTH 4U +#define XHC_CSRSPC__MIN_RESETVALUE 0x0U +#define XHC_CSRSPC__RLS_L 23U +#define XHC_CSRSPC__RLS_R 20U +#define XHC_CSRSPC__RLS_WIDTH 4U +#define XHC_CSRSPC__RLS_RESETVALUE 0x0U +#define XHC_CSRSPC__reserved_L 19U +#define XHC_CSRSPC__reserved_R 3U +#define XHC_CSRSPC__reserved_WIDTH 17U +#define XHC_CSRSPC__reserved_RESETVALUE 0x0U +#define XHC_CSRSPC__ASP 2U +#define XHC_CSRSPC__ASP_L 2U +#define XHC_CSRSPC__ASP_R 2U +#define XHC_CSRSPC__ASP_WIDTH 1U +#define XHC_CSRSPC__ASP_RESETVALUE 0x0U +#define XHC_CSRSPC__TYP_L 1U +#define XHC_CSRSPC__TYP_R 0U +#define XHC_CSRSPC__TYP_WIDTH 2U +#define XHC_CSRSPC__TYP_RESETVALUE 0x0U +#define XHC_CSRSPC_WIDTH 32U +#define XHC_CSRSPC__WIDTH 32U +#define XHC_CSRSPC_ALL_L 31U +#define XHC_CSRSPC_ALL_R 0U +#define XHC_CSRSPC__ALL_L 31U +#define XHC_CSRSPC__ALL_R 0U +#define XHC_CSRSPC_DATAMASK 0xffffffffU +#define XHC_CSRSPC_RDWRMASK 0x00000000U +#define XHC_CSRSPC_RESETVALUE 0x00000000U + +#define XHC_ECHAIU_OFFSET 0xc30U +#define XHC_ECHAIU_BASE 0xc30U +#define XHC_ECHAIU__DMA_L 31U +#define XHC_ECHAIU__DMA_R 30U +#define XHC_ECHAIU__DMA_WIDTH 2U +#define XHC_ECHAIU__DMA_RESETVALUE 0x1U +#define XHC_ECHAIU__PBRS_L 29U +#define XHC_ECHAIU__PBRS_R 28U +#define XHC_ECHAIU__PBRS_WIDTH 2U +#define XHC_ECHAIU__PBRS_RESETVALUE 0x0U +#define XHC_ECHAIU__PBR2_L 27U +#define XHC_ECHAIU__PBR2_R 26U +#define XHC_ECHAIU__PBR2_WIDTH 2U +#define XHC_ECHAIU__PBR2_RESETVALUE 0x0U +#define XHC_ECHAIU__SCHS_L 25U +#define XHC_ECHAIU__SCHS_R 24U +#define XHC_ECHAIU__SCHS_WIDTH 2U +#define XHC_ECHAIU__SCHS_RESETVALUE 0x0U +#define XHC_ECHAIU__SCH2_L 23U +#define XHC_ECHAIU__SCH2_R 22U +#define XHC_ECHAIU__SCH2_WIDTH 2U +#define XHC_ECHAIU__SCH2_RESETVALUE 0x0U +#define XHC_ECHAIU__CHMS_L 21U +#define XHC_ECHAIU__CHMS_R 20U +#define XHC_ECHAIU__CHMS_WIDTH 2U +#define XHC_ECHAIU__CHMS_RESETVALUE 0x3U +#define XHC_ECHAIU__CHM2_L 19U +#define XHC_ECHAIU__CHM2_R 18U +#define XHC_ECHAIU__CHM2_WIDTH 2U +#define XHC_ECHAIU__CHM2_RESETVALUE 0x0U +#define XHC_ECHAIU__reserved_L 17U +#define XHC_ECHAIU__reserved_R 16U +#define XHC_ECHAIU__reserved_WIDTH 2U +#define XHC_ECHAIU__reserved_RESETVALUE 0x0U +#define XHC_ECHAIU__NCP_L 15U +#define XHC_ECHAIU__NCP_R 8U +#define XHC_ECHAIU__NCP_WIDTH 8U +#define XHC_ECHAIU__NCP_RESETVALUE 0x04U +#define XHC_ECHAIU__CID_L 7U +#define XHC_ECHAIU__CID_R 0U +#define XHC_ECHAIU__CID_WIDTH 8U +#define XHC_ECHAIU__CID_RESETVALUE 0xc2U +#define XHC_ECHAIU_WIDTH 32U +#define XHC_ECHAIU__WIDTH 32U +#define XHC_ECHAIU_ALL_L 31U +#define XHC_ECHAIU_ALL_R 0U +#define XHC_ECHAIU__ALL_L 31U +#define XHC_ECHAIU__ALL_R 0U +#define XHC_ECHAIU_DATAMASK 0xffffffffU +#define XHC_ECHAIU_RDWRMASK 0x00000000U +#define XHC_ECHAIU_RESETVALUE 0x403004c2U + +#define XHC_AIUDMA_OFFSET 0xc34U +#define XHC_AIUDMA_BASE 0xc34U +#define XHC_AIUDMA__WRMB_L 31U +#define XHC_AIUDMA__WRMB_R 28U +#define XHC_AIUDMA__WRMB_WIDTH 4U +#define XHC_AIUDMA__WRMB_RESETVALUE 0x0U +#define XHC_AIUDMA__WRD_L 27U +#define XHC_AIUDMA__WRD_R 26U +#define XHC_AIUDMA__WRD_WIDTH 2U +#define XHC_AIUDMA__WRD_RESETVALUE 0x0U +#define XHC_AIUDMA__WED_L 25U +#define XHC_AIUDMA__WED_R 24U +#define XHC_AIUDMA__WED_WIDTH 2U +#define XHC_AIUDMA__WED_RESETVALUE 0x0U +#define XHC_AIUDMA__WMS_L 23U +#define XHC_AIUDMA__WMS_R 22U +#define XHC_AIUDMA__WMS_WIDTH 2U +#define XHC_AIUDMA__WMS_RESETVALUE 0x0U +#define XHC_AIUDMA__WMI_L 21U +#define XHC_AIUDMA__WMI_R 20U +#define XHC_AIUDMA__WMI_WIDTH 2U +#define XHC_AIUDMA__WMI_RESETVALUE 0x0U +#define XHC_AIUDMA__WPF_L 19U +#define XHC_AIUDMA__WPF_R 16U +#define XHC_AIUDMA__WPF_WIDTH 4U +#define XHC_AIUDMA__WPF_RESETVALUE 0x6U +#define XHC_AIUDMA__RRMB_L 15U +#define XHC_AIUDMA__RRMB_R 12U +#define XHC_AIUDMA__RRMB_WIDTH 4U +#define XHC_AIUDMA__RRMB_RESETVALUE 0x0U +#define XHC_AIUDMA__RTD_L 11U +#define XHC_AIUDMA__RTD_R 10U +#define XHC_AIUDMA__RTD_WIDTH 2U +#define XHC_AIUDMA__RTD_RESETVALUE 0x0U +#define XHC_AIUDMA__RTF_L 9U +#define XHC_AIUDMA__RTF_R 8U +#define XHC_AIUDMA__RTF_WIDTH 2U +#define XHC_AIUDMA__RTF_RESETVALUE 0x0U +#define XHC_AIUDMA__RM_S_L 7U +#define XHC_AIUDMA__RM_S_R 6U +#define XHC_AIUDMA__RM_S_WIDTH 2U +#define XHC_AIUDMA__RM_S_RESETVALUE 0x0U +#define XHC_AIUDMA__TFBS_L 5U +#define XHC_AIUDMA__TFBS_R 3U +#define XHC_AIUDMA__TFBS_WIDTH 3U +#define XHC_AIUDMA__TFBS_RESETVALUE 0x0U +#define XHC_AIUDMA__reserved_L 2U +#define XHC_AIUDMA__reserved_R 0U +#define XHC_AIUDMA__reserved_WIDTH 3U +#define XHC_AIUDMA__reserved_RESETVALUE 0x0U +#define XHC_AIUDMA_WIDTH 32U +#define XHC_AIUDMA__WIDTH 32U +#define XHC_AIUDMA_ALL_L 31U +#define XHC_AIUDMA_ALL_R 0U +#define XHC_AIUDMA__ALL_L 31U +#define XHC_AIUDMA__ALL_R 0U +#define XHC_AIUDMA_DATAMASK 0xffffffffU +#define XHC_AIUDMA_RDWRMASK 0x00000000U +#define XHC_AIUDMA_RESETVALUE 0x00060000U + +#define XHC_AIUFLA_OFFSET 0xc38U +#define XHC_AIUFLA_BASE 0xc38U +#define XHC_AIUFLA__ACLK_L 31U +#define XHC_AIUFLA__ACLK_R 23U +#define XHC_AIUFLA__ACLK_WIDTH 9U +#define XHC_AIUFLA__ACLK_RESETVALUE 0x0U +#define XHC_AIUFLA__MFLV_L 22U +#define XHC_AIUFLA__MFLV_R 7U +#define XHC_AIUFLA__MFLV_WIDTH 16U +#define XHC_AIUFLA__MFLV_RESETVALUE 0x0000U +#define XHC_AIUFLA__NFC 6U +#define XHC_AIUFLA__NFC_L 6U +#define XHC_AIUFLA__NFC_R 6U +#define XHC_AIUFLA__NFC_WIDTH 1U +#define XHC_AIUFLA__NFC_RESETVALUE 0x1U +#define XHC_AIUFLA__FLADJ_L 5U +#define XHC_AIUFLA__FLADJ_R 0U +#define XHC_AIUFLA__FLADJ_WIDTH 6U +#define XHC_AIUFLA__FLADJ_RESETVALUE 0x20U +#define XHC_AIUFLA_WIDTH 32U +#define XHC_AIUFLA__WIDTH 32U +#define XHC_AIUFLA_ALL_L 31U +#define XHC_AIUFLA_ALL_R 0U +#define XHC_AIUFLA__ALL_L 31U +#define XHC_AIUFLA__ALL_R 0U +#define XHC_AIUFLA_DATAMASK 0xffffffffU +#define XHC_AIUFLA_RDWRMASK 0x00000000U +#define XHC_AIUFLA_RESETVALUE 0x00000060U + +#define XHC_AIUCFG_OFFSET 0xc3cU +#define XHC_AIUCFG_BASE 0xc3cU +#define XHC_AIUCFG__ISO_L 30U +#define XHC_AIUCFG__ISO_R 28U +#define XHC_AIUCFG__ISO_WIDTH 3U +#define XHC_AIUCFG__ISO_RESETVALUE 0x0U +#define XHC_AIUCFG__EPC_L 26U +#define XHC_AIUCFG__EPC_R 24U +#define XHC_AIUCFG__EPC_WIDTH 3U +#define XHC_AIUCFG__EPC_RESETVALUE 0x5U +#define XHC_AIUCFG__PTQ_L 22U +#define XHC_AIUCFG__PTQ_R 20U +#define XHC_AIUCFG__PTQ_WIDTH 3U +#define XHC_AIUCFG__PTQ_RESETVALUE 0x3U +#define XHC_AIUCFG__NTQ_L 18U +#define XHC_AIUCFG__NTQ_R 16U +#define XHC_AIUCFG__NTQ_WIDTH 3U +#define XHC_AIUCFG__NTQ_RESETVALUE 0x3U +#define XHC_AIUCFG__HID 15U +#define XHC_AIUCFG__HID_L 15U +#define XHC_AIUCFG__HID_R 15U +#define XHC_AIUCFG__HID_WIDTH 1U +#define XHC_AIUCFG__HID_RESETVALUE 0x0U +#define XHC_AIUCFG__EPS_L 14U +#define XHC_AIUCFG__EPS_R 12U +#define XHC_AIUCFG__EPS_WIDTH 3U +#define XHC_AIUCFG__EPS_RESETVALUE 0x0U +#define XHC_AIUCFG__reserved_L 11U +#define XHC_AIUCFG__reserved_R 9U +#define XHC_AIUCFG__reserved_WIDTH 3U +#define XHC_AIUCFG__reserved_RESETVALUE 0x0U +#define XHC_AIUCFG__PEP2_L 8U +#define XHC_AIUCFG__PEP2_R 6U +#define XHC_AIUCFG__PEP2_WIDTH 3U +#define XHC_AIUCFG__PEP2_RESETVALUE 0x4U +#define XHC_AIUCFG__MELADJ_L 5U +#define XHC_AIUCFG__MELADJ_R 0U +#define XHC_AIUCFG__MELADJ_WIDTH 6U +#define XHC_AIUCFG__MELADJ_RESETVALUE 0x0U +#define XHC_AIUCFG__RESERVED_0 31U +#define XHC_AIUCFG__RESERVED_0_L 31U +#define XHC_AIUCFG__RESERVED_0_R 31U +#define XHC_AIUCFG__RESERVED_1 27U +#define XHC_AIUCFG__RESERVED_1_L 27U +#define XHC_AIUCFG__RESERVED_1_R 27U +#define XHC_AIUCFG__RESERVED_2 23U +#define XHC_AIUCFG__RESERVED_2_L 23U +#define XHC_AIUCFG__RESERVED_2_R 23U +#define XHC_AIUCFG__RESERVED_3 19U +#define XHC_AIUCFG__RESERVED_3_L 19U +#define XHC_AIUCFG__RESERVED_3_R 19U +#define XHC_AIUCFG_WIDTH 31U +#define XHC_AIUCFG__WIDTH 31U +#define XHC_AIUCFG_ALL_L 30U +#define XHC_AIUCFG_ALL_R 0U +#define XHC_AIUCFG__ALL_L 30U +#define XHC_AIUCFG__ALL_R 0U +#define XHC_AIUCFG_DATAMASK 0x7777ffffU +#define XHC_AIUCFG_RDWRMASK 0x88880000U +#define XHC_AIUCFG_RESETVALUE 0x05330100U + +#define XHC_ECHFSC_OFFSET 0xc40U +#define XHC_ECHFSC_BASE 0xc40U +#define XHC_ECHFSC__reserved_L 31U +#define XHC_ECHFSC__reserved_R 24U +#define XHC_ECHFSC__reserved_WIDTH 8U +#define XHC_ECHFSC__reserved_RESETVALUE 0x00U +#define XHC_ECHFSC__WRMB_L 23U +#define XHC_ECHFSC__WRMB_R 20U +#define XHC_ECHFSC__WRMB_WIDTH 4U +#define XHC_ECHFSC__WRMB_RESETVALUE 0x0U +#define XHC_ECHFSC__RRMB_L 19U +#define XHC_ECHFSC__RRMB_R 16U +#define XHC_ECHFSC__RRMB_WIDTH 4U +#define XHC_ECHFSC__RRMB_RESETVALUE 0x0U +#define XHC_ECHFSC__NCP_L 15U +#define XHC_ECHFSC__NCP_R 8U +#define XHC_ECHFSC__NCP_WIDTH 8U +#define XHC_ECHFSC__NCP_RESETVALUE 0x50U +#define XHC_ECHFSC__CID_L 7U +#define XHC_ECHFSC__CID_R 0U +#define XHC_ECHFSC__CID_WIDTH 8U +#define XHC_ECHFSC__CID_RESETVALUE 0xc3U +#define XHC_ECHFSC_WIDTH 32U +#define XHC_ECHFSC__WIDTH 32U +#define XHC_ECHFSC_ALL_L 31U +#define XHC_ECHFSC_ALL_R 0U +#define XHC_ECHFSC__ALL_L 31U +#define XHC_ECHFSC__ALL_R 0U +#define XHC_ECHFSC_DATAMASK 0xffffffffU +#define XHC_ECHFSC_RDWRMASK 0x00000000U +#define XHC_ECHFSC_RESETVALUE 0x000050c3U + +#define XHC_FSCPOC_OFFSET 0xc54U +#define XHC_FSCPOC_BASE 0xc54U +#define XHC_FSCPOC__NCS_L 31U +#define XHC_FSCPOC__NCS_R 28U +#define XHC_FSCPOC__NCS_WIDTH 4U +#define XHC_FSCPOC__NCS_RESETVALUE 0x0U +#define XHC_FSCPOC__FSIZ_L 22U +#define XHC_FSCPOC__FSIZ_R 18U +#define XHC_FSCPOC__FSIZ_WIDTH 5U +#define XHC_FSCPOC__FSIZ_RESETVALUE 0x0U +#define XHC_FSCPOC__PSIZ_L 16U +#define XHC_FSCPOC__PSIZ_R 12U +#define XHC_FSCPOC__PSIZ_WIDTH 5U +#define XHC_FSCPOC__PSIZ_RESETVALUE 0x0U +#define XHC_FSCPOC__reserved_L 11U +#define XHC_FSCPOC__reserved_R 5U +#define XHC_FSCPOC__reserved_WIDTH 7U +#define XHC_FSCPOC__reserved_RESETVALUE 0x0U +#define XHC_FSCPOC__TSIZ_L 4U +#define XHC_FSCPOC__TSIZ_R 0U +#define XHC_FSCPOC__TSIZ_WIDTH 5U +#define XHC_FSCPOC__TSIZ_RESETVALUE 0x0U +#define XHC_FSCPOC__RESERVED_L 27U +#define XHC_FSCPOC__RESERVED_R 23U +#define XHC_FSCPOC_WIDTH 32U +#define XHC_FSCPOC__WIDTH 32U +#define XHC_FSCPOC_ALL_L 31U +#define XHC_FSCPOC_ALL_R 0U +#define XHC_FSCPOC__ALL_L 31U +#define XHC_FSCPOC__ALL_R 0U +#define XHC_FSCPOC_DATAMASK 0xf07dffffU +#define XHC_FSCPOC_RDWRMASK 0x0f820000U +#define XHC_FSCPOC_RESETVALUE 0x00000000U + +#define XHC_FSCGOC_OFFSET 0xc58U +#define XHC_FSCGOC_BASE 0xc58U +#define XHC_FSCGOC__NCS_L 31U +#define XHC_FSCGOC__NCS_R 28U +#define XHC_FSCGOC__NCS_WIDTH 4U +#define XHC_FSCGOC__NCS_RESETVALUE 0x0U +#define XHC_FSCGOC__FSIZ_L 22U +#define XHC_FSCGOC__FSIZ_R 18U +#define XHC_FSCGOC__FSIZ_WIDTH 5U +#define XHC_FSCGOC__FSIZ_RESETVALUE 0x0U +#define XHC_FSCGOC__PSIZ_L 16U +#define XHC_FSCGOC__PSIZ_R 12U +#define XHC_FSCGOC__PSIZ_WIDTH 5U +#define XHC_FSCGOC__PSIZ_RESETVALUE 0x0U +#define XHC_FSCGOC__reserved_L 11U +#define XHC_FSCGOC__reserved_R 5U +#define XHC_FSCGOC__reserved_WIDTH 7U +#define XHC_FSCGOC__reserved_RESETVALUE 0x0U +#define XHC_FSCGOC__TSIZ_L 4U +#define XHC_FSCGOC__TSIZ_R 0U +#define XHC_FSCGOC__TSIZ_WIDTH 5U +#define XHC_FSCGOC__TSIZ_RESETVALUE 0x0U +#define XHC_FSCGOC__RESERVED_L 27U +#define XHC_FSCGOC__RESERVED_R 23U +#define XHC_FSCGOC_WIDTH 32U +#define XHC_FSCGOC__WIDTH 32U +#define XHC_FSCGOC_ALL_L 31U +#define XHC_FSCGOC_ALL_R 0U +#define XHC_FSCGOC__ALL_L 31U +#define XHC_FSCGOC__ALL_R 0U +#define XHC_FSCGOC_DATAMASK 0xf07dffffU +#define XHC_FSCGOC_RDWRMASK 0x0f820000U +#define XHC_FSCGOC_RESETVALUE 0x00000000U + +#define XHC_FSCNOC_OFFSET 0xc5cU +#define XHC_FSCNOC_BASE 0xc5cU +#define XHC_FSCNOC__NCS_L 31U +#define XHC_FSCNOC__NCS_R 28U +#define XHC_FSCNOC__NCS_WIDTH 4U +#define XHC_FSCNOC__NCS_RESETVALUE 0x0U +#define XHC_FSCNOC__FSIZ_L 22U +#define XHC_FSCNOC__FSIZ_R 18U +#define XHC_FSCNOC__FSIZ_WIDTH 5U +#define XHC_FSCNOC__FSIZ_RESETVALUE 0x0U +#define XHC_FSCNOC__PSIZ_L 16U +#define XHC_FSCNOC__PSIZ_R 12U +#define XHC_FSCNOC__PSIZ_WIDTH 5U +#define XHC_FSCNOC__PSIZ_RESETVALUE 0x0U +#define XHC_FSCNOC__reserved_L 11U +#define XHC_FSCNOC__reserved_R 5U +#define XHC_FSCNOC__reserved_WIDTH 7U +#define XHC_FSCNOC__reserved_RESETVALUE 0x0U +#define XHC_FSCNOC__TSIZ_L 4U +#define XHC_FSCNOC__TSIZ_R 0U +#define XHC_FSCNOC__TSIZ_WIDTH 5U +#define XHC_FSCNOC__TSIZ_RESETVALUE 0x0U +#define XHC_FSCNOC__RESERVED_L 27U +#define XHC_FSCNOC__RESERVED_R 23U +#define XHC_FSCNOC_WIDTH 32U +#define XHC_FSCNOC__WIDTH 32U +#define XHC_FSCNOC_ALL_L 31U +#define XHC_FSCNOC_ALL_R 0U +#define XHC_FSCNOC__ALL_L 31U +#define XHC_FSCNOC__ALL_R 0U +#define XHC_FSCNOC_DATAMASK 0xf07dffffU +#define XHC_FSCNOC_RDWRMASK 0x0f820000U +#define XHC_FSCNOC_RESETVALUE 0x00000000U + +#define XHC_FSCAIC_OFFSET 0xc60U +#define XHC_FSCAIC_BASE 0xc60U +#define XHC_FSCAIC__FSIZ_L 22U +#define XHC_FSCAIC__FSIZ_R 18U +#define XHC_FSCAIC__FSIZ_WIDTH 5U +#define XHC_FSCAIC__FSIZ_RESETVALUE 0x0U +#define XHC_FSCAIC__PSIZ_L 16U +#define XHC_FSCAIC__PSIZ_R 12U +#define XHC_FSCAIC__PSIZ_WIDTH 5U +#define XHC_FSCAIC__PSIZ_RESETVALUE 0x0U +#define XHC_FSCAIC__reserved_L 11U +#define XHC_FSCAIC__reserved_R 0U +#define XHC_FSCAIC__reserved_WIDTH 12U +#define XHC_FSCAIC__reserved_RESETVALUE 0x000U +#define XHC_FSCAIC__RESERVED_L 31U +#define XHC_FSCAIC__RESERVED_R 23U +#define XHC_FSCAIC_WIDTH 23U +#define XHC_FSCAIC__WIDTH 23U +#define XHC_FSCAIC_ALL_L 22U +#define XHC_FSCAIC_ALL_R 0U +#define XHC_FSCAIC__ALL_L 22U +#define XHC_FSCAIC__ALL_R 0U +#define XHC_FSCAIC_DATAMASK 0x007dffffU +#define XHC_FSCAIC_RDWRMASK 0xff820000U +#define XHC_FSCAIC_RESETVALUE 0x000000U + +#define XHC_FSCPIC_OFFSET 0xc64U +#define XHC_FSCPIC_BASE 0xc64U +#define XHC_FSCPIC__NCS_L 31U +#define XHC_FSCPIC__NCS_R 28U +#define XHC_FSCPIC__NCS_WIDTH 4U +#define XHC_FSCPIC__NCS_RESETVALUE 0x0U +#define XHC_FSCPIC__reserved_L 27U +#define XHC_FSCPIC__reserved_R 5U +#define XHC_FSCPIC__reserved_WIDTH 23U +#define XHC_FSCPIC__reserved_RESETVALUE 0x0U +#define XHC_FSCPIC__TSIZ_L 4U +#define XHC_FSCPIC__TSIZ_R 0U +#define XHC_FSCPIC__TSIZ_WIDTH 5U +#define XHC_FSCPIC__TSIZ_RESETVALUE 0x0U +#define XHC_FSCPIC_WIDTH 32U +#define XHC_FSCPIC__WIDTH 32U +#define XHC_FSCPIC_ALL_L 31U +#define XHC_FSCPIC_ALL_R 0U +#define XHC_FSCPIC__ALL_L 31U +#define XHC_FSCPIC__ALL_R 0U +#define XHC_FSCPIC_DATAMASK 0xffffffffU +#define XHC_FSCPIC_RDWRMASK 0x00000000U +#define XHC_FSCPIC_RESETVALUE 0x00000000U + +#define XHC_FSCGIC_OFFSET 0xc68U +#define XHC_FSCGIC_BASE 0xc68U +#define XHC_FSCGIC__NCS_L 31U +#define XHC_FSCGIC__NCS_R 28U +#define XHC_FSCGIC__NCS_WIDTH 4U +#define XHC_FSCGIC__NCS_RESETVALUE 0x0U +#define XHC_FSCGIC__reserved_L 27U +#define XHC_FSCGIC__reserved_R 5U +#define XHC_FSCGIC__reserved_WIDTH 23U +#define XHC_FSCGIC__reserved_RESETVALUE 0x0U +#define XHC_FSCGIC__TSIZ_L 4U +#define XHC_FSCGIC__TSIZ_R 0U +#define XHC_FSCGIC__TSIZ_WIDTH 5U +#define XHC_FSCGIC__TSIZ_RESETVALUE 0x0U +#define XHC_FSCGIC_WIDTH 32U +#define XHC_FSCGIC__WIDTH 32U +#define XHC_FSCGIC_ALL_L 31U +#define XHC_FSCGIC_ALL_R 0U +#define XHC_FSCGIC__ALL_L 31U +#define XHC_FSCGIC__ALL_R 0U +#define XHC_FSCGIC_DATAMASK 0xffffffffU +#define XHC_FSCGIC_RDWRMASK 0x00000000U +#define XHC_FSCGIC_RESETVALUE 0x00000000U + +#define XHC_FSCNIC_OFFSET 0xc6cU +#define XHC_FSCNIC_BASE 0xc6cU +#define XHC_FSCNIC__NCS_L 31U +#define XHC_FSCNIC__NCS_R 28U +#define XHC_FSCNIC__NCS_WIDTH 4U +#define XHC_FSCNIC__NCS_RESETVALUE 0x0U +#define XHC_FSCNIC__reserved_L 27U +#define XHC_FSCNIC__reserved_R 5U +#define XHC_FSCNIC__reserved_WIDTH 23U +#define XHC_FSCNIC__reserved_RESETVALUE 0x0U +#define XHC_FSCNIC__TSIZ_L 4U +#define XHC_FSCNIC__TSIZ_R 0U +#define XHC_FSCNIC__TSIZ_WIDTH 5U +#define XHC_FSCNIC__TSIZ_RESETVALUE 0x0U +#define XHC_FSCNIC_WIDTH 32U +#define XHC_FSCNIC__WIDTH 32U +#define XHC_FSCNIC_ALL_L 31U +#define XHC_FSCNIC_ALL_R 0U +#define XHC_FSCNIC__ALL_L 31U +#define XHC_FSCNIC__ALL_R 0U +#define XHC_FSCNIC_DATAMASK 0xffffffffU +#define XHC_FSCNIC_RDWRMASK 0x00000000U +#define XHC_FSCNIC_RESETVALUE 0x00000000U + +#define XHC_ECHPRT_OFFSET 0xc70U +#define XHC_ECHPRT_BASE 0xc70U +#define XHC_ECHPRT__TDP 31U +#define XHC_ECHPRT__TDP_L 31U +#define XHC_ECHPRT__TDP_R 31U +#define XHC_ECHPRT__TDP_WIDTH 1U +#define XHC_ECHPRT__TDP_RESETVALUE 0x0U +#define XHC_ECHPRT__RDP 30U +#define XHC_ECHPRT__RDP_L 30U +#define XHC_ECHPRT__RDP_R 30U +#define XHC_ECHPRT__RDP_WIDTH 1U +#define XHC_ECHPRT__RDP_RESETVALUE 0x0U +#define XHC_ECHPRT__reserved_L 29U +#define XHC_ECHPRT__reserved_R 25U +#define XHC_ECHPRT__reserved_WIDTH 5U +#define XHC_ECHPRT__reserved_RESETVALUE 0x0U +#define XHC_ECHPRT__MFT_L 24U +#define XHC_ECHPRT__MFT_R 17U +#define XHC_ECHPRT__MFT_WIDTH 8U +#define XHC_ECHPRT__MFT_RESETVALUE 0x7dU +#define XHC_ECHPRT__HST 16U +#define XHC_ECHPRT__HST_L 16U +#define XHC_ECHPRT__HST_R 16U +#define XHC_ECHPRT__HST_WIDTH 1U +#define XHC_ECHPRT__HST_RESETVALUE 0x0U +#define XHC_ECHPRT__NCP_L 15U +#define XHC_ECHPRT__NCP_R 8U +#define XHC_ECHPRT__NCP_WIDTH 8U +#define XHC_ECHPRT__NCP_RESETVALUE 0x04U +#define XHC_ECHPRT__CID_L 7U +#define XHC_ECHPRT__CID_R 0U +#define XHC_ECHPRT__CID_WIDTH 8U +#define XHC_ECHPRT__CID_RESETVALUE 0xc4U +#define XHC_ECHPRT_WIDTH 32U +#define XHC_ECHPRT__WIDTH 32U +#define XHC_ECHPRT_ALL_L 31U +#define XHC_ECHPRT_ALL_R 0U +#define XHC_ECHPRT__ALL_L 31U +#define XHC_ECHPRT__ALL_R 0U +#define XHC_ECHPRT_DATAMASK 0xffffffffU +#define XHC_ECHPRT_RDWRMASK 0x00000000U +#define XHC_ECHPRT_RESETVALUE 0x00fa04c4U + +#define XHC_PRTHSC_OFFSET 0xc78U +#define XHC_PRTHSC_BASE 0xc78U +#define XHC_PRTHSC__TMR_L 31U +#define XHC_PRTHSC__TMR_R 16U +#define XHC_PRTHSC__TMR_WIDTH 16U +#define XHC_PRTHSC__TMR_RESETVALUE 0x0000U +#define XHC_PRTHSC__RSL_L 7U +#define XHC_PRTHSC__RSL_R 6U +#define XHC_PRTHSC__RSL_WIDTH 2U +#define XHC_PRTHSC__RSL_RESETVALUE 0x0U +#define XHC_PRTHSC__AS_M_L 5U +#define XHC_PRTHSC__AS_M_R 4U +#define XHC_PRTHSC__AS_M_WIDTH 2U +#define XHC_PRTHSC__AS_M_RESETVALUE 0x0U +#define XHC_PRTHSC__CMD_L 3U +#define XHC_PRTHSC__CMD_R 2U +#define XHC_PRTHSC__CMD_WIDTH 2U +#define XHC_PRTHSC__CMD_RESETVALUE 0x0U +#define XHC_PRTHSC__reserved 1U +#define XHC_PRTHSC__reserved_L 1U +#define XHC_PRTHSC__reserved_R 1U +#define XHC_PRTHSC__reserved_WIDTH 1U +#define XHC_PRTHSC__reserved_RESETVALUE 0x0U +#define XHC_PRTHSC__STB 0U +#define XHC_PRTHSC__STB_L 0U +#define XHC_PRTHSC__STB_R 0U +#define XHC_PRTHSC__STB_WIDTH 1U +#define XHC_PRTHSC__STB_RESETVALUE 0x0U +#define XHC_PRTHSC__RESERVED_L 15U +#define XHC_PRTHSC__RESERVED_R 8U +#define XHC_PRTHSC_WIDTH 32U +#define XHC_PRTHSC__WIDTH 32U +#define XHC_PRTHSC_ALL_L 31U +#define XHC_PRTHSC_ALL_R 0U +#define XHC_PRTHSC__ALL_L 31U +#define XHC_PRTHSC__ALL_R 0U +#define XHC_PRTHSC_DATAMASK 0xffff00ffU +#define XHC_PRTHSC_RDWRMASK 0x0000ff00U +#define XHC_PRTHSC_RESETVALUE 0x00000000U + +#define XHC_PRTHSR_OFFSET 0xc7cU +#define XHC_PRTHSR_BASE 0xc7cU +#define XHC_PRTHSR__RDLY_L 31U +#define XHC_PRTHSR__RDLY_R 24U +#define XHC_PRTHSR__RDLY_WIDTH 8U +#define XHC_PRTHSR__RDLY_RESETVALUE 0x00U +#define XHC_PRTHSR__TDPP_L 23U +#define XHC_PRTHSR__TDPP_R 16U +#define XHC_PRTHSR__TDPP_WIDTH 8U +#define XHC_PRTHSR__TDPP_RESETVALUE 0x00U +#define XHC_PRTHSR__RDPP_L 15U +#define XHC_PRTHSR__RDPP_R 8U +#define XHC_PRTHSR__RDPP_WIDTH 8U +#define XHC_PRTHSR__RDPP_RESETVALUE 0x00U +#define XHC_PRTHSR__TRTY_L 7U +#define XHC_PRTHSR__TRTY_R 0U +#define XHC_PRTHSR__TRTY_WIDTH 8U +#define XHC_PRTHSR__TRTY_RESETVALUE 0x00U +#define XHC_PRTHSR_WIDTH 32U +#define XHC_PRTHSR__WIDTH 32U +#define XHC_PRTHSR_ALL_L 31U +#define XHC_PRTHSR_ALL_R 0U +#define XHC_PRTHSR__ALL_L 31U +#define XHC_PRTHSR__ALL_R 0U +#define XHC_PRTHSR_DATAMASK 0xffffffffU +#define XHC_PRTHSR_RDWRMASK 0x00000000U +#define XHC_PRTHSR_RESETVALUE 0x00000000U + +#define XHC_ECHRHS_OFFSET 0xc80U +#define XHC_ECHRHS_BASE 0xc80U +#define XHC_ECHRHS__RPO_L 30U +#define XHC_ECHRHS__RPO_R 24U +#define XHC_ECHRHS__RPO_WIDTH 7U +#define XHC_ECHRHS__RPO_RESETVALUE 0x0U +#define XHC_ECHRHS__reserved_L 23U +#define XHC_ECHRHS__reserved_R 22U +#define XHC_ECHRHS__reserved_WIDTH 2U +#define XHC_ECHRHS__reserved_RESETVALUE 0x0U +#define XHC_ECHRHS__RPN_L 21U +#define XHC_ECHRHS__RPN_R 20U +#define XHC_ECHRHS__RPN_WIDTH 2U +#define XHC_ECHRHS__RPN_RESETVALUE 0x0U +#define XHC_ECHRHS__DNR_L 19U +#define XHC_ECHRHS__DNR_R 16U +#define XHC_ECHRHS__DNR_WIDTH 4U +#define XHC_ECHRHS__DNR_RESETVALUE 0x0U +#define XHC_ECHRHS__NCP_L 15U +#define XHC_ECHRHS__NCP_R 8U +#define XHC_ECHRHS__NCP_WIDTH 8U +#define XHC_ECHRHS__NCP_RESETVALUE 0x0cU +#define XHC_ECHRHS__CID_L 7U +#define XHC_ECHRHS__CID_R 0U +#define XHC_ECHRHS__CID_WIDTH 8U +#define XHC_ECHRHS__CID_RESETVALUE 0xc8U +#define XHC_ECHRHS__RESERVED 31U +#define XHC_ECHRHS__RESERVED_L 31U +#define XHC_ECHRHS__RESERVED_R 31U +#define XHC_ECHRHS_WIDTH 31U +#define XHC_ECHRHS__WIDTH 31U +#define XHC_ECHRHS_ALL_L 30U +#define XHC_ECHRHS_ALL_R 0U +#define XHC_ECHRHS__ALL_L 30U +#define XHC_ECHRHS__ALL_R 0U +#define XHC_ECHRHS_DATAMASK 0x7fffffffU +#define XHC_ECHRHS_RDWRMASK 0x80000000U +#define XHC_ECHRHS_RESETVALUE 0x00000cc8U + +#define XHC_RHSDES_OFFSET 0xc84U +#define XHC_RHSDES_BASE 0xc84U +#define XHC_RHSDES__PIS3_L 31U +#define XHC_RHSDES__PIS3_R 30U +#define XHC_RHSDES__PIS3_WIDTH 2U +#define XHC_RHSDES__PIS3_RESETVALUE 0x0U +#define XHC_RHSDES__HIST3 24U +#define XHC_RHSDES__HIST3_L 24U +#define XHC_RHSDES__HIST3_R 24U +#define XHC_RHSDES__HIST3_WIDTH 1U +#define XHC_RHSDES__HIST3_RESETVALUE 0x0U +#define XHC_RHSDES__PIS2_L 23U +#define XHC_RHSDES__PIS2_R 22U +#define XHC_RHSDES__PIS2_WIDTH 2U +#define XHC_RHSDES__PIS2_RESETVALUE 0x0U +#define XHC_RHSDES__HIST2 16U +#define XHC_RHSDES__HIST2_L 16U +#define XHC_RHSDES__HIST2_R 16U +#define XHC_RHSDES__HIST2_WIDTH 1U +#define XHC_RHSDES__HIST2_RESETVALUE 0x0U +#define XHC_RHSDES__PIS1_L 15U +#define XHC_RHSDES__PIS1_R 14U +#define XHC_RHSDES__PIS1_WIDTH 2U +#define XHC_RHSDES__PIS1_RESETVALUE 0x0U +#define XHC_RHSDES__HIST1 8U +#define XHC_RHSDES__HIST1_L 8U +#define XHC_RHSDES__HIST1_R 8U +#define XHC_RHSDES__HIST1_WIDTH 1U +#define XHC_RHSDES__HIST1_RESETVALUE 0x0U +#define XHC_RHSDES__PIS0_L 7U +#define XHC_RHSDES__PIS0_R 6U +#define XHC_RHSDES__PIS0_WIDTH 2U +#define XHC_RHSDES__PIS0_RESETVALUE 0x0U +#define XHC_RHSDES__reserved_L 5U +#define XHC_RHSDES__reserved_R 1U +#define XHC_RHSDES__reserved_WIDTH 5U +#define XHC_RHSDES__reserved_RESETVALUE 0x0U +#define XHC_RHSDES__HIST0 0U +#define XHC_RHSDES__HIST0_L 0U +#define XHC_RHSDES__HIST0_R 0U +#define XHC_RHSDES__HIST0_WIDTH 1U +#define XHC_RHSDES__HIST0_RESETVALUE 0x0U +#define XHC_RHSDES__RESERVED_0_L 29U +#define XHC_RHSDES__RESERVED_0_R 25U +#define XHC_RHSDES__RESERVED_1_L 21U +#define XHC_RHSDES__RESERVED_1_R 17U +#define XHC_RHSDES__RESERVED_2_L 13U +#define XHC_RHSDES__RESERVED_2_R 9U +#define XHC_RHSDES__RESERVED_L 29U +#define XHC_RHSDES__RESERVED_R 25U +#define XHC_RHSDES_WIDTH 32U +#define XHC_RHSDES__WIDTH 32U +#define XHC_RHSDES_ALL_L 31U +#define XHC_RHSDES_ALL_R 0U +#define XHC_RHSDES__ALL_L 31U +#define XHC_RHSDES__ALL_R 0U +#define XHC_RHSDES_DATAMASK 0xc1c1c1ffU +#define XHC_RHSDES_RDWRMASK 0x3e3e3e00U +#define XHC_RHSDES_RESETVALUE 0x00000000U + +#define XHC_RHSHSC0_OFFSET 0xc90U +#define XHC_RHSHSC0_BASE 0xc90U +#define XHC_RHSHSC0__TMR_L 31U +#define XHC_RHSHSC0__TMR_R 16U +#define XHC_RHSHSC0__TMR_WIDTH 16U +#define XHC_RHSHSC0__TMR_RESETVALUE 0x0000U +#define XHC_RHSHSC0__RSL_L 7U +#define XHC_RHSHSC0__RSL_R 6U +#define XHC_RHSHSC0__RSL_WIDTH 2U +#define XHC_RHSHSC0__RSL_RESETVALUE 0x0U +#define XHC_RHSHSC0__AS_M_L 5U +#define XHC_RHSHSC0__AS_M_R 4U +#define XHC_RHSHSC0__AS_M_WIDTH 2U +#define XHC_RHSHSC0__AS_M_RESETVALUE 0x0U +#define XHC_RHSHSC0__CMD_L 3U +#define XHC_RHSHSC0__CMD_R 2U +#define XHC_RHSHSC0__CMD_WIDTH 2U +#define XHC_RHSHSC0__CMD_RESETVALUE 0x0U +#define XHC_RHSHSC0__reserved 1U +#define XHC_RHSHSC0__reserved_L 1U +#define XHC_RHSHSC0__reserved_R 1U +#define XHC_RHSHSC0__reserved_WIDTH 1U +#define XHC_RHSHSC0__reserved_RESETVALUE 0x0U +#define XHC_RHSHSC0__STB 0U +#define XHC_RHSHSC0__STB_L 0U +#define XHC_RHSHSC0__STB_R 0U +#define XHC_RHSHSC0__STB_WIDTH 1U +#define XHC_RHSHSC0__STB_RESETVALUE 0x0U +#define XHC_RHSHSC0__RESERVED_L 15U +#define XHC_RHSHSC0__RESERVED_R 8U +#define XHC_RHSHSC0_WIDTH 32U +#define XHC_RHSHSC0__WIDTH 32U +#define XHC_RHSHSC0_ALL_L 31U +#define XHC_RHSHSC0_ALL_R 0U +#define XHC_RHSHSC0__ALL_L 31U +#define XHC_RHSHSC0__ALL_R 0U +#define XHC_RHSHSC0_DATAMASK 0xffff00ffU +#define XHC_RHSHSC0_RDWRMASK 0x0000ff00U +#define XHC_RHSHSC0_RESETVALUE 0x00000000U + +#define XHC_RHSHSR0_OFFSET 0xc94U +#define XHC_RHSHSR0_BASE 0xc94U +#define XHC_RHSHSR0__C2U_L 31U +#define XHC_RHSHSR0__C2U_R 24U +#define XHC_RHSHSR0__C2U_WIDTH 8U +#define XHC_RHSHSR0__C2U_RESETVALUE 0x00U +#define XHC_RHSHSR0__C1U_L 23U +#define XHC_RHSHSR0__C1U_R 16U +#define XHC_RHSHSR0__C1U_WIDTH 8U +#define XHC_RHSHSR0__C1U_RESETVALUE 0x00U +#define XHC_RHSHSR0__RCV_L 15U +#define XHC_RHSHSR0__RCV_R 8U +#define XHC_RHSHSR0__RCV_WIDTH 8U +#define XHC_RHSHSR0__RCV_RESETVALUE 0x00U +#define XHC_RHSHSR0__RTY_L 7U +#define XHC_RHSHSR0__RTY_R 0U +#define XHC_RHSHSR0__RTY_WIDTH 8U +#define XHC_RHSHSR0__RTY_RESETVALUE 0x00U +#define XHC_RHSHSR0_WIDTH 32U +#define XHC_RHSHSR0__WIDTH 32U +#define XHC_RHSHSR0_ALL_L 31U +#define XHC_RHSHSR0_ALL_R 0U +#define XHC_RHSHSR0__ALL_L 31U +#define XHC_RHSHSR0__ALL_R 0U +#define XHC_RHSHSR0_DATAMASK 0xffffffffU +#define XHC_RHSHSR0_RDWRMASK 0x00000000U +#define XHC_RHSHSR0_RESETVALUE 0x00000000U + +#define XHC_RHSHSC1_OFFSET 0xc98U +#define XHC_RHSHSC1_BASE 0xc98U +#define XHC_RHSHSC1__TMR_L 31U +#define XHC_RHSHSC1__TMR_R 16U +#define XHC_RHSHSC1__TMR_WIDTH 16U +#define XHC_RHSHSC1__TMR_RESETVALUE 0x0000U +#define XHC_RHSHSC1__RSL_L 7U +#define XHC_RHSHSC1__RSL_R 6U +#define XHC_RHSHSC1__RSL_WIDTH 2U +#define XHC_RHSHSC1__RSL_RESETVALUE 0x0U +#define XHC_RHSHSC1__AS_M_L 5U +#define XHC_RHSHSC1__AS_M_R 4U +#define XHC_RHSHSC1__AS_M_WIDTH 2U +#define XHC_RHSHSC1__AS_M_RESETVALUE 0x0U +#define XHC_RHSHSC1__CMD_L 3U +#define XHC_RHSHSC1__CMD_R 2U +#define XHC_RHSHSC1__CMD_WIDTH 2U +#define XHC_RHSHSC1__CMD_RESETVALUE 0x0U +#define XHC_RHSHSC1__reserved 1U +#define XHC_RHSHSC1__reserved_L 1U +#define XHC_RHSHSC1__reserved_R 1U +#define XHC_RHSHSC1__reserved_WIDTH 1U +#define XHC_RHSHSC1__reserved_RESETVALUE 0x0U +#define XHC_RHSHSC1__STB 0U +#define XHC_RHSHSC1__STB_L 0U +#define XHC_RHSHSC1__STB_R 0U +#define XHC_RHSHSC1__STB_WIDTH 1U +#define XHC_RHSHSC1__STB_RESETVALUE 0x0U +#define XHC_RHSHSC1__RESERVED_L 15U +#define XHC_RHSHSC1__RESERVED_R 8U +#define XHC_RHSHSC1_WIDTH 32U +#define XHC_RHSHSC1__WIDTH 32U +#define XHC_RHSHSC1_ALL_L 31U +#define XHC_RHSHSC1_ALL_R 0U +#define XHC_RHSHSC1__ALL_L 31U +#define XHC_RHSHSC1__ALL_R 0U +#define XHC_RHSHSC1_DATAMASK 0xffff00ffU +#define XHC_RHSHSC1_RDWRMASK 0x0000ff00U +#define XHC_RHSHSC1_RESETVALUE 0x00000000U + +#define XHC_RHSHSR1_OFFSET 0xc9cU +#define XHC_RHSHSR1_BASE 0xc9cU +#define XHC_RHSHSR1__C2U_L 31U +#define XHC_RHSHSR1__C2U_R 24U +#define XHC_RHSHSR1__C2U_WIDTH 8U +#define XHC_RHSHSR1__C2U_RESETVALUE 0x00U +#define XHC_RHSHSR1__C1U_L 23U +#define XHC_RHSHSR1__C1U_R 16U +#define XHC_RHSHSR1__C1U_WIDTH 8U +#define XHC_RHSHSR1__C1U_RESETVALUE 0x00U +#define XHC_RHSHSR1__RCV_L 15U +#define XHC_RHSHSR1__RCV_R 8U +#define XHC_RHSHSR1__RCV_WIDTH 8U +#define XHC_RHSHSR1__RCV_RESETVALUE 0x00U +#define XHC_RHSHSR1__RTY_L 7U +#define XHC_RHSHSR1__RTY_R 0U +#define XHC_RHSHSR1__RTY_WIDTH 8U +#define XHC_RHSHSR1__RTY_RESETVALUE 0x00U +#define XHC_RHSHSR1_WIDTH 32U +#define XHC_RHSHSR1__WIDTH 32U +#define XHC_RHSHSR1_ALL_L 31U +#define XHC_RHSHSR1_ALL_R 0U +#define XHC_RHSHSR1__ALL_L 31U +#define XHC_RHSHSR1__ALL_R 0U +#define XHC_RHSHSR1_DATAMASK 0xffffffffU +#define XHC_RHSHSR1_RDWRMASK 0x00000000U +#define XHC_RHSHSR1_RESETVALUE 0x00000000U + +#define XHC_RHSHSC2_OFFSET 0xca0U +#define XHC_RHSHSC2_BASE 0xca0U +#define XHC_RHSHSC2__TMR_L 31U +#define XHC_RHSHSC2__TMR_R 16U +#define XHC_RHSHSC2__TMR_WIDTH 16U +#define XHC_RHSHSC2__TMR_RESETVALUE 0x0000U +#define XHC_RHSHSC2__RSL_L 7U +#define XHC_RHSHSC2__RSL_R 6U +#define XHC_RHSHSC2__RSL_WIDTH 2U +#define XHC_RHSHSC2__RSL_RESETVALUE 0x0U +#define XHC_RHSHSC2__AS_M_L 5U +#define XHC_RHSHSC2__AS_M_R 4U +#define XHC_RHSHSC2__AS_M_WIDTH 2U +#define XHC_RHSHSC2__AS_M_RESETVALUE 0x0U +#define XHC_RHSHSC2__CMD_L 3U +#define XHC_RHSHSC2__CMD_R 2U +#define XHC_RHSHSC2__CMD_WIDTH 2U +#define XHC_RHSHSC2__CMD_RESETVALUE 0x0U +#define XHC_RHSHSC2__reserved 1U +#define XHC_RHSHSC2__reserved_L 1U +#define XHC_RHSHSC2__reserved_R 1U +#define XHC_RHSHSC2__reserved_WIDTH 1U +#define XHC_RHSHSC2__reserved_RESETVALUE 0x0U +#define XHC_RHSHSC2__STB 0U +#define XHC_RHSHSC2__STB_L 0U +#define XHC_RHSHSC2__STB_R 0U +#define XHC_RHSHSC2__STB_WIDTH 1U +#define XHC_RHSHSC2__STB_RESETVALUE 0x0U +#define XHC_RHSHSC2__RESERVED_L 15U +#define XHC_RHSHSC2__RESERVED_R 8U +#define XHC_RHSHSC2_WIDTH 32U +#define XHC_RHSHSC2__WIDTH 32U +#define XHC_RHSHSC2_ALL_L 31U +#define XHC_RHSHSC2_ALL_R 0U +#define XHC_RHSHSC2__ALL_L 31U +#define XHC_RHSHSC2__ALL_R 0U +#define XHC_RHSHSC2_DATAMASK 0xffff00ffU +#define XHC_RHSHSC2_RDWRMASK 0x0000ff00U +#define XHC_RHSHSC2_RESETVALUE 0x00000000U + +#define XHC_RHSHSR2_OFFSET 0xca4U +#define XHC_RHSHSR2_BASE 0xca4U +#define XHC_RHSHSR2__C2U_L 31U +#define XHC_RHSHSR2__C2U_R 24U +#define XHC_RHSHSR2__C2U_WIDTH 8U +#define XHC_RHSHSR2__C2U_RESETVALUE 0x00U +#define XHC_RHSHSR2__C1U_L 23U +#define XHC_RHSHSR2__C1U_R 16U +#define XHC_RHSHSR2__C1U_WIDTH 8U +#define XHC_RHSHSR2__C1U_RESETVALUE 0x00U +#define XHC_RHSHSR2__RCV_L 15U +#define XHC_RHSHSR2__RCV_R 8U +#define XHC_RHSHSR2__RCV_WIDTH 8U +#define XHC_RHSHSR2__RCV_RESETVALUE 0x00U +#define XHC_RHSHSR2__RTY_L 7U +#define XHC_RHSHSR2__RTY_R 0U +#define XHC_RHSHSR2__RTY_WIDTH 8U +#define XHC_RHSHSR2__RTY_RESETVALUE 0x00U +#define XHC_RHSHSR2_WIDTH 32U +#define XHC_RHSHSR2__WIDTH 32U +#define XHC_RHSHSR2_ALL_L 31U +#define XHC_RHSHSR2_ALL_R 0U +#define XHC_RHSHSR2__ALL_L 31U +#define XHC_RHSHSR2__ALL_R 0U +#define XHC_RHSHSR2_DATAMASK 0xffffffffU +#define XHC_RHSHSR2_RDWRMASK 0x00000000U +#define XHC_RHSHSR2_RESETVALUE 0x00000000U + +#define XHC_RHSHSC3_OFFSET 0xca8U +#define XHC_RHSHSC3_BASE 0xca8U +#define XHC_RHSHSC3__TMR_L 31U +#define XHC_RHSHSC3__TMR_R 16U +#define XHC_RHSHSC3__TMR_WIDTH 16U +#define XHC_RHSHSC3__TMR_RESETVALUE 0x0000U +#define XHC_RHSHSC3__RSL_L 7U +#define XHC_RHSHSC3__RSL_R 6U +#define XHC_RHSHSC3__RSL_WIDTH 2U +#define XHC_RHSHSC3__RSL_RESETVALUE 0x0U +#define XHC_RHSHSC3__AS_M_L 5U +#define XHC_RHSHSC3__AS_M_R 4U +#define XHC_RHSHSC3__AS_M_WIDTH 2U +#define XHC_RHSHSC3__AS_M_RESETVALUE 0x0U +#define XHC_RHSHSC3__CMD_L 3U +#define XHC_RHSHSC3__CMD_R 2U +#define XHC_RHSHSC3__CMD_WIDTH 2U +#define XHC_RHSHSC3__CMD_RESETVALUE 0x0U +#define XHC_RHSHSC3__reserved 1U +#define XHC_RHSHSC3__reserved_L 1U +#define XHC_RHSHSC3__reserved_R 1U +#define XHC_RHSHSC3__reserved_WIDTH 1U +#define XHC_RHSHSC3__reserved_RESETVALUE 0x0U +#define XHC_RHSHSC3__STB 0U +#define XHC_RHSHSC3__STB_L 0U +#define XHC_RHSHSC3__STB_R 0U +#define XHC_RHSHSC3__STB_WIDTH 1U +#define XHC_RHSHSC3__STB_RESETVALUE 0x0U +#define XHC_RHSHSC3__RESERVED_L 15U +#define XHC_RHSHSC3__RESERVED_R 8U +#define XHC_RHSHSC3_WIDTH 32U +#define XHC_RHSHSC3__WIDTH 32U +#define XHC_RHSHSC3_ALL_L 31U +#define XHC_RHSHSC3_ALL_R 0U +#define XHC_RHSHSC3__ALL_L 31U +#define XHC_RHSHSC3__ALL_R 0U +#define XHC_RHSHSC3_DATAMASK 0xffff00ffU +#define XHC_RHSHSC3_RDWRMASK 0x0000ff00U +#define XHC_RHSHSC3_RESETVALUE 0x00000000U + +#define XHC_RHSHSR3_OFFSET 0xcacU +#define XHC_RHSHSR3_BASE 0xcacU +#define XHC_RHSHSR3__C2U_L 31U +#define XHC_RHSHSR3__C2U_R 24U +#define XHC_RHSHSR3__C2U_WIDTH 8U +#define XHC_RHSHSR3__C2U_RESETVALUE 0x00U +#define XHC_RHSHSR3__C1U_L 23U +#define XHC_RHSHSR3__C1U_R 16U +#define XHC_RHSHSR3__C1U_WIDTH 8U +#define XHC_RHSHSR3__C1U_RESETVALUE 0x00U +#define XHC_RHSHSR3__RCV_L 15U +#define XHC_RHSHSR3__RCV_R 8U +#define XHC_RHSHSR3__RCV_WIDTH 8U +#define XHC_RHSHSR3__RCV_RESETVALUE 0x00U +#define XHC_RHSHSR3__RTY_L 7U +#define XHC_RHSHSR3__RTY_R 0U +#define XHC_RHSHSR3__RTY_WIDTH 8U +#define XHC_RHSHSR3__RTY_RESETVALUE 0x00U +#define XHC_RHSHSR3_WIDTH 32U +#define XHC_RHSHSR3__WIDTH 32U +#define XHC_RHSHSR3_ALL_L 31U +#define XHC_RHSHSR3_ALL_R 0U +#define XHC_RHSHSR3__ALL_L 31U +#define XHC_RHSHSR3__ALL_R 0U +#define XHC_RHSHSR3_DATAMASK 0xffffffffU +#define XHC_RHSHSR3_RDWRMASK 0x00000000U +#define XHC_RHSHSR3_RESETVALUE 0x00000000U + +#define XHC_ECHSSP_OFFSET 0xcb0U +#define XHC_ECHSSP_BASE 0xcb0U +#define XHC_ECHSSP__reserved_L 31U +#define XHC_ECHSSP__reserved_R 16U +#define XHC_ECHSSP__reserved_WIDTH 16U +#define XHC_ECHSSP__reserved_RESETVALUE 0x0000U +#define XHC_ECHSSP__NCP_L 15U +#define XHC_ECHSSP__NCP_R 8U +#define XHC_ECHSSP__NCP_WIDTH 8U +#define XHC_ECHSSP__NCP_RESETVALUE 0x04U +#define XHC_ECHSSP__CID_L 7U +#define XHC_ECHSSP__CID_R 0U +#define XHC_ECHSSP__CID_WIDTH 8U +#define XHC_ECHSSP__CID_RESETVALUE 0xc6U +#define XHC_ECHSSP_WIDTH 32U +#define XHC_ECHSSP__WIDTH 32U +#define XHC_ECHSSP_ALL_L 31U +#define XHC_ECHSSP_ALL_R 0U +#define XHC_ECHSSP__ALL_L 31U +#define XHC_ECHSSP__ALL_R 0U +#define XHC_ECHSSP_DATAMASK 0xffffffffU +#define XHC_ECHSSP_RDWRMASK 0x00000000U +#define XHC_ECHSSP_RESETVALUE 0x000004c6U + +#define XHC_SSPVER_OFFSET 0xcb4U +#define XHC_SSPVER_BASE 0xcb4U +#define XHC_SSPVER__MAJ_L 31U +#define XHC_SSPVER__MAJ_R 28U +#define XHC_SSPVER__MAJ_WIDTH 4U +#define XHC_SSPVER__MAJ_RESETVALUE 0x0U +#define XHC_SSPVER__MIN_L 27U +#define XHC_SSPVER__MIN_R 24U +#define XHC_SSPVER__MIN_WIDTH 4U +#define XHC_SSPVER__MIN_RESETVALUE 0x0U +#define XHC_SSPVER__RLS_L 23U +#define XHC_SSPVER__RLS_R 20U +#define XHC_SSPVER__RLS_WIDTH 4U +#define XHC_SSPVER__RLS_RESETVALUE 0x0U +#define XHC_SSPVER__reserved_L 19U +#define XHC_SSPVER__reserved_R 0U +#define XHC_SSPVER__reserved_WIDTH 20U +#define XHC_SSPVER__reserved_RESETVALUE 0x00000U +#define XHC_SSPVER_WIDTH 32U +#define XHC_SSPVER__WIDTH 32U +#define XHC_SSPVER_ALL_L 31U +#define XHC_SSPVER_ALL_R 0U +#define XHC_SSPVER__ALL_L 31U +#define XHC_SSPVER__ALL_R 0U +#define XHC_SSPVER_DATAMASK 0xffffffffU +#define XHC_SSPVER_RDWRMASK 0x00000000U +#define XHC_SSPVER_RESETVALUE 0x00000000U + +#define XHC_SSPMGN_OFFSET 0xcb8U +#define XHC_SSPMGN_BASE 0xcb8U +#define XHC_SSPMGN__MGN_L 31U +#define XHC_SSPMGN__MGN_R 0U +#define XHC_SSPMGN__MGN_WIDTH 32U +#define XHC_SSPMGN__MGN_RESETVALUE 0x4b535040U +#define XHC_SSPMGN_WIDTH 32U +#define XHC_SSPMGN__WIDTH 32U +#define XHC_SSPMGN_ALL_L 31U +#define XHC_SSPMGN_ALL_R 0U +#define XHC_SSPMGN__ALL_L 31U +#define XHC_SSPMGN__ALL_R 0U +#define XHC_SSPMGN_DATAMASK 0xffffffffU +#define XHC_SSPMGN_RDWRMASK 0x00000000U +#define XHC_SSPMGN_RESETVALUE 0x4b535040U + +#define XHC_ECHFSC2_OFFSET 0xcc0U +#define XHC_ECHFSC2_BASE 0xcc0U +#define XHC_ECHFSC2__reserved_L 31U +#define XHC_ECHFSC2__reserved_R 16U +#define XHC_ECHFSC2__reserved_WIDTH 16U +#define XHC_ECHFSC2__reserved_RESETVALUE 0x0000U +#define XHC_ECHFSC2__NCP_L 15U +#define XHC_ECHFSC2__NCP_R 8U +#define XHC_ECHFSC2__NCP_WIDTH 8U +#define XHC_ECHFSC2__NCP_RESETVALUE 0x50U +#define XHC_ECHFSC2__CID_L 7U +#define XHC_ECHFSC2__CID_R 0U +#define XHC_ECHFSC2__CID_WIDTH 8U +#define XHC_ECHFSC2__CID_RESETVALUE 0xc7U +#define XHC_ECHFSC2_WIDTH 32U +#define XHC_ECHFSC2__WIDTH 32U +#define XHC_ECHFSC2_ALL_L 31U +#define XHC_ECHFSC2_ALL_R 0U +#define XHC_ECHFSC2__ALL_L 31U +#define XHC_ECHFSC2__ALL_R 0U +#define XHC_ECHFSC2_DATAMASK 0xffffffffU +#define XHC_ECHFSC2_RDWRMASK 0x00000000U +#define XHC_ECHFSC2_RESETVALUE 0x000050c7U + +#define XHC_FSC2POC_OFFSET 0xcd4U +#define XHC_FSC2POC_BASE 0xcd4U +#define XHC_FSC2POC__NCS_L 31U +#define XHC_FSC2POC__NCS_R 28U +#define XHC_FSC2POC__NCS_WIDTH 4U +#define XHC_FSC2POC__NCS_RESETVALUE 0x0U +#define XHC_FSC2POC__FSIZ_L 22U +#define XHC_FSC2POC__FSIZ_R 18U +#define XHC_FSC2POC__FSIZ_WIDTH 5U +#define XHC_FSC2POC__FSIZ_RESETVALUE 0x0U +#define XHC_FSC2POC__PSIZ_L 16U +#define XHC_FSC2POC__PSIZ_R 12U +#define XHC_FSC2POC__PSIZ_WIDTH 5U +#define XHC_FSC2POC__PSIZ_RESETVALUE 0x0U +#define XHC_FSC2POC__reserved_L 11U +#define XHC_FSC2POC__reserved_R 5U +#define XHC_FSC2POC__reserved_WIDTH 7U +#define XHC_FSC2POC__reserved_RESETVALUE 0x0U +#define XHC_FSC2POC__TSIZ_L 4U +#define XHC_FSC2POC__TSIZ_R 0U +#define XHC_FSC2POC__TSIZ_WIDTH 5U +#define XHC_FSC2POC__TSIZ_RESETVALUE 0x0U +#define XHC_FSC2POC__RESERVED_L 27U +#define XHC_FSC2POC__RESERVED_R 23U +#define XHC_FSC2POC_WIDTH 32U +#define XHC_FSC2POC__WIDTH 32U +#define XHC_FSC2POC_ALL_L 31U +#define XHC_FSC2POC_ALL_R 0U +#define XHC_FSC2POC__ALL_L 31U +#define XHC_FSC2POC__ALL_R 0U +#define XHC_FSC2POC_DATAMASK 0xf07dffffU +#define XHC_FSC2POC_RDWRMASK 0x0f820000U +#define XHC_FSC2POC_RESETVALUE 0x00000000U + +#define XHC_FSC2GOC_OFFSET 0xcd8U +#define XHC_FSC2GOC_BASE 0xcd8U +#define XHC_FSC2GOC__NCS_L 31U +#define XHC_FSC2GOC__NCS_R 28U +#define XHC_FSC2GOC__NCS_WIDTH 4U +#define XHC_FSC2GOC__NCS_RESETVALUE 0x0U +#define XHC_FSC2GOC__FSIZ_L 22U +#define XHC_FSC2GOC__FSIZ_R 18U +#define XHC_FSC2GOC__FSIZ_WIDTH 5U +#define XHC_FSC2GOC__FSIZ_RESETVALUE 0x0U +#define XHC_FSC2GOC__PSIZ_L 16U +#define XHC_FSC2GOC__PSIZ_R 12U +#define XHC_FSC2GOC__PSIZ_WIDTH 5U +#define XHC_FSC2GOC__PSIZ_RESETVALUE 0x0U +#define XHC_FSC2GOC__reserved_L 11U +#define XHC_FSC2GOC__reserved_R 5U +#define XHC_FSC2GOC__reserved_WIDTH 7U +#define XHC_FSC2GOC__reserved_RESETVALUE 0x0U +#define XHC_FSC2GOC__TSIZ_L 4U +#define XHC_FSC2GOC__TSIZ_R 0U +#define XHC_FSC2GOC__TSIZ_WIDTH 5U +#define XHC_FSC2GOC__TSIZ_RESETVALUE 0x0U +#define XHC_FSC2GOC__RESERVED_L 27U +#define XHC_FSC2GOC__RESERVED_R 23U +#define XHC_FSC2GOC_WIDTH 32U +#define XHC_FSC2GOC__WIDTH 32U +#define XHC_FSC2GOC_ALL_L 31U +#define XHC_FSC2GOC_ALL_R 0U +#define XHC_FSC2GOC__ALL_L 31U +#define XHC_FSC2GOC__ALL_R 0U +#define XHC_FSC2GOC_DATAMASK 0xf07dffffU +#define XHC_FSC2GOC_RDWRMASK 0x0f820000U +#define XHC_FSC2GOC_RESETVALUE 0x00000000U + +#define XHC_FSC2NOC_OFFSET 0xcdcU +#define XHC_FSC2NOC_BASE 0xcdcU +#define XHC_FSC2NOC__NCS_L 31U +#define XHC_FSC2NOC__NCS_R 28U +#define XHC_FSC2NOC__NCS_WIDTH 4U +#define XHC_FSC2NOC__NCS_RESETVALUE 0x0U +#define XHC_FSC2NOC__FSIZ_L 22U +#define XHC_FSC2NOC__FSIZ_R 18U +#define XHC_FSC2NOC__FSIZ_WIDTH 5U +#define XHC_FSC2NOC__FSIZ_RESETVALUE 0x0U +#define XHC_FSC2NOC__PSIZ_L 16U +#define XHC_FSC2NOC__PSIZ_R 12U +#define XHC_FSC2NOC__PSIZ_WIDTH 5U +#define XHC_FSC2NOC__PSIZ_RESETVALUE 0x0U +#define XHC_FSC2NOC__reserved_L 11U +#define XHC_FSC2NOC__reserved_R 5U +#define XHC_FSC2NOC__reserved_WIDTH 7U +#define XHC_FSC2NOC__reserved_RESETVALUE 0x0U +#define XHC_FSC2NOC__TSIZ_L 4U +#define XHC_FSC2NOC__TSIZ_R 0U +#define XHC_FSC2NOC__TSIZ_WIDTH 5U +#define XHC_FSC2NOC__TSIZ_RESETVALUE 0x0U +#define XHC_FSC2NOC__RESERVED_L 27U +#define XHC_FSC2NOC__RESERVED_R 23U +#define XHC_FSC2NOC_WIDTH 32U +#define XHC_FSC2NOC__WIDTH 32U +#define XHC_FSC2NOC_ALL_L 31U +#define XHC_FSC2NOC_ALL_R 0U +#define XHC_FSC2NOC__ALL_L 31U +#define XHC_FSC2NOC__ALL_R 0U +#define XHC_FSC2NOC_DATAMASK 0xf07dffffU +#define XHC_FSC2NOC_RDWRMASK 0x0f820000U +#define XHC_FSC2NOC_RESETVALUE 0x00000000U + +#define XHC_FSC2AIC_OFFSET 0xce0U +#define XHC_FSC2AIC_BASE 0xce0U +#define XHC_FSC2AIC__FSIZ_L 22U +#define XHC_FSC2AIC__FSIZ_R 18U +#define XHC_FSC2AIC__FSIZ_WIDTH 5U +#define XHC_FSC2AIC__FSIZ_RESETVALUE 0x0U +#define XHC_FSC2AIC__PSIZ_L 16U +#define XHC_FSC2AIC__PSIZ_R 12U +#define XHC_FSC2AIC__PSIZ_WIDTH 5U +#define XHC_FSC2AIC__PSIZ_RESETVALUE 0x0U +#define XHC_FSC2AIC__reserved_L 11U +#define XHC_FSC2AIC__reserved_R 0U +#define XHC_FSC2AIC__reserved_WIDTH 12U +#define XHC_FSC2AIC__reserved_RESETVALUE 0x000U +#define XHC_FSC2AIC__RESERVED_L 31U +#define XHC_FSC2AIC__RESERVED_R 23U +#define XHC_FSC2AIC_WIDTH 23U +#define XHC_FSC2AIC__WIDTH 23U +#define XHC_FSC2AIC_ALL_L 22U +#define XHC_FSC2AIC_ALL_R 0U +#define XHC_FSC2AIC__ALL_L 22U +#define XHC_FSC2AIC__ALL_R 0U +#define XHC_FSC2AIC_DATAMASK 0x007dffffU +#define XHC_FSC2AIC_RDWRMASK 0xff820000U +#define XHC_FSC2AIC_RESETVALUE 0x000000U + +#define XHC_FSC2PIC_OFFSET 0xce4U +#define XHC_FSC2PIC_BASE 0xce4U +#define XHC_FSC2PIC__NCS_L 31U +#define XHC_FSC2PIC__NCS_R 28U +#define XHC_FSC2PIC__NCS_WIDTH 4U +#define XHC_FSC2PIC__NCS_RESETVALUE 0x0U +#define XHC_FSC2PIC__reserved_L 27U +#define XHC_FSC2PIC__reserved_R 5U +#define XHC_FSC2PIC__reserved_WIDTH 23U +#define XHC_FSC2PIC__reserved_RESETVALUE 0x0U +#define XHC_FSC2PIC__TSIZ_L 4U +#define XHC_FSC2PIC__TSIZ_R 0U +#define XHC_FSC2PIC__TSIZ_WIDTH 5U +#define XHC_FSC2PIC__TSIZ_RESETVALUE 0x0U +#define XHC_FSC2PIC_WIDTH 32U +#define XHC_FSC2PIC__WIDTH 32U +#define XHC_FSC2PIC_ALL_L 31U +#define XHC_FSC2PIC_ALL_R 0U +#define XHC_FSC2PIC__ALL_L 31U +#define XHC_FSC2PIC__ALL_R 0U +#define XHC_FSC2PIC_DATAMASK 0xffffffffU +#define XHC_FSC2PIC_RDWRMASK 0x00000000U +#define XHC_FSC2PIC_RESETVALUE 0x00000000U + +#define XHC_FSC2GIC_OFFSET 0xce8U +#define XHC_FSC2GIC_BASE 0xce8U +#define XHC_FSC2GIC__NCS_L 31U +#define XHC_FSC2GIC__NCS_R 28U +#define XHC_FSC2GIC__NCS_WIDTH 4U +#define XHC_FSC2GIC__NCS_RESETVALUE 0x0U +#define XHC_FSC2GIC__reserved_L 27U +#define XHC_FSC2GIC__reserved_R 5U +#define XHC_FSC2GIC__reserved_WIDTH 23U +#define XHC_FSC2GIC__reserved_RESETVALUE 0x0U +#define XHC_FSC2GIC__TSIZ_L 4U +#define XHC_FSC2GIC__TSIZ_R 0U +#define XHC_FSC2GIC__TSIZ_WIDTH 5U +#define XHC_FSC2GIC__TSIZ_RESETVALUE 0x0U +#define XHC_FSC2GIC_WIDTH 32U +#define XHC_FSC2GIC__WIDTH 32U +#define XHC_FSC2GIC_ALL_L 31U +#define XHC_FSC2GIC_ALL_R 0U +#define XHC_FSC2GIC__ALL_L 31U +#define XHC_FSC2GIC__ALL_R 0U +#define XHC_FSC2GIC_DATAMASK 0xffffffffU +#define XHC_FSC2GIC_RDWRMASK 0x00000000U +#define XHC_FSC2GIC_RESETVALUE 0x00000000U + +#define XHC_FSC2NIC_OFFSET 0xcecU +#define XHC_FSC2NIC_BASE 0xcecU +#define XHC_FSC2NIC__NCS_L 31U +#define XHC_FSC2NIC__NCS_R 28U +#define XHC_FSC2NIC__NCS_WIDTH 4U +#define XHC_FSC2NIC__NCS_RESETVALUE 0x0U +#define XHC_FSC2NIC__reserved_L 27U +#define XHC_FSC2NIC__reserved_R 5U +#define XHC_FSC2NIC__reserved_WIDTH 23U +#define XHC_FSC2NIC__reserved_RESETVALUE 0x0U +#define XHC_FSC2NIC__TSIZ_L 4U +#define XHC_FSC2NIC__TSIZ_R 0U +#define XHC_FSC2NIC__TSIZ_WIDTH 5U +#define XHC_FSC2NIC__TSIZ_RESETVALUE 0x0U +#define XHC_FSC2NIC_WIDTH 32U +#define XHC_FSC2NIC__WIDTH 32U +#define XHC_FSC2NIC_ALL_L 31U +#define XHC_FSC2NIC_ALL_R 0U +#define XHC_FSC2NIC__ALL_L 31U +#define XHC_FSC2NIC__ALL_R 0U +#define XHC_FSC2NIC_DATAMASK 0xffffffffU +#define XHC_FSC2NIC_RDWRMASK 0x00000000U +#define XHC_FSC2NIC_RESETVALUE 0x00000000U + +#define XHC_ECHPRT2_OFFSET 0xcf0U +#define XHC_ECHPRT2_BASE 0xcf0U +#define XHC_ECHPRT2__HDP 31U +#define XHC_ECHPRT2__HDP_L 31U +#define XHC_ECHPRT2__HDP_R 31U +#define XHC_ECHPRT2__HDP_WIDTH 1U +#define XHC_ECHPRT2__HDP_RESETVALUE 0x0U +#define XHC_ECHPRT2__FDP 30U +#define XHC_ECHPRT2__FDP_L 30U +#define XHC_ECHPRT2__FDP_R 30U +#define XHC_ECHPRT2__FDP_WIDTH 1U +#define XHC_ECHPRT2__FDP_RESETVALUE 0x0U +#define XHC_ECHPRT2__reserved_L 29U +#define XHC_ECHPRT2__reserved_R 17U +#define XHC_ECHPRT2__reserved_WIDTH 13U +#define XHC_ECHPRT2__reserved_RESETVALUE 0x0U +#define XHC_ECHPRT2__HST 16U +#define XHC_ECHPRT2__HST_L 16U +#define XHC_ECHPRT2__HST_R 16U +#define XHC_ECHPRT2__HST_WIDTH 1U +#define XHC_ECHPRT2__HST_RESETVALUE 0x0U +#define XHC_ECHPRT2__NCP_L 15U +#define XHC_ECHPRT2__NCP_R 8U +#define XHC_ECHPRT2__NCP_WIDTH 8U +#define XHC_ECHPRT2__NCP_RESETVALUE 0x04U +#define XHC_ECHPRT2__CID_L 7U +#define XHC_ECHPRT2__CID_R 0U +#define XHC_ECHPRT2__CID_WIDTH 8U +#define XHC_ECHPRT2__CID_RESETVALUE 0xc8U +#define XHC_ECHPRT2_WIDTH 32U +#define XHC_ECHPRT2__WIDTH 32U +#define XHC_ECHPRT2_ALL_L 31U +#define XHC_ECHPRT2_ALL_R 0U +#define XHC_ECHPRT2__ALL_L 31U +#define XHC_ECHPRT2__ALL_R 0U +#define XHC_ECHPRT2_DATAMASK 0xffffffffU +#define XHC_ECHPRT2_RDWRMASK 0x00000000U +#define XHC_ECHPRT2_RESETVALUE 0x000004c8U + +#define XHC_PRT2HSC_OFFSET 0xcf8U +#define XHC_PRT2HSC_BASE 0xcf8U +#define XHC_PRT2HSC__TMR_L 31U +#define XHC_PRT2HSC__TMR_R 16U +#define XHC_PRT2HSC__TMR_WIDTH 16U +#define XHC_PRT2HSC__TMR_RESETVALUE 0x0000U +#define XHC_PRT2HSC__RSL_L 7U +#define XHC_PRT2HSC__RSL_R 6U +#define XHC_PRT2HSC__RSL_WIDTH 2U +#define XHC_PRT2HSC__RSL_RESETVALUE 0x0U +#define XHC_PRT2HSC__AS_M_L 5U +#define XHC_PRT2HSC__AS_M_R 4U +#define XHC_PRT2HSC__AS_M_WIDTH 2U +#define XHC_PRT2HSC__AS_M_RESETVALUE 0x0U +#define XHC_PRT2HSC__CMD_L 3U +#define XHC_PRT2HSC__CMD_R 2U +#define XHC_PRT2HSC__CMD_WIDTH 2U +#define XHC_PRT2HSC__CMD_RESETVALUE 0x0U +#define XHC_PRT2HSC__reserved 1U +#define XHC_PRT2HSC__reserved_L 1U +#define XHC_PRT2HSC__reserved_R 1U +#define XHC_PRT2HSC__reserved_WIDTH 1U +#define XHC_PRT2HSC__reserved_RESETVALUE 0x0U +#define XHC_PRT2HSC__STB 0U +#define XHC_PRT2HSC__STB_L 0U +#define XHC_PRT2HSC__STB_R 0U +#define XHC_PRT2HSC__STB_WIDTH 1U +#define XHC_PRT2HSC__STB_RESETVALUE 0x0U +#define XHC_PRT2HSC__RESERVED_L 15U +#define XHC_PRT2HSC__RESERVED_R 8U +#define XHC_PRT2HSC_WIDTH 32U +#define XHC_PRT2HSC__WIDTH 32U +#define XHC_PRT2HSC_ALL_L 31U +#define XHC_PRT2HSC_ALL_R 0U +#define XHC_PRT2HSC__ALL_L 31U +#define XHC_PRT2HSC__ALL_R 0U +#define XHC_PRT2HSC_DATAMASK 0xffff00ffU +#define XHC_PRT2HSC_RDWRMASK 0x0000ff00U +#define XHC_PRT2HSC_RESETVALUE 0x00000000U + +#define XHC_PRT2HSR_OFFSET 0xcfcU +#define XHC_PRT2HSR_BASE 0xcfcU +#define XHC_PRT2HSR__RNAK_L 31U +#define XHC_PRT2HSR__RNAK_R 24U +#define XHC_PRT2HSR__RNAK_WIDTH 8U +#define XHC_PRT2HSR__RNAK_RESETVALUE 0x00U +#define XHC_PRT2HSR__HSTX_L 23U +#define XHC_PRT2HSR__HSTX_R 16U +#define XHC_PRT2HSR__HSTX_WIDTH 8U +#define XHC_PRT2HSR__HSTX_RESETVALUE 0x00U +#define XHC_PRT2HSR__HSRX_L 15U +#define XHC_PRT2HSR__HSRX_R 8U +#define XHC_PRT2HSR__HSRX_WIDTH 8U +#define XHC_PRT2HSR__HSRX_RESETVALUE 0x00U +#define XHC_PRT2HSR__SPLT_L 7U +#define XHC_PRT2HSR__SPLT_R 0U +#define XHC_PRT2HSR__SPLT_WIDTH 8U +#define XHC_PRT2HSR__SPLT_RESETVALUE 0x00U +#define XHC_PRT2HSR_WIDTH 32U +#define XHC_PRT2HSR__WIDTH 32U +#define XHC_PRT2HSR_ALL_L 31U +#define XHC_PRT2HSR_ALL_R 0U +#define XHC_PRT2HSR__ALL_L 31U +#define XHC_PRT2HSR__ALL_R 0U +#define XHC_PRT2HSR_DATAMASK 0xffffffffU +#define XHC_PRT2HSR_RDWRMASK 0x00000000U +#define XHC_PRT2HSR_RESETVALUE 0x00000000U + +#define XHC_ECHRH2_OFFSET 0xd00U +#define XHC_ECHRH2_BASE 0xd00U +#define XHC_ECHRH2__MTT 31U +#define XHC_ECHRH2__MTT_L 31U +#define XHC_ECHRH2__MTT_R 31U +#define XHC_ECHRH2__MTT_WIDTH 1U +#define XHC_ECHRH2__MTT_RESETVALUE 0x0U +#define XHC_ECHRH2__RPO_L 30U +#define XHC_ECHRH2__RPO_R 24U +#define XHC_ECHRH2__RPO_WIDTH 7U +#define XHC_ECHRH2__RPO_RESETVALUE 0x0U +#define XHC_ECHRH2__reserved_L 23U +#define XHC_ECHRH2__reserved_R 22U +#define XHC_ECHRH2__reserved_WIDTH 2U +#define XHC_ECHRH2__reserved_RESETVALUE 0x0U +#define XHC_ECHRH2__RPN_L 21U +#define XHC_ECHRH2__RPN_R 20U +#define XHC_ECHRH2__RPN_WIDTH 2U +#define XHC_ECHRH2__RPN_RESETVALUE 0x0U +#define XHC_ECHRH2__DNR_L 19U +#define XHC_ECHRH2__DNR_R 16U +#define XHC_ECHRH2__DNR_WIDTH 4U +#define XHC_ECHRH2__DNR_RESETVALUE 0x0U +#define XHC_ECHRH2__NCP_L 15U +#define XHC_ECHRH2__NCP_R 8U +#define XHC_ECHRH2__NCP_WIDTH 8U +#define XHC_ECHRH2__NCP_RESETVALUE 0x0cU +#define XHC_ECHRH2__CID_L 7U +#define XHC_ECHRH2__CID_R 0U +#define XHC_ECHRH2__CID_WIDTH 8U +#define XHC_ECHRH2__CID_RESETVALUE 0xc9U +#define XHC_ECHRH2_WIDTH 32U +#define XHC_ECHRH2__WIDTH 32U +#define XHC_ECHRH2_ALL_L 31U +#define XHC_ECHRH2_ALL_R 0U +#define XHC_ECHRH2__ALL_L 31U +#define XHC_ECHRH2__ALL_R 0U +#define XHC_ECHRH2_DATAMASK 0xffffffffU +#define XHC_ECHRH2_RDWRMASK 0x00000000U +#define XHC_ECHRH2_RESETVALUE 0x00000cc9U + +#define XHC_RH2DES_OFFSET 0xd04U +#define XHC_RH2DES_BASE 0xd04U +#define XHC_RH2DES__PIS3_L 31U +#define XHC_RH2DES__PIS3_R 30U +#define XHC_RH2DES__PIS3_WIDTH 2U +#define XHC_RH2DES__PIS3_RESETVALUE 0x0U +#define XHC_RH2DES__HIST3 24U +#define XHC_RH2DES__HIST3_L 24U +#define XHC_RH2DES__HIST3_R 24U +#define XHC_RH2DES__HIST3_WIDTH 1U +#define XHC_RH2DES__HIST3_RESETVALUE 0x0U +#define XHC_RH2DES__PIS2_L 23U +#define XHC_RH2DES__PIS2_R 22U +#define XHC_RH2DES__PIS2_WIDTH 2U +#define XHC_RH2DES__PIS2_RESETVALUE 0x0U +#define XHC_RH2DES__HIST2 16U +#define XHC_RH2DES__HIST2_L 16U +#define XHC_RH2DES__HIST2_R 16U +#define XHC_RH2DES__HIST2_WIDTH 1U +#define XHC_RH2DES__HIST2_RESETVALUE 0x0U +#define XHC_RH2DES__PIS1_L 15U +#define XHC_RH2DES__PIS1_R 14U +#define XHC_RH2DES__PIS1_WIDTH 2U +#define XHC_RH2DES__PIS1_RESETVALUE 0x0U +#define XHC_RH2DES__HIST1 8U +#define XHC_RH2DES__HIST1_L 8U +#define XHC_RH2DES__HIST1_R 8U +#define XHC_RH2DES__HIST1_WIDTH 1U +#define XHC_RH2DES__HIST1_RESETVALUE 0x0U +#define XHC_RH2DES__PIS0_L 7U +#define XHC_RH2DES__PIS0_R 6U +#define XHC_RH2DES__PIS0_WIDTH 2U +#define XHC_RH2DES__PIS0_RESETVALUE 0x0U +#define XHC_RH2DES__reserved_L 5U +#define XHC_RH2DES__reserved_R 1U +#define XHC_RH2DES__reserved_WIDTH 5U +#define XHC_RH2DES__reserved_RESETVALUE 0x0U +#define XHC_RH2DES__HIST0 0U +#define XHC_RH2DES__HIST0_L 0U +#define XHC_RH2DES__HIST0_R 0U +#define XHC_RH2DES__HIST0_WIDTH 1U +#define XHC_RH2DES__HIST0_RESETVALUE 0x0U +#define XHC_RH2DES__RESERVED_0_L 29U +#define XHC_RH2DES__RESERVED_0_R 25U +#define XHC_RH2DES__RESERVED_1_L 21U +#define XHC_RH2DES__RESERVED_1_R 17U +#define XHC_RH2DES__RESERVED_2_L 13U +#define XHC_RH2DES__RESERVED_2_R 9U +#define XHC_RH2DES__RESERVED_L 29U +#define XHC_RH2DES__RESERVED_R 25U +#define XHC_RH2DES_WIDTH 32U +#define XHC_RH2DES__WIDTH 32U +#define XHC_RH2DES_ALL_L 31U +#define XHC_RH2DES_ALL_R 0U +#define XHC_RH2DES__ALL_L 31U +#define XHC_RH2DES__ALL_R 0U +#define XHC_RH2DES_DATAMASK 0xc1c1c1ffU +#define XHC_RH2DES_RDWRMASK 0x3e3e3e00U +#define XHC_RH2DES_RESETVALUE 0x00000000U + +#define XHC_RH2HSC0_OFFSET 0xd10U +#define XHC_RH2HSC0_BASE 0xd10U +#define XHC_RH2HSC0__TMR_L 31U +#define XHC_RH2HSC0__TMR_R 16U +#define XHC_RH2HSC0__TMR_WIDTH 16U +#define XHC_RH2HSC0__TMR_RESETVALUE 0x0000U +#define XHC_RH2HSC0__RSL_L 7U +#define XHC_RH2HSC0__RSL_R 6U +#define XHC_RH2HSC0__RSL_WIDTH 2U +#define XHC_RH2HSC0__RSL_RESETVALUE 0x0U +#define XHC_RH2HSC0__AS_M_L 5U +#define XHC_RH2HSC0__AS_M_R 4U +#define XHC_RH2HSC0__AS_M_WIDTH 2U +#define XHC_RH2HSC0__AS_M_RESETVALUE 0x0U +#define XHC_RH2HSC0__CMD_L 3U +#define XHC_RH2HSC0__CMD_R 2U +#define XHC_RH2HSC0__CMD_WIDTH 2U +#define XHC_RH2HSC0__CMD_RESETVALUE 0x0U +#define XHC_RH2HSC0__reserved 1U +#define XHC_RH2HSC0__reserved_L 1U +#define XHC_RH2HSC0__reserved_R 1U +#define XHC_RH2HSC0__reserved_WIDTH 1U +#define XHC_RH2HSC0__reserved_RESETVALUE 0x0U +#define XHC_RH2HSC0__STB 0U +#define XHC_RH2HSC0__STB_L 0U +#define XHC_RH2HSC0__STB_R 0U +#define XHC_RH2HSC0__STB_WIDTH 1U +#define XHC_RH2HSC0__STB_RESETVALUE 0x0U +#define XHC_RH2HSC0__RESERVED_L 15U +#define XHC_RH2HSC0__RESERVED_R 8U +#define XHC_RH2HSC0_WIDTH 32U +#define XHC_RH2HSC0__WIDTH 32U +#define XHC_RH2HSC0_ALL_L 31U +#define XHC_RH2HSC0_ALL_R 0U +#define XHC_RH2HSC0__ALL_L 31U +#define XHC_RH2HSC0__ALL_R 0U +#define XHC_RH2HSC0_DATAMASK 0xffff00ffU +#define XHC_RH2HSC0_RDWRMASK 0x0000ff00U +#define XHC_RH2HSC0_RESETVALUE 0x00000000U + +#define XHC_RH2HSR0_OFFSET 0xd14U +#define XHC_RH2HSR0_BASE 0xd14U +#define XHC_RH2HSR0__C2U_L 31U +#define XHC_RH2HSR0__C2U_R 24U +#define XHC_RH2HSR0__C2U_WIDTH 8U +#define XHC_RH2HSR0__C2U_RESETVALUE 0x00U +#define XHC_RH2HSR0__C1U_L 23U +#define XHC_RH2HSR0__C1U_R 16U +#define XHC_RH2HSR0__C1U_WIDTH 8U +#define XHC_RH2HSR0__C1U_RESETVALUE 0x00U +#define XHC_RH2HSR0__reserved_L 15U +#define XHC_RH2HSR0__reserved_R 8U +#define XHC_RH2HSR0__reserved_WIDTH 8U +#define XHC_RH2HSR0__reserved_RESETVALUE 0x00U +#define XHC_RH2HSR0__RTY_L 7U +#define XHC_RH2HSR0__RTY_R 0U +#define XHC_RH2HSR0__RTY_WIDTH 8U +#define XHC_RH2HSR0__RTY_RESETVALUE 0x00U +#define XHC_RH2HSR0_WIDTH 32U +#define XHC_RH2HSR0__WIDTH 32U +#define XHC_RH2HSR0_ALL_L 31U +#define XHC_RH2HSR0_ALL_R 0U +#define XHC_RH2HSR0__ALL_L 31U +#define XHC_RH2HSR0__ALL_R 0U +#define XHC_RH2HSR0_DATAMASK 0xffffffffU +#define XHC_RH2HSR0_RDWRMASK 0x00000000U +#define XHC_RH2HSR0_RESETVALUE 0x00000000U + +#define XHC_RH2HSC1_OFFSET 0xd18U +#define XHC_RH2HSC1_BASE 0xd18U +#define XHC_RH2HSC1__TMR_L 31U +#define XHC_RH2HSC1__TMR_R 16U +#define XHC_RH2HSC1__TMR_WIDTH 16U +#define XHC_RH2HSC1__TMR_RESETVALUE 0x0000U +#define XHC_RH2HSC1__RSL_L 7U +#define XHC_RH2HSC1__RSL_R 6U +#define XHC_RH2HSC1__RSL_WIDTH 2U +#define XHC_RH2HSC1__RSL_RESETVALUE 0x0U +#define XHC_RH2HSC1__AS_M_L 5U +#define XHC_RH2HSC1__AS_M_R 4U +#define XHC_RH2HSC1__AS_M_WIDTH 2U +#define XHC_RH2HSC1__AS_M_RESETVALUE 0x0U +#define XHC_RH2HSC1__CMD_L 3U +#define XHC_RH2HSC1__CMD_R 2U +#define XHC_RH2HSC1__CMD_WIDTH 2U +#define XHC_RH2HSC1__CMD_RESETVALUE 0x0U +#define XHC_RH2HSC1__reserved 1U +#define XHC_RH2HSC1__reserved_L 1U +#define XHC_RH2HSC1__reserved_R 1U +#define XHC_RH2HSC1__reserved_WIDTH 1U +#define XHC_RH2HSC1__reserved_RESETVALUE 0x0U +#define XHC_RH2HSC1__STB 0U +#define XHC_RH2HSC1__STB_L 0U +#define XHC_RH2HSC1__STB_R 0U +#define XHC_RH2HSC1__STB_WIDTH 1U +#define XHC_RH2HSC1__STB_RESETVALUE 0x0U +#define XHC_RH2HSC1__RESERVED_L 15U +#define XHC_RH2HSC1__RESERVED_R 8U +#define XHC_RH2HSC1_WIDTH 32U +#define XHC_RH2HSC1__WIDTH 32U +#define XHC_RH2HSC1_ALL_L 31U +#define XHC_RH2HSC1_ALL_R 0U +#define XHC_RH2HSC1__ALL_L 31U +#define XHC_RH2HSC1__ALL_R 0U +#define XHC_RH2HSC1_DATAMASK 0xffff00ffU +#define XHC_RH2HSC1_RDWRMASK 0x0000ff00U +#define XHC_RH2HSC1_RESETVALUE 0x00000000U + +#define XHC_RH2HSR1_OFFSET 0xd1cU +#define XHC_RH2HSR1_BASE 0xd1cU +#define XHC_RH2HSR1__C2U_L 31U +#define XHC_RH2HSR1__C2U_R 24U +#define XHC_RH2HSR1__C2U_WIDTH 8U +#define XHC_RH2HSR1__C2U_RESETVALUE 0x00U +#define XHC_RH2HSR1__C1U_L 23U +#define XHC_RH2HSR1__C1U_R 16U +#define XHC_RH2HSR1__C1U_WIDTH 8U +#define XHC_RH2HSR1__C1U_RESETVALUE 0x00U +#define XHC_RH2HSR1__reserved_L 15U +#define XHC_RH2HSR1__reserved_R 8U +#define XHC_RH2HSR1__reserved_WIDTH 8U +#define XHC_RH2HSR1__reserved_RESETVALUE 0x00U +#define XHC_RH2HSR1__RTY_L 7U +#define XHC_RH2HSR1__RTY_R 0U +#define XHC_RH2HSR1__RTY_WIDTH 8U +#define XHC_RH2HSR1__RTY_RESETVALUE 0x00U +#define XHC_RH2HSR1_WIDTH 32U +#define XHC_RH2HSR1__WIDTH 32U +#define XHC_RH2HSR1_ALL_L 31U +#define XHC_RH2HSR1_ALL_R 0U +#define XHC_RH2HSR1__ALL_L 31U +#define XHC_RH2HSR1__ALL_R 0U +#define XHC_RH2HSR1_DATAMASK 0xffffffffU +#define XHC_RH2HSR1_RDWRMASK 0x00000000U +#define XHC_RH2HSR1_RESETVALUE 0x00000000U + +#define XHC_RH2HSC2_OFFSET 0xd20U +#define XHC_RH2HSC2_BASE 0xd20U +#define XHC_RH2HSC2__TMR_L 31U +#define XHC_RH2HSC2__TMR_R 16U +#define XHC_RH2HSC2__TMR_WIDTH 16U +#define XHC_RH2HSC2__TMR_RESETVALUE 0x0000U +#define XHC_RH2HSC2__RSL_L 7U +#define XHC_RH2HSC2__RSL_R 6U +#define XHC_RH2HSC2__RSL_WIDTH 2U +#define XHC_RH2HSC2__RSL_RESETVALUE 0x0U +#define XHC_RH2HSC2__AS_M_L 5U +#define XHC_RH2HSC2__AS_M_R 4U +#define XHC_RH2HSC2__AS_M_WIDTH 2U +#define XHC_RH2HSC2__AS_M_RESETVALUE 0x0U +#define XHC_RH2HSC2__CMD_L 3U +#define XHC_RH2HSC2__CMD_R 2U +#define XHC_RH2HSC2__CMD_WIDTH 2U +#define XHC_RH2HSC2__CMD_RESETVALUE 0x0U +#define XHC_RH2HSC2__reserved 1U +#define XHC_RH2HSC2__reserved_L 1U +#define XHC_RH2HSC2__reserved_R 1U +#define XHC_RH2HSC2__reserved_WIDTH 1U +#define XHC_RH2HSC2__reserved_RESETVALUE 0x0U +#define XHC_RH2HSC2__STB 0U +#define XHC_RH2HSC2__STB_L 0U +#define XHC_RH2HSC2__STB_R 0U +#define XHC_RH2HSC2__STB_WIDTH 1U +#define XHC_RH2HSC2__STB_RESETVALUE 0x0U +#define XHC_RH2HSC2__RESERVED_L 15U +#define XHC_RH2HSC2__RESERVED_R 8U +#define XHC_RH2HSC2_WIDTH 32U +#define XHC_RH2HSC2__WIDTH 32U +#define XHC_RH2HSC2_ALL_L 31U +#define XHC_RH2HSC2_ALL_R 0U +#define XHC_RH2HSC2__ALL_L 31U +#define XHC_RH2HSC2__ALL_R 0U +#define XHC_RH2HSC2_DATAMASK 0xffff00ffU +#define XHC_RH2HSC2_RDWRMASK 0x0000ff00U +#define XHC_RH2HSC2_RESETVALUE 0x00000000U + +#define XHC_RH2HSR2_OFFSET 0xd24U +#define XHC_RH2HSR2_BASE 0xd24U +#define XHC_RH2HSR2__C2U_L 31U +#define XHC_RH2HSR2__C2U_R 24U +#define XHC_RH2HSR2__C2U_WIDTH 8U +#define XHC_RH2HSR2__C2U_RESETVALUE 0x00U +#define XHC_RH2HSR2__C1U_L 23U +#define XHC_RH2HSR2__C1U_R 16U +#define XHC_RH2HSR2__C1U_WIDTH 8U +#define XHC_RH2HSR2__C1U_RESETVALUE 0x00U +#define XHC_RH2HSR2__reserved_L 15U +#define XHC_RH2HSR2__reserved_R 8U +#define XHC_RH2HSR2__reserved_WIDTH 8U +#define XHC_RH2HSR2__reserved_RESETVALUE 0x00U +#define XHC_RH2HSR2__RTY_L 7U +#define XHC_RH2HSR2__RTY_R 0U +#define XHC_RH2HSR2__RTY_WIDTH 8U +#define XHC_RH2HSR2__RTY_RESETVALUE 0x00U +#define XHC_RH2HSR2_WIDTH 32U +#define XHC_RH2HSR2__WIDTH 32U +#define XHC_RH2HSR2_ALL_L 31U +#define XHC_RH2HSR2_ALL_R 0U +#define XHC_RH2HSR2__ALL_L 31U +#define XHC_RH2HSR2__ALL_R 0U +#define XHC_RH2HSR2_DATAMASK 0xffffffffU +#define XHC_RH2HSR2_RDWRMASK 0x00000000U +#define XHC_RH2HSR2_RESETVALUE 0x00000000U + +#define XHC_RH2HSC3_OFFSET 0xd28U +#define XHC_RH2HSC3_BASE 0xd28U +#define XHC_RH2HSC3__TMR_L 31U +#define XHC_RH2HSC3__TMR_R 16U +#define XHC_RH2HSC3__TMR_WIDTH 16U +#define XHC_RH2HSC3__TMR_RESETVALUE 0x0000U +#define XHC_RH2HSC3__RSL_L 7U +#define XHC_RH2HSC3__RSL_R 6U +#define XHC_RH2HSC3__RSL_WIDTH 2U +#define XHC_RH2HSC3__RSL_RESETVALUE 0x0U +#define XHC_RH2HSC3__AS_M_L 5U +#define XHC_RH2HSC3__AS_M_R 4U +#define XHC_RH2HSC3__AS_M_WIDTH 2U +#define XHC_RH2HSC3__AS_M_RESETVALUE 0x0U +#define XHC_RH2HSC3__CMD_L 3U +#define XHC_RH2HSC3__CMD_R 2U +#define XHC_RH2HSC3__CMD_WIDTH 2U +#define XHC_RH2HSC3__CMD_RESETVALUE 0x0U +#define XHC_RH2HSC3__reserved 1U +#define XHC_RH2HSC3__reserved_L 1U +#define XHC_RH2HSC3__reserved_R 1U +#define XHC_RH2HSC3__reserved_WIDTH 1U +#define XHC_RH2HSC3__reserved_RESETVALUE 0x0U +#define XHC_RH2HSC3__STB 0U +#define XHC_RH2HSC3__STB_L 0U +#define XHC_RH2HSC3__STB_R 0U +#define XHC_RH2HSC3__STB_WIDTH 1U +#define XHC_RH2HSC3__STB_RESETVALUE 0x0U +#define XHC_RH2HSC3__RESERVED_L 15U +#define XHC_RH2HSC3__RESERVED_R 8U +#define XHC_RH2HSC3_WIDTH 32U +#define XHC_RH2HSC3__WIDTH 32U +#define XHC_RH2HSC3_ALL_L 31U +#define XHC_RH2HSC3_ALL_R 0U +#define XHC_RH2HSC3__ALL_L 31U +#define XHC_RH2HSC3__ALL_R 0U +#define XHC_RH2HSC3_DATAMASK 0xffff00ffU +#define XHC_RH2HSC3_RDWRMASK 0x0000ff00U +#define XHC_RH2HSC3_RESETVALUE 0x00000000U + +#define XHC_RH2HSR3_OFFSET 0xd2cU +#define XHC_RH2HSR3_BASE 0xd2cU +#define XHC_RH2HSR3__C2U_L 31U +#define XHC_RH2HSR3__C2U_R 24U +#define XHC_RH2HSR3__C2U_WIDTH 8U +#define XHC_RH2HSR3__C2U_RESETVALUE 0x00U +#define XHC_RH2HSR3__C1U_L 23U +#define XHC_RH2HSR3__C1U_R 16U +#define XHC_RH2HSR3__C1U_WIDTH 8U +#define XHC_RH2HSR3__C1U_RESETVALUE 0x00U +#define XHC_RH2HSR3__reserved_L 15U +#define XHC_RH2HSR3__reserved_R 8U +#define XHC_RH2HSR3__reserved_WIDTH 8U +#define XHC_RH2HSR3__reserved_RESETVALUE 0x00U +#define XHC_RH2HSR3__RTY_L 7U +#define XHC_RH2HSR3__RTY_R 0U +#define XHC_RH2HSR3__RTY_WIDTH 8U +#define XHC_RH2HSR3__RTY_RESETVALUE 0x00U +#define XHC_RH2HSR3_WIDTH 32U +#define XHC_RH2HSR3__WIDTH 32U +#define XHC_RH2HSR3_ALL_L 31U +#define XHC_RH2HSR3_ALL_R 0U +#define XHC_RH2HSR3__ALL_L 31U +#define XHC_RH2HSR3__ALL_R 0U +#define XHC_RH2HSR3_DATAMASK 0xffffffffU +#define XHC_RH2HSR3_RDWRMASK 0x00000000U +#define XHC_RH2HSR3_RESETVALUE 0x00000000U + +#define XHC_ECHU2P_OFFSET 0xd30U +#define XHC_ECHU2P_BASE 0xd30U +#define XHC_ECHU2P__reserved_L 31U +#define XHC_ECHU2P__reserved_R 16U +#define XHC_ECHU2P__reserved_WIDTH 16U +#define XHC_ECHU2P__reserved_RESETVALUE 0x0000U +#define XHC_ECHU2P__NCP_L 15U +#define XHC_ECHU2P__NCP_R 8U +#define XHC_ECHU2P__NCP_WIDTH 8U +#define XHC_ECHU2P__NCP_RESETVALUE 0x04U +#define XHC_ECHU2P__CID_L 7U +#define XHC_ECHU2P__CID_R 0U +#define XHC_ECHU2P__CID_WIDTH 8U +#define XHC_ECHU2P__CID_RESETVALUE 0xcaU +#define XHC_ECHU2P_WIDTH 32U +#define XHC_ECHU2P__WIDTH 32U +#define XHC_ECHU2P_ALL_L 31U +#define XHC_ECHU2P_ALL_R 0U +#define XHC_ECHU2P__ALL_L 31U +#define XHC_ECHU2P__ALL_R 0U +#define XHC_ECHU2P_DATAMASK 0xffffffffU +#define XHC_ECHU2P_RDWRMASK 0x00000000U +#define XHC_ECHU2P_RESETVALUE 0x000004caU + +#define XHC_U2PVER_OFFSET 0xd34U +#define XHC_U2PVER_BASE 0xd34U +#define XHC_U2PVER__MAJ_L 31U +#define XHC_U2PVER__MAJ_R 28U +#define XHC_U2PVER__MAJ_WIDTH 4U +#define XHC_U2PVER__MAJ_RESETVALUE 0x0U +#define XHC_U2PVER__MIN_L 27U +#define XHC_U2PVER__MIN_R 24U +#define XHC_U2PVER__MIN_WIDTH 4U +#define XHC_U2PVER__MIN_RESETVALUE 0x0U +#define XHC_U2PVER__RLS_L 23U +#define XHC_U2PVER__RLS_R 20U +#define XHC_U2PVER__RLS_WIDTH 4U +#define XHC_U2PVER__RLS_RESETVALUE 0x0U +#define XHC_U2PVER__reserved_L 19U +#define XHC_U2PVER__reserved_R 0U +#define XHC_U2PVER__reserved_WIDTH 20U +#define XHC_U2PVER__reserved_RESETVALUE 0x00000U +#define XHC_U2PVER_WIDTH 32U +#define XHC_U2PVER__WIDTH 32U +#define XHC_U2PVER_ALL_L 31U +#define XHC_U2PVER_ALL_R 0U +#define XHC_U2PVER__ALL_L 31U +#define XHC_U2PVER__ALL_R 0U +#define XHC_U2PVER_DATAMASK 0xffffffffU +#define XHC_U2PVER_RDWRMASK 0x00000000U +#define XHC_U2PVER_RESETVALUE 0x00000000U + +#define XHC_U2PMGN_OFFSET 0xd38U +#define XHC_U2PMGN_BASE 0xd38U +#define XHC_U2PMGN__MGN_L 31U +#define XHC_U2PMGN__MGN_R 0U +#define XHC_U2PMGN__MGN_WIDTH 32U +#define XHC_U2PMGN__MGN_RESETVALUE 0x4b534b4dU +#define XHC_U2PMGN_WIDTH 32U +#define XHC_U2PMGN__WIDTH 32U +#define XHC_U2PMGN_ALL_L 31U +#define XHC_U2PMGN_ALL_R 0U +#define XHC_U2PMGN__ALL_L 31U +#define XHC_U2PMGN__ALL_R 0U +#define XHC_U2PMGN_DATAMASK 0xffffffffU +#define XHC_U2PMGN_RDWRMASK 0x00000000U +#define XHC_U2PMGN_RESETVALUE 0x4b534b4dU + +#define XHC_ECHRSV2_OFFSET 0xd40U +#define XHC_ECHRSV2_BASE 0xd40U +#define XHC_ECHRSV2__reserved_L 31U +#define XHC_ECHRSV2__reserved_R 16U +#define XHC_ECHRSV2__reserved_WIDTH 16U +#define XHC_ECHRSV2__reserved_RESETVALUE 0x0000U +#define XHC_ECHRSV2__NCP_L 15U +#define XHC_ECHRSV2__NCP_R 8U +#define XHC_ECHRSV2__NCP_WIDTH 8U +#define XHC_ECHRSV2__NCP_RESETVALUE 0x00U +#define XHC_ECHRSV2__CID_L 7U +#define XHC_ECHRSV2__CID_R 0U +#define XHC_ECHRSV2__CID_WIDTH 8U +#define XHC_ECHRSV2__CID_RESETVALUE 0xffU +#define XHC_ECHRSV2_WIDTH 32U +#define XHC_ECHRSV2__WIDTH 32U +#define XHC_ECHRSV2_ALL_L 31U +#define XHC_ECHRSV2_ALL_R 0U +#define XHC_ECHRSV2__ALL_L 31U +#define XHC_ECHRSV2__ALL_R 0U +#define XHC_ECHRSV2_DATAMASK 0xffffffffU +#define XHC_ECHRSV2_RDWRMASK 0x00000000U +#define XHC_ECHRSV2_RESETVALUE 0x000000ffU + +#define XHC_ECHIRA_OFFSET 0xf90U +#define XHC_ECHIRA_BASE 0xf90U +#define XHC_ECHIRA__reserved_L 31U +#define XHC_ECHIRA__reserved_R 16U +#define XHC_ECHIRA__reserved_WIDTH 16U +#define XHC_ECHIRA__reserved_RESETVALUE 0x0000U +#define XHC_ECHIRA__NCP_L 15U +#define XHC_ECHIRA__NCP_R 8U +#define XHC_ECHIRA__NCP_WIDTH 8U +#define XHC_ECHIRA__NCP_RESETVALUE 0x04U +#define XHC_ECHIRA__CID_L 7U +#define XHC_ECHIRA__CID_R 0U +#define XHC_ECHIRA__CID_WIDTH 8U +#define XHC_ECHIRA__CID_RESETVALUE 0xfdU +#define XHC_ECHIRA_WIDTH 32U +#define XHC_ECHIRA__WIDTH 32U +#define XHC_ECHIRA_ALL_L 31U +#define XHC_ECHIRA_ALL_R 0U +#define XHC_ECHIRA__ALL_L 31U +#define XHC_ECHIRA__ALL_R 0U +#define XHC_ECHIRA_DATAMASK 0xffffffffU +#define XHC_ECHIRA_RDWRMASK 0x00000000U +#define XHC_ECHIRA_RESETVALUE 0x000004fdU + +#define XHC_IRAADR_OFFSET 0xf98U +#define XHC_IRAADR_BASE 0xf98U +#define XHC_IRAADR__ADR_L 23U +#define XHC_IRAADR__ADR_R 2U +#define XHC_IRAADR__ADR_WIDTH 22U +#define XHC_IRAADR__ADR_RESETVALUE 0x0U +#define XHC_IRAADR__reserved 1U +#define XHC_IRAADR__reserved_L 1U +#define XHC_IRAADR__reserved_R 1U +#define XHC_IRAADR__reserved_WIDTH 1U +#define XHC_IRAADR__reserved_RESETVALUE 0x0U +#define XHC_IRAADR__MOD 0U +#define XHC_IRAADR__MOD_L 0U +#define XHC_IRAADR__MOD_R 0U +#define XHC_IRAADR__MOD_WIDTH 1U +#define XHC_IRAADR__MOD_RESETVALUE 0x0U +#define XHC_IRAADR__RESERVED_L 31U +#define XHC_IRAADR__RESERVED_R 24U +#define XHC_IRAADR_WIDTH 24U +#define XHC_IRAADR__WIDTH 24U +#define XHC_IRAADR_ALL_L 23U +#define XHC_IRAADR_ALL_R 0U +#define XHC_IRAADR__ALL_L 23U +#define XHC_IRAADR__ALL_R 0U +#define XHC_IRAADR_DATAMASK 0x00ffffffU +#define XHC_IRAADR_RDWRMASK 0xff000000U +#define XHC_IRAADR_RESETVALUE 0x000000U + +#define XHC_IRADAT_OFFSET 0xf9cU +#define XHC_IRADAT_BASE 0xf9cU +#define XHC_IRADAT__DAT_L 31U +#define XHC_IRADAT__DAT_R 0U +#define XHC_IRADAT__DAT_WIDTH 32U +#define XHC_IRADAT__DAT_RESETVALUE 0x00000000U +#define XHC_IRADAT_WIDTH 32U +#define XHC_IRADAT__WIDTH 32U +#define XHC_IRADAT_ALL_L 31U +#define XHC_IRADAT_ALL_R 0U +#define XHC_IRADAT__ALL_L 31U +#define XHC_IRADAT__ALL_R 0U +#define XHC_IRADAT_DATAMASK 0xffffffffU +#define XHC_IRADAT_RDWRMASK 0x00000000U +#define XHC_IRADAT_RESETVALUE 0x00000000U + + +#define XHC_ECHHST_OFFSET 0xfa0U +#define XHC_ECHHST_BASE 0xfa0U +#define XHC_ECHHST__CCC 31U +#define XHC_ECHHST__CCC_L 31U +#define XHC_ECHHST__CCC_R 31U +#define XHC_ECHHST__CCC_WIDTH 1U +#define XHC_ECHHST__CCC_RESETVALUE 0x1U +#define XHC_ECHHST__PME 30U +#define XHC_ECHHST__PME_L 30U +#define XHC_ECHHST__PME_R 30U +#define XHC_ECHHST__PME_WIDTH 1U +#define XHC_ECHHST__PME_RESETVALUE 0x0U +#define XHC_ECHHST__AUX_L 29U +#define XHC_ECHHST__AUX_R 24U +#define XHC_ECHHST__AUX_WIDTH 6U +#define XHC_ECHHST__AUX_RESETVALUE 0x0U +#define XHC_ECHHST__IRA 20U +#define XHC_ECHHST__IRA_L 20U +#define XHC_ECHHST__IRA_R 20U +#define XHC_ECHHST__IRA_WIDTH 1U +#define XHC_ECHHST__IRA_RESETVALUE 0x0U +#define XHC_ECHHST__ULS 19U +#define XHC_ECHHST__ULS_L 19U +#define XHC_ECHHST__ULS_R 19U +#define XHC_ECHHST__ULS_WIDTH 1U +#define XHC_ECHHST__ULS_RESETVALUE 0x0U +#define XHC_ECHHST__reserved 18U +#define XHC_ECHHST__reserved_L 18U +#define XHC_ECHHST__reserved_R 18U +#define XHC_ECHHST__reserved_WIDTH 1U +#define XHC_ECHHST__reserved_RESETVALUE 0x0U +#define XHC_ECHHST__TEDA 17U +#define XHC_ECHHST__TEDA_L 17U +#define XHC_ECHHST__TEDA_R 17U +#define XHC_ECHHST__TEDA_WIDTH 1U +#define XHC_ECHHST__TEDA_RESETVALUE 0x0U +#define XHC_ECHHST__FSW 16U +#define XHC_ECHHST__FSW_L 16U +#define XHC_ECHHST__FSW_R 16U +#define XHC_ECHHST__FSW_WIDTH 1U +#define XHC_ECHHST__FSW_RESETVALUE 0x1U +#define XHC_ECHHST__NCP_L 15U +#define XHC_ECHHST__NCP_R 8U +#define XHC_ECHHST__NCP_WIDTH 8U +#define XHC_ECHHST__NCP_RESETVALUE 0x04U +#define XHC_ECHHST__CID_L 7U +#define XHC_ECHHST__CID_R 0U +#define XHC_ECHHST__CID_WIDTH 8U +#define XHC_ECHHST__CID_RESETVALUE 0xfcU +#define XHC_ECHHST__RESERVED_L 23U +#define XHC_ECHHST__RESERVED_R 21U +#define XHC_ECHHST_WIDTH 32U +#define XHC_ECHHST__WIDTH 32U +#define XHC_ECHHST_ALL_L 31U +#define XHC_ECHHST_ALL_R 0U +#define XHC_ECHHST__ALL_L 31U +#define XHC_ECHHST__ALL_R 0U +#define XHC_ECHHST_DATAMASK 0xff1fffffU +#define XHC_ECHHST_RDWRMASK 0x00e00000U +#define XHC_ECHHST_RESETVALUE 0x800104fcU + +#define XHC_HSTDBG_OFFSET 0xfa4U +#define XHC_HSTDBG_BASE 0xfa4U +#define XHC_HSTDBG__ETE 31U +#define XHC_HSTDBG__ETE_L 31U +#define XHC_HSTDBG__ETE_R 31U +#define XHC_HSTDBG__ETE_WIDTH 1U +#define XHC_HSTDBG__ETE_RESETVALUE 0x0U +#define XHC_HSTDBG__reserved_L 30U +#define XHC_HSTDBG__reserved_R 16U +#define XHC_HSTDBG__reserved_WIDTH 15U +#define XHC_HSTDBG__reserved_RESETVALUE 0x0U +#define XHC_HSTDBG__OUTP_L 15U +#define XHC_HSTDBG__OUTP_R 8U +#define XHC_HSTDBG__OUTP_WIDTH 8U +#define XHC_HSTDBG__OUTP_RESETVALUE 0x00U +#define XHC_HSTDBG__INP_L 7U +#define XHC_HSTDBG__INP_R 0U +#define XHC_HSTDBG__INP_WIDTH 8U +#define XHC_HSTDBG__INP_RESETVALUE 0x00U +#define XHC_HSTDBG_WIDTH 32U +#define XHC_HSTDBG__WIDTH 32U +#define XHC_HSTDBG_ALL_L 31U +#define XHC_HSTDBG_ALL_R 0U +#define XHC_HSTDBG__ALL_L 31U +#define XHC_HSTDBG__ALL_R 0U +#define XHC_HSTDBG_DATAMASK 0xffffffffU +#define XHC_HSTDBG_RDWRMASK 0x00000000U +#define XHC_HSTDBG_RESETVALUE 0x00000000U + +#define XHC_HSTNPL_OFFSET 0xfa8U +#define XHC_HSTNPL_BASE 0xfa8U +#define XHC_HSTNPL__NPL_L 31U +#define XHC_HSTNPL__NPL_R 9U +#define XHC_HSTNPL__NPL_WIDTH 23U +#define XHC_HSTNPL__NPL_RESETVALUE 0x0U +#define XHC_HSTNPL__reserved_L 8U +#define XHC_HSTNPL__reserved_R 0U +#define XHC_HSTNPL__reserved_WIDTH 9U +#define XHC_HSTNPL__reserved_RESETVALUE 0x0U +#define XHC_HSTNPL_WIDTH 32U +#define XHC_HSTNPL__WIDTH 32U +#define XHC_HSTNPL_ALL_L 31U +#define XHC_HSTNPL_ALL_R 0U +#define XHC_HSTNPL__ALL_L 31U +#define XHC_HSTNPL__ALL_R 0U +#define XHC_HSTNPL_DATAMASK 0xffffffffU +#define XHC_HSTNPL_RDWRMASK 0x00000000U +#define XHC_HSTNPL_RESETVALUE 0x00000000U + +#define XHC_HSTNPH_OFFSET 0xfacU +#define XHC_HSTNPH_BASE 0xfacU +#define XHC_HSTNPH__NPH_L 31U +#define XHC_HSTNPH__NPH_R 0U +#define XHC_HSTNPH__NPH_WIDTH 32U +#define XHC_HSTNPH__NPH_RESETVALUE 0x00000000U +#define XHC_HSTNPH_WIDTH 32U +#define XHC_HSTNPH__WIDTH 32U +#define XHC_HSTNPH_ALL_L 31U +#define XHC_HSTNPH_ALL_R 0U +#define XHC_HSTNPH__ALL_L 31U +#define XHC_HSTNPH__ALL_R 0U +#define XHC_HSTNPH_DATAMASK 0xffffffffU +#define XHC_HSTNPH_RDWRMASK 0x00000000U +#define XHC_HSTNPH_RESETVALUE 0x00000000U + +#define XHC_ECHRBV_OFFSET 0xfb0U +#define XHC_ECHRBV_BASE 0xfb0U +#define XHC_ECHRBV__MAJ_L 31U +#define XHC_ECHRBV__MAJ_R 28U +#define XHC_ECHRBV__MAJ_WIDTH 4U +#define XHC_ECHRBV__MAJ_RESETVALUE 0x0U +#define XHC_ECHRBV__MIN_L 27U +#define XHC_ECHRBV__MIN_R 24U +#define XHC_ECHRBV__MIN_WIDTH 4U +#define XHC_ECHRBV__MIN_RESETVALUE 0x0U +#define XHC_ECHRBV__RLS_L 23U +#define XHC_ECHRBV__RLS_R 16U +#define XHC_ECHRBV__RLS_WIDTH 8U +#define XHC_ECHRBV__RLS_RESETVALUE 0x00U +#define XHC_ECHRBV__NCP_L 15U +#define XHC_ECHRBV__NCP_R 8U +#define XHC_ECHRBV__NCP_WIDTH 8U +#define XHC_ECHRBV__NCP_RESETVALUE 0x00U +#define XHC_ECHRBV__CID_L 7U +#define XHC_ECHRBV__CID_R 0U +#define XHC_ECHRBV__CID_WIDTH 8U +#define XHC_ECHRBV__CID_RESETVALUE 0xfeU +#define XHC_ECHRBV_WIDTH 32U +#define XHC_ECHRBV__WIDTH 32U +#define XHC_ECHRBV_ALL_L 31U +#define XHC_ECHRBV_ALL_R 0U +#define XHC_ECHRBV__ALL_L 31U +#define XHC_ECHRBV__ALL_R 0U +#define XHC_ECHRBV_DATAMASK 0xffffffffU +#define XHC_ECHRBV_RDWRMASK 0x00000000U +#define XHC_ECHRBV_RESETVALUE 0x000000feU + +#define XHC_RBVPDT_OFFSET 0xfb4U +#define XHC_RBVPDT_BASE 0xfb4U +#define XHC_RBVPDT__VDR_L 31U +#define XHC_RBVPDT__VDR_R 16U +#define XHC_RBVPDT__VDR_WIDTH 16U +#define XHC_RBVPDT__VDR_RESETVALUE 0x0a5cU +#define XHC_RBVPDT__PDT_L 15U +#define XHC_RBVPDT__PDT_R 0U +#define XHC_RBVPDT__PDT_WIDTH 16U +#define XHC_RBVPDT__PDT_RESETVALUE 0x0000U +#define XHC_RBVPDT_WIDTH 32U +#define XHC_RBVPDT__WIDTH 32U +#define XHC_RBVPDT_ALL_L 31U +#define XHC_RBVPDT_ALL_R 0U +#define XHC_RBVPDT__ALL_L 31U +#define XHC_RBVPDT__ALL_R 0U +#define XHC_RBVPDT_DATAMASK 0xffffffffU +#define XHC_RBVPDT_RDWRMASK 0x00000000U +#define XHC_RBVPDT_RESETVALUE 0x0a5c0000U + +#define XHC_RBVMGN_OFFSET 0xfbcU +#define XHC_RBVMGN_BASE 0xfbcU +#define XHC_RBVMGN__MGN_L 31U +#define XHC_RBVMGN__MGN_R 0U +#define XHC_RBVMGN__MGN_WIDTH 32U +#define XHC_RBVMGN__MGN_RESETVALUE 0x52535354U +#define XHC_RBVMGN_WIDTH 32U +#define XHC_RBVMGN__WIDTH 32U +#define XHC_RBVMGN_ALL_L 31U +#define XHC_RBVMGN_ALL_R 0U +#define XHC_RBVMGN__ALL_L 31U +#define XHC_RBVMGN__ALL_R 0U +#define XHC_RBVMGN_DATAMASK 0xffffffffU +#define XHC_RBVMGN_RDWRMASK 0x00000000U +#define XHC_RBVMGN_RESETVALUE 0x52535354U + +/* PORTSC field defines */ +#define XHC_PORTSC__PS_LINK_STATE_U0 0U +#define XHC_PORTSC__PS_LINK_STATE_U1 1U +#define XHC_PORTSC__PS_LINK_STATE_U2 2U +#define XHC_PORTSC__PS_LINK_STATE_U3 3U +#define XHC_PORTSC__PS_LINK_STATE_DISABLED 4U +#define XHC_PORTSC__PS_LINK_STATE_RX_DETECT 5U +#define XHC_PORTSC__PS_LINK_STATE_INACTIVE 6U +#define XHC_PORTSC__PS_LINK_STATE_POLLING 7U +#define XHC_PORTSC__PS_LINK_STATE_RECOVERY 8U +#define XHC_PORTSC__PS_LINK_STATE_HOT_RESET 9U +#define XHC_PORTSC__PS_LINK_STATE_COMPLIANCE 10U +#define XHC_PORTSC__PS_LINK_STATE_TEST 11U +#define XHC_PORTSC__PS_LINK_STATE_RESUME 15U + +#define XHC_PORTSC__PS_SPEED_UNDEFINED 0U +#define XHC_PORTSC__PS_FS 1U +#define XHC_PORTSC__PS_LS 2U +#define XHC_PORTSC__PS_HS 3U +#define XHC_PORTSC__PS_SS 4U + +/* macros and inline functions */ + +/* write 64bit ptr 'p' to destination 'd' with offset 'v' */ +inline void WRITE64_REG_PTRL(uint32_t r, uint32_t *p) +{ + uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r); + + *ptr = (uint32_t) ((uint64_t) p & (uint64_t) 0xffffffffU); +} + +inline void WRITE64_REG_PTRH(uint32_t r, uint32_t *p) +{ + uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r); + + *ptr = (uint32_t) ((uint64_t) p >> 32U); +} + +#define XHC_REG_RD(addr) mmio_read_32(XHC_BASE + addr) + +#define XHC_REG_WR(addr, val) mmio_write_32(XHC_BASE+addr, val) + +#endif /* USBH_XHCI_REGS_H */ + |