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-rw-r--r--drivers/renesas/rcar/pfc/D3/pfc_init_d3.c667
-rw-r--r--drivers/renesas/rcar/pfc/D3/pfc_init_d3.h12
-rw-r--r--drivers/renesas/rcar/pfc/E3/pfc_init_e3.c651
-rw-r--r--drivers/renesas/rcar/pfc/E3/pfc_init_e3.h12
-rw-r--r--drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c1183
-rw-r--r--drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.h12
-rw-r--r--drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c1216
-rw-r--r--drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.h12
-rw-r--r--drivers/renesas/rcar/pfc/M3/pfc_init_m3.c1311
-rw-r--r--drivers/renesas/rcar/pfc/M3/pfc_init_m3.h12
-rw-r--r--drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c1218
-rw-r--r--drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.h12
-rw-r--r--drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c906
-rw-r--r--drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.h13
-rw-r--r--drivers/renesas/rcar/pfc/pfc.mk69
-rw-r--r--drivers/renesas/rcar/pfc/pfc_init.c199
16 files changed, 7505 insertions, 0 deletions
diff --git a/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
new file mode 100644
index 0000000..aaa3b43
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
@@ -0,0 +1,667 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <lib/mmio.h>
+#include "pfc_init_d3.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+/* PFC */
+#define GPSR0_D15 BIT(15)
+#define GPSR0_D14 BIT(14)
+#define GPSR0_D13 BIT(13)
+#define GPSR0_D12 BIT(12)
+#define GPSR0_D11 BIT(11)
+#define GPSR0_D10 BIT(10)
+#define GPSR0_D9 BIT(9)
+#define GPSR0_D8 BIT(8)
+#define GPSR0_D7 BIT(7)
+#define GPSR0_D6 BIT(6)
+#define GPSR0_D5 BIT(5)
+#define GPSR0_D4 BIT(4)
+#define GPSR0_D3 BIT(3)
+#define GPSR0_D2 BIT(2)
+#define GPSR0_D1 BIT(1)
+#define GPSR0_D0 BIT(0)
+#define GPSR1_CLKOUT BIT(28)
+#define GPSR1_EX_WAIT0_A BIT(27)
+#define GPSR1_WE1 BIT(26)
+#define GPSR1_WE0 BIT(25)
+#define GPSR1_RD_WR BIT(24)
+#define GPSR1_RD BIT(23)
+#define GPSR1_BS BIT(22)
+#define GPSR1_CS1_A26 BIT(21)
+#define GPSR1_CS0 BIT(20)
+#define GPSR1_A19 BIT(19)
+#define GPSR1_A18 BIT(18)
+#define GPSR1_A17 BIT(17)
+#define GPSR1_A16 BIT(16)
+#define GPSR1_A15 BIT(15)
+#define GPSR1_A14 BIT(14)
+#define GPSR1_A13 BIT(13)
+#define GPSR1_A12 BIT(12)
+#define GPSR1_A11 BIT(11)
+#define GPSR1_A10 BIT(10)
+#define GPSR1_A9 BIT(9)
+#define GPSR1_A8 BIT(8)
+#define GPSR1_A7 BIT(7)
+#define GPSR1_A6 BIT(6)
+#define GPSR1_A5 BIT(5)
+#define GPSR1_A4 BIT(4)
+#define GPSR1_A3 BIT(3)
+#define GPSR1_A2 BIT(2)
+#define GPSR1_A1 BIT(1)
+#define GPSR1_A0 BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A BIT(13)
+#define GPSR2_AVB_LINK BIT(12)
+#define GPSR2_AVB_PHY_INT BIT(11)
+#define GPSR2_AVB_MAGIC BIT(10)
+#define GPSR2_AVB_MDC BIT(9)
+#define GPSR2_PWM2_A BIT(8)
+#define GPSR2_PWM1_A BIT(7)
+#define GPSR2_PWM0 BIT(6)
+#define GPSR2_IRQ5 BIT(5)
+#define GPSR2_IRQ4 BIT(4)
+#define GPSR2_IRQ3 BIT(3)
+#define GPSR2_IRQ2 BIT(2)
+#define GPSR2_IRQ1 BIT(1)
+#define GPSR2_IRQ0 BIT(0)
+#define GPSR3_SD1_WP BIT(15)
+#define GPSR3_SD1_CD BIT(14)
+#define GPSR3_SD0_WP BIT(13)
+#define GPSR3_SD0_CD BIT(12)
+#define GPSR3_SD1_DAT3 BIT(11)
+#define GPSR3_SD1_DAT2 BIT(10)
+#define GPSR3_SD1_DAT1 BIT(9)
+#define GPSR3_SD1_DAT0 BIT(8)
+#define GPSR3_SD1_CMD BIT(7)
+#define GPSR3_SD1_CLK BIT(6)
+#define GPSR3_SD0_DAT3 BIT(5)
+#define GPSR3_SD0_DAT2 BIT(4)
+#define GPSR3_SD0_DAT1 BIT(3)
+#define GPSR3_SD0_DAT0 BIT(2)
+#define GPSR3_SD0_CMD BIT(1)
+#define GPSR3_SD0_CLK BIT(0)
+#define GPSR4_SD3_DS BIT(17)
+#define GPSR4_SD3_DAT7 BIT(16)
+#define GPSR4_SD3_DAT6 BIT(15)
+#define GPSR4_SD3_DAT5 BIT(14)
+#define GPSR4_SD3_DAT4 BIT(13)
+#define GPSR4_SD3_DAT3 BIT(12)
+#define GPSR4_SD3_DAT2 BIT(11)
+#define GPSR4_SD3_DAT1 BIT(10)
+#define GPSR4_SD3_DAT0 BIT(9)
+#define GPSR4_SD3_CMD BIT(8)
+#define GPSR4_SD3_CLK BIT(7)
+#define GPSR4_SD2_DS BIT(6)
+#define GPSR4_SD2_DAT3 BIT(5)
+#define GPSR4_SD2_DAT2 BIT(4)
+#define GPSR4_SD2_DAT1 BIT(3)
+#define GPSR4_SD2_DAT0 BIT(2)
+#define GPSR4_SD2_CMD BIT(1)
+#define GPSR4_SD2_CLK BIT(0)
+#define GPSR5_MLB_DAT BIT(25)
+#define GPSR5_MLB_SIG BIT(24)
+#define GPSR5_MLB_CLK BIT(23)
+#define GPSR5_MSIOF0_RXD BIT(22)
+#define GPSR5_MSIOF0_SS2 BIT(21)
+#define GPSR5_MSIOF0_TXD BIT(20)
+#define GPSR5_MSIOF0_SS1 BIT(19)
+#define GPSR5_MSIOF0_SYNC BIT(18)
+#define GPSR5_MSIOF0_SCK BIT(17)
+#define GPSR5_HRTS0 BIT(16)
+#define GPSR5_HCTS0 BIT(15)
+#define GPSR5_HTX0 BIT(14)
+#define GPSR5_HRX0 BIT(13)
+#define GPSR5_HSCK0 BIT(12)
+#define GPSR5_RX2_A BIT(11)
+#define GPSR5_TX2_A BIT(10)
+#define GPSR5_SCK2 BIT(9)
+#define GPSR5_RTS1_TANS BIT(8)
+#define GPSR5_CTS1 BIT(7)
+#define GPSR5_TX1_A BIT(6)
+#define GPSR5_RX1_A BIT(5)
+#define GPSR5_RTS0_TANS BIT(4)
+#define GPSR5_CTS0 BIT(3)
+#define GPSR5_TX0 BIT(2)
+#define GPSR5_RX0 BIT(1)
+#define GPSR5_SCK0 BIT(0)
+#define GPSR6_USB31_OVC BIT(31)
+#define GPSR6_USB31_PWEN BIT(30)
+#define GPSR6_USB30_OVC BIT(29)
+#define GPSR6_USB30_PWEN BIT(28)
+#define GPSR6_USB1_OVC BIT(27)
+#define GPSR6_USB1_PWEN BIT(26)
+#define GPSR6_USB0_OVC BIT(25)
+#define GPSR6_USB0_PWEN BIT(24)
+#define GPSR6_AUDIO_CLKB_B BIT(23)
+#define GPSR6_AUDIO_CLKA_A BIT(22)
+#define GPSR6_SSI_SDATA9_A BIT(21)
+#define GPSR6_SSI_SDATA8 BIT(20)
+#define GPSR6_SSI_SDATA7 BIT(19)
+#define GPSR6_SSI_WS78 BIT(18)
+#define GPSR6_SSI_SCK78 BIT(17)
+#define GPSR6_SSI_SDATA6 BIT(16)
+#define GPSR6_SSI_WS6 BIT(15)
+#define GPSR6_SSI_SCK6 BIT(14)
+#define GPSR6_SSI_SDATA5 BIT(13)
+#define GPSR6_SSI_WS5 BIT(12)
+#define GPSR6_SSI_SCK5 BIT(11)
+#define GPSR6_SSI_SDATA4 BIT(10)
+#define GPSR6_SSI_WS4 BIT(9)
+#define GPSR6_SSI_SCK4 BIT(8)
+#define GPSR6_SSI_SDATA3 BIT(7)
+#define GPSR6_SSI_WS34 BIT(6)
+#define GPSR6_SSI_SCK34 BIT(5)
+#define GPSR6_SSI_SDATA2_A BIT(4)
+#define GPSR6_SSI_SDATA1_A BIT(3)
+#define GPSR6_SSI_SDATA0 BIT(2)
+#define GPSR6_SSI_WS0129 BIT(1)
+#define GPSR6_SSI_SCK0129 BIT(0)
+#define GPSR7_HDMI1_CEC BIT(3)
+#define GPSR7_HDMI0_CEC BIT(2)
+#define GPSR7_AVS2 BIT(1)
+#define GPSR7_AVS1 BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V BIT(29)
+#define POC_SD3_DAT7_33V BIT(28)
+#define POC_SD3_DAT6_33V BIT(27)
+#define POC_SD3_DAT5_33V BIT(26)
+#define POC_SD3_DAT4_33V BIT(25)
+#define POC_SD3_DAT3_33V BIT(24)
+#define POC_SD3_DAT2_33V BIT(23)
+#define POC_SD3_DAT1_33V BIT(22)
+#define POC_SD3_DAT0_33V BIT(21)
+#define POC_SD3_CMD_33V BIT(20)
+#define POC_SD3_CLK_33V BIT(19)
+#define POC_SD2_DS_33V BIT(18)
+#define POC_SD2_DAT3_33V BIT(17)
+#define POC_SD2_DAT2_33V BIT(16)
+#define POC_SD2_DAT1_33V BIT(15)
+#define POC_SD2_DAT0_33V BIT(14)
+#define POC_SD2_CMD_33V BIT(13)
+#define POC_SD2_CLK_33V BIT(12)
+#define POC_SD1_DAT3_33V BIT(11)
+#define POC_SD1_DAT2_33V BIT(10)
+#define POC_SD1_DAT1_33V BIT(9)
+#define POC_SD1_DAT0_33V BIT(8)
+#define POC_SD1_CMD_33V BIT(7)
+#define POC_SD1_CLK_33V BIT(6)
+#define POC_SD0_DAT3_33V BIT(5)
+#define POC_SD0_DAT2_33V BIT(4)
+#define POC_SD0_DAT1_33V BIT(3)
+#define POC_SD0_DAT0_33V BIT(2)
+#define POC_SD0_CMD_33V BIT(1)
+#define POC_SD0_CLK_33V BIT(0)
+
+#define DRVCTRL0_MASK (0xCCCCCCCCU)
+#define DRVCTRL1_MASK (0xCCCCCCC8U)
+#define DRVCTRL2_MASK (0x88888888U)
+#define DRVCTRL3_MASK (0x88888888U)
+#define DRVCTRL4_MASK (0x88888888U)
+#define DRVCTRL5_MASK (0x88888888U)
+#define DRVCTRL6_MASK (0x88888888U)
+#define DRVCTRL7_MASK (0x88888888U)
+#define DRVCTRL8_MASK (0x88888888U)
+#define DRVCTRL9_MASK (0x88888888U)
+#define DRVCTRL10_MASK (0x88888888U)
+#define DRVCTRL11_MASK (0x888888CCU)
+#define DRVCTRL12_MASK (0xCCCFFFCFU)
+#define DRVCTRL13_MASK (0xCC888888U)
+#define DRVCTRL14_MASK (0x88888888U)
+#define DRVCTRL15_MASK (0x88888888U)
+#define DRVCTRL16_MASK (0x88888888U)
+#define DRVCTRL17_MASK (0x88888888U)
+#define DRVCTRL18_MASK (0x88888888U)
+#define DRVCTRL19_MASK (0x88888888U)
+#define DRVCTRL20_MASK (0x88888888U)
+#define DRVCTRL21_MASK (0x88888888U)
+#define DRVCTRL22_MASK (0x88888888U)
+#define DRVCTRL23_MASK (0x88888888U)
+#define DRVCTRL24_MASK (0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ mmio_write_32(PFC_PMMR, ~data);
+ mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_d3(void)
+{
+ /* initialize module select */
+ pfc_reg_write(PFC_MOD_SEL0, 0x00000000U);
+ pfc_reg_write(PFC_MOD_SEL1, 0x00000000U);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0, 0x00000001U);
+ pfc_reg_write(PFC_IPSR1, 0x00000000U);
+ pfc_reg_write(PFC_IPSR2, 0x00000000U);
+ pfc_reg_write(PFC_IPSR3, 0x00000000U);
+ pfc_reg_write(PFC_IPSR4, 0x00002000U);
+ pfc_reg_write(PFC_IPSR5, 0x00000000U);
+ pfc_reg_write(PFC_IPSR6, 0x00000000U);
+ pfc_reg_write(PFC_IPSR7, 0x00000000U);
+ pfc_reg_write(PFC_IPSR8, 0x11003301U);
+ pfc_reg_write(PFC_IPSR9, 0x11111111U);
+ pfc_reg_write(PFC_IPSR10, 0x00020000U);
+ pfc_reg_write(PFC_IPSR11, 0x40001110U);
+ pfc_reg_write(PFC_IPSR12, 0x00000000U);
+ pfc_reg_write(PFC_IPSR13, 0x00000000U);
+
+ /* initialize GPIO/perihperal function select */
+ pfc_reg_write(PFC_GPSR0, 0x0000001FU);
+ pfc_reg_write(PFC_GPSR1, 0x3FFFFFFFU);
+ pfc_reg_write(PFC_GPSR2, 0xFFFFFFFFU);
+ pfc_reg_write(PFC_GPSR3, 0x000003FFU);
+ pfc_reg_write(PFC_GPSR4, 0xFC7F0F7EU);
+ pfc_reg_write(PFC_GPSR5, 0x001BFFFBU);
+ pfc_reg_write(PFC_GPSR6, 0x00003FFFU);
+
+ /* initialize POC control register */
+ pfc_reg_write(PFC_POCCTRL0, 0xC00FFFFFU);
+ pfc_reg_write(PFC_POCCTRL2, 0XFFFFFFFEU);
+ pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
+
+ /* initialize LSI pin pull-up/down control */
+ pfc_reg_write(PFC_PUD0, 0x0047C1A2U);
+ pfc_reg_write(PFC_PUD1, 0x4E13ABFFU);
+ pfc_reg_write(PFC_PUD2, 0xFFFFFFFFU);
+ pfc_reg_write(PFC_PUD3, 0xFF0FFFFFU);
+ pfc_reg_write(PFC_PUD4, 0xE0000000U);
+ pfc_reg_write(PFC_PUD5, 0x60000000U);
+
+ /* initialize LSI pin pull-enable register */
+ pfc_reg_write(PFC_PUEN0, 0x00000000U);
+ pfc_reg_write(PFC_PUEN1, 0x00000000U);
+ pfc_reg_write(PFC_PUEN2, 0x00000000U);
+ pfc_reg_write(PFC_PUEN3, 0x000F008CU);
+ pfc_reg_write(PFC_PUEN4, 0x00000000U);
+ pfc_reg_write(PFC_PUEN5, 0x00000000U);
+
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT0, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+ mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+ mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00802000U);
+ mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL6, 0x00000000U);
+}
diff --git a/drivers/renesas/rcar/pfc/D3/pfc_init_d3.h b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.h
new file mode 100644
index 0000000..b7b1754
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_D3_H
+#define PFC_INIT_D3_H
+
+void pfc_init_d3(void);
+
+#endif /* PFC_INIT_D3_H */
diff --git a/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
new file mode 100644
index 0000000..bd0048e
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
@@ -0,0 +1,651 @@
+/*
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h> /* for uint32_t */
+#include <lib/mmio.h>
+#include "pfc_init_e3.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+/* PFC */
+#define GPSR0_SDA4 BIT(17)
+#define GPSR0_SCL4 BIT(16)
+#define GPSR0_D15 BIT(15)
+#define GPSR0_D14 BIT(14)
+#define GPSR0_D13 BIT(13)
+#define GPSR0_D12 BIT(12)
+#define GPSR0_D11 BIT(11)
+#define GPSR0_D10 BIT(10)
+#define GPSR0_D9 BIT(9)
+#define GPSR0_D8 BIT(8)
+#define GPSR0_D7 BIT(7)
+#define GPSR0_D6 BIT(6)
+#define GPSR0_D5 BIT(5)
+#define GPSR0_D4 BIT(4)
+#define GPSR0_D3 BIT(3)
+#define GPSR0_D2 BIT(2)
+#define GPSR0_D1 BIT(1)
+#define GPSR0_D0 BIT(0)
+#define GPSR1_WE0 BIT(22)
+#define GPSR1_CS0 BIT(21)
+#define GPSR1_CLKOUT BIT(20)
+#define GPSR1_A19 BIT(19)
+#define GPSR1_A18 BIT(18)
+#define GPSR1_A17 BIT(17)
+#define GPSR1_A16 BIT(16)
+#define GPSR1_A15 BIT(15)
+#define GPSR1_A14 BIT(14)
+#define GPSR1_A13 BIT(13)
+#define GPSR1_A12 BIT(12)
+#define GPSR1_A11 BIT(11)
+#define GPSR1_A10 BIT(10)
+#define GPSR1_A9 BIT(9)
+#define GPSR1_A8 BIT(8)
+#define GPSR1_A7 BIT(7)
+#define GPSR1_A6 BIT(6)
+#define GPSR1_A5 BIT(5)
+#define GPSR1_A4 BIT(4)
+#define GPSR1_A3 BIT(3)
+#define GPSR1_A2 BIT(2)
+#define GPSR1_A1 BIT(1)
+#define GPSR1_A0 BIT(0)
+#define GPSR2_BIT27_REVERSED BIT(27)
+#define GPSR2_BIT26_REVERSED BIT(26)
+#define GPSR2_EX_WAIT0 BIT(25)
+#define GPSR2_RD_WR BIT(24)
+#define GPSR2_RD BIT(23)
+#define GPSR2_BS BIT(22)
+#define GPSR2_AVB_PHY_INT BIT(21)
+#define GPSR2_AVB_TXCREFCLK BIT(20)
+#define GPSR2_AVB_RD3 BIT(19)
+#define GPSR2_AVB_RD2 BIT(18)
+#define GPSR2_AVB_RD1 BIT(17)
+#define GPSR2_AVB_RD0 BIT(16)
+#define GPSR2_AVB_RXC BIT(15)
+#define GPSR2_AVB_RX_CTL BIT(14)
+#define GPSR2_RPC_RESET BIT(13)
+#define GPSR2_RPC_RPC_INT BIT(12)
+#define GPSR2_QSPI1_SSL BIT(11)
+#define GPSR2_QSPI1_IO3 BIT(10)
+#define GPSR2_QSPI1_IO2 BIT(9)
+#define GPSR2_QSPI1_MISO_IO1 BIT(8)
+#define GPSR2_QSPI1_MOSI_IO0 BIT(7)
+#define GPSR2_QSPI1_SPCLK BIT(6)
+#define GPSR2_QSPI0_SSL BIT(5)
+#define GPSR2_QSPI0_IO3 BIT(4)
+#define GPSR2_QSPI0_IO2 BIT(3)
+#define GPSR2_QSPI0_MISO_IO1 BIT(2)
+#define GPSR2_QSPI0_MOSI_IO0 BIT(1)
+#define GPSR2_QSPI0_SPCLK BIT(0)
+#define GPSR3_SD1_WP BIT(15)
+#define GPSR3_SD1_CD BIT(14)
+#define GPSR3_SD0_WP BIT(13)
+#define GPSR3_SD0_CD BIT(12)
+#define GPSR3_SD1_DAT3 BIT(11)
+#define GPSR3_SD1_DAT2 BIT(10)
+#define GPSR3_SD1_DAT1 BIT(9)
+#define GPSR3_SD1_DAT0 BIT(8)
+#define GPSR3_SD1_CMD BIT(7)
+#define GPSR3_SD1_CLK BIT(6)
+#define GPSR3_SD0_DAT3 BIT(5)
+#define GPSR3_SD0_DAT2 BIT(4)
+#define GPSR3_SD0_DAT1 BIT(3)
+#define GPSR3_SD0_DAT0 BIT(2)
+#define GPSR3_SD0_CMD BIT(1)
+#define GPSR3_SD0_CLK BIT(0)
+#define GPSR4_SD3_DS BIT(10)
+#define GPSR4_SD3_DAT7 BIT(9)
+#define GPSR4_SD3_DAT6 BIT(8)
+#define GPSR4_SD3_DAT5 BIT(7)
+#define GPSR4_SD3_DAT4 BIT(6)
+#define GPSR4_SD3_DAT3 BIT(5)
+#define GPSR4_SD3_DAT2 BIT(4)
+#define GPSR4_SD3_DAT1 BIT(3)
+#define GPSR4_SD3_DAT0 BIT(2)
+#define GPSR4_SD3_CMD BIT(1)
+#define GPSR4_SD3_CLK BIT(0)
+#define GPSR5_MLB_DAT BIT(19)
+#define GPSR5_MLB_SIG BIT(18)
+#define GPSR5_MLB_CLK BIT(17)
+#define GPSR5_SSI_SDATA9 BIT(16)
+#define GPSR5_MSIOF0_SS2 BIT(15)
+#define GPSR5_MSIOF0_SS1 BIT(14)
+#define GPSR5_MSIOF0_SYNC BIT(13)
+#define GPSR5_MSIOF0_TXD BIT(12)
+#define GPSR5_MSIOF0_RXD BIT(11)
+#define GPSR5_MSIOF0_SCK BIT(10)
+#define GPSR5_RX2_A BIT(9)
+#define GPSR5_TX2_A BIT(8)
+#define GPSR5_SCK2_A BIT(7)
+#define GPSR5_TX1 BIT(6)
+#define GPSR5_RX1 BIT(5)
+#define GPSR5_RTS0_A BIT(4)
+#define GPSR5_CTS0_A BIT(3)
+#define GPSR5_TX0_A BIT(2)
+#define GPSR5_RX0_A BIT(1)
+#define GPSR5_SCK0_A BIT(0)
+#define GPSR6_USB30_PWEN BIT(17)
+#define GPSR6_SSI_SDATA6 BIT(16)
+#define GPSR6_SSI_WS6 BIT(15)
+#define GPSR6_SSI_SCK6 BIT(14)
+#define GPSR6_SSI_SDATA5 BIT(13)
+#define GPSR6_SSI_WS5 BIT(12)
+#define GPSR6_SSI_SCK5 BIT(11)
+#define GPSR6_SSI_SDATA4 BIT(10)
+#define GPSR6_USB30_OVC BIT(9)
+#define GPSR6_AUDIO_CLKA BIT(8)
+#define GPSR6_SSI_SDATA3 BIT(7)
+#define GPSR6_SSI_WS349 BIT(6)
+#define GPSR6_SSI_SCK349 BIT(5)
+#define GPSR6_SSI_SDATA2 BIT(4)
+#define GPSR6_SSI_SDATA1 BIT(3)
+#define GPSR6_SSI_SDATA0 BIT(2)
+#define GPSR6_SSI_WS01239 BIT(1)
+#define GPSR6_SSI_SCK01239 BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define POCCTRL0_MASK (0x0007F000U)
+#define POC_SD3_DS_33V BIT(29)
+#define POC_SD3_DAT7_33V BIT(28)
+#define POC_SD3_DAT6_33V BIT(27)
+#define POC_SD3_DAT5_33V BIT(26)
+#define POC_SD3_DAT4_33V BIT(25)
+#define POC_SD3_DAT3_33V BIT(24)
+#define POC_SD3_DAT2_33V BIT(23)
+#define POC_SD3_DAT1_33V BIT(22)
+#define POC_SD3_DAT0_33V BIT(21)
+#define POC_SD3_CMD_33V BIT(20)
+#define POC_SD3_CLK_33V BIT(19)
+#define POC_SD1_DAT3_33V BIT(11)
+#define POC_SD1_DAT2_33V BIT(10)
+#define POC_SD1_DAT1_33V BIT(9)
+#define POC_SD1_DAT0_33V BIT(8)
+#define POC_SD1_CMD_33V BIT(7)
+#define POC_SD1_CLK_33V BIT(6)
+#define POC_SD0_DAT3_33V BIT(5)
+#define POC_SD0_DAT2_33V BIT(4)
+#define POC_SD0_DAT1_33V BIT(3)
+#define POC_SD0_DAT0_33V BIT(2)
+#define POC_SD0_CMD_33V BIT(1)
+#define POC_SD0_CLK_33V BIT(0)
+
+#define POCCTRL2_MASK (0xFFFFFFFEU)
+#define POC2_VREF_33V BIT(0)
+
+#define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_ADGB_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_ADGB_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 28U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 28U)
+#define MOD_SEL0_FM_A ((uint32_t)0U << 26U)
+#define MOD_SEL0_FM_B ((uint32_t)1U << 26U)
+#define MOD_SEL0_FM_C ((uint32_t)2U << 26U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 25U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 25U)
+#define MOD_SEL0_HSCIF0_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_HSCIF0_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_I2C1_C ((uint32_t)2U << 20U)
+#define MOD_SEL0_I2C1_D ((uint32_t)3U << 20U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_I2C2_C ((uint32_t)2U << 17U)
+#define MOD_SEL0_I2C2_D ((uint32_t)3U << 17U)
+#define MOD_SEL0_I2C2_E ((uint32_t)4U << 17U)
+#define MOD_SEL0_NDFC_A ((uint32_t)0U << 16U)
+#define MOD_SEL0_NDFC_B ((uint32_t)1U << 16U)
+#define MOD_SEL0_PWM0_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_PWM0_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_PWM1_A ((uint32_t)0U << 14U)
+#define MOD_SEL0_PWM1_B ((uint32_t)1U << 14U)
+#define MOD_SEL0_PWM2_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_PWM2_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_PWM2_C ((uint32_t)2U << 12U)
+#define MOD_SEL0_PWM3_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_PWM3_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_PWM3_C ((uint32_t)2U << 10U)
+#define MOD_SEL0_PWM4_A ((uint32_t)0U << 9U)
+#define MOD_SEL0_PWM4_B ((uint32_t)1U << 9U)
+#define MOD_SEL0_PWM5_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_PWM5_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_PWM6_A ((uint32_t)0U << 7U)
+#define MOD_SEL0_PWM6_B ((uint32_t)1U << 7U)
+#define MOD_SEL0_REMOCON_A ((uint32_t)0U << 5U)
+#define MOD_SEL0_REMOCON_B ((uint32_t)1U << 5U)
+#define MOD_SEL0_REMOCON_C ((uint32_t)2U << 5U)
+#define MOD_SEL0_SCIF_A ((uint32_t)0U << 4U)
+#define MOD_SEL0_SCIF_B ((uint32_t)1U << 4U)
+#define MOD_SEL0_SCIF0_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_SCIF0_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_SCIF2_A ((uint32_t)0U << 2U)
+#define MOD_SEL0_SCIF2_B ((uint32_t)1U << 2U)
+#define MOD_SEL0_SPEED_PULSE_IF_A ((uint32_t)0U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_B ((uint32_t)1U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_C ((uint32_t)2U << 0U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 31U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 31U)
+#define MOD_SEL1_SSI2_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_SSI2_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 29U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 29U)
+#define MOD_SEL1_USB20_CH0_A ((uint32_t)0U << 28U)
+#define MOD_SEL1_USB20_CH0_B ((uint32_t)1U << 28U)
+#define MOD_SEL1_DRIF2_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_DRIF2_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_DRIF3_A ((uint32_t)0U << 25U)
+#define MOD_SEL1_DRIF3_B ((uint32_t)1U << 25U)
+#define MOD_SEL1_HSCIF3_A ((uint32_t)0U << 22U)
+#define MOD_SEL1_HSCIF3_B ((uint32_t)1U << 22U)
+#define MOD_SEL1_HSCIF3_C ((uint32_t)2U << 22U)
+#define MOD_SEL1_HSCIF3_D ((uint32_t)3U << 22U)
+#define MOD_SEL1_HSCIF3_E ((uint32_t)4U << 22U)
+#define MOD_SEL1_HSCIF4_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_HSCIF4_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_HSCIF4_C ((uint32_t)2U << 19U)
+#define MOD_SEL1_HSCIF4_D ((uint32_t)3U << 19U)
+#define MOD_SEL1_HSCIF4_E ((uint32_t)4U << 19U)
+#define MOD_SEL1_I2C6_A ((uint32_t)0U << 18U)
+#define MOD_SEL1_I2C6_B ((uint32_t)1U << 18U)
+#define MOD_SEL1_I2C7_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_I2C7_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_MSIOF2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_MSIOF2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_MSIOF3_A ((uint32_t)0U << 15U)
+#define MOD_SEL1_MSIOF3_B ((uint32_t)1U << 15U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF3_C ((uint32_t)2U << 13U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 11U)
+#define MOD_SEL1_SCIF5_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_SCIF5_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_SCIF5_C ((uint32_t)2U << 9U)
+#define MOD_SEL1_VIN4_A ((uint32_t)0U << 8U)
+#define MOD_SEL1_VIN4_B ((uint32_t)1U << 8U)
+#define MOD_SEL1_VIN5_A ((uint32_t)0U << 7U)
+#define MOD_SEL1_VIN5_B ((uint32_t)1U << 7U)
+#define MOD_SEL1_ADGC_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_ADGC_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_ADGC_C ((uint32_t)2U << 5U)
+#define MOD_SEL1_SSI9_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_SSI9_B ((uint32_t)1U << 4U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ mmio_write_32(PFC_PMMR, ~data);
+ mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_e3(void)
+{
+ uint32_t reg;
+
+ /* initialize module select */
+ pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_ADGB_A
+ | MOD_SEL0_DRIF0_A
+ | MOD_SEL0_FM_A
+ | MOD_SEL0_FSO_A
+ | MOD_SEL0_HSCIF0_A
+ | MOD_SEL0_HSCIF1_A
+ | MOD_SEL0_HSCIF2_A
+ | MOD_SEL0_I2C1_A
+ | MOD_SEL0_I2C2_A
+ | MOD_SEL0_NDFC_A
+ | MOD_SEL0_PWM0_A
+ | MOD_SEL0_PWM1_A
+ | MOD_SEL0_PWM2_A
+ | MOD_SEL0_PWM3_A
+ | MOD_SEL0_PWM4_A
+ | MOD_SEL0_PWM5_A
+ | MOD_SEL0_PWM6_A
+ | MOD_SEL0_REMOCON_A
+ | MOD_SEL0_SCIF_A
+ | MOD_SEL0_SCIF0_A
+ | MOD_SEL0_SCIF2_A
+ | MOD_SEL0_SPEED_PULSE_IF_A);
+ pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
+ | MOD_SEL1_SSI2_A
+ | MOD_SEL1_TIMER_TMU_A
+ | MOD_SEL1_USB20_CH0_B
+ | MOD_SEL1_DRIF2_A
+ | MOD_SEL1_DRIF3_A
+ | MOD_SEL1_HSCIF3_A
+ | MOD_SEL1_HSCIF4_A
+ | MOD_SEL1_I2C6_A
+ | MOD_SEL1_I2C7_A
+ | MOD_SEL1_MSIOF2_A
+ | MOD_SEL1_MSIOF3_A
+ | MOD_SEL1_SCIF3_A
+ | MOD_SEL1_SCIF4_A
+ | MOD_SEL1_SCIF5_A
+ | MOD_SEL1_VIN4_A
+ | MOD_SEL1_VIN5_A
+ | MOD_SEL1_ADGC_A
+ | MOD_SEL1_SSI9_A);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) /* QSPI1_MISO/IO1 */
+ | IPSR_24_FUNC(0) /* QSPI1_MOSI/IO0 */
+ | IPSR_20_FUNC(0) /* QSPI1_SPCLK */
+ | IPSR_16_FUNC(0) /* QSPI0_IO3 */
+ | IPSR_12_FUNC(0) /* QSPI0_IO2 */
+ | IPSR_8_FUNC(0) /* QSPI0_MISO/IO1 */
+ | IPSR_4_FUNC(0) /* QSPI0_MOSI/IO0 */
+ | IPSR_0_FUNC(0)); /* QSPI0_SPCLK */
+ pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) /* AVB_RD2 */
+ | IPSR_24_FUNC(0) /* AVB_RD1 */
+ | IPSR_20_FUNC(0) /* AVB_RD0 */
+ | IPSR_16_FUNC(0) /* RPC_RESET# */
+ | IPSR_12_FUNC(0) /* RPC_INT# */
+ | IPSR_8_FUNC(0) /* QSPI1_SSL */
+ | IPSR_4_FUNC(0) /* QSPI1_IO3 */
+ | IPSR_0_FUNC(0)); /* QSPI1_IO2 */
+ pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1) /* IRQ0 */
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(2) /* AVB_LINK */
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0) /* AVB_MDC */
+ | IPSR_4_FUNC(0) /* AVB_MDIO */
+ | IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */
+ pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5) /* DU_HSYNC */
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(5) /* DU_DG4 */
+ | IPSR_8_FUNC(5) /* DU_DOTCLKOUT0 */
+ | IPSR_4_FUNC(5) /* DU_DISP */
+ | IPSR_0_FUNC(1)); /* IRQ1 */
+ pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5) /* DU_DB5 */
+ | IPSR_24_FUNC(5) /* DU_DB4 */
+ | IPSR_20_FUNC(5) /* DU_DB3 */
+ | IPSR_16_FUNC(5) /* DU_DB2 */
+ | IPSR_12_FUNC(5) /* DU_DG6 */
+ | IPSR_8_FUNC(5) /* DU_VSYNC */
+ | IPSR_4_FUNC(5) /* DU_DG5 */
+ | IPSR_0_FUNC(5)); /* DU_DG7 */
+ pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5) /* DU_DR3 */
+ | IPSR_24_FUNC(5) /* DU_DB7 */
+ | IPSR_20_FUNC(5) /* DU_DR2 */
+ | IPSR_16_FUNC(5) /* DU_DR1 */
+ | IPSR_12_FUNC(5) /* DU_DR0 */
+ | IPSR_8_FUNC(5) /* DU_DB1 */
+ | IPSR_4_FUNC(5) /* DU_DB0 */
+ | IPSR_0_FUNC(5)); /* DU_DB6 */
+ pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5) /* DU_DG1 */
+ | IPSR_24_FUNC(5) /* DU_DG0 */
+ | IPSR_20_FUNC(5) /* DU_DR7 */
+ | IPSR_16_FUNC(2) /* IRQ5 */
+ | IPSR_12_FUNC(5) /* DU_DR6 */
+ | IPSR_8_FUNC(5) /* DU_DR5 */
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(5)); /* DU_DR4 */
+ pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) /* SD0_CLK */
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(5) /* DU_DOTCLKIN0 */
+ | IPSR_16_FUNC(5) /* DU_DG3 */
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(5)); /* DU_DG2 */
+ pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) /* SD1_DAT0 */
+ | IPSR_24_FUNC(0) /* SD1_CMD */
+ | IPSR_20_FUNC(0) /* SD1_CLK */
+ | IPSR_16_FUNC(0) /* SD0_DAT3 */
+ | IPSR_12_FUNC(0) /* SD0_DAT2 */
+ | IPSR_8_FUNC(0) /* SD0_DAT1 */
+ | IPSR_4_FUNC(0) /* SD0_DAT0 */
+ | IPSR_0_FUNC(0)); /* SD0_CMD */
+ pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) /* SD3_DAT2 */
+ | IPSR_24_FUNC(0) /* SD3_DAT1 */
+ | IPSR_20_FUNC(0) /* SD3_DAT0 */
+ | IPSR_16_FUNC(0) /* SD3_CMD */
+ | IPSR_12_FUNC(0) /* SD3_CLK */
+ | IPSR_8_FUNC(0) /* SD1_DAT3 */
+ | IPSR_4_FUNC(0) /* SD1_DAT2 */
+ | IPSR_0_FUNC(0)); /* SD1_DAT1 */
+ pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) /* SD0_WP */
+ | IPSR_24_FUNC(0) /* SD0_CD */
+ | IPSR_20_FUNC(0) /* SD3_DS */
+ | IPSR_16_FUNC(0) /* SD3_DAT7 */
+ | IPSR_12_FUNC(0) /* SD3_DAT6 */
+ | IPSR_8_FUNC(0) /* SD3_DAT5 */
+ | IPSR_4_FUNC(0) /* SD3_DAT4 */
+ | IPSR_0_FUNC(0)); /* SD3_DAT3 */
+ pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(2) /* AUDIO_CLKOUT1_A */
+ | IPSR_16_FUNC(2) /* AUDIO_CLKOUT_A */
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0) /* SD1_WP */
+ | IPSR_0_FUNC(0)); /* SD1_CD */
+ pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0) /* RX2_A */
+ | IPSR_8_FUNC(0) /* TX2_A */
+ | IPSR_4_FUNC(2) /* AUDIO_CLKB_A */
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(2) /* AUDIO_CLKC_A */
+ | IPSR_4_FUNC(1) /* HTX2_A */
+ | IPSR_0_FUNC(1)); /* HRX2_A */
+ pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3) /* USB0_PWEN_B */
+ | IPSR_24_FUNC(0) /* SSI_SDATA4 */
+ | IPSR_20_FUNC(0) /* SSI_SDATA3 */
+ | IPSR_16_FUNC(0) /* SSI_WS349 */
+ | IPSR_12_FUNC(0) /* SSI_SCK349 */
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0) /* SSI_SDATA1 */
+ | IPSR_0_FUNC(0)); /* SSI_SDATA0 */
+ pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) /* USB30_OVC */
+ | IPSR_24_FUNC(0) /* USB30_PWEN */
+ | IPSR_20_FUNC(0) /* AUDIO_CLKA */
+ | IPSR_16_FUNC(1) /* HRTS2#_A */
+ | IPSR_12_FUNC(1) /* HCTS2#_A */
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(3)); /* USB0_OVC_B */
+
+ /* initialize GPIO/perihperal function select */
+ pfc_reg_write(PFC_GPSR0, GPSR0_SCL4
+ | GPSR0_D15
+ | GPSR0_D11
+ | GPSR0_D10
+ | GPSR0_D9
+ | GPSR0_D8
+ | GPSR0_D7
+ | GPSR0_D6
+ | GPSR0_D5
+ | GPSR0_D3
+ | GPSR0_D2
+ | GPSR0_D1
+ | GPSR0_D0);
+ pfc_reg_write(PFC_GPSR1, GPSR1_WE0
+ | GPSR1_CS0
+ | GPSR1_A19
+ | GPSR1_A18
+ | GPSR1_A17
+ | GPSR1_A16
+ | GPSR1_A15
+ | GPSR1_A14
+ | GPSR1_A13
+ | GPSR1_A12
+ | GPSR1_A11
+ | GPSR1_A10
+ | GPSR1_A9
+ | GPSR1_A8
+ | GPSR1_A4
+ | GPSR1_A3
+ | GPSR1_A2
+ | GPSR1_A1
+ | GPSR1_A0);
+ pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERSED
+ | GPSR2_BIT26_REVERSED
+ | GPSR2_RD
+ | GPSR2_AVB_PHY_INT
+ | GPSR2_AVB_TXCREFCLK
+ | GPSR2_AVB_RD3
+ | GPSR2_AVB_RD2
+ | GPSR2_AVB_RD1
+ | GPSR2_AVB_RD0
+ | GPSR2_AVB_RXC
+ | GPSR2_AVB_RX_CTL
+ | GPSR2_RPC_RESET
+ | GPSR2_RPC_RPC_INT
+ | GPSR2_QSPI1_SSL
+ | GPSR2_QSPI1_IO3
+ | GPSR2_QSPI1_IO2
+ | GPSR2_QSPI1_MISO_IO1
+ | GPSR2_QSPI1_MOSI_IO0
+ | GPSR2_QSPI1_SPCLK
+ | GPSR2_QSPI0_SSL
+ | GPSR2_QSPI0_IO3
+ | GPSR2_QSPI0_IO2
+ | GPSR2_QSPI0_MISO_IO1
+ | GPSR2_QSPI0_MOSI_IO0
+ | GPSR2_QSPI0_SPCLK);
+ pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
+ | GPSR3_SD1_CD
+ | GPSR3_SD0_WP
+ | GPSR3_SD0_CD
+ | GPSR3_SD1_DAT3
+ | GPSR3_SD1_DAT2
+ | GPSR3_SD1_DAT1
+ | GPSR3_SD1_DAT0
+ | GPSR3_SD1_CMD
+ | GPSR3_SD1_CLK
+ | GPSR3_SD0_DAT3
+ | GPSR3_SD0_DAT2
+ | GPSR3_SD0_DAT1
+ | GPSR3_SD0_DAT0
+ | GPSR3_SD0_CMD
+ | GPSR3_SD0_CLK);
+ pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
+ | GPSR4_SD3_DAT7
+ | GPSR4_SD3_DAT6
+ | GPSR4_SD3_DAT5
+ | GPSR4_SD3_DAT4
+ | GPSR4_SD3_DAT3
+ | GPSR4_SD3_DAT2
+ | GPSR4_SD3_DAT1
+ | GPSR4_SD3_DAT0
+ | GPSR4_SD3_CMD
+ | GPSR4_SD3_CLK);
+ pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
+ | GPSR5_MSIOF0_SS2
+ | GPSR5_MSIOF0_SS1
+ | GPSR5_RX2_A
+ | GPSR5_TX2_A
+ | GPSR5_SCK2_A
+ | GPSR5_RTS0_A
+ | GPSR5_CTS0_A);
+ pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
+ | GPSR6_SSI_SDATA6
+ | GPSR6_SSI_WS6
+ | GPSR6_SSI_WS5
+ | GPSR6_SSI_SCK5
+ | GPSR6_SSI_SDATA4
+ | GPSR6_USB30_OVC
+ | GPSR6_AUDIO_CLKA
+ | GPSR6_SSI_SDATA3
+ | GPSR6_SSI_WS349
+ | GPSR6_SSI_SCK349
+ | GPSR6_SSI_SDATA1
+ | GPSR6_SSI_SDATA0
+ | GPSR6_SSI_WS01239
+ | GPSR6_SSI_SCK01239);
+
+ /* initialize POC control */
+ reg = mmio_read_32(PFC_POCCTRL0);
+ reg = ((reg & POCCTRL0_MASK) | POC_SD1_DAT3_33V
+ | POC_SD1_DAT2_33V
+ | POC_SD1_DAT1_33V
+ | POC_SD1_DAT0_33V
+ | POC_SD1_CMD_33V
+ | POC_SD1_CLK_33V
+ | POC_SD0_DAT3_33V
+ | POC_SD0_DAT2_33V
+ | POC_SD0_DAT1_33V
+ | POC_SD0_DAT0_33V
+ | POC_SD0_CMD_33V
+ | POC_SD0_CLK_33V);
+ pfc_reg_write(PFC_POCCTRL0, reg);
+ reg = mmio_read_32(PFC_POCCTRL2);
+ reg = (reg & POCCTRL2_MASK);
+ pfc_reg_write(PFC_POCCTRL2, reg);
+
+ /* initialize LSI pin pull-up/down control */
+ pfc_reg_write(PFC_PUD0, 0xFDF80000U);
+ pfc_reg_write(PFC_PUD1, 0xCE298464U);
+ pfc_reg_write(PFC_PUD2, 0xA4C380F4U);
+ pfc_reg_write(PFC_PUD3, 0x0000079FU);
+ pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU);
+ pfc_reg_write(PFC_PUD5, 0x40000000U);
+
+ /* initialize LSI pin pull-enable register */
+ pfc_reg_write(PFC_PUEN0, 0xFFF00000U);
+ pfc_reg_write(PFC_PUEN1, 0x00000000U);
+ pfc_reg_write(PFC_PUEN2, 0x00000004U);
+ pfc_reg_write(PFC_PUEN3, 0x00000000U);
+ pfc_reg_write(PFC_PUEN4, 0x07800010U);
+ pfc_reg_write(PFC_PUEN5, 0x00000000U);
+
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00020000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT0, 0x00000010U);
+ mmio_write_32(GPIO_OUTDT1, 0x00100000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT3, 0x00008000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00060000U);
+ mmio_write_32(GPIO_OUTDT6, 0x00000000U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00000010U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x00100020U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x03000000U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x00008000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL5, 0x00060000U);
+ mmio_write_32(GPIO_INOUTSEL6, 0x00004000U);
+}
diff --git a/drivers/renesas/rcar/pfc/E3/pfc_init_e3.h b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.h
new file mode 100644
index 0000000..647a937
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_E3_H
+#define PFC_INIT_E3_H
+
+void pfc_init_e3(void);
+
+#endif /* PFC_INIT_E3_H */
diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
new file mode 100644
index 0000000..effdc76
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
@@ -0,0 +1,1183 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <lib/mmio.h>
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15 BIT(15)
+#define GPSR0_D14 BIT(14)
+#define GPSR0_D13 BIT(13)
+#define GPSR0_D12 BIT(12)
+#define GPSR0_D11 BIT(11)
+#define GPSR0_D10 BIT(10)
+#define GPSR0_D9 BIT(9)
+#define GPSR0_D8 BIT(8)
+#define GPSR0_D7 BIT(7)
+#define GPSR0_D6 BIT(6)
+#define GPSR0_D5 BIT(5)
+#define GPSR0_D4 BIT(4)
+#define GPSR0_D3 BIT(3)
+#define GPSR0_D2 BIT(2)
+#define GPSR0_D1 BIT(1)
+#define GPSR0_D0 BIT(0)
+#define GPSR1_EX_WAIT0_A BIT(27)
+#define GPSR1_WE1 BIT(26)
+#define GPSR1_WE0 BIT(25)
+#define GPSR1_RD_WR BIT(24)
+#define GPSR1_RD BIT(23)
+#define GPSR1_BS BIT(22)
+#define GPSR1_CS1_A26 BIT(21)
+#define GPSR1_CS0 BIT(20)
+#define GPSR1_A19 BIT(19)
+#define GPSR1_A18 BIT(18)
+#define GPSR1_A17 BIT(17)
+#define GPSR1_A16 BIT(16)
+#define GPSR1_A15 BIT(15)
+#define GPSR1_A14 BIT(14)
+#define GPSR1_A13 BIT(13)
+#define GPSR1_A12 BIT(12)
+#define GPSR1_A11 BIT(11)
+#define GPSR1_A10 BIT(10)
+#define GPSR1_A9 BIT(9)
+#define GPSR1_A8 BIT(8)
+#define GPSR1_A7 BIT(7)
+#define GPSR1_A6 BIT(6)
+#define GPSR1_A5 BIT(5)
+#define GPSR1_A4 BIT(4)
+#define GPSR1_A3 BIT(3)
+#define GPSR1_A2 BIT(2)
+#define GPSR1_A1 BIT(1)
+#define GPSR1_A0 BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A BIT(13)
+#define GPSR2_AVB_LINK BIT(12)
+#define GPSR2_AVB_PHY_INT BIT(11)
+#define GPSR2_AVB_MAGIC BIT(10)
+#define GPSR2_AVB_MDC BIT(9)
+#define GPSR2_PWM2_A BIT(8)
+#define GPSR2_PWM1_A BIT(7)
+#define GPSR2_PWM0 BIT(6)
+#define GPSR2_IRQ5 BIT(5)
+#define GPSR2_IRQ4 BIT(4)
+#define GPSR2_IRQ3 BIT(3)
+#define GPSR2_IRQ2 BIT(2)
+#define GPSR2_IRQ1 BIT(1)
+#define GPSR2_IRQ0 BIT(0)
+#define GPSR3_SD1_WP BIT(15)
+#define GPSR3_SD1_CD BIT(14)
+#define GPSR3_SD0_WP BIT(13)
+#define GPSR3_SD0_CD BIT(12)
+#define GPSR3_SD1_DAT3 BIT(11)
+#define GPSR3_SD1_DAT2 BIT(10)
+#define GPSR3_SD1_DAT1 BIT(9)
+#define GPSR3_SD1_DAT0 BIT(8)
+#define GPSR3_SD1_CMD BIT(7)
+#define GPSR3_SD1_CLK BIT(6)
+#define GPSR3_SD0_DAT3 BIT(5)
+#define GPSR3_SD0_DAT2 BIT(4)
+#define GPSR3_SD0_DAT1 BIT(3)
+#define GPSR3_SD0_DAT0 BIT(2)
+#define GPSR3_SD0_CMD BIT(1)
+#define GPSR3_SD0_CLK BIT(0)
+#define GPSR4_SD3_DS BIT(17)
+#define GPSR4_SD3_DAT7 BIT(16)
+#define GPSR4_SD3_DAT6 BIT(15)
+#define GPSR4_SD3_DAT5 BIT(14)
+#define GPSR4_SD3_DAT4 BIT(13)
+#define GPSR4_SD3_DAT3 BIT(12)
+#define GPSR4_SD3_DAT2 BIT(11)
+#define GPSR4_SD3_DAT1 BIT(10)
+#define GPSR4_SD3_DAT0 BIT(9)
+#define GPSR4_SD3_CMD BIT(8)
+#define GPSR4_SD3_CLK BIT(7)
+#define GPSR4_SD2_DS BIT(6)
+#define GPSR4_SD2_DAT3 BIT(5)
+#define GPSR4_SD2_DAT2 BIT(4)
+#define GPSR4_SD2_DAT1 BIT(3)
+#define GPSR4_SD2_DAT0 BIT(2)
+#define GPSR4_SD2_CMD BIT(1)
+#define GPSR4_SD2_CLK BIT(0)
+#define GPSR5_MLB_DAT BIT(25)
+#define GPSR5_MLB_SIG BIT(24)
+#define GPSR5_MLB_CLK BIT(23)
+#define GPSR5_MSIOF0_RXD BIT(22)
+#define GPSR5_MSIOF0_SS2 BIT(21)
+#define GPSR5_MSIOF0_TXD BIT(20)
+#define GPSR5_MSIOF0_SS1 BIT(19)
+#define GPSR5_MSIOF0_SYNC BIT(18)
+#define GPSR5_MSIOF0_SCK BIT(17)
+#define GPSR5_HRTS0 BIT(16)
+#define GPSR5_HCTS0 BIT(15)
+#define GPSR5_HTX0 BIT(14)
+#define GPSR5_HRX0 BIT(13)
+#define GPSR5_HSCK0 BIT(12)
+#define GPSR5_RX2_A BIT(11)
+#define GPSR5_TX2_A BIT(10)
+#define GPSR5_SCK2 BIT(9)
+#define GPSR5_RTS1 BIT(8)
+#define GPSR5_CTS1 BIT(7)
+#define GPSR5_TX1_A BIT(6)
+#define GPSR5_RX1_A BIT(5)
+#define GPSR5_RTS0 BIT(4)
+#define GPSR5_CTS0 BIT(3)
+#define GPSR5_TX0 BIT(2)
+#define GPSR5_RX0 BIT(1)
+#define GPSR5_SCK0 BIT(0)
+#define GPSR6_USB31_OVC BIT(31)
+#define GPSR6_USB31_PWEN BIT(30)
+#define GPSR6_USB30_OVC BIT(29)
+#define GPSR6_USB30_PWEN BIT(28)
+#define GPSR6_USB1_OVC BIT(27)
+#define GPSR6_USB1_PWEN BIT(26)
+#define GPSR6_USB0_OVC BIT(25)
+#define GPSR6_USB0_PWEN BIT(24)
+#define GPSR6_AUDIO_CLKB_B BIT(23)
+#define GPSR6_AUDIO_CLKA_A BIT(22)
+#define GPSR6_SSI_SDATA9_A BIT(21)
+#define GPSR6_SSI_SDATA8 BIT(20)
+#define GPSR6_SSI_SDATA7 BIT(19)
+#define GPSR6_SSI_WS78 BIT(18)
+#define GPSR6_SSI_SCK78 BIT(17)
+#define GPSR6_SSI_SDATA6 BIT(16)
+#define GPSR6_SSI_WS6 BIT(15)
+#define GPSR6_SSI_SCK6 BIT(14)
+#define GPSR6_SSI_SDATA5 BIT(13)
+#define GPSR6_SSI_WS5 BIT(12)
+#define GPSR6_SSI_SCK5 BIT(11)
+#define GPSR6_SSI_SDATA4 BIT(10)
+#define GPSR6_SSI_WS4 BIT(9)
+#define GPSR6_SSI_SCK4 BIT(8)
+#define GPSR6_SSI_SDATA3 BIT(7)
+#define GPSR6_SSI_WS34 BIT(6)
+#define GPSR6_SSI_SCK34 BIT(5)
+#define GPSR6_SSI_SDATA2_A BIT(4)
+#define GPSR6_SSI_SDATA1_A BIT(3)
+#define GPSR6_SSI_SDATA0 BIT(2)
+#define GPSR6_SSI_WS0129 BIT(1)
+#define GPSR6_SSI_SCK0129 BIT(0)
+#define GPSR7_AVS2 BIT(1)
+#define GPSR7_AVS1 BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V BIT(29)
+#define POC_SD3_DAT7_33V BIT(28)
+#define POC_SD3_DAT6_33V BIT(27)
+#define POC_SD3_DAT5_33V BIT(26)
+#define POC_SD3_DAT4_33V BIT(25)
+#define POC_SD3_DAT3_33V BIT(24)
+#define POC_SD3_DAT2_33V BIT(23)
+#define POC_SD3_DAT1_33V BIT(22)
+#define POC_SD3_DAT0_33V BIT(21)
+#define POC_SD3_CMD_33V BIT(20)
+#define POC_SD3_CLK_33V BIT(19)
+#define POC_SD2_DS_33V BIT(18)
+#define POC_SD2_DAT3_33V BIT(17)
+#define POC_SD2_DAT2_33V BIT(16)
+#define POC_SD2_DAT1_33V BIT(15)
+#define POC_SD2_DAT0_33V BIT(14)
+#define POC_SD2_CMD_33V BIT(13)
+#define POC_SD2_CLK_33V BIT(12)
+#define POC_SD1_DAT3_33V BIT(11)
+#define POC_SD1_DAT2_33V BIT(10)
+#define POC_SD1_DAT1_33V BIT(9)
+#define POC_SD1_DAT0_33V BIT(8)
+#define POC_SD1_CMD_33V BIT(7)
+#define POC_SD1_CLK_33V BIT(6)
+#define POC_SD0_DAT3_33V BIT(5)
+#define POC_SD0_DAT2_33V BIT(4)
+#define POC_SD0_DAT1_33V BIT(3)
+#define POC_SD0_DAT0_33V BIT(2)
+#define POC_SD0_CMD_33V BIT(1)
+#define POC_SD0_CLK_33V BIT(0)
+
+#define DRVCTRL0_MASK (0xCCCCCCCCU)
+#define DRVCTRL1_MASK (0xCCCCCCC8U)
+#define DRVCTRL2_MASK (0x88888888U)
+#define DRVCTRL3_MASK (0x88888888U)
+#define DRVCTRL4_MASK (0x88888888U)
+#define DRVCTRL5_MASK (0x88888888U)
+#define DRVCTRL6_MASK (0x88888888U)
+#define DRVCTRL7_MASK (0x88888888U)
+#define DRVCTRL8_MASK (0x88888888U)
+#define DRVCTRL9_MASK (0x88888888U)
+#define DRVCTRL10_MASK (0x88888888U)
+#define DRVCTRL11_MASK (0x888888CCU)
+#define DRVCTRL12_MASK (0xCCCFFFCFU)
+#define DRVCTRL13_MASK (0xCC888888U)
+#define DRVCTRL14_MASK (0x88888888U)
+#define DRVCTRL15_MASK (0x88888888U)
+#define DRVCTRL16_MASK (0x88888888U)
+#define DRVCTRL17_MASK (0x88888888U)
+#define DRVCTRL18_MASK (0x88888888U)
+#define DRVCTRL19_MASK (0x88888888U)
+#define DRVCTRL20_MASK (0x88888888U)
+#define DRVCTRL21_MASK (0x88888888U)
+#define DRVCTRL22_MASK (0x88888888U)
+#define DRVCTRL23_MASK (0x88888888U)
+#define DRVCTRL24_MASK (0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C6_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C6_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_I2C6_C ((uint32_t)2U << 20U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 19U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 19U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 18U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 18U)
+#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 15U)
+#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 15U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 14U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 14U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 13U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_FM_A ((uint32_t)0U << 11U)
+#define MOD_SEL0_FM_B ((uint32_t)1U << 11U)
+#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 9U)
+#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 9U)
+#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 6U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 4U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 4U)
+#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 4U)
+#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A ((uint32_t)0U << 1U)
+#define MOD_SEL0_ADG_B ((uint32_t)1U << 1U)
+#define MOD_SEL0_ADG_C ((uint32_t)2U << 1U)
+#define MOD_SEL0_ADG_D ((uint32_t)3U << 1U)
+#define MOD_SEL0_5LINE_A ((uint32_t)0U << 0U)
+#define MOD_SEL0_5LINE_B ((uint32_t)1U << 0U)
+#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
+#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ mmio_write_32(PFC_PMMR, ~data);
+ mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_h3_v1(void)
+{
+ uint32_t reg;
+
+ /* initialize module select */
+ pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+ | MOD_SEL0_MSIOF2_A
+ | MOD_SEL0_MSIOF1_A
+ | MOD_SEL0_LBSC_A
+ | MOD_SEL0_IEBUS_A
+ | MOD_SEL0_I2C6_A
+ | MOD_SEL0_I2C2_A
+ | MOD_SEL0_I2C1_A
+ | MOD_SEL0_HSCIF4_A
+ | MOD_SEL0_HSCIF3_A
+ | MOD_SEL0_HSCIF2_A
+ | MOD_SEL0_HSCIF1_A
+ | MOD_SEL0_FM_A
+ | MOD_SEL0_ETHERAVB_A
+ | MOD_SEL0_DRIF3_A
+ | MOD_SEL0_DRIF2_A
+ | MOD_SEL0_DRIF1_A
+ | MOD_SEL0_DRIF0_A
+ | MOD_SEL0_CANFD0_A
+ | MOD_SEL0_ADG_A
+ | MOD_SEL0_5LINE_A);
+ pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+ | MOD_SEL1_TSIF0_A
+ | MOD_SEL1_TIMER_TMU_A
+ | MOD_SEL1_SSP1_1_A
+ | MOD_SEL1_SSP1_0_A
+ | MOD_SEL1_SSI_A
+ | MOD_SEL1_SPEED_PULSE_IF_A
+ | MOD_SEL1_SIMCARD_A
+ | MOD_SEL1_SDHI2_A
+ | MOD_SEL1_SCIF4_A
+ | MOD_SEL1_SCIF3_A
+ | MOD_SEL1_SCIF2_A
+ | MOD_SEL1_SCIF1_A
+ | MOD_SEL1_SCIF_A
+ | MOD_SEL1_REMOCON_A
+ | MOD_SEL1_RCAN0_A
+ | MOD_SEL1_PWM6_A
+ | MOD_SEL1_PWM5_A
+ | MOD_SEL1_PWM4_A
+ | MOD_SEL1_PWM3_A
+ | MOD_SEL1_PWM2_A
+ | MOD_SEL1_PWM1_A);
+ pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+ | MOD_SEL2_I2C_3_A
+ | MOD_SEL2_I2C_0_A
+ | MOD_SEL2_VIN4_A);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(3)
+ | IPSR_8_FUNC(3)
+ | IPSR_4_FUNC(3)
+ | IPSR_0_FUNC(3));
+ pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+ | IPSR_24_FUNC(1)
+ | IPSR_20_FUNC(1)
+ | IPSR_16_FUNC(1)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(4)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(1)
+ | IPSR_0_FUNC(1));
+ pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(4)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(8)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(3)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(3)
+ | IPSR_0_FUNC(8));
+ pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(1)
+ | IPSR_0_FUNC(1));
+ pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(1)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR17, IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ /* initialize GPIO/perihperal function select */
+ pfc_reg_write(PFC_GPSR0, GPSR0_D15
+ | GPSR0_D14
+ | GPSR0_D13
+ | GPSR0_D12
+ | GPSR0_D11
+ | GPSR0_D10
+ | GPSR0_D9
+ | GPSR0_D8);
+ pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
+ | GPSR1_A19
+ | GPSR1_A18
+ | GPSR1_A17
+ | GPSR1_A16
+ | GPSR1_A15
+ | GPSR1_A14
+ | GPSR1_A13
+ | GPSR1_A12
+ | GPSR1_A7
+ | GPSR1_A6
+ | GPSR1_A5
+ | GPSR1_A4
+ | GPSR1_A3
+ | GPSR1_A2
+ | GPSR1_A1
+ | GPSR1_A0);
+ pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+ | GPSR2_AVB_AVTP_MATCH_A
+ | GPSR2_AVB_LINK
+ | GPSR2_AVB_PHY_INT
+ | GPSR2_AVB_MDC
+ | GPSR2_PWM2_A
+ | GPSR2_PWM1_A
+ | GPSR2_IRQ5
+ | GPSR2_IRQ4
+ | GPSR2_IRQ3
+ | GPSR2_IRQ2
+ | GPSR2_IRQ1
+ | GPSR2_IRQ0);
+ pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+ | GPSR3_SD0_CD
+ | GPSR3_SD1_DAT3
+ | GPSR3_SD1_DAT2
+ | GPSR3_SD1_DAT1
+ | GPSR3_SD1_DAT0
+ | GPSR3_SD0_DAT3
+ | GPSR3_SD0_DAT2
+ | GPSR3_SD0_DAT1
+ | GPSR3_SD0_DAT0
+ | GPSR3_SD0_CMD
+ | GPSR3_SD0_CLK);
+ pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+ | GPSR4_SD3_DAT6
+ | GPSR4_SD3_DAT3
+ | GPSR4_SD3_DAT2
+ | GPSR4_SD3_DAT1
+ | GPSR4_SD3_DAT0
+ | GPSR4_SD3_CMD
+ | GPSR4_SD3_CLK
+ | GPSR4_SD2_DS
+ | GPSR4_SD2_DAT3
+ | GPSR4_SD2_DAT2
+ | GPSR4_SD2_DAT1
+ | GPSR4_SD2_DAT0
+ | GPSR4_SD2_CMD
+ | GPSR4_SD2_CLK);
+ pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+ | GPSR5_MSIOF0_SS1
+ | GPSR5_MSIOF0_SYNC
+ | GPSR5_HRTS0
+ | GPSR5_HCTS0
+ | GPSR5_HTX0
+ | GPSR5_HRX0
+ | GPSR5_HSCK0
+ | GPSR5_RX2_A
+ | GPSR5_TX2_A
+ | GPSR5_SCK2
+ | GPSR5_RTS1
+ | GPSR5_CTS1
+ | GPSR5_TX1_A
+ | GPSR5_RX1_A
+ | GPSR5_RTS0
+ | GPSR5_SCK0);
+ pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+ | GPSR6_USB30_PWEN
+ | GPSR6_USB1_OVC
+ | GPSR6_USB1_PWEN
+ | GPSR6_USB0_OVC
+ | GPSR6_USB0_PWEN
+ | GPSR6_AUDIO_CLKB_B
+ | GPSR6_AUDIO_CLKA_A
+ | GPSR6_SSI_SDATA8
+ | GPSR6_SSI_SDATA7
+ | GPSR6_SSI_WS78
+ | GPSR6_SSI_SCK78
+ | GPSR6_SSI_WS6
+ | GPSR6_SSI_SCK6
+ | GPSR6_SSI_SDATA4
+ | GPSR6_SSI_WS4
+ | GPSR6_SSI_SCK4
+ | GPSR6_SSI_SDATA1_A
+ | GPSR6_SSI_SDATA0
+ | GPSR6_SSI_WS0129
+ | GPSR6_SSI_SCK0129);
+ pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
+ | GPSR7_AVS1);
+
+ /* initialize POC control register */
+ pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+ | POC_SD3_DAT7_33V
+ | POC_SD3_DAT6_33V
+ | POC_SD3_DAT5_33V
+ | POC_SD3_DAT4_33V
+ | POC_SD3_DAT3_33V
+ | POC_SD3_DAT2_33V
+ | POC_SD3_DAT1_33V
+ | POC_SD3_DAT0_33V
+ | POC_SD3_CMD_33V
+ | POC_SD3_CLK_33V
+ | POC_SD0_DAT3_33V
+ | POC_SD0_DAT2_33V
+ | POC_SD0_DAT1_33V
+ | POC_SD0_DAT0_33V
+ | POC_SD0_CMD_33V
+ | POC_SD0_CLK_33V);
+
+ /* initialize DRV control register */
+ reg = mmio_read_32(PFC_DRVCTRL0);
+ reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+ | DRVCTRL0_QSPI0_MOSI_IO0(3)
+ | DRVCTRL0_QSPI0_MISO_IO1(3)
+ | DRVCTRL0_QSPI0_IO2(3)
+ | DRVCTRL0_QSPI0_IO3(3)
+ | DRVCTRL0_QSPI0_SSL(3)
+ | DRVCTRL0_QSPI1_SPCLK(3)
+ | DRVCTRL0_QSPI1_MOSI_IO0(3));
+ pfc_reg_write(PFC_DRVCTRL0, reg);
+ reg = mmio_read_32(PFC_DRVCTRL1);
+ reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+ | DRVCTRL1_QSPI1_IO2(3)
+ | DRVCTRL1_QSPI1_IO3(3)
+ | DRVCTRL1_QSPI1_SS(3)
+ | DRVCTRL1_RPC_INT(3)
+ | DRVCTRL1_RPC_WP(3)
+ | DRVCTRL1_RPC_RESET(3)
+ | DRVCTRL1_AVB_RX_CTL(7));
+ pfc_reg_write(PFC_DRVCTRL1, reg);
+ reg = mmio_read_32(PFC_DRVCTRL2);
+ reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+ | DRVCTRL2_AVB_RD0(7)
+ | DRVCTRL2_AVB_RD1(7)
+ | DRVCTRL2_AVB_RD2(7)
+ | DRVCTRL2_AVB_RD3(7)
+ | DRVCTRL2_AVB_TX_CTL(3)
+ | DRVCTRL2_AVB_TXC(3)
+ | DRVCTRL2_AVB_TD0(3));
+ pfc_reg_write(PFC_DRVCTRL2, reg);
+ reg = mmio_read_32(PFC_DRVCTRL3);
+ reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+ | DRVCTRL3_AVB_TD2(3)
+ | DRVCTRL3_AVB_TD3(3)
+ | DRVCTRL3_AVB_TXCREFCLK(7)
+ | DRVCTRL3_AVB_MDIO(7)
+ | DRVCTRL3_AVB_MDC(7)
+ | DRVCTRL3_AVB_MAGIC(7)
+ | DRVCTRL3_AVB_PHY_INT(7));
+ pfc_reg_write(PFC_DRVCTRL3, reg);
+ reg = mmio_read_32(PFC_DRVCTRL4);
+ reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+ | DRVCTRL4_AVB_AVTP_MATCH(7)
+ | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+ | DRVCTRL4_IRQ0(7)
+ | DRVCTRL4_IRQ1(7)
+ | DRVCTRL4_IRQ2(7)
+ | DRVCTRL4_IRQ3(7)
+ | DRVCTRL4_IRQ4(7));
+ pfc_reg_write(PFC_DRVCTRL4, reg);
+ reg = mmio_read_32(PFC_DRVCTRL5);
+ reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+ | DRVCTRL5_PWM0(7)
+ | DRVCTRL5_PWM1(7)
+ | DRVCTRL5_PWM2(7)
+ | DRVCTRL5_A0(3)
+ | DRVCTRL5_A1(3)
+ | DRVCTRL5_A2(3)
+ | DRVCTRL5_A3(3));
+ pfc_reg_write(PFC_DRVCTRL5, reg);
+ reg = mmio_read_32(PFC_DRVCTRL6);
+ reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+ | DRVCTRL6_A5(3)
+ | DRVCTRL6_A6(3)
+ | DRVCTRL6_A7(3)
+ | DRVCTRL6_A8(7)
+ | DRVCTRL6_A9(7)
+ | DRVCTRL6_A10(7)
+ | DRVCTRL6_A11(7));
+ pfc_reg_write(PFC_DRVCTRL6, reg);
+ reg = mmio_read_32(PFC_DRVCTRL7);
+ reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+ | DRVCTRL7_A13(3)
+ | DRVCTRL7_A14(3)
+ | DRVCTRL7_A15(3)
+ | DRVCTRL7_A16(3)
+ | DRVCTRL7_A17(3)
+ | DRVCTRL7_A18(3)
+ | DRVCTRL7_A19(3));
+ pfc_reg_write(PFC_DRVCTRL7, reg);
+ reg = mmio_read_32(PFC_DRVCTRL8);
+ reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+ | DRVCTRL8_CS0(7)
+ | DRVCTRL8_CS1_A2(7)
+ | DRVCTRL8_BS(7)
+ | DRVCTRL8_RD(7)
+ | DRVCTRL8_RD_W(7)
+ | DRVCTRL8_WE0(7)
+ | DRVCTRL8_WE1(7));
+ pfc_reg_write(PFC_DRVCTRL8, reg);
+ reg = mmio_read_32(PFC_DRVCTRL9);
+ reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+ | DRVCTRL9_PRESETOU(7)
+ | DRVCTRL9_D0(7)
+ | DRVCTRL9_D1(7)
+ | DRVCTRL9_D2(7)
+ | DRVCTRL9_D3(7)
+ | DRVCTRL9_D4(7)
+ | DRVCTRL9_D5(7));
+ pfc_reg_write(PFC_DRVCTRL9, reg);
+ reg = mmio_read_32(PFC_DRVCTRL10);
+ reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+ | DRVCTRL10_D7(7)
+ | DRVCTRL10_D8(3)
+ | DRVCTRL10_D9(3)
+ | DRVCTRL10_D10(3)
+ | DRVCTRL10_D11(3)
+ | DRVCTRL10_D12(3)
+ | DRVCTRL10_D13(3));
+ pfc_reg_write(PFC_DRVCTRL10, reg);
+ reg = mmio_read_32(PFC_DRVCTRL11);
+ reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+ | DRVCTRL11_D15(3)
+ | DRVCTRL11_AVS1(7)
+ | DRVCTRL11_AVS2(7)
+ | DRVCTRL11_GP7_02(7)
+ | DRVCTRL11_GP7_03(7)
+ | DRVCTRL11_DU_DOTCLKIN0(3)
+ | DRVCTRL11_DU_DOTCLKIN1(3));
+ pfc_reg_write(PFC_DRVCTRL11, reg);
+ reg = mmio_read_32(PFC_DRVCTRL12);
+ reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+ | DRVCTRL12_DU_DOTCLKIN3(3)
+ | DRVCTRL12_DU_FSCLKST(3)
+ | DRVCTRL12_DU_TMS(3));
+ pfc_reg_write(PFC_DRVCTRL12, reg);
+ reg = mmio_read_32(PFC_DRVCTRL13);
+ reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+ | DRVCTRL13_ASEBRK(3)
+ | DRVCTRL13_SD0_CLK(2)
+ | DRVCTRL13_SD0_CMD(2)
+ | DRVCTRL13_SD0_DAT0(2)
+ | DRVCTRL13_SD0_DAT1(2)
+ | DRVCTRL13_SD0_DAT2(2)
+ | DRVCTRL13_SD0_DAT3(2));
+ pfc_reg_write(PFC_DRVCTRL13, reg);
+ reg = mmio_read_32(PFC_DRVCTRL14);
+ reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+ | DRVCTRL14_SD1_CMD(7)
+ | DRVCTRL14_SD1_DAT0(5)
+ | DRVCTRL14_SD1_DAT1(5)
+ | DRVCTRL14_SD1_DAT2(5)
+ | DRVCTRL14_SD1_DAT3(5)
+ | DRVCTRL14_SD2_CLK(5)
+ | DRVCTRL14_SD2_CMD(5));
+ pfc_reg_write(PFC_DRVCTRL14, reg);
+ reg = mmio_read_32(PFC_DRVCTRL15);
+ reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+ | DRVCTRL15_SD2_DAT1(5)
+ | DRVCTRL15_SD2_DAT2(5)
+ | DRVCTRL15_SD2_DAT3(5)
+ | DRVCTRL15_SD2_DS(5)
+ | DRVCTRL15_SD3_CLK(2)
+ | DRVCTRL15_SD3_CMD(2)
+ | DRVCTRL15_SD3_DAT0(2));
+ pfc_reg_write(PFC_DRVCTRL15, reg);
+ reg = mmio_read_32(PFC_DRVCTRL16);
+ reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(2)
+ | DRVCTRL16_SD3_DAT2(2)
+ | DRVCTRL16_SD3_DAT3(2)
+ | DRVCTRL16_SD3_DAT4(7)
+ | DRVCTRL16_SD3_DAT5(7)
+ | DRVCTRL16_SD3_DAT6(7)
+ | DRVCTRL16_SD3_DAT7(7)
+ | DRVCTRL16_SD3_DS(7));
+ pfc_reg_write(PFC_DRVCTRL16, reg);
+ reg = mmio_read_32(PFC_DRVCTRL17);
+ reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+ | DRVCTRL17_SD0_WP(7)
+ | DRVCTRL17_SD1_CD(7)
+ | DRVCTRL17_SD1_WP(7)
+ | DRVCTRL17_SCK0(7)
+ | DRVCTRL17_RX0(7)
+ | DRVCTRL17_TX0(7)
+ | DRVCTRL17_CTS0(7));
+ pfc_reg_write(PFC_DRVCTRL17, reg);
+ reg = mmio_read_32(PFC_DRVCTRL18);
+ reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+ | DRVCTRL18_RX1(7)
+ | DRVCTRL18_TX1(7)
+ | DRVCTRL18_CTS1(7)
+ | DRVCTRL18_RTS1_TANS(7)
+ | DRVCTRL18_SCK2(7)
+ | DRVCTRL18_TX2(7)
+ | DRVCTRL18_RX2(7));
+ pfc_reg_write(PFC_DRVCTRL18, reg);
+ reg = mmio_read_32(PFC_DRVCTRL19);
+ reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+ | DRVCTRL19_HRX0(7)
+ | DRVCTRL19_HTX0(7)
+ | DRVCTRL19_HCTS0(7)
+ | DRVCTRL19_HRTS0(7)
+ | DRVCTRL19_MSIOF0_SCK(7)
+ | DRVCTRL19_MSIOF0_SYNC(7)
+ | DRVCTRL19_MSIOF0_SS1(7));
+ pfc_reg_write(PFC_DRVCTRL19, reg);
+ reg = mmio_read_32(PFC_DRVCTRL20);
+ reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+ | DRVCTRL20_MSIOF0_SS2(7)
+ | DRVCTRL20_MSIOF0_RXD(7)
+ | DRVCTRL20_MLB_CLK(7)
+ | DRVCTRL20_MLB_SIG(7)
+ | DRVCTRL20_MLB_DAT(7)
+ | DRVCTRL20_MLB_REF(7)
+ | DRVCTRL20_SSI_SCK0129(7));
+ pfc_reg_write(PFC_DRVCTRL20, reg);
+ reg = mmio_read_32(PFC_DRVCTRL21);
+ reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+ | DRVCTRL21_SSI_SDATA0(7)
+ | DRVCTRL21_SSI_SDATA1(7)
+ | DRVCTRL21_SSI_SDATA2(7)
+ | DRVCTRL21_SSI_SCK34(7)
+ | DRVCTRL21_SSI_WS34(7)
+ | DRVCTRL21_SSI_SDATA3(7)
+ | DRVCTRL21_SSI_SCK4(7));
+ pfc_reg_write(PFC_DRVCTRL21, reg);
+ reg = mmio_read_32(PFC_DRVCTRL22);
+ reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+ | DRVCTRL22_SSI_SDATA4(7)
+ | DRVCTRL22_SSI_SCK5(7)
+ | DRVCTRL22_SSI_WS5(7)
+ | DRVCTRL22_SSI_SDATA5(7)
+ | DRVCTRL22_SSI_SCK6(7)
+ | DRVCTRL22_SSI_WS6(7)
+ | DRVCTRL22_SSI_SDATA6(7));
+ pfc_reg_write(PFC_DRVCTRL22, reg);
+ reg = mmio_read_32(PFC_DRVCTRL23);
+ reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+ | DRVCTRL23_SSI_WS78(7)
+ | DRVCTRL23_SSI_SDATA7(7)
+ | DRVCTRL23_SSI_SDATA8(7)
+ | DRVCTRL23_SSI_SDATA9(7)
+ | DRVCTRL23_AUDIO_CLKA(7)
+ | DRVCTRL23_AUDIO_CLKB(7)
+ | DRVCTRL23_USB0_PWEN(7));
+ pfc_reg_write(PFC_DRVCTRL23, reg);
+ reg = mmio_read_32(PFC_DRVCTRL24);
+ reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+ | DRVCTRL24_USB1_PWEN(7)
+ | DRVCTRL24_USB1_OVC(7)
+ | DRVCTRL24_USB30_PWEN(7)
+ | DRVCTRL24_USB30_OVC(7)
+ | DRVCTRL24_USB31_PWEN(7)
+ | DRVCTRL24_USB31_OVC(7));
+ pfc_reg_write(PFC_DRVCTRL24, reg);
+
+ /* initialize LSI pin pull-up/down control */
+ pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+ pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+ pfc_reg_write(PFC_PUD2, 0x330001E6U);
+ pfc_reg_write(PFC_PUD3, 0x000002E0U);
+ pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+ pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+ pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+ /* initialize LSI pin pull-enable register */
+ pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+ pfc_reg_write(PFC_PUEN1, 0x00100234U);
+ pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+ pfc_reg_write(PFC_PUEN3, 0x00000200U);
+ pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+ pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+ pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+ mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+ mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+#if (RCAR_GEN3_ULCB == 1)
+ mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
+#else
+ mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+#endif
+ mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
+}
diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.h b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
new file mode 100644
index 0000000..2478e1c
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_H3_V1_H
+#define PFC_INIT_H3_V1_H
+
+void pfc_init_h3_v1(void);
+
+#endif /* PFC_INIT_H3_V1_H */
diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
new file mode 100644
index 0000000..a54b14b
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
@@ -0,0 +1,1216 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h> /* for uint32_t */
+#include <lib/mmio.h>
+#include "pfc_init_h3_v2.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15 BIT(15)
+#define GPSR0_D14 BIT(14)
+#define GPSR0_D13 BIT(13)
+#define GPSR0_D12 BIT(12)
+#define GPSR0_D11 BIT(11)
+#define GPSR0_D10 BIT(10)
+#define GPSR0_D9 BIT(9)
+#define GPSR0_D8 BIT(8)
+#define GPSR0_D7 BIT(7)
+#define GPSR0_D6 BIT(6)
+#define GPSR0_D5 BIT(5)
+#define GPSR0_D4 BIT(4)
+#define GPSR0_D3 BIT(3)
+#define GPSR0_D2 BIT(2)
+#define GPSR0_D1 BIT(1)
+#define GPSR0_D0 BIT(0)
+#define GPSR1_CLKOUT BIT(28)
+#define GPSR1_EX_WAIT0_A BIT(27)
+#define GPSR1_WE1 BIT(26)
+#define GPSR1_WE0 BIT(25)
+#define GPSR1_RD_WR BIT(24)
+#define GPSR1_RD BIT(23)
+#define GPSR1_BS BIT(22)
+#define GPSR1_CS1_A26 BIT(21)
+#define GPSR1_CS0 BIT(20)
+#define GPSR1_A19 BIT(19)
+#define GPSR1_A18 BIT(18)
+#define GPSR1_A17 BIT(17)
+#define GPSR1_A16 BIT(16)
+#define GPSR1_A15 BIT(15)
+#define GPSR1_A14 BIT(14)
+#define GPSR1_A13 BIT(13)
+#define GPSR1_A12 BIT(12)
+#define GPSR1_A11 BIT(11)
+#define GPSR1_A10 BIT(10)
+#define GPSR1_A9 BIT(9)
+#define GPSR1_A8 BIT(8)
+#define GPSR1_A7 BIT(7)
+#define GPSR1_A6 BIT(6)
+#define GPSR1_A5 BIT(5)
+#define GPSR1_A4 BIT(4)
+#define GPSR1_A3 BIT(3)
+#define GPSR1_A2 BIT(2)
+#define GPSR1_A1 BIT(1)
+#define GPSR1_A0 BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A BIT(13)
+#define GPSR2_AVB_LINK BIT(12)
+#define GPSR2_AVB_PHY_INT BIT(11)
+#define GPSR2_AVB_MAGIC BIT(10)
+#define GPSR2_AVB_MDC BIT(9)
+#define GPSR2_PWM2_A BIT(8)
+#define GPSR2_PWM1_A BIT(7)
+#define GPSR2_PWM0 BIT(6)
+#define GPSR2_IRQ5 BIT(5)
+#define GPSR2_IRQ4 BIT(4)
+#define GPSR2_IRQ3 BIT(3)
+#define GPSR2_IRQ2 BIT(2)
+#define GPSR2_IRQ1 BIT(1)
+#define GPSR2_IRQ0 BIT(0)
+#define GPSR3_SD1_WP BIT(15)
+#define GPSR3_SD1_CD BIT(14)
+#define GPSR3_SD0_WP BIT(13)
+#define GPSR3_SD0_CD BIT(12)
+#define GPSR3_SD1_DAT3 BIT(11)
+#define GPSR3_SD1_DAT2 BIT(10)
+#define GPSR3_SD1_DAT1 BIT(9)
+#define GPSR3_SD1_DAT0 BIT(8)
+#define GPSR3_SD1_CMD BIT(7)
+#define GPSR3_SD1_CLK BIT(6)
+#define GPSR3_SD0_DAT3 BIT(5)
+#define GPSR3_SD0_DAT2 BIT(4)
+#define GPSR3_SD0_DAT1 BIT(3)
+#define GPSR3_SD0_DAT0 BIT(2)
+#define GPSR3_SD0_CMD BIT(1)
+#define GPSR3_SD0_CLK BIT(0)
+#define GPSR4_SD3_DS BIT(17)
+#define GPSR4_SD3_DAT7 BIT(16)
+#define GPSR4_SD3_DAT6 BIT(15)
+#define GPSR4_SD3_DAT5 BIT(14)
+#define GPSR4_SD3_DAT4 BIT(13)
+#define GPSR4_SD3_DAT3 BIT(12)
+#define GPSR4_SD3_DAT2 BIT(11)
+#define GPSR4_SD3_DAT1 BIT(10)
+#define GPSR4_SD3_DAT0 BIT(9)
+#define GPSR4_SD3_CMD BIT(8)
+#define GPSR4_SD3_CLK BIT(7)
+#define GPSR4_SD2_DS BIT(6)
+#define GPSR4_SD2_DAT3 BIT(5)
+#define GPSR4_SD2_DAT2 BIT(4)
+#define GPSR4_SD2_DAT1 BIT(3)
+#define GPSR4_SD2_DAT0 BIT(2)
+#define GPSR4_SD2_CMD BIT(1)
+#define GPSR4_SD2_CLK BIT(0)
+#define GPSR5_MLB_DAT BIT(25)
+#define GPSR5_MLB_SIG BIT(24)
+#define GPSR5_MLB_CLK BIT(23)
+#define GPSR5_MSIOF0_RXD BIT(22)
+#define GPSR5_MSIOF0_SS2 BIT(21)
+#define GPSR5_MSIOF0_TXD BIT(20)
+#define GPSR5_MSIOF0_SS1 BIT(19)
+#define GPSR5_MSIOF0_SYNC BIT(18)
+#define GPSR5_MSIOF0_SCK BIT(17)
+#define GPSR5_HRTS0 BIT(16)
+#define GPSR5_HCTS0 BIT(15)
+#define GPSR5_HTX0 BIT(14)
+#define GPSR5_HRX0 BIT(13)
+#define GPSR5_HSCK0 BIT(12)
+#define GPSR5_RX2_A BIT(11)
+#define GPSR5_TX2_A BIT(10)
+#define GPSR5_SCK2 BIT(9)
+#define GPSR5_RTS1 BIT(8)
+#define GPSR5_CTS1 BIT(7)
+#define GPSR5_TX1_A BIT(6)
+#define GPSR5_RX1_A BIT(5)
+#define GPSR5_RTS0 BIT(4)
+#define GPSR5_CTS0 BIT(3)
+#define GPSR5_TX0 BIT(2)
+#define GPSR5_RX0 BIT(1)
+#define GPSR5_SCK0 BIT(0)
+#define GPSR6_USB31_OVC BIT(31)
+#define GPSR6_USB31_PWEN BIT(30)
+#define GPSR6_USB30_OVC BIT(29)
+#define GPSR6_USB30_PWEN BIT(28)
+#define GPSR6_USB1_OVC BIT(27)
+#define GPSR6_USB1_PWEN BIT(26)
+#define GPSR6_USB0_OVC BIT(25)
+#define GPSR6_USB0_PWEN BIT(24)
+#define GPSR6_AUDIO_CLKB_B BIT(23)
+#define GPSR6_AUDIO_CLKA_A BIT(22)
+#define GPSR6_SSI_SDATA9_A BIT(21)
+#define GPSR6_SSI_SDATA8 BIT(20)
+#define GPSR6_SSI_SDATA7 BIT(19)
+#define GPSR6_SSI_WS78 BIT(18)
+#define GPSR6_SSI_SCK78 BIT(17)
+#define GPSR6_SSI_SDATA6 BIT(16)
+#define GPSR6_SSI_WS6 BIT(15)
+#define GPSR6_SSI_SCK6 BIT(14)
+#define GPSR6_SSI_SDATA5 BIT(13)
+#define GPSR6_SSI_WS5 BIT(12)
+#define GPSR6_SSI_SCK5 BIT(11)
+#define GPSR6_SSI_SDATA4 BIT(10)
+#define GPSR6_SSI_WS4 BIT(9)
+#define GPSR6_SSI_SCK4 BIT(8)
+#define GPSR6_SSI_SDATA3 BIT(7)
+#define GPSR6_SSI_WS34 BIT(6)
+#define GPSR6_SSI_SCK34 BIT(5)
+#define GPSR6_SSI_SDATA2_A BIT(4)
+#define GPSR6_SSI_SDATA1_A BIT(3)
+#define GPSR6_SSI_SDATA0 BIT(2)
+#define GPSR6_SSI_WS0129 BIT(1)
+#define GPSR6_SSI_SCK0129 BIT(0)
+#define GPSR7_AVS2 BIT(1)
+#define GPSR7_AVS1 BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V BIT(29)
+#define POC_SD3_DAT7_33V BIT(28)
+#define POC_SD3_DAT6_33V BIT(27)
+#define POC_SD3_DAT5_33V BIT(26)
+#define POC_SD3_DAT4_33V BIT(25)
+#define POC_SD3_DAT3_33V BIT(24)
+#define POC_SD3_DAT2_33V BIT(23)
+#define POC_SD3_DAT1_33V BIT(22)
+#define POC_SD3_DAT0_33V BIT(21)
+#define POC_SD3_CMD_33V BIT(20)
+#define POC_SD3_CLK_33V BIT(19)
+#define POC_SD2_DS_33V BIT(18)
+#define POC_SD2_DAT3_33V BIT(17)
+#define POC_SD2_DAT2_33V BIT(16)
+#define POC_SD2_DAT1_33V BIT(15)
+#define POC_SD2_DAT0_33V BIT(14)
+#define POC_SD2_CMD_33V BIT(13)
+#define POC_SD2_CLK_33V BIT(12)
+#define POC_SD1_DAT3_33V BIT(11)
+#define POC_SD1_DAT2_33V BIT(10)
+#define POC_SD1_DAT1_33V BIT(9)
+#define POC_SD1_DAT0_33V BIT(8)
+#define POC_SD1_CMD_33V BIT(7)
+#define POC_SD1_CLK_33V BIT(6)
+#define POC_SD0_DAT3_33V BIT(5)
+#define POC_SD0_DAT2_33V BIT(4)
+#define POC_SD0_DAT1_33V BIT(3)
+#define POC_SD0_DAT0_33V BIT(2)
+#define POC_SD0_CMD_33V BIT(1)
+#define POC_SD0_CLK_33V BIT(0)
+
+#define DRVCTRL0_MASK (0xCCCCCCCCU)
+#define DRVCTRL1_MASK (0xCCCCCCC8U)
+#define DRVCTRL2_MASK (0x88888888U)
+#define DRVCTRL3_MASK (0x88888888U)
+#define DRVCTRL4_MASK (0x88888888U)
+#define DRVCTRL5_MASK (0x88888888U)
+#define DRVCTRL6_MASK (0x88888888U)
+#define DRVCTRL7_MASK (0x88888888U)
+#define DRVCTRL8_MASK (0x88888888U)
+#define DRVCTRL9_MASK (0x88888888U)
+#define DRVCTRL10_MASK (0x88888888U)
+#define DRVCTRL11_MASK (0x888888CCU)
+#define DRVCTRL12_MASK (0xCCCFFFCFU)
+#define DRVCTRL13_MASK (0xCC888888U)
+#define DRVCTRL14_MASK (0x88888888U)
+#define DRVCTRL15_MASK (0x88888888U)
+#define DRVCTRL16_MASK (0x88888888U)
+#define DRVCTRL17_MASK (0x88888888U)
+#define DRVCTRL18_MASK (0x88888888U)
+#define DRVCTRL19_MASK (0x88888888U)
+#define DRVCTRL20_MASK (0x88888888U)
+#define DRVCTRL21_MASK (0x88888888U)
+#define DRVCTRL22_MASK (0x88888888U)
+#define DRVCTRL23_MASK (0x88888888U)
+#define DRVCTRL24_MASK (0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ mmio_write_32(PFC_PMMR, ~data);
+ mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_h3_v2(void)
+{
+ uint32_t reg;
+
+ /* initialize module select */
+ pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+ | MOD_SEL0_MSIOF2_A
+ | MOD_SEL0_MSIOF1_A
+ | MOD_SEL0_LBSC_A
+ | MOD_SEL0_IEBUS_A
+ | MOD_SEL0_I2C2_A
+ | MOD_SEL0_I2C1_A
+ | MOD_SEL0_HSCIF4_A
+ | MOD_SEL0_HSCIF3_A
+ | MOD_SEL0_HSCIF1_A
+ | MOD_SEL0_FSO_A
+ | MOD_SEL0_HSCIF2_A
+ | MOD_SEL0_ETHERAVB_A
+ | MOD_SEL0_DRIF3_A
+ | MOD_SEL0_DRIF2_A
+ | MOD_SEL0_DRIF1_A
+ | MOD_SEL0_DRIF0_A
+ | MOD_SEL0_CANFD0_A
+ | MOD_SEL0_ADG_A_A);
+ pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+ | MOD_SEL1_TSIF0_A
+ | MOD_SEL1_TIMER_TMU_A
+ | MOD_SEL1_SSP1_1_A
+ | MOD_SEL1_SSP1_0_A
+ | MOD_SEL1_SSI_A
+ | MOD_SEL1_SPEED_PULSE_IF_A
+ | MOD_SEL1_SIMCARD_A
+ | MOD_SEL1_SDHI2_A
+ | MOD_SEL1_SCIF4_A
+ | MOD_SEL1_SCIF3_A
+ | MOD_SEL1_SCIF2_A
+ | MOD_SEL1_SCIF1_A
+ | MOD_SEL1_SCIF_A
+ | MOD_SEL1_REMOCON_A
+ | MOD_SEL1_RCAN0_A
+ | MOD_SEL1_PWM6_A
+ | MOD_SEL1_PWM5_A
+ | MOD_SEL1_PWM4_A
+ | MOD_SEL1_PWM3_A
+ | MOD_SEL1_PWM2_A
+ | MOD_SEL1_PWM1_A);
+ pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+ | MOD_SEL2_I2C_3_A
+ | MOD_SEL2_I2C_0_A
+ | MOD_SEL2_FM_A
+ | MOD_SEL2_SCIF5_A
+ | MOD_SEL2_I2C6_A
+ | MOD_SEL2_NDF_A
+ | MOD_SEL2_SSI2_A
+ | MOD_SEL2_SSI9_A
+ | MOD_SEL2_TIMER_TMU2_A
+ | MOD_SEL2_ADG_B_A
+ | MOD_SEL2_ADG_C_A
+ | MOD_SEL2_VIN4_A);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(3)
+ | IPSR_8_FUNC(3)
+ | IPSR_4_FUNC(3)
+ | IPSR_0_FUNC(3));
+ pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+ | IPSR_24_FUNC(1)
+ | IPSR_20_FUNC(1)
+ | IPSR_16_FUNC(1)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(4)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(1));
+ pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(4)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(3)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(3)
+ | IPSR_0_FUNC(8));
+ pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(1)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ /* initialize GPIO/perihperal function select */
+ pfc_reg_write(PFC_GPSR0, GPSR0_D15
+ | GPSR0_D14
+ | GPSR0_D13
+ | GPSR0_D12
+ | GPSR0_D11
+ | GPSR0_D10
+ | GPSR0_D9
+ | GPSR0_D8);
+ pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
+ | GPSR1_EX_WAIT0_A
+ | GPSR1_A19
+ | GPSR1_A18
+ | GPSR1_A17
+ | GPSR1_A16
+ | GPSR1_A15
+ | GPSR1_A14
+ | GPSR1_A13
+ | GPSR1_A12
+ | GPSR1_A7
+ | GPSR1_A6
+ | GPSR1_A5
+ | GPSR1_A4
+ | GPSR1_A3
+ | GPSR1_A2
+ | GPSR1_A1
+ | GPSR1_A0);
+ pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+ | GPSR2_AVB_AVTP_MATCH_A
+ | GPSR2_AVB_LINK
+ | GPSR2_AVB_PHY_INT
+ | GPSR2_AVB_MDC
+ | GPSR2_PWM2_A
+ | GPSR2_PWM1_A
+ | GPSR2_IRQ5
+ | GPSR2_IRQ4
+ | GPSR2_IRQ3
+ | GPSR2_IRQ2
+ | GPSR2_IRQ1
+ | GPSR2_IRQ0);
+ pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+ | GPSR3_SD0_CD
+ | GPSR3_SD1_DAT3
+ | GPSR3_SD1_DAT2
+ | GPSR3_SD1_DAT1
+ | GPSR3_SD1_DAT0
+ | GPSR3_SD0_DAT3
+ | GPSR3_SD0_DAT2
+ | GPSR3_SD0_DAT1
+ | GPSR3_SD0_DAT0
+ | GPSR3_SD0_CMD
+ | GPSR3_SD0_CLK);
+ pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+ | GPSR4_SD3_DAT6
+ | GPSR4_SD3_DAT3
+ | GPSR4_SD3_DAT2
+ | GPSR4_SD3_DAT1
+ | GPSR4_SD3_DAT0
+ | GPSR4_SD3_CMD
+ | GPSR4_SD3_CLK
+ | GPSR4_SD2_DS
+ | GPSR4_SD2_DAT3
+ | GPSR4_SD2_DAT2
+ | GPSR4_SD2_DAT1
+ | GPSR4_SD2_DAT0
+ | GPSR4_SD2_CMD
+ | GPSR4_SD2_CLK);
+ pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+ | GPSR5_MSIOF0_SS1
+ | GPSR5_MSIOF0_SYNC
+ | GPSR5_HRTS0
+ | GPSR5_HCTS0
+ | GPSR5_HTX0
+ | GPSR5_HRX0
+ | GPSR5_HSCK0
+ | GPSR5_RX2_A
+ | GPSR5_TX2_A
+ | GPSR5_SCK2
+ | GPSR5_RTS1
+ | GPSR5_CTS1
+ | GPSR5_TX1_A
+ | GPSR5_RX1_A
+ | GPSR5_RTS0
+ | GPSR5_SCK0);
+ pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+ | GPSR6_USB30_PWEN
+ | GPSR6_USB1_OVC
+ | GPSR6_USB1_PWEN
+ | GPSR6_USB0_OVC
+ | GPSR6_USB0_PWEN
+ | GPSR6_AUDIO_CLKB_B
+ | GPSR6_AUDIO_CLKA_A
+ | GPSR6_SSI_SDATA8
+ | GPSR6_SSI_SDATA7
+ | GPSR6_SSI_WS78
+ | GPSR6_SSI_SCK78
+ | GPSR6_SSI_WS6
+ | GPSR6_SSI_SCK6
+ | GPSR6_SSI_SDATA4
+ | GPSR6_SSI_WS4
+ | GPSR6_SSI_SCK4
+ | GPSR6_SSI_SDATA1_A
+ | GPSR6_SSI_SDATA0
+ | GPSR6_SSI_WS0129
+ | GPSR6_SSI_SCK0129);
+ pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
+ | GPSR7_AVS1);
+
+ /* initialize POC control register */
+ pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+ | POC_SD3_DAT7_33V
+ | POC_SD3_DAT6_33V
+ | POC_SD3_DAT5_33V
+ | POC_SD3_DAT4_33V
+ | POC_SD3_DAT3_33V
+ | POC_SD3_DAT2_33V
+ | POC_SD3_DAT1_33V
+ | POC_SD3_DAT0_33V
+ | POC_SD3_CMD_33V
+ | POC_SD3_CLK_33V
+ | POC_SD0_DAT3_33V
+ | POC_SD0_DAT2_33V
+ | POC_SD0_DAT1_33V
+ | POC_SD0_DAT0_33V
+ | POC_SD0_CMD_33V
+ | POC_SD0_CLK_33V);
+
+ /* initialize DRV control register */
+ reg = mmio_read_32(PFC_DRVCTRL0);
+ reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+ | DRVCTRL0_QSPI0_MOSI_IO0(3)
+ | DRVCTRL0_QSPI0_MISO_IO1(3)
+ | DRVCTRL0_QSPI0_IO2(3)
+ | DRVCTRL0_QSPI0_IO3(3)
+ | DRVCTRL0_QSPI0_SSL(3)
+ | DRVCTRL0_QSPI1_SPCLK(3)
+ | DRVCTRL0_QSPI1_MOSI_IO0(3));
+ pfc_reg_write(PFC_DRVCTRL0, reg);
+ reg = mmio_read_32(PFC_DRVCTRL1);
+ reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+ | DRVCTRL1_QSPI1_IO2(3)
+ | DRVCTRL1_QSPI1_IO3(3)
+ | DRVCTRL1_QSPI1_SS(3)
+ | DRVCTRL1_RPC_INT(3)
+ | DRVCTRL1_RPC_WP(3)
+ | DRVCTRL1_RPC_RESET(3)
+ | DRVCTRL1_AVB_RX_CTL(7));
+ pfc_reg_write(PFC_DRVCTRL1, reg);
+ reg = mmio_read_32(PFC_DRVCTRL2);
+ reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+ | DRVCTRL2_AVB_RD0(7)
+ | DRVCTRL2_AVB_RD1(7)
+ | DRVCTRL2_AVB_RD2(7)
+ | DRVCTRL2_AVB_RD3(7)
+ | DRVCTRL2_AVB_TX_CTL(3)
+ | DRVCTRL2_AVB_TXC(3)
+ | DRVCTRL2_AVB_TD0(3));
+ pfc_reg_write(PFC_DRVCTRL2, reg);
+ reg = mmio_read_32(PFC_DRVCTRL3);
+ reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+ | DRVCTRL3_AVB_TD2(3)
+ | DRVCTRL3_AVB_TD3(3)
+ | DRVCTRL3_AVB_TXCREFCLK(7)
+ | DRVCTRL3_AVB_MDIO(7)
+ | DRVCTRL3_AVB_MDC(7)
+ | DRVCTRL3_AVB_MAGIC(7)
+ | DRVCTRL3_AVB_PHY_INT(7));
+ pfc_reg_write(PFC_DRVCTRL3, reg);
+ reg = mmio_read_32(PFC_DRVCTRL4);
+ reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+ | DRVCTRL4_AVB_AVTP_MATCH(7)
+ | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+ | DRVCTRL4_IRQ0(7)
+ | DRVCTRL4_IRQ1(7)
+ | DRVCTRL4_IRQ2(7)
+ | DRVCTRL4_IRQ3(7)
+ | DRVCTRL4_IRQ4(7));
+ pfc_reg_write(PFC_DRVCTRL4, reg);
+ reg = mmio_read_32(PFC_DRVCTRL5);
+ reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+ | DRVCTRL5_PWM0(7)
+ | DRVCTRL5_PWM1(7)
+ | DRVCTRL5_PWM2(7)
+ | DRVCTRL5_A0(3)
+ | DRVCTRL5_A1(3)
+ | DRVCTRL5_A2(3)
+ | DRVCTRL5_A3(3));
+ pfc_reg_write(PFC_DRVCTRL5, reg);
+ reg = mmio_read_32(PFC_DRVCTRL6);
+ reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+ | DRVCTRL6_A5(3)
+ | DRVCTRL6_A6(3)
+ | DRVCTRL6_A7(3)
+ | DRVCTRL6_A8(7)
+ | DRVCTRL6_A9(7)
+ | DRVCTRL6_A10(7)
+ | DRVCTRL6_A11(7));
+ pfc_reg_write(PFC_DRVCTRL6, reg);
+ reg = mmio_read_32(PFC_DRVCTRL7);
+ reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+ | DRVCTRL7_A13(3)
+ | DRVCTRL7_A14(3)
+ | DRVCTRL7_A15(3)
+ | DRVCTRL7_A16(3)
+ | DRVCTRL7_A17(3)
+ | DRVCTRL7_A18(3)
+ | DRVCTRL7_A19(3));
+ pfc_reg_write(PFC_DRVCTRL7, reg);
+ reg = mmio_read_32(PFC_DRVCTRL8);
+ reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+ | DRVCTRL8_CS0(7)
+ | DRVCTRL8_CS1_A2(7)
+ | DRVCTRL8_BS(7)
+ | DRVCTRL8_RD(7)
+ | DRVCTRL8_RD_W(7)
+ | DRVCTRL8_WE0(7)
+ | DRVCTRL8_WE1(7));
+ pfc_reg_write(PFC_DRVCTRL8, reg);
+ reg = mmio_read_32(PFC_DRVCTRL9);
+ reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+ | DRVCTRL9_PRESETOU(7)
+ | DRVCTRL9_D0(7)
+ | DRVCTRL9_D1(7)
+ | DRVCTRL9_D2(7)
+ | DRVCTRL9_D3(7)
+ | DRVCTRL9_D4(7)
+ | DRVCTRL9_D5(7));
+ pfc_reg_write(PFC_DRVCTRL9, reg);
+ reg = mmio_read_32(PFC_DRVCTRL10);
+ reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+ | DRVCTRL10_D7(7)
+ | DRVCTRL10_D8(3)
+ | DRVCTRL10_D9(3)
+ | DRVCTRL10_D10(3)
+ | DRVCTRL10_D11(3)
+ | DRVCTRL10_D12(3)
+ | DRVCTRL10_D13(3));
+ pfc_reg_write(PFC_DRVCTRL10, reg);
+ reg = mmio_read_32(PFC_DRVCTRL11);
+ reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+ | DRVCTRL11_D15(3)
+ | DRVCTRL11_AVS1(7)
+ | DRVCTRL11_AVS2(7)
+ | DRVCTRL11_GP7_02(7)
+ | DRVCTRL11_GP7_03(7)
+ | DRVCTRL11_DU_DOTCLKIN0(3)
+ | DRVCTRL11_DU_DOTCLKIN1(3));
+ pfc_reg_write(PFC_DRVCTRL11, reg);
+ reg = mmio_read_32(PFC_DRVCTRL12);
+ reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+ | DRVCTRL12_DU_DOTCLKIN3(3)
+ | DRVCTRL12_DU_FSCLKST(3)
+ | DRVCTRL12_DU_TMS(3));
+ pfc_reg_write(PFC_DRVCTRL12, reg);
+ reg = mmio_read_32(PFC_DRVCTRL13);
+ reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+ | DRVCTRL13_ASEBRK(3)
+ | DRVCTRL13_SD0_CLK(7)
+ | DRVCTRL13_SD0_CMD(7)
+ | DRVCTRL13_SD0_DAT0(7)
+ | DRVCTRL13_SD0_DAT1(7)
+ | DRVCTRL13_SD0_DAT2(7)
+ | DRVCTRL13_SD0_DAT3(7));
+ pfc_reg_write(PFC_DRVCTRL13, reg);
+ reg = mmio_read_32(PFC_DRVCTRL14);
+ reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+ | DRVCTRL14_SD1_CMD(7)
+ | DRVCTRL14_SD1_DAT0(5)
+ | DRVCTRL14_SD1_DAT1(5)
+ | DRVCTRL14_SD1_DAT2(5)
+ | DRVCTRL14_SD1_DAT3(5)
+ | DRVCTRL14_SD2_CLK(5)
+ | DRVCTRL14_SD2_CMD(5));
+ pfc_reg_write(PFC_DRVCTRL14, reg);
+ reg = mmio_read_32(PFC_DRVCTRL15);
+ reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+ | DRVCTRL15_SD2_DAT1(5)
+ | DRVCTRL15_SD2_DAT2(5)
+ | DRVCTRL15_SD2_DAT3(5)
+ | DRVCTRL15_SD2_DS(5)
+ | DRVCTRL15_SD3_CLK(7)
+ | DRVCTRL15_SD3_CMD(7)
+ | DRVCTRL15_SD3_DAT0(7));
+ pfc_reg_write(PFC_DRVCTRL15, reg);
+ reg = mmio_read_32(PFC_DRVCTRL16);
+ reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
+ | DRVCTRL16_SD3_DAT2(7)
+ | DRVCTRL16_SD3_DAT3(7)
+ | DRVCTRL16_SD3_DAT4(7)
+ | DRVCTRL16_SD3_DAT5(7)
+ | DRVCTRL16_SD3_DAT6(7)
+ | DRVCTRL16_SD3_DAT7(7)
+ | DRVCTRL16_SD3_DS(7));
+ pfc_reg_write(PFC_DRVCTRL16, reg);
+ reg = mmio_read_32(PFC_DRVCTRL17);
+ reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+ | DRVCTRL17_SD0_WP(7)
+ | DRVCTRL17_SD1_CD(7)
+ | DRVCTRL17_SD1_WP(7)
+ | DRVCTRL17_SCK0(7)
+ | DRVCTRL17_RX0(7)
+ | DRVCTRL17_TX0(7)
+ | DRVCTRL17_CTS0(7));
+ pfc_reg_write(PFC_DRVCTRL17, reg);
+ reg = mmio_read_32(PFC_DRVCTRL18);
+ reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+ | DRVCTRL18_RX1(7)
+ | DRVCTRL18_TX1(7)
+ | DRVCTRL18_CTS1(7)
+ | DRVCTRL18_RTS1_TANS(7)
+ | DRVCTRL18_SCK2(7)
+ | DRVCTRL18_TX2(7)
+ | DRVCTRL18_RX2(7));
+ pfc_reg_write(PFC_DRVCTRL18, reg);
+ reg = mmio_read_32(PFC_DRVCTRL19);
+ reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+ | DRVCTRL19_HRX0(7)
+ | DRVCTRL19_HTX0(7)
+ | DRVCTRL19_HCTS0(7)
+ | DRVCTRL19_HRTS0(7)
+ | DRVCTRL19_MSIOF0_SCK(7)
+ | DRVCTRL19_MSIOF0_SYNC(7)
+ | DRVCTRL19_MSIOF0_SS1(7));
+ pfc_reg_write(PFC_DRVCTRL19, reg);
+ reg = mmio_read_32(PFC_DRVCTRL20);
+ reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+ | DRVCTRL20_MSIOF0_SS2(7)
+ | DRVCTRL20_MSIOF0_RXD(7)
+ | DRVCTRL20_MLB_CLK(7)
+ | DRVCTRL20_MLB_SIG(7)
+ | DRVCTRL20_MLB_DAT(7)
+ | DRVCTRL20_MLB_REF(7)
+ | DRVCTRL20_SSI_SCK0129(7));
+ pfc_reg_write(PFC_DRVCTRL20, reg);
+ reg = mmio_read_32(PFC_DRVCTRL21);
+ reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+ | DRVCTRL21_SSI_SDATA0(7)
+ | DRVCTRL21_SSI_SDATA1(7)
+ | DRVCTRL21_SSI_SDATA2(7)
+ | DRVCTRL21_SSI_SCK34(7)
+ | DRVCTRL21_SSI_WS34(7)
+ | DRVCTRL21_SSI_SDATA3(7)
+ | DRVCTRL21_SSI_SCK4(7));
+ pfc_reg_write(PFC_DRVCTRL21, reg);
+ reg = mmio_read_32(PFC_DRVCTRL22);
+ reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+ | DRVCTRL22_SSI_SDATA4(7)
+ | DRVCTRL22_SSI_SCK5(7)
+ | DRVCTRL22_SSI_WS5(7)
+ | DRVCTRL22_SSI_SDATA5(7)
+ | DRVCTRL22_SSI_SCK6(7)
+ | DRVCTRL22_SSI_WS6(7)
+ | DRVCTRL22_SSI_SDATA6(7));
+ pfc_reg_write(PFC_DRVCTRL22, reg);
+ reg = mmio_read_32(PFC_DRVCTRL23);
+ reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+ | DRVCTRL23_SSI_WS78(7)
+ | DRVCTRL23_SSI_SDATA7(7)
+ | DRVCTRL23_SSI_SDATA8(7)
+ | DRVCTRL23_SSI_SDATA9(7)
+ | DRVCTRL23_AUDIO_CLKA(7)
+ | DRVCTRL23_AUDIO_CLKB(7)
+ | DRVCTRL23_USB0_PWEN(7));
+ pfc_reg_write(PFC_DRVCTRL23, reg);
+ reg = mmio_read_32(PFC_DRVCTRL24);
+ reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+ | DRVCTRL24_USB1_PWEN(7)
+ | DRVCTRL24_USB1_OVC(7)
+ | DRVCTRL24_USB30_PWEN(7)
+ | DRVCTRL24_USB30_OVC(7)
+ | DRVCTRL24_USB31_PWEN(7)
+ | DRVCTRL24_USB31_OVC(7));
+ pfc_reg_write(PFC_DRVCTRL24, reg);
+
+ /* initialize LSI pin pull-up/down control */
+ pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+ pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+ pfc_reg_write(PFC_PUD2, 0x330001E6U);
+ pfc_reg_write(PFC_PUD3, 0x000002E0U);
+ pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+ pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+ pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+ /* initialize LSI pin pull-enable register */
+ pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+ pfc_reg_write(PFC_PUEN1, 0x00100234U);
+ pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+ pfc_reg_write(PFC_PUEN3, 0x00000200U);
+ pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+ pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+ pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+ mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+ mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+#if (RCAR_GEN3_ULCB == 1)
+ mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
+#else
+ mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+#endif
+ mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
+}
diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.h b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
new file mode 100644
index 0000000..b02f93e
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_H3_V2_H
+#define PFC_INIT_H3_V2_H
+
+void pfc_init_h3_v2(void);
+
+#endif /* PFC_INIT_H3_V2_H */
diff --git a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
new file mode 100644
index 0000000..7684c62
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -0,0 +1,1311 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h> /* for uint32_t */
+
+#include <lib/mmio.h>
+
+#include "pfc_init_m3.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15 BIT(15)
+#define GPSR0_D14 BIT(14)
+#define GPSR0_D13 BIT(13)
+#define GPSR0_D12 BIT(12)
+#define GPSR0_D11 BIT(11)
+#define GPSR0_D10 BIT(10)
+#define GPSR0_D9 BIT(9)
+#define GPSR0_D8 BIT(8)
+#define GPSR0_D7 BIT(7)
+#define GPSR0_D6 BIT(6)
+#define GPSR0_D5 BIT(5)
+#define GPSR0_D4 BIT(4)
+#define GPSR0_D3 BIT(3)
+#define GPSR0_D2 BIT(2)
+#define GPSR0_D1 BIT(1)
+#define GPSR0_D0 BIT(0)
+#define GPSR1_CLKOUT BIT(28)
+#define GPSR1_EX_WAIT0_A BIT(27)
+#define GPSR1_WE1 BIT(26)
+#define GPSR1_WE0 BIT(25)
+#define GPSR1_RD_WR BIT(24)
+#define GPSR1_RD BIT(23)
+#define GPSR1_BS BIT(22)
+#define GPSR1_CS1_A26 BIT(21)
+#define GPSR1_CS0 BIT(20)
+#define GPSR1_A19 BIT(19)
+#define GPSR1_A18 BIT(18)
+#define GPSR1_A17 BIT(17)
+#define GPSR1_A16 BIT(16)
+#define GPSR1_A15 BIT(15)
+#define GPSR1_A14 BIT(14)
+#define GPSR1_A13 BIT(13)
+#define GPSR1_A12 BIT(12)
+#define GPSR1_A11 BIT(11)
+#define GPSR1_A10 BIT(10)
+#define GPSR1_A9 BIT(9)
+#define GPSR1_A8 BIT(8)
+#define GPSR1_A7 BIT(7)
+#define GPSR1_A6 BIT(6)
+#define GPSR1_A5 BIT(5)
+#define GPSR1_A4 BIT(4)
+#define GPSR1_A3 BIT(3)
+#define GPSR1_A2 BIT(2)
+#define GPSR1_A1 BIT(1)
+#define GPSR1_A0 BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A BIT(13)
+#define GPSR2_AVB_LINK BIT(12)
+#define GPSR2_AVB_PHY_INT BIT(11)
+#define GPSR2_AVB_MAGIC BIT(10)
+#define GPSR2_AVB_MDC BIT(9)
+#define GPSR2_PWM2_A BIT(8)
+#define GPSR2_PWM1_A BIT(7)
+#define GPSR2_PWM0 BIT(6)
+#define GPSR2_IRQ5 BIT(5)
+#define GPSR2_IRQ4 BIT(4)
+#define GPSR2_IRQ3 BIT(3)
+#define GPSR2_IRQ2 BIT(2)
+#define GPSR2_IRQ1 BIT(1)
+#define GPSR2_IRQ0 BIT(0)
+#define GPSR3_SD1_WP BIT(15)
+#define GPSR3_SD1_CD BIT(14)
+#define GPSR3_SD0_WP BIT(13)
+#define GPSR3_SD0_CD BIT(12)
+#define GPSR3_SD1_DAT3 BIT(11)
+#define GPSR3_SD1_DAT2 BIT(10)
+#define GPSR3_SD1_DAT1 BIT(9)
+#define GPSR3_SD1_DAT0 BIT(8)
+#define GPSR3_SD1_CMD BIT(7)
+#define GPSR3_SD1_CLK BIT(6)
+#define GPSR3_SD0_DAT3 BIT(5)
+#define GPSR3_SD0_DAT2 BIT(4)
+#define GPSR3_SD0_DAT1 BIT(3)
+#define GPSR3_SD0_DAT0 BIT(2)
+#define GPSR3_SD0_CMD BIT(1)
+#define GPSR3_SD0_CLK BIT(0)
+#define GPSR4_SD3_DS BIT(17)
+#define GPSR4_SD3_DAT7 BIT(16)
+#define GPSR4_SD3_DAT6 BIT(15)
+#define GPSR4_SD3_DAT5 BIT(14)
+#define GPSR4_SD3_DAT4 BIT(13)
+#define GPSR4_SD3_DAT3 BIT(12)
+#define GPSR4_SD3_DAT2 BIT(11)
+#define GPSR4_SD3_DAT1 BIT(10)
+#define GPSR4_SD3_DAT0 BIT(9)
+#define GPSR4_SD3_CMD BIT(8)
+#define GPSR4_SD3_CLK BIT(7)
+#define GPSR4_SD2_DS BIT(6)
+#define GPSR4_SD2_DAT3 BIT(5)
+#define GPSR4_SD2_DAT2 BIT(4)
+#define GPSR4_SD2_DAT1 BIT(3)
+#define GPSR4_SD2_DAT0 BIT(2)
+#define GPSR4_SD2_CMD BIT(1)
+#define GPSR4_SD2_CLK BIT(0)
+#define GPSR5_MLB_DAT BIT(25)
+#define GPSR5_MLB_SIG BIT(24)
+#define GPSR5_MLB_CLK BIT(23)
+#define GPSR5_MSIOF0_RXD BIT(22)
+#define GPSR5_MSIOF0_SS2 BIT(21)
+#define GPSR5_MSIOF0_TXD BIT(20)
+#define GPSR5_MSIOF0_SS1 BIT(19)
+#define GPSR5_MSIOF0_SYNC BIT(18)
+#define GPSR5_MSIOF0_SCK BIT(17)
+#define GPSR5_HRTS0 BIT(16)
+#define GPSR5_HCTS0 BIT(15)
+#define GPSR5_HTX0 BIT(14)
+#define GPSR5_HRX0 BIT(13)
+#define GPSR5_HSCK0 BIT(12)
+#define GPSR5_RX2_A BIT(11)
+#define GPSR5_TX2_A BIT(10)
+#define GPSR5_SCK2 BIT(9)
+#define GPSR5_RTS1 BIT(8)
+#define GPSR5_CTS1 BIT(7)
+#define GPSR5_TX1_A BIT(6)
+#define GPSR5_RX1_A BIT(5)
+#define GPSR5_RTS0 BIT(4)
+#define GPSR5_CTS0 BIT(3)
+#define GPSR5_TX0 BIT(2)
+#define GPSR5_RX0 BIT(1)
+#define GPSR5_SCK0 BIT(0)
+#define GPSR6_USB31_OVC BIT(31)
+#define GPSR6_USB31_PWEN BIT(30)
+#define GPSR6_USB30_OVC BIT(29)
+#define GPSR6_USB30_PWEN BIT(28)
+#define GPSR6_USB1_OVC BIT(27)
+#define GPSR6_USB1_PWEN BIT(26)
+#define GPSR6_USB0_OVC BIT(25)
+#define GPSR6_USB0_PWEN BIT(24)
+#define GPSR6_AUDIO_CLKB_B BIT(23)
+#define GPSR6_AUDIO_CLKA_A BIT(22)
+#define GPSR6_SSI_SDATA9_A BIT(21)
+#define GPSR6_SSI_SDATA8 BIT(20)
+#define GPSR6_SSI_SDATA7 BIT(19)
+#define GPSR6_SSI_WS78 BIT(18)
+#define GPSR6_SSI_SCK78 BIT(17)
+#define GPSR6_SSI_SDATA6 BIT(16)
+#define GPSR6_SSI_WS6 BIT(15)
+#define GPSR6_SSI_SCK6 BIT(14)
+#define GPSR6_SSI_SDATA5 BIT(13)
+#define GPSR6_SSI_WS5 BIT(12)
+#define GPSR6_SSI_SCK5 BIT(11)
+#define GPSR6_SSI_SDATA4 BIT(10)
+#define GPSR6_SSI_WS4 BIT(9)
+#define GPSR6_SSI_SCK4 BIT(8)
+#define GPSR6_SSI_SDATA3 BIT(7)
+#define GPSR6_SSI_WS34 BIT(6)
+#define GPSR6_SSI_SCK34 BIT(5)
+#define GPSR6_SSI_SDATA2_A BIT(4)
+#define GPSR6_SSI_SDATA1_A BIT(3)
+#define GPSR6_SSI_SDATA0 BIT(2)
+#define GPSR6_SSI_WS0129 BIT(1)
+#define GPSR6_SSI_SCK0129 BIT(0)
+#define GPSR7_AVS2 BIT(1)
+#define GPSR7_AVS1 BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V BIT(29)
+#define POC_SD3_DAT7_33V BIT(28)
+#define POC_SD3_DAT6_33V BIT(27)
+#define POC_SD3_DAT5_33V BIT(26)
+#define POC_SD3_DAT4_33V BIT(25)
+#define POC_SD3_DAT3_33V BIT(24)
+#define POC_SD3_DAT2_33V BIT(23)
+#define POC_SD3_DAT1_33V BIT(22)
+#define POC_SD3_DAT0_33V BIT(21)
+#define POC_SD3_CMD_33V BIT(20)
+#define POC_SD3_CLK_33V BIT(19)
+#define POC_SD2_DS_33V BIT(18)
+#define POC_SD2_DAT3_33V BIT(17)
+#define POC_SD2_DAT2_33V BIT(16)
+#define POC_SD2_DAT1_33V BIT(15)
+#define POC_SD2_DAT0_33V BIT(14)
+#define POC_SD2_CMD_33V BIT(13)
+#define POC_SD2_CLK_33V BIT(12)
+#define POC_SD1_DAT3_33V BIT(11)
+#define POC_SD1_DAT2_33V BIT(10)
+#define POC_SD1_DAT1_33V BIT(9)
+#define POC_SD1_DAT0_33V BIT(8)
+#define POC_SD1_CMD_33V BIT(7)
+#define POC_SD1_CLK_33V BIT(6)
+#define POC_SD0_DAT3_33V BIT(5)
+#define POC_SD0_DAT2_33V BIT(4)
+#define POC_SD0_DAT1_33V BIT(3)
+#define POC_SD0_DAT0_33V BIT(2)
+#define POC_SD0_CMD_33V BIT(1)
+#define POC_SD0_CLK_33V BIT(0)
+
+#define DRVCTRL0_MASK (0xCCCCCCCCU)
+#define DRVCTRL1_MASK (0xCCCCCCC8U)
+#define DRVCTRL2_MASK (0x88888888U)
+#define DRVCTRL3_MASK (0x88888888U)
+#define DRVCTRL4_MASK (0x88888888U)
+#define DRVCTRL5_MASK (0x88888888U)
+#define DRVCTRL6_MASK (0x88888888U)
+#define DRVCTRL7_MASK (0x88888888U)
+#define DRVCTRL8_MASK (0x88888888U)
+#define DRVCTRL9_MASK (0x88888888U)
+#define DRVCTRL10_MASK (0x88888888U)
+#define DRVCTRL11_MASK (0x888888CCU)
+#define DRVCTRL12_MASK (0xCCCFFFCFU)
+#define DRVCTRL13_MASK (0xCC888888U)
+#define DRVCTRL14_MASK (0x88888888U)
+#define DRVCTRL15_MASK (0x88888888U)
+#define DRVCTRL16_MASK (0x88888888U)
+#define DRVCTRL17_MASK (0x88888888U)
+#define DRVCTRL18_MASK (0x88888888U)
+#define DRVCTRL19_MASK (0x88888888U)
+#define DRVCTRL20_MASK (0x88888888U)
+#define DRVCTRL21_MASK (0x88888888U)
+#define DRVCTRL22_MASK (0x88888888U)
+#define DRVCTRL23_MASK (0x88888888U)
+#define DRVCTRL24_MASK (0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
+
+/* SCIF3 Registers for Dummy write */
+#define SCIF3_BASE (0xE6C50000U)
+#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U)
+#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU)
+#define SCFCR_DATA (0x0000U)
+
+/* Realtime module stop control */
+#define CPG_BASE (0xE6150000U)
+#define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U)
+#define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
+#define SCMSTPCR0_RTDMAC (0x00200000U)
+
+/* RT-DMAC Registers */
+#define RTDMAC_CH (0U) /* choose 0 to 15 */
+
+#define RTDMAC_BASE (0xFFC10000U)
+#define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U)
+#define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U)
+#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x)))
+#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x)))
+#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x)))
+#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x)))
+#define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x)))
+#define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x)))
+#define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U)
+#define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U)
+#define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U)
+#define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U)
+
+#define RDMOR_DME (0x0001U) /* DMA Master Enable */
+#define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */
+#define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */
+#define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */
+#define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */
+#define RDMCHCR_DE (0x00000001U) /* DMA Enable */
+#define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */
+#define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */
+#define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */
+
+static void start_rtdma0_descriptor(void)
+{
+ uint32_t reg;
+
+ reg = mmio_read_32(RCAR_PRR);
+ reg &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+ if (reg == (PRR_PRODUCT_M3_CUT10)) {
+ /* Enable clock supply to RTDMAC. */
+ mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
+
+ /* Initialize ch0, Reset Descriptor */
+ mmio_write_32(RTDMAC_RDMCHCLR, BIT(RTDMAC_CH));
+ mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
+
+ /* Enable DMA */
+ mmio_write_16(RTDMAC_RDMOR, RDMOR_DME);
+
+ /* Set first transfer */
+ mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR);
+ mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR);
+ mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U);
+
+ /* Set descriptor */
+ mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U);
+ mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U);
+ mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U);
+ mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256);
+ mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE
+ | RDMDPBASE_SEL_EXT);
+
+ /* Set transfer parameter, Start transfer */
+ mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
+ | RDMCHCR_RPT_TCR
+ | RDMCHCR_TS_2
+ | RDMCHCR_RS_AUTO
+ | RDMCHCR_DE);
+ }
+}
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ uint32_t prr;
+
+ prr = mmio_read_32(RCAR_PRR);
+ prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+
+ mmio_write_32(PFC_PMMR, ~data);
+ if (prr == (PRR_PRODUCT_M3_CUT10)) {
+ mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
+ }
+ mmio_write_32((uintptr_t)addr, data);
+ if (prr == (PRR_PRODUCT_M3_CUT10)) {
+ mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
+ }
+}
+
+void pfc_init_m3(void)
+{
+ uint32_t reg;
+
+ /* Work around for PFC eratta */
+ start_rtdma0_descriptor();
+
+ /* initialize module select */
+ pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+ | MOD_SEL0_MSIOF2_A
+ | MOD_SEL0_MSIOF1_A
+ | MOD_SEL0_LBSC_A
+ | MOD_SEL0_IEBUS_A
+ | MOD_SEL0_I2C2_A
+ | MOD_SEL0_I2C1_A
+ | MOD_SEL0_HSCIF4_A
+ | MOD_SEL0_HSCIF3_A
+ | MOD_SEL0_HSCIF1_A
+ | MOD_SEL0_FSO_A
+ | MOD_SEL0_HSCIF2_A
+ | MOD_SEL0_ETHERAVB_A
+ | MOD_SEL0_DRIF3_A
+ | MOD_SEL0_DRIF2_A
+ | MOD_SEL0_DRIF1_A
+ | MOD_SEL0_DRIF0_A
+ | MOD_SEL0_CANFD0_A
+ | MOD_SEL0_ADG_A_A);
+ pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+ | MOD_SEL1_TSIF0_A
+ | MOD_SEL1_TIMER_TMU_A
+ | MOD_SEL1_SSP1_1_A
+ | MOD_SEL1_SSP1_0_A
+ | MOD_SEL1_SSI_A
+ | MOD_SEL1_SPEED_PULSE_IF_A
+ | MOD_SEL1_SIMCARD_A
+ | MOD_SEL1_SDHI2_A
+ | MOD_SEL1_SCIF4_A
+ | MOD_SEL1_SCIF3_A
+ | MOD_SEL1_SCIF2_A
+ | MOD_SEL1_SCIF1_A
+ | MOD_SEL1_SCIF_A
+ | MOD_SEL1_REMOCON_A
+ | MOD_SEL1_RCAN0_A
+ | MOD_SEL1_PWM6_A
+ | MOD_SEL1_PWM5_A
+ | MOD_SEL1_PWM4_A
+ | MOD_SEL1_PWM3_A
+ | MOD_SEL1_PWM2_A
+ | MOD_SEL1_PWM1_A);
+ pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+ | MOD_SEL2_I2C_3_A
+ | MOD_SEL2_I2C_0_A
+ | MOD_SEL2_FM_A
+ | MOD_SEL2_SCIF5_A
+ | MOD_SEL2_I2C6_A
+ | MOD_SEL2_NDF_A
+ | MOD_SEL2_SSI2_A
+ | MOD_SEL2_SSI9_A
+ | MOD_SEL2_TIMER_TMU2_A
+ | MOD_SEL2_ADG_B_A
+ | MOD_SEL2_ADG_C_A
+ | MOD_SEL2_VIN4_A);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(3)
+ | IPSR_8_FUNC(3)
+ | IPSR_4_FUNC(3)
+ | IPSR_0_FUNC(3));
+ pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+ | IPSR_24_FUNC(1)
+ | IPSR_20_FUNC(1)
+ | IPSR_16_FUNC(1)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(4)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(1));
+ pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(4)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(3)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(3)
+ | IPSR_0_FUNC(8));
+ pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(1)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ /* initialize GPIO/perihperal function select */
+ pfc_reg_write(PFC_GPSR0, GPSR0_D15
+ | GPSR0_D14
+ | GPSR0_D13
+ | GPSR0_D12
+ | GPSR0_D11
+ | GPSR0_D10
+ | GPSR0_D9
+ | GPSR0_D8);
+ pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
+ | GPSR1_EX_WAIT0_A
+ | GPSR1_A19
+ | GPSR1_A18
+ | GPSR1_A17
+ | GPSR1_A16
+ | GPSR1_A15
+ | GPSR1_A14
+ | GPSR1_A13
+ | GPSR1_A12
+ | GPSR1_A7
+ | GPSR1_A6
+ | GPSR1_A5
+ | GPSR1_A4
+ | GPSR1_A3
+ | GPSR1_A2
+ | GPSR1_A1
+ | GPSR1_A0);
+ pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+ | GPSR2_AVB_AVTP_MATCH_A
+ | GPSR2_AVB_LINK
+ | GPSR2_AVB_PHY_INT
+ | GPSR2_AVB_MDC
+ | GPSR2_PWM2_A
+ | GPSR2_PWM1_A
+ | GPSR2_IRQ5
+ | GPSR2_IRQ4
+ | GPSR2_IRQ3
+ | GPSR2_IRQ2
+ | GPSR2_IRQ1
+ | GPSR2_IRQ0);
+ pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+ | GPSR3_SD0_CD
+ | GPSR3_SD1_DAT3
+ | GPSR3_SD1_DAT2
+ | GPSR3_SD1_DAT1
+ | GPSR3_SD1_DAT0
+ | GPSR3_SD0_DAT3
+ | GPSR3_SD0_DAT2
+ | GPSR3_SD0_DAT1
+ | GPSR3_SD0_DAT0
+ | GPSR3_SD0_CMD
+ | GPSR3_SD0_CLK);
+ pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+ | GPSR4_SD3_DAT6
+ | GPSR4_SD3_DAT3
+ | GPSR4_SD3_DAT2
+ | GPSR4_SD3_DAT1
+ | GPSR4_SD3_DAT0
+ | GPSR4_SD3_CMD
+ | GPSR4_SD3_CLK
+ | GPSR4_SD2_DS
+ | GPSR4_SD2_DAT3
+ | GPSR4_SD2_DAT2
+ | GPSR4_SD2_DAT1
+ | GPSR4_SD2_DAT0
+ | GPSR4_SD2_CMD
+ | GPSR4_SD2_CLK);
+ pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+ | GPSR5_MSIOF0_SS1
+ | GPSR5_MSIOF0_SYNC
+ | GPSR5_HRTS0
+ | GPSR5_HCTS0
+ | GPSR5_HTX0
+ | GPSR5_HRX0
+ | GPSR5_HSCK0
+ | GPSR5_RX2_A
+ | GPSR5_TX2_A
+ | GPSR5_SCK2
+ | GPSR5_RTS1
+ | GPSR5_CTS1
+ | GPSR5_TX1_A
+ | GPSR5_RX1_A
+ | GPSR5_RTS0
+ | GPSR5_SCK0);
+ pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+ | GPSR6_USB30_PWEN
+ | GPSR6_USB1_OVC
+ | GPSR6_USB1_PWEN
+ | GPSR6_USB0_OVC
+ | GPSR6_USB0_PWEN
+ | GPSR6_AUDIO_CLKB_B
+ | GPSR6_AUDIO_CLKA_A
+ | GPSR6_SSI_SDATA8
+ | GPSR6_SSI_SDATA7
+ | GPSR6_SSI_WS78
+ | GPSR6_SSI_SCK78
+ | GPSR6_SSI_WS6
+ | GPSR6_SSI_SCK6
+ | GPSR6_SSI_SDATA4
+ | GPSR6_SSI_WS4
+ | GPSR6_SSI_SCK4
+ | GPSR6_SSI_SDATA1_A
+ | GPSR6_SSI_SDATA0
+ | GPSR6_SSI_WS0129
+ | GPSR6_SSI_SCK0129);
+ pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
+ | GPSR7_AVS1);
+
+ /* initialize POC control register */
+ pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+ | POC_SD3_DAT7_33V
+ | POC_SD3_DAT6_33V
+ | POC_SD3_DAT5_33V
+ | POC_SD3_DAT4_33V
+ | POC_SD3_DAT3_33V
+ | POC_SD3_DAT2_33V
+ | POC_SD3_DAT1_33V
+ | POC_SD3_DAT0_33V
+ | POC_SD3_CMD_33V
+ | POC_SD3_CLK_33V
+ | POC_SD0_DAT3_33V
+ | POC_SD0_DAT2_33V
+ | POC_SD0_DAT1_33V
+ | POC_SD0_DAT0_33V
+ | POC_SD0_CMD_33V
+ | POC_SD0_CLK_33V);
+
+ /* initialize DRV control register */
+ reg = mmio_read_32(PFC_DRVCTRL0);
+ reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+ | DRVCTRL0_QSPI0_MOSI_IO0(3)
+ | DRVCTRL0_QSPI0_MISO_IO1(3)
+ | DRVCTRL0_QSPI0_IO2(3)
+ | DRVCTRL0_QSPI0_IO3(3)
+ | DRVCTRL0_QSPI0_SSL(3)
+ | DRVCTRL0_QSPI1_SPCLK(3)
+ | DRVCTRL0_QSPI1_MOSI_IO0(3));
+ pfc_reg_write(PFC_DRVCTRL0, reg);
+ reg = mmio_read_32(PFC_DRVCTRL1);
+ reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+ | DRVCTRL1_QSPI1_IO2(3)
+ | DRVCTRL1_QSPI1_IO3(3)
+ | DRVCTRL1_QSPI1_SS(3)
+ | DRVCTRL1_RPC_INT(3)
+ | DRVCTRL1_RPC_WP(3)
+ | DRVCTRL1_RPC_RESET(3)
+ | DRVCTRL1_AVB_RX_CTL(7));
+ pfc_reg_write(PFC_DRVCTRL1, reg);
+ reg = mmio_read_32(PFC_DRVCTRL2);
+ reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+ | DRVCTRL2_AVB_RD0(7)
+ | DRVCTRL2_AVB_RD1(7)
+ | DRVCTRL2_AVB_RD2(7)
+ | DRVCTRL2_AVB_RD3(7)
+ | DRVCTRL2_AVB_TX_CTL(3)
+ | DRVCTRL2_AVB_TXC(3)
+ | DRVCTRL2_AVB_TD0(3));
+ pfc_reg_write(PFC_DRVCTRL2, reg);
+ reg = mmio_read_32(PFC_DRVCTRL3);
+ reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+ | DRVCTRL3_AVB_TD2(3)
+ | DRVCTRL3_AVB_TD3(3)
+ | DRVCTRL3_AVB_TXCREFCLK(7)
+ | DRVCTRL3_AVB_MDIO(7)
+ | DRVCTRL3_AVB_MDC(7)
+ | DRVCTRL3_AVB_MAGIC(7)
+ | DRVCTRL3_AVB_PHY_INT(7));
+ pfc_reg_write(PFC_DRVCTRL3, reg);
+ reg = mmio_read_32(PFC_DRVCTRL4);
+ reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+ | DRVCTRL4_AVB_AVTP_MATCH(7)
+ | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+ | DRVCTRL4_IRQ0(7)
+ | DRVCTRL4_IRQ1(7)
+ | DRVCTRL4_IRQ2(7)
+ | DRVCTRL4_IRQ3(7)
+ | DRVCTRL4_IRQ4(7));
+ pfc_reg_write(PFC_DRVCTRL4, reg);
+ reg = mmio_read_32(PFC_DRVCTRL5);
+ reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+ | DRVCTRL5_PWM0(7)
+ | DRVCTRL5_PWM1(7)
+ | DRVCTRL5_PWM2(7)
+ | DRVCTRL5_A0(3)
+ | DRVCTRL5_A1(3)
+ | DRVCTRL5_A2(3)
+ | DRVCTRL5_A3(3));
+ pfc_reg_write(PFC_DRVCTRL5, reg);
+ reg = mmio_read_32(PFC_DRVCTRL6);
+ reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+ | DRVCTRL6_A5(3)
+ | DRVCTRL6_A6(3)
+ | DRVCTRL6_A7(3)
+ | DRVCTRL6_A8(7)
+ | DRVCTRL6_A9(7)
+ | DRVCTRL6_A10(7)
+ | DRVCTRL6_A11(7));
+ pfc_reg_write(PFC_DRVCTRL6, reg);
+ reg = mmio_read_32(PFC_DRVCTRL7);
+ reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+ | DRVCTRL7_A13(3)
+ | DRVCTRL7_A14(3)
+ | DRVCTRL7_A15(3)
+ | DRVCTRL7_A16(3)
+ | DRVCTRL7_A17(3)
+ | DRVCTRL7_A18(3)
+ | DRVCTRL7_A19(3));
+ pfc_reg_write(PFC_DRVCTRL7, reg);
+ reg = mmio_read_32(PFC_DRVCTRL8);
+ reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+ | DRVCTRL8_CS0(7)
+ | DRVCTRL8_CS1_A2(7)
+ | DRVCTRL8_BS(7)
+ | DRVCTRL8_RD(7)
+ | DRVCTRL8_RD_W(7)
+ | DRVCTRL8_WE0(7)
+ | DRVCTRL8_WE1(7));
+ pfc_reg_write(PFC_DRVCTRL8, reg);
+ reg = mmio_read_32(PFC_DRVCTRL9);
+ reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+ | DRVCTRL9_PRESETOU(7)
+ | DRVCTRL9_D0(7)
+ | DRVCTRL9_D1(7)
+ | DRVCTRL9_D2(7)
+ | DRVCTRL9_D3(7)
+ | DRVCTRL9_D4(7)
+ | DRVCTRL9_D5(7));
+ pfc_reg_write(PFC_DRVCTRL9, reg);
+ reg = mmio_read_32(PFC_DRVCTRL10);
+ reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+ | DRVCTRL10_D7(7)
+ | DRVCTRL10_D8(3)
+ | DRVCTRL10_D9(3)
+ | DRVCTRL10_D10(3)
+ | DRVCTRL10_D11(3)
+ | DRVCTRL10_D12(3)
+ | DRVCTRL10_D13(3));
+ pfc_reg_write(PFC_DRVCTRL10, reg);
+ reg = mmio_read_32(PFC_DRVCTRL11);
+ reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+ | DRVCTRL11_D15(3)
+ | DRVCTRL11_AVS1(7)
+ | DRVCTRL11_AVS2(7)
+ | DRVCTRL11_GP7_02(7)
+ | DRVCTRL11_GP7_03(7)
+ | DRVCTRL11_DU_DOTCLKIN0(3)
+ | DRVCTRL11_DU_DOTCLKIN1(3));
+ pfc_reg_write(PFC_DRVCTRL11, reg);
+ reg = mmio_read_32(PFC_DRVCTRL12);
+ reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+ | DRVCTRL12_DU_DOTCLKIN3(3)
+ | DRVCTRL12_DU_FSCLKST(3)
+ | DRVCTRL12_DU_TMS(3));
+ pfc_reg_write(PFC_DRVCTRL12, reg);
+ reg = mmio_read_32(PFC_DRVCTRL13);
+ reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+ | DRVCTRL13_ASEBRK(3)
+ | DRVCTRL13_SD0_CLK(7)
+ | DRVCTRL13_SD0_CMD(7)
+ | DRVCTRL13_SD0_DAT0(7)
+ | DRVCTRL13_SD0_DAT1(7)
+ | DRVCTRL13_SD0_DAT2(7)
+ | DRVCTRL13_SD0_DAT3(7));
+ pfc_reg_write(PFC_DRVCTRL13, reg);
+ reg = mmio_read_32(PFC_DRVCTRL14);
+ reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+ | DRVCTRL14_SD1_CMD(7)
+ | DRVCTRL14_SD1_DAT0(5)
+ | DRVCTRL14_SD1_DAT1(5)
+ | DRVCTRL14_SD1_DAT2(5)
+ | DRVCTRL14_SD1_DAT3(5)
+ | DRVCTRL14_SD2_CLK(5)
+ | DRVCTRL14_SD2_CMD(5));
+ pfc_reg_write(PFC_DRVCTRL14, reg);
+ reg = mmio_read_32(PFC_DRVCTRL15);
+ reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+ | DRVCTRL15_SD2_DAT1(5)
+ | DRVCTRL15_SD2_DAT2(5)
+ | DRVCTRL15_SD2_DAT3(5)
+ | DRVCTRL15_SD2_DS(5)
+ | DRVCTRL15_SD3_CLK(7)
+ | DRVCTRL15_SD3_CMD(7)
+ | DRVCTRL15_SD3_DAT0(7));
+ pfc_reg_write(PFC_DRVCTRL15, reg);
+ reg = mmio_read_32(PFC_DRVCTRL16);
+ reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
+ | DRVCTRL16_SD3_DAT2(7)
+ | DRVCTRL16_SD3_DAT3(7)
+ | DRVCTRL16_SD3_DAT4(7)
+ | DRVCTRL16_SD3_DAT5(7)
+ | DRVCTRL16_SD3_DAT6(7)
+ | DRVCTRL16_SD3_DAT7(7)
+ | DRVCTRL16_SD3_DS(7));
+ pfc_reg_write(PFC_DRVCTRL16, reg);
+ reg = mmio_read_32(PFC_DRVCTRL17);
+ reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+ | DRVCTRL17_SD0_WP(7)
+ | DRVCTRL17_SD1_CD(7)
+ | DRVCTRL17_SD1_WP(7)
+ | DRVCTRL17_SCK0(7)
+ | DRVCTRL17_RX0(7)
+ | DRVCTRL17_TX0(7)
+ | DRVCTRL17_CTS0(7));
+ pfc_reg_write(PFC_DRVCTRL17, reg);
+ reg = mmio_read_32(PFC_DRVCTRL18);
+ reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+ | DRVCTRL18_RX1(7)
+ | DRVCTRL18_TX1(7)
+ | DRVCTRL18_CTS1(7)
+ | DRVCTRL18_RTS1_TANS(7)
+ | DRVCTRL18_SCK2(7)
+ | DRVCTRL18_TX2(7)
+ | DRVCTRL18_RX2(7));
+ pfc_reg_write(PFC_DRVCTRL18, reg);
+ reg = mmio_read_32(PFC_DRVCTRL19);
+ reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+ | DRVCTRL19_HRX0(7)
+ | DRVCTRL19_HTX0(7)
+ | DRVCTRL19_HCTS0(7)
+ | DRVCTRL19_HRTS0(7)
+ | DRVCTRL19_MSIOF0_SCK(7)
+ | DRVCTRL19_MSIOF0_SYNC(7)
+ | DRVCTRL19_MSIOF0_SS1(7));
+ pfc_reg_write(PFC_DRVCTRL19, reg);
+ reg = mmio_read_32(PFC_DRVCTRL20);
+ reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+ | DRVCTRL20_MSIOF0_SS2(7)
+ | DRVCTRL20_MSIOF0_RXD(7)
+ | DRVCTRL20_MLB_CLK(7)
+ | DRVCTRL20_MLB_SIG(7)
+ | DRVCTRL20_MLB_DAT(7)
+ | DRVCTRL20_MLB_REF(7)
+ | DRVCTRL20_SSI_SCK0129(7));
+ pfc_reg_write(PFC_DRVCTRL20, reg);
+ reg = mmio_read_32(PFC_DRVCTRL21);
+ reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+ | DRVCTRL21_SSI_SDATA0(7)
+ | DRVCTRL21_SSI_SDATA1(7)
+ | DRVCTRL21_SSI_SDATA2(7)
+ | DRVCTRL21_SSI_SCK34(7)
+ | DRVCTRL21_SSI_WS34(7)
+ | DRVCTRL21_SSI_SDATA3(7)
+ | DRVCTRL21_SSI_SCK4(7));
+ pfc_reg_write(PFC_DRVCTRL21, reg);
+ reg = mmio_read_32(PFC_DRVCTRL22);
+ reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+ | DRVCTRL22_SSI_SDATA4(7)
+ | DRVCTRL22_SSI_SCK5(7)
+ | DRVCTRL22_SSI_WS5(7)
+ | DRVCTRL22_SSI_SDATA5(7)
+ | DRVCTRL22_SSI_SCK6(7)
+ | DRVCTRL22_SSI_WS6(7)
+ | DRVCTRL22_SSI_SDATA6(7));
+ pfc_reg_write(PFC_DRVCTRL22, reg);
+ reg = mmio_read_32(PFC_DRVCTRL23);
+ reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+ | DRVCTRL23_SSI_WS78(7)
+ | DRVCTRL23_SSI_SDATA7(7)
+ | DRVCTRL23_SSI_SDATA8(7)
+ | DRVCTRL23_SSI_SDATA9(7)
+ | DRVCTRL23_AUDIO_CLKA(7)
+ | DRVCTRL23_AUDIO_CLKB(7)
+ | DRVCTRL23_USB0_PWEN(7));
+ pfc_reg_write(PFC_DRVCTRL23, reg);
+ reg = mmio_read_32(PFC_DRVCTRL24);
+ reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+ | DRVCTRL24_USB1_PWEN(7)
+ | DRVCTRL24_USB1_OVC(7)
+ | DRVCTRL24_USB30_PWEN(7)
+ | DRVCTRL24_USB30_OVC(7)
+ | DRVCTRL24_USB31_PWEN(7)
+ | DRVCTRL24_USB31_OVC(7));
+ pfc_reg_write(PFC_DRVCTRL24, reg);
+
+ /* initialize LSI pin pull-up/down control */
+ pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+ pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+ pfc_reg_write(PFC_PUD2, 0x330001E6U);
+ pfc_reg_write(PFC_PUD3, 0x000002E0U);
+ pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+ pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+ pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+ /* initialize LSI pin pull-enable register */
+ pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+ pfc_reg_write(PFC_PUEN1, 0x00100234U);
+ pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+ pfc_reg_write(PFC_PUEN3, 0x00000200U);
+ pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+ pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+ pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+ mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+ mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+#if (RCAR_GEN3_ULCB == 1)
+ mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
+#else
+ mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+#endif
+ mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
+}
diff --git a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.h b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.h
new file mode 100644
index 0000000..70885de
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_M3_H
+#define PFC_INIT_M3_H
+
+void pfc_init_m3(void);
+
+#endif /* PFC_INIT_M3_H */
diff --git a/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
new file mode 100644
index 0000000..5014556
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
@@ -0,0 +1,1218 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h> /* for uint32_t */
+
+#include <lib/mmio.h>
+
+#include "pfc_init_m3n.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15 BIT(15)
+#define GPSR0_D14 BIT(14)
+#define GPSR0_D13 BIT(13)
+#define GPSR0_D12 BIT(12)
+#define GPSR0_D11 BIT(11)
+#define GPSR0_D10 BIT(10)
+#define GPSR0_D9 BIT(9)
+#define GPSR0_D8 BIT(8)
+#define GPSR0_D7 BIT(7)
+#define GPSR0_D6 BIT(6)
+#define GPSR0_D5 BIT(5)
+#define GPSR0_D4 BIT(4)
+#define GPSR0_D3 BIT(3)
+#define GPSR0_D2 BIT(2)
+#define GPSR0_D1 BIT(1)
+#define GPSR0_D0 BIT(0)
+#define GPSR1_CLKOUT BIT(28)
+#define GPSR1_EX_WAIT0_A BIT(27)
+#define GPSR1_WE1 BIT(26)
+#define GPSR1_WE0 BIT(25)
+#define GPSR1_RD_WR BIT(24)
+#define GPSR1_RD BIT(23)
+#define GPSR1_BS BIT(22)
+#define GPSR1_CS1_A26 BIT(21)
+#define GPSR1_CS0 BIT(20)
+#define GPSR1_A19 BIT(19)
+#define GPSR1_A18 BIT(18)
+#define GPSR1_A17 BIT(17)
+#define GPSR1_A16 BIT(16)
+#define GPSR1_A15 BIT(15)
+#define GPSR1_A14 BIT(14)
+#define GPSR1_A13 BIT(13)
+#define GPSR1_A12 BIT(12)
+#define GPSR1_A11 BIT(11)
+#define GPSR1_A10 BIT(10)
+#define GPSR1_A9 BIT(9)
+#define GPSR1_A8 BIT(8)
+#define GPSR1_A7 BIT(7)
+#define GPSR1_A6 BIT(6)
+#define GPSR1_A5 BIT(5)
+#define GPSR1_A4 BIT(4)
+#define GPSR1_A3 BIT(3)
+#define GPSR1_A2 BIT(2)
+#define GPSR1_A1 BIT(1)
+#define GPSR1_A0 BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A BIT(13)
+#define GPSR2_AVB_LINK BIT(12)
+#define GPSR2_AVB_PHY_INT BIT(11)
+#define GPSR2_AVB_MAGIC BIT(10)
+#define GPSR2_AVB_MDC BIT(9)
+#define GPSR2_PWM2_A BIT(8)
+#define GPSR2_PWM1_A BIT(7)
+#define GPSR2_PWM0 BIT(6)
+#define GPSR2_IRQ5 BIT(5)
+#define GPSR2_IRQ4 BIT(4)
+#define GPSR2_IRQ3 BIT(3)
+#define GPSR2_IRQ2 BIT(2)
+#define GPSR2_IRQ1 BIT(1)
+#define GPSR2_IRQ0 BIT(0)
+#define GPSR3_SD1_WP BIT(15)
+#define GPSR3_SD1_CD BIT(14)
+#define GPSR3_SD0_WP BIT(13)
+#define GPSR3_SD0_CD BIT(12)
+#define GPSR3_SD1_DAT3 BIT(11)
+#define GPSR3_SD1_DAT2 BIT(10)
+#define GPSR3_SD1_DAT1 BIT(9)
+#define GPSR3_SD1_DAT0 BIT(8)
+#define GPSR3_SD1_CMD BIT(7)
+#define GPSR3_SD1_CLK BIT(6)
+#define GPSR3_SD0_DAT3 BIT(5)
+#define GPSR3_SD0_DAT2 BIT(4)
+#define GPSR3_SD0_DAT1 BIT(3)
+#define GPSR3_SD0_DAT0 BIT(2)
+#define GPSR3_SD0_CMD BIT(1)
+#define GPSR3_SD0_CLK BIT(0)
+#define GPSR4_SD3_DS BIT(17)
+#define GPSR4_SD3_DAT7 BIT(16)
+#define GPSR4_SD3_DAT6 BIT(15)
+#define GPSR4_SD3_DAT5 BIT(14)
+#define GPSR4_SD3_DAT4 BIT(13)
+#define GPSR4_SD3_DAT3 BIT(12)
+#define GPSR4_SD3_DAT2 BIT(11)
+#define GPSR4_SD3_DAT1 BIT(10)
+#define GPSR4_SD3_DAT0 BIT(9)
+#define GPSR4_SD3_CMD BIT(8)
+#define GPSR4_SD3_CLK BIT(7)
+#define GPSR4_SD2_DS BIT(6)
+#define GPSR4_SD2_DAT3 BIT(5)
+#define GPSR4_SD2_DAT2 BIT(4)
+#define GPSR4_SD2_DAT1 BIT(3)
+#define GPSR4_SD2_DAT0 BIT(2)
+#define GPSR4_SD2_CMD BIT(1)
+#define GPSR4_SD2_CLK BIT(0)
+#define GPSR5_MLB_DAT BIT(25)
+#define GPSR5_MLB_SIG BIT(24)
+#define GPSR5_MLB_CLK BIT(23)
+#define GPSR5_MSIOF0_RXD BIT(22)
+#define GPSR5_MSIOF0_SS2 BIT(21)
+#define GPSR5_MSIOF0_TXD BIT(20)
+#define GPSR5_MSIOF0_SS1 BIT(19)
+#define GPSR5_MSIOF0_SYNC BIT(18)
+#define GPSR5_MSIOF0_SCK BIT(17)
+#define GPSR5_HRTS0 BIT(16)
+#define GPSR5_HCTS0 BIT(15)
+#define GPSR5_HTX0 BIT(14)
+#define GPSR5_HRX0 BIT(13)
+#define GPSR5_HSCK0 BIT(12)
+#define GPSR5_RX2_A BIT(11)
+#define GPSR5_TX2_A BIT(10)
+#define GPSR5_SCK2 BIT(9)
+#define GPSR5_RTS1 BIT(8)
+#define GPSR5_CTS1 BIT(7)
+#define GPSR5_TX1_A BIT(6)
+#define GPSR5_RX1_A BIT(5)
+#define GPSR5_RTS0 BIT(4)
+#define GPSR5_CTS0 BIT(3)
+#define GPSR5_TX0 BIT(2)
+#define GPSR5_RX0 BIT(1)
+#define GPSR5_SCK0 BIT(0)
+#define GPSR6_USB31_OVC BIT(31)
+#define GPSR6_USB31_PWEN BIT(30)
+#define GPSR6_USB30_OVC BIT(29)
+#define GPSR6_USB30_PWEN BIT(28)
+#define GPSR6_USB1_OVC BIT(27)
+#define GPSR6_USB1_PWEN BIT(26)
+#define GPSR6_USB0_OVC BIT(25)
+#define GPSR6_USB0_PWEN BIT(24)
+#define GPSR6_AUDIO_CLKB_B BIT(23)
+#define GPSR6_AUDIO_CLKA_A BIT(22)
+#define GPSR6_SSI_SDATA9_A BIT(21)
+#define GPSR6_SSI_SDATA8 BIT(20)
+#define GPSR6_SSI_SDATA7 BIT(19)
+#define GPSR6_SSI_WS78 BIT(18)
+#define GPSR6_SSI_SCK78 BIT(17)
+#define GPSR6_SSI_SDATA6 BIT(16)
+#define GPSR6_SSI_WS6 BIT(15)
+#define GPSR6_SSI_SCK6 BIT(14)
+#define GPSR6_SSI_SDATA5 BIT(13)
+#define GPSR6_SSI_WS5 BIT(12)
+#define GPSR6_SSI_SCK5 BIT(11)
+#define GPSR6_SSI_SDATA4 BIT(10)
+#define GPSR6_SSI_WS4 BIT(9)
+#define GPSR6_SSI_SCK4 BIT(8)
+#define GPSR6_SSI_SDATA3 BIT(7)
+#define GPSR6_SSI_WS34 BIT(6)
+#define GPSR6_SSI_SCK34 BIT(5)
+#define GPSR6_SSI_SDATA2_A BIT(4)
+#define GPSR6_SSI_SDATA1_A BIT(3)
+#define GPSR6_SSI_SDATA0 BIT(2)
+#define GPSR6_SSI_WS0129 BIT(1)
+#define GPSR6_SSI_SCK0129 BIT(0)
+#define GPSR7_AVS2 BIT(1)
+#define GPSR7_AVS1 BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V BIT(29)
+#define POC_SD3_DAT7_33V BIT(28)
+#define POC_SD3_DAT6_33V BIT(27)
+#define POC_SD3_DAT5_33V BIT(26)
+#define POC_SD3_DAT4_33V BIT(25)
+#define POC_SD3_DAT3_33V BIT(24)
+#define POC_SD3_DAT2_33V BIT(23)
+#define POC_SD3_DAT1_33V BIT(22)
+#define POC_SD3_DAT0_33V BIT(21)
+#define POC_SD3_CMD_33V BIT(20)
+#define POC_SD3_CLK_33V BIT(19)
+#define POC_SD2_DS_33V BIT(18)
+#define POC_SD2_DAT3_33V BIT(17)
+#define POC_SD2_DAT2_33V BIT(16)
+#define POC_SD2_DAT1_33V BIT(15)
+#define POC_SD2_DAT0_33V BIT(14)
+#define POC_SD2_CMD_33V BIT(13)
+#define POC_SD2_CLK_33V BIT(12)
+#define POC_SD1_DAT3_33V BIT(11)
+#define POC_SD1_DAT2_33V BIT(10)
+#define POC_SD1_DAT1_33V BIT(9)
+#define POC_SD1_DAT0_33V BIT(8)
+#define POC_SD1_CMD_33V BIT(7)
+#define POC_SD1_CLK_33V BIT(6)
+#define POC_SD0_DAT3_33V BIT(5)
+#define POC_SD0_DAT2_33V BIT(4)
+#define POC_SD0_DAT1_33V BIT(3)
+#define POC_SD0_DAT0_33V BIT(2)
+#define POC_SD0_CMD_33V BIT(1)
+#define POC_SD0_CLK_33V BIT(0)
+
+#define DRVCTRL0_MASK (0xCCCCCCCCU)
+#define DRVCTRL1_MASK (0xCCCCCCC8U)
+#define DRVCTRL2_MASK (0x88888888U)
+#define DRVCTRL3_MASK (0x88888888U)
+#define DRVCTRL4_MASK (0x88888888U)
+#define DRVCTRL5_MASK (0x88888888U)
+#define DRVCTRL6_MASK (0x88888888U)
+#define DRVCTRL7_MASK (0x88888888U)
+#define DRVCTRL8_MASK (0x88888888U)
+#define DRVCTRL9_MASK (0x88888888U)
+#define DRVCTRL10_MASK (0x88888888U)
+#define DRVCTRL11_MASK (0x888888CCU)
+#define DRVCTRL12_MASK (0xCCCFFFCFU)
+#define DRVCTRL13_MASK (0xCC888888U)
+#define DRVCTRL14_MASK (0x88888888U)
+#define DRVCTRL15_MASK (0x88888888U)
+#define DRVCTRL16_MASK (0x88888888U)
+#define DRVCTRL17_MASK (0x88888888U)
+#define DRVCTRL18_MASK (0x88888888U)
+#define DRVCTRL19_MASK (0x88888888U)
+#define DRVCTRL20_MASK (0x88888888U)
+#define DRVCTRL21_MASK (0x88888888U)
+#define DRVCTRL22_MASK (0x88888888U)
+#define DRVCTRL23_MASK (0x88888888U)
+#define DRVCTRL24_MASK (0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ mmio_write_32(PFC_PMMR, ~data);
+ mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_m3n(void)
+{
+ uint32_t reg;
+
+ /* initialize module select */
+ pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+ | MOD_SEL0_MSIOF2_A
+ | MOD_SEL0_MSIOF1_A
+ | MOD_SEL0_LBSC_A
+ | MOD_SEL0_IEBUS_A
+ | MOD_SEL0_I2C2_A
+ | MOD_SEL0_I2C1_A
+ | MOD_SEL0_HSCIF4_A
+ | MOD_SEL0_HSCIF3_A
+ | MOD_SEL0_HSCIF1_A
+ | MOD_SEL0_FSO_A
+ | MOD_SEL0_HSCIF2_A
+ | MOD_SEL0_ETHERAVB_A
+ | MOD_SEL0_DRIF3_A
+ | MOD_SEL0_DRIF2_A
+ | MOD_SEL0_DRIF1_A
+ | MOD_SEL0_DRIF0_A
+ | MOD_SEL0_CANFD0_A
+ | MOD_SEL0_ADG_A_A);
+ pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+ | MOD_SEL1_TSIF0_A
+ | MOD_SEL1_TIMER_TMU_A
+ | MOD_SEL1_SSP1_1_A
+ | MOD_SEL1_SSP1_0_A
+ | MOD_SEL1_SSI_A
+ | MOD_SEL1_SPEED_PULSE_IF_A
+ | MOD_SEL1_SIMCARD_A
+ | MOD_SEL1_SDHI2_A
+ | MOD_SEL1_SCIF4_A
+ | MOD_SEL1_SCIF3_A
+ | MOD_SEL1_SCIF2_A
+ | MOD_SEL1_SCIF1_A
+ | MOD_SEL1_SCIF_A
+ | MOD_SEL1_REMOCON_A
+ | MOD_SEL1_RCAN0_A
+ | MOD_SEL1_PWM6_A
+ | MOD_SEL1_PWM5_A
+ | MOD_SEL1_PWM4_A
+ | MOD_SEL1_PWM3_A
+ | MOD_SEL1_PWM2_A
+ | MOD_SEL1_PWM1_A);
+ pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+ | MOD_SEL2_I2C_3_A
+ | MOD_SEL2_I2C_0_A
+ | MOD_SEL2_FM_A
+ | MOD_SEL2_SCIF5_A
+ | MOD_SEL2_I2C6_A
+ | MOD_SEL2_NDF_A
+ | MOD_SEL2_SSI2_A
+ | MOD_SEL2_SSI9_A
+ | MOD_SEL2_TIMER_TMU2_A
+ | MOD_SEL2_ADG_B_A
+ | MOD_SEL2_ADG_C_A
+ | MOD_SEL2_VIN4_A);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(3)
+ | IPSR_8_FUNC(3)
+ | IPSR_4_FUNC(3)
+ | IPSR_0_FUNC(3));
+ pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+ | IPSR_24_FUNC(6)
+ | IPSR_20_FUNC(6)
+ | IPSR_16_FUNC(6)
+ | IPSR_12_FUNC(6)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_8_FUNC(6)
+ | IPSR_4_FUNC(6)
+ | IPSR_0_FUNC(6));
+ pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+ | IPSR_24_FUNC(1)
+ | IPSR_20_FUNC(1)
+ | IPSR_16_FUNC(1)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(4)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(1));
+ pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(4)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(3)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(3)
+ | IPSR_0_FUNC(8));
+ pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(1)
+ | IPSR_0_FUNC(0));
+ pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ /* initialize GPIO/perihperal function select */
+ pfc_reg_write(PFC_GPSR0, GPSR0_D15
+ | GPSR0_D14
+ | GPSR0_D13
+ | GPSR0_D12
+ | GPSR0_D11
+ | GPSR0_D10
+ | GPSR0_D9
+ | GPSR0_D8);
+ pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
+ | GPSR1_EX_WAIT0_A
+ | GPSR1_A19
+ | GPSR1_A18
+ | GPSR1_A17
+ | GPSR1_A16
+ | GPSR1_A15
+ | GPSR1_A14
+ | GPSR1_A13
+ | GPSR1_A12
+ | GPSR1_A7
+ | GPSR1_A6
+ | GPSR1_A5
+ | GPSR1_A4
+ | GPSR1_A3
+ | GPSR1_A2
+ | GPSR1_A1
+ | GPSR1_A0);
+ pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+ | GPSR2_AVB_AVTP_MATCH_A
+ | GPSR2_AVB_LINK
+ | GPSR2_AVB_PHY_INT
+ | GPSR2_AVB_MDC
+ | GPSR2_PWM2_A
+ | GPSR2_PWM1_A
+ | GPSR2_IRQ5
+ | GPSR2_IRQ4
+ | GPSR2_IRQ3
+ | GPSR2_IRQ2
+ | GPSR2_IRQ1
+ | GPSR2_IRQ0);
+ pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+ | GPSR3_SD0_CD
+ | GPSR3_SD1_DAT3
+ | GPSR3_SD1_DAT2
+ | GPSR3_SD1_DAT1
+ | GPSR3_SD1_DAT0
+ | GPSR3_SD0_DAT3
+ | GPSR3_SD0_DAT2
+ | GPSR3_SD0_DAT1
+ | GPSR3_SD0_DAT0
+ | GPSR3_SD0_CMD
+ | GPSR3_SD0_CLK);
+ pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+ | GPSR4_SD3_DAT6
+ | GPSR4_SD3_DAT3
+ | GPSR4_SD3_DAT2
+ | GPSR4_SD3_DAT1
+ | GPSR4_SD3_DAT0
+ | GPSR4_SD3_CMD
+ | GPSR4_SD3_CLK
+ | GPSR4_SD2_DS
+ | GPSR4_SD2_DAT3
+ | GPSR4_SD2_DAT2
+ | GPSR4_SD2_DAT1
+ | GPSR4_SD2_DAT0
+ | GPSR4_SD2_CMD
+ | GPSR4_SD2_CLK);
+ pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+ | GPSR5_MSIOF0_SS1
+ | GPSR5_MSIOF0_SYNC
+ | GPSR5_HRTS0
+ | GPSR5_HCTS0
+ | GPSR5_HTX0
+ | GPSR5_HRX0
+ | GPSR5_HSCK0
+ | GPSR5_RX2_A
+ | GPSR5_TX2_A
+ | GPSR5_SCK2
+ | GPSR5_RTS1
+ | GPSR5_CTS1
+ | GPSR5_TX1_A
+ | GPSR5_RX1_A
+ | GPSR5_RTS0
+ | GPSR5_SCK0);
+ pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+ | GPSR6_USB30_PWEN
+ | GPSR6_USB1_OVC
+ | GPSR6_USB1_PWEN
+ | GPSR6_USB0_OVC
+ | GPSR6_USB0_PWEN
+ | GPSR6_AUDIO_CLKB_B
+ | GPSR6_AUDIO_CLKA_A
+ | GPSR6_SSI_SDATA8
+ | GPSR6_SSI_SDATA7
+ | GPSR6_SSI_WS78
+ | GPSR6_SSI_SCK78
+ | GPSR6_SSI_WS6
+ | GPSR6_SSI_SCK6
+ | GPSR6_SSI_SDATA4
+ | GPSR6_SSI_WS4
+ | GPSR6_SSI_SCK4
+ | GPSR6_SSI_SDATA1_A
+ | GPSR6_SSI_SDATA0
+ | GPSR6_SSI_WS0129
+ | GPSR6_SSI_SCK0129);
+ pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
+ | GPSR7_AVS1);
+
+ /* initialize POC control register */
+ pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+ | POC_SD3_DAT7_33V
+ | POC_SD3_DAT6_33V
+ | POC_SD3_DAT5_33V
+ | POC_SD3_DAT4_33V
+ | POC_SD3_DAT3_33V
+ | POC_SD3_DAT2_33V
+ | POC_SD3_DAT1_33V
+ | POC_SD3_DAT0_33V
+ | POC_SD3_CMD_33V
+ | POC_SD3_CLK_33V
+ | POC_SD0_DAT3_33V
+ | POC_SD0_DAT2_33V
+ | POC_SD0_DAT1_33V
+ | POC_SD0_DAT0_33V
+ | POC_SD0_CMD_33V
+ | POC_SD0_CLK_33V);
+
+ /* initialize DRV control register */
+ reg = mmio_read_32(PFC_DRVCTRL0);
+ reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+ | DRVCTRL0_QSPI0_MOSI_IO0(3)
+ | DRVCTRL0_QSPI0_MISO_IO1(3)
+ | DRVCTRL0_QSPI0_IO2(3)
+ | DRVCTRL0_QSPI0_IO3(3)
+ | DRVCTRL0_QSPI0_SSL(3)
+ | DRVCTRL0_QSPI1_SPCLK(3)
+ | DRVCTRL0_QSPI1_MOSI_IO0(3));
+ pfc_reg_write(PFC_DRVCTRL0, reg);
+ reg = mmio_read_32(PFC_DRVCTRL1);
+ reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+ | DRVCTRL1_QSPI1_IO2(3)
+ | DRVCTRL1_QSPI1_IO3(3)
+ | DRVCTRL1_QSPI1_SS(3)
+ | DRVCTRL1_RPC_INT(3)
+ | DRVCTRL1_RPC_WP(3)
+ | DRVCTRL1_RPC_RESET(3)
+ | DRVCTRL1_AVB_RX_CTL(7));
+ pfc_reg_write(PFC_DRVCTRL1, reg);
+ reg = mmio_read_32(PFC_DRVCTRL2);
+ reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+ | DRVCTRL2_AVB_RD0(7)
+ | DRVCTRL2_AVB_RD1(7)
+ | DRVCTRL2_AVB_RD2(7)
+ | DRVCTRL2_AVB_RD3(7)
+ | DRVCTRL2_AVB_TX_CTL(3)
+ | DRVCTRL2_AVB_TXC(3)
+ | DRVCTRL2_AVB_TD0(3));
+ pfc_reg_write(PFC_DRVCTRL2, reg);
+ reg = mmio_read_32(PFC_DRVCTRL3);
+ reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+ | DRVCTRL3_AVB_TD2(3)
+ | DRVCTRL3_AVB_TD3(3)
+ | DRVCTRL3_AVB_TXCREFCLK(7)
+ | DRVCTRL3_AVB_MDIO(7)
+ | DRVCTRL3_AVB_MDC(7)
+ | DRVCTRL3_AVB_MAGIC(7)
+ | DRVCTRL3_AVB_PHY_INT(7));
+ pfc_reg_write(PFC_DRVCTRL3, reg);
+ reg = mmio_read_32(PFC_DRVCTRL4);
+ reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+ | DRVCTRL4_AVB_AVTP_MATCH(7)
+ | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+ | DRVCTRL4_IRQ0(7)
+ | DRVCTRL4_IRQ1(7)
+ | DRVCTRL4_IRQ2(7)
+ | DRVCTRL4_IRQ3(7)
+ | DRVCTRL4_IRQ4(7));
+ pfc_reg_write(PFC_DRVCTRL4, reg);
+ reg = mmio_read_32(PFC_DRVCTRL5);
+ reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+ | DRVCTRL5_PWM0(7)
+ | DRVCTRL5_PWM1(7)
+ | DRVCTRL5_PWM2(7)
+ | DRVCTRL5_A0(3)
+ | DRVCTRL5_A1(3)
+ | DRVCTRL5_A2(3)
+ | DRVCTRL5_A3(3));
+ pfc_reg_write(PFC_DRVCTRL5, reg);
+ reg = mmio_read_32(PFC_DRVCTRL6);
+ reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+ | DRVCTRL6_A5(3)
+ | DRVCTRL6_A6(3)
+ | DRVCTRL6_A7(3)
+ | DRVCTRL6_A8(7)
+ | DRVCTRL6_A9(7)
+ | DRVCTRL6_A10(7)
+ | DRVCTRL6_A11(7));
+ pfc_reg_write(PFC_DRVCTRL6, reg);
+ reg = mmio_read_32(PFC_DRVCTRL7);
+ reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+ | DRVCTRL7_A13(3)
+ | DRVCTRL7_A14(3)
+ | DRVCTRL7_A15(3)
+ | DRVCTRL7_A16(3)
+ | DRVCTRL7_A17(3)
+ | DRVCTRL7_A18(3)
+ | DRVCTRL7_A19(3));
+ pfc_reg_write(PFC_DRVCTRL7, reg);
+ reg = mmio_read_32(PFC_DRVCTRL8);
+ reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+ | DRVCTRL8_CS0(7)
+ | DRVCTRL8_CS1_A2(7)
+ | DRVCTRL8_BS(7)
+ | DRVCTRL8_RD(7)
+ | DRVCTRL8_RD_W(7)
+ | DRVCTRL8_WE0(7)
+ | DRVCTRL8_WE1(7));
+ pfc_reg_write(PFC_DRVCTRL8, reg);
+ reg = mmio_read_32(PFC_DRVCTRL9);
+ reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+ | DRVCTRL9_PRESETOU(7)
+ | DRVCTRL9_D0(7)
+ | DRVCTRL9_D1(7)
+ | DRVCTRL9_D2(7)
+ | DRVCTRL9_D3(7)
+ | DRVCTRL9_D4(7)
+ | DRVCTRL9_D5(7));
+ pfc_reg_write(PFC_DRVCTRL9, reg);
+ reg = mmio_read_32(PFC_DRVCTRL10);
+ reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+ | DRVCTRL10_D7(7)
+ | DRVCTRL10_D8(3)
+ | DRVCTRL10_D9(3)
+ | DRVCTRL10_D10(3)
+ | DRVCTRL10_D11(3)
+ | DRVCTRL10_D12(3)
+ | DRVCTRL10_D13(3));
+ pfc_reg_write(PFC_DRVCTRL10, reg);
+ reg = mmio_read_32(PFC_DRVCTRL11);
+ reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+ | DRVCTRL11_D15(3)
+ | DRVCTRL11_AVS1(7)
+ | DRVCTRL11_AVS2(7)
+ | DRVCTRL11_GP7_02(7)
+ | DRVCTRL11_GP7_03(7)
+ | DRVCTRL11_DU_DOTCLKIN0(3)
+ | DRVCTRL11_DU_DOTCLKIN1(3));
+ pfc_reg_write(PFC_DRVCTRL11, reg);
+ reg = mmio_read_32(PFC_DRVCTRL12);
+ reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+ | DRVCTRL12_DU_DOTCLKIN3(3)
+ | DRVCTRL12_DU_FSCLKST(3)
+ | DRVCTRL12_DU_TMS(3));
+ pfc_reg_write(PFC_DRVCTRL12, reg);
+ reg = mmio_read_32(PFC_DRVCTRL13);
+ reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+ | DRVCTRL13_ASEBRK(3)
+ | DRVCTRL13_SD0_CLK(7)
+ | DRVCTRL13_SD0_CMD(7)
+ | DRVCTRL13_SD0_DAT0(7)
+ | DRVCTRL13_SD0_DAT1(7)
+ | DRVCTRL13_SD0_DAT2(7)
+ | DRVCTRL13_SD0_DAT3(7));
+ pfc_reg_write(PFC_DRVCTRL13, reg);
+ reg = mmio_read_32(PFC_DRVCTRL14);
+ reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+ | DRVCTRL14_SD1_CMD(7)
+ | DRVCTRL14_SD1_DAT0(5)
+ | DRVCTRL14_SD1_DAT1(5)
+ | DRVCTRL14_SD1_DAT2(5)
+ | DRVCTRL14_SD1_DAT3(5)
+ | DRVCTRL14_SD2_CLK(5)
+ | DRVCTRL14_SD2_CMD(5));
+ pfc_reg_write(PFC_DRVCTRL14, reg);
+ reg = mmio_read_32(PFC_DRVCTRL15);
+ reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+ | DRVCTRL15_SD2_DAT1(5)
+ | DRVCTRL15_SD2_DAT2(5)
+ | DRVCTRL15_SD2_DAT3(5)
+ | DRVCTRL15_SD2_DS(5)
+ | DRVCTRL15_SD3_CLK(7)
+ | DRVCTRL15_SD3_CMD(7)
+ | DRVCTRL15_SD3_DAT0(7));
+ pfc_reg_write(PFC_DRVCTRL15, reg);
+ reg = mmio_read_32(PFC_DRVCTRL16);
+ reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
+ | DRVCTRL16_SD3_DAT2(7)
+ | DRVCTRL16_SD3_DAT3(7)
+ | DRVCTRL16_SD3_DAT4(7)
+ | DRVCTRL16_SD3_DAT5(7)
+ | DRVCTRL16_SD3_DAT6(7)
+ | DRVCTRL16_SD3_DAT7(7)
+ | DRVCTRL16_SD3_DS(7));
+ pfc_reg_write(PFC_DRVCTRL16, reg);
+ reg = mmio_read_32(PFC_DRVCTRL17);
+ reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+ | DRVCTRL17_SD0_WP(7)
+ | DRVCTRL17_SD1_CD(7)
+ | DRVCTRL17_SD1_WP(7)
+ | DRVCTRL17_SCK0(7)
+ | DRVCTRL17_RX0(7)
+ | DRVCTRL17_TX0(7)
+ | DRVCTRL17_CTS0(7));
+ pfc_reg_write(PFC_DRVCTRL17, reg);
+ reg = mmio_read_32(PFC_DRVCTRL18);
+ reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+ | DRVCTRL18_RX1(7)
+ | DRVCTRL18_TX1(7)
+ | DRVCTRL18_CTS1(7)
+ | DRVCTRL18_RTS1_TANS(7)
+ | DRVCTRL18_SCK2(7)
+ | DRVCTRL18_TX2(7)
+ | DRVCTRL18_RX2(7));
+ pfc_reg_write(PFC_DRVCTRL18, reg);
+ reg = mmio_read_32(PFC_DRVCTRL19);
+ reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+ | DRVCTRL19_HRX0(7)
+ | DRVCTRL19_HTX0(7)
+ | DRVCTRL19_HCTS0(7)
+ | DRVCTRL19_HRTS0(7)
+ | DRVCTRL19_MSIOF0_SCK(7)
+ | DRVCTRL19_MSIOF0_SYNC(7)
+ | DRVCTRL19_MSIOF0_SS1(7));
+ pfc_reg_write(PFC_DRVCTRL19, reg);
+ reg = mmio_read_32(PFC_DRVCTRL20);
+ reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+ | DRVCTRL20_MSIOF0_SS2(7)
+ | DRVCTRL20_MSIOF0_RXD(7)
+ | DRVCTRL20_MLB_CLK(7)
+ | DRVCTRL20_MLB_SIG(7)
+ | DRVCTRL20_MLB_DAT(7)
+ | DRVCTRL20_MLB_REF(7)
+ | DRVCTRL20_SSI_SCK0129(7));
+ pfc_reg_write(PFC_DRVCTRL20, reg);
+ reg = mmio_read_32(PFC_DRVCTRL21);
+ reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+ | DRVCTRL21_SSI_SDATA0(7)
+ | DRVCTRL21_SSI_SDATA1(7)
+ | DRVCTRL21_SSI_SDATA2(7)
+ | DRVCTRL21_SSI_SCK34(7)
+ | DRVCTRL21_SSI_WS34(7)
+ | DRVCTRL21_SSI_SDATA3(7)
+ | DRVCTRL21_SSI_SCK4(7));
+ pfc_reg_write(PFC_DRVCTRL21, reg);
+ reg = mmio_read_32(PFC_DRVCTRL22);
+ reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+ | DRVCTRL22_SSI_SDATA4(7)
+ | DRVCTRL22_SSI_SCK5(7)
+ | DRVCTRL22_SSI_WS5(7)
+ | DRVCTRL22_SSI_SDATA5(7)
+ | DRVCTRL22_SSI_SCK6(7)
+ | DRVCTRL22_SSI_WS6(7)
+ | DRVCTRL22_SSI_SDATA6(7));
+ pfc_reg_write(PFC_DRVCTRL22, reg);
+ reg = mmio_read_32(PFC_DRVCTRL23);
+ reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+ | DRVCTRL23_SSI_WS78(7)
+ | DRVCTRL23_SSI_SDATA7(7)
+ | DRVCTRL23_SSI_SDATA8(7)
+ | DRVCTRL23_SSI_SDATA9(7)
+ | DRVCTRL23_AUDIO_CLKA(7)
+ | DRVCTRL23_AUDIO_CLKB(7)
+ | DRVCTRL23_USB0_PWEN(7));
+ pfc_reg_write(PFC_DRVCTRL23, reg);
+ reg = mmio_read_32(PFC_DRVCTRL24);
+ reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+ | DRVCTRL24_USB1_PWEN(7)
+ | DRVCTRL24_USB1_OVC(7)
+ | DRVCTRL24_USB30_PWEN(7)
+ | DRVCTRL24_USB30_OVC(7)
+ | DRVCTRL24_USB31_PWEN(7)
+ | DRVCTRL24_USB31_OVC(7));
+ pfc_reg_write(PFC_DRVCTRL24, reg);
+
+ /* initialize LSI pin pull-up/down control */
+ pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+ pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+ pfc_reg_write(PFC_PUD2, 0x330001E6U);
+ pfc_reg_write(PFC_PUD3, 0x000002E0U);
+ pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+ pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+ pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+ /* initialize LSI pin pull-enable register */
+ pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+ pfc_reg_write(PFC_PUEN1, 0x00100234U);
+ pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+ pfc_reg_write(PFC_PUEN3, 0x00000200U);
+ pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+ pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+ pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+ mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+ mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+#if (RCAR_GEN3_ULCB == 1)
+ mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
+#else
+ mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+#endif
+ mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
+}
diff --git a/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.h b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.h
new file mode 100644
index 0000000..3e6f879
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_M3N_H
+#define PFC_INIT_M3N_H
+
+void pfc_init_m3n(void);
+
+#endif /* PFC_INIT_M3N_H */
diff --git a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
new file mode 100644
index 0000000..6063758
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
@@ -0,0 +1,906 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h> /* for uint32_t */
+#include <lib/mmio.h>
+#include "pfc_init_v3m.h"
+#include "include/rcar_def.h"
+#include "rcar_private.h"
+#include "../pfc_regs.h"
+
+/* Pin functon bit */
+#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
+#define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)
+#define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)
+#define GPSR0_DU_DOTCLKOUT BIT(18)
+#define GPSR0_DU_DB7 BIT(17)
+#define GPSR0_DU_DB6 BIT(16)
+#define GPSR0_DU_DB5 BIT(15)
+#define GPSR0_DU_DB4 BIT(14)
+#define GPSR0_DU_DB3 BIT(13)
+#define GPSR0_DU_DB2 BIT(12)
+#define GPSR0_DU_DG7 BIT(11)
+#define GPSR0_DU_DG6 BIT(10)
+#define GPSR0_DU_DG5 BIT(9)
+#define GPSR0_DU_DG4 BIT(8)
+#define GPSR0_DU_DG3 BIT(7)
+#define GPSR0_DU_DG2 BIT(6)
+#define GPSR0_DU_DR7 BIT(5)
+#define GPSR0_DU_DR6 BIT(4)
+#define GPSR0_DU_DR5 BIT(3)
+#define GPSR0_DU_DR4 BIT(2)
+#define GPSR0_DU_DR3 BIT(1)
+#define GPSR0_DU_DR2 BIT(0)
+
+#define GPSR1_DIGRF_CLKOUT BIT(27)
+#define GPSR1_DIGRF_CLKIN BIT(26)
+#define GPSR1_CANFD_CLK BIT(25)
+#define GPSR1_CANFD1_RX BIT(24)
+#define GPSR1_CANFD1_TX BIT(23)
+#define GPSR1_CANFD0_RX BIT(22)
+#define GPSR1_CANFD0_TX BIT(21)
+#define GPSR1_AVB0_AVTP_CAPTURE BIT(20)
+#define GPSR1_AVB0_AVTP_MATCH BIT(19)
+#define GPSR1_AVB0_LINK BIT(18)
+#define GPSR1_AVB0_PHY_INT BIT(17)
+#define GPSR1_AVB0_MAGIC BIT(16)
+#define GPSR1_AVB0_MDC BIT(15)
+#define GPSR1_AVB0_MDIO BIT(14)
+#define GPSR1_AVB0_TXCREFCLK BIT(13)
+#define GPSR1_AVB0_TD3 BIT(12)
+#define GPSR1_AVB0_TD2 BIT(11)
+#define GPSR1_AVB0_TD1 BIT(10)
+#define GPSR1_AVB0_TD0 BIT(9)
+#define GPSR1_AVB0_TXC BIT(8)
+#define GPSR1_AVB0_TX_CTL BIT(7)
+#define GPSR1_AVB0_RD3 BIT(6)
+#define GPSR1_AVB0_RD2 BIT(5)
+#define GPSR1_AVB0_RD1 BIT(4)
+#define GPSR1_AVB0_RD0 BIT(3)
+#define GPSR1_AVB0_RXC BIT(2)
+#define GPSR1_AVB0_RX_CTL BIT(1)
+#define GPSR1_IRQ0 BIT(0)
+
+#define GPSR2_VI0_FIELD BIT(16)
+#define GPSR2_VI0_DATA11 BIT(15)
+#define GPSR2_VI0_DATA10 BIT(14)
+#define GPSR2_VI0_DATA9 BIT(13)
+#define GPSR2_VI0_DATA8 BIT(12)
+#define GPSR2_VI0_DATA7 BIT(11)
+#define GPSR2_VI0_DATA6 BIT(10)
+#define GPSR2_VI0_DATA5 BIT(9)
+#define GPSR2_VI0_DATA4 BIT(8)
+#define GPSR2_VI0_DATA3 BIT(7)
+#define GPSR2_VI0_DATA2 BIT(6)
+#define GPSR2_VI0_DATA1 BIT(5)
+#define GPSR2_VI0_DATA0 BIT(4)
+#define GPSR2_VI0_VSYNC_N BIT(3)
+#define GPSR2_VI0_HSYNC_N BIT(2)
+#define GPSR2_VI0_CLKENB BIT(1)
+#define GPSR2_VI0_CLK BIT(0)
+
+#define GPSR3_VI1_FIELD BIT(16)
+#define GPSR3_VI1_DATA11 BIT(15)
+#define GPSR3_VI1_DATA10 BIT(14)
+#define GPSR3_VI1_DATA9 BIT(13)
+#define GPSR3_VI1_DATA8 BIT(12)
+#define GPSR3_VI1_DATA7 BIT(11)
+#define GPSR3_VI1_DATA6 BIT(10)
+#define GPSR3_VI1_DATA5 BIT(9)
+#define GPSR3_VI1_DATA4 BIT(8)
+#define GPSR3_VI1_DATA3 BIT(7)
+#define GPSR3_VI1_DATA2 BIT(6)
+#define GPSR3_VI1_DATA1 BIT(5)
+#define GPSR3_VI1_DATA0 BIT(4)
+#define GPSR3_VI1_VSYNC_N BIT(3)
+#define GPSR3_VI1_HSYNC_N BIT(2)
+#define GPSR3_VI1_CLKENB BIT(1)
+#define GPSR3_VI1_CLK BIT(0)
+
+#define GPSR4_SDA2 BIT(5)
+#define GPSR4_SCL2 BIT(4)
+#define GPSR4_SDA1 BIT(3)
+#define GPSR4_SCL1 BIT(2)
+#define GPSR4_SDA0 BIT(1)
+#define GPSR4_SCL0 BIT(0)
+
+#define GPSR5_RPC_INT_N BIT(14)
+#define GPSR5_RPC_WP_N BIT(13)
+#define GPSR5_RPC_RESET_N BIT(12)
+#define GPSR5_QSPI1_SSL BIT(11)
+#define GPSR5_QSPI1_IO3 BIT(10)
+#define GPSR5_QSPI1_IO2 BIT(9)
+#define GPSR5_QSPI1_MISO_IO1 BIT(8)
+#define GPSR5_QSPI1_MOSI_IO0 BIT(7)
+#define GPSR5_QSPI1_SPCLK BIT(6)
+#define GPSR5_QSPI0_SSL BIT(5)
+#define GPSR5_QSPI0_IO3 BIT(4)
+#define GPSR5_QSPI0_IO2 BIT(3)
+#define GPSR5_QSPI0_MISO_IO1 BIT(2)
+#define GPSR5_QSPI0_MOSI_IO0 BIT(1)
+#define GPSR5_QSPI0_SPCLK BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define IOCTRL30_POC_VI0_DATA5 BIT(31)
+#define IOCTRL30_POC_VI0_DATA4 BIT(30)
+#define IOCTRL30_POC_VI0_DATA3 BIT(29)
+#define IOCTRL30_POC_VI0_DATA2 BIT(28)
+#define IOCTRL30_POC_VI0_DATA1 BIT(27)
+#define IOCTRL30_POC_VI0_DATA0 BIT(26)
+#define IOCTRL30_POC_VI0_VSYNC_N BIT(25)
+#define IOCTRL30_POC_VI0_HSYNC_N BIT(24)
+#define IOCTRL30_POC_VI0_CLKENB BIT(23)
+#define IOCTRL30_POC_VI0_CLK BIT(22)
+#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
+#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC BIT(20)
+#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC BIT(19)
+#define IOCTRL30_POC_DU_DOTCLKOUT BIT(18)
+#define IOCTRL30_POC_DU_DB7 BIT(17)
+#define IOCTRL30_POC_DU_DB6 BIT(16)
+#define IOCTRL30_POC_DU_DB5 BIT(15)
+#define IOCTRL30_POC_DU_DB4 BIT(14)
+#define IOCTRL30_POC_DU_DB3 BIT(13)
+#define IOCTRL30_POC_DU_DB2 BIT(12)
+#define IOCTRL30_POC_DU_DG7 BIT(11)
+#define IOCTRL30_POC_DU_DG6 BIT(10)
+#define IOCTRL30_POC_DU_DG5 BIT(9)
+#define IOCTRL30_POC_DU_DG4 BIT(8)
+#define IOCTRL30_POC_DU_DG3 BIT(7)
+#define IOCTRL30_POC_DU_DG2 BIT(6)
+#define IOCTRL30_POC_DU_DR7 BIT(5)
+#define IOCTRL30_POC_DU_DR6 BIT(4)
+#define IOCTRL30_POC_DU_DR5 BIT(3)
+#define IOCTRL30_POC_DU_DR4 BIT(2)
+#define IOCTRL30_POC_DU_DR3 BIT(1)
+#define IOCTRL30_POC_DU_DR2 BIT(0)
+
+#define IOCTRL31_POC_DUMMY_31 BIT(31)
+#define IOCTRL31_POC_DUMMY_30 BIT(30)
+#define IOCTRL31_POC_DUMMY_29 BIT(29)
+#define IOCTRL31_POC_DUMMY_28 BIT(28)
+#define IOCTRL31_POC_DUMMY_27 BIT(27)
+#define IOCTRL31_POC_DUMMY_26 BIT(26)
+#define IOCTRL31_POC_DUMMY_25 BIT(25)
+#define IOCTRL31_POC_DUMMY_24 BIT(24)
+#define IOCTRL31_POC_VI1_FIELD BIT(23)
+#define IOCTRL31_POC_VI1_DATA11 BIT(22)
+#define IOCTRL31_POC_VI1_DATA10 BIT(21)
+#define IOCTRL31_POC_VI1_DATA9 BIT(20)
+#define IOCTRL31_POC_VI1_DATA8 BIT(19)
+#define IOCTRL31_POC_VI1_DATA7 BIT(18)
+#define IOCTRL31_POC_VI1_DATA6 BIT(17)
+#define IOCTRL31_POC_VI1_DATA5 BIT(16)
+#define IOCTRL31_POC_VI1_DATA4 BIT(15)
+#define IOCTRL31_POC_VI1_DATA3 BIT(14)
+#define IOCTRL31_POC_VI1_DATA2 BIT(13)
+#define IOCTRL31_POC_VI1_DATA1 BIT(12)
+#define IOCTRL31_POC_VI1_DATA0 BIT(11)
+#define IOCTRL31_POC_VI1_VSYNC_N BIT(10)
+#define IOCTRL31_POC_VI1_HSYNC_N BIT(9)
+#define IOCTRL31_POC_VI1_CLKENB BIT(8)
+#define IOCTRL31_POC_VI1_CLK BIT(7)
+#define IOCTRL31_POC_VI0_FIELD BIT(6)
+#define IOCTRL31_POC_VI0_DATA11 BIT(5)
+#define IOCTRL31_POC_VI0_DATA10 BIT(4)
+#define IOCTRL31_POC_VI0_DATA9 BIT(3)
+#define IOCTRL31_POC_VI0_DATA8 BIT(2)
+#define IOCTRL31_POC_VI0_DATA7 BIT(1)
+#define IOCTRL31_POC_VI0_DATA6 BIT(0)
+#define IOCTRL32_POC2_VREF BIT(0)
+#define IOCTRL40_SD0TDSEL1 BIT(1)
+#define IOCTRL40_SD0TDSEL0 BIT(0)
+
+#define PUEN0_PUEN_VI0_CLK BIT(31)
+#define PUEN0_PUEN_TDI BIT(30)
+#define PUEN0_PUEN_TMS BIT(29)
+#define PUEN0_PUEN_TCK BIT(28)
+#define PUEN0_PUEN_TRST_N BIT(27)
+#define PUEN0_PUEN_IRQ0 BIT(26)
+#define PUEN0_PUEN_FSCLKST_N BIT(25)
+#define PUEN0_PUEN_EXTALR BIT(24)
+#define PUEN0_PUEN_PRESETOUT_N BIT(23)
+#define PUEN0_PUEN_DU_DOTCLKIN BIT(22)
+#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
+#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC BIT(20)
+#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC BIT(19)
+#define PUEN0_PUEN_DU_DOTCLKOUT BIT(18)
+#define PUEN0_PUEN_DU_DB7 BIT(17)
+#define PUEN0_PUEN_DU_DB6 BIT(16)
+#define PUEN0_PUEN_DU_DB5 BIT(15)
+#define PUEN0_PUEN_DU_DB4 BIT(14)
+#define PUEN0_PUEN_DU_DB3 BIT(13)
+#define PUEN0_PUEN_DU_DB2 BIT(12)
+#define PUEN0_PUEN_DU_DG7 BIT(11)
+#define PUEN0_PUEN_DU_DG6 BIT(10)
+#define PUEN0_PUEN_DU_DG5 BIT(9)
+#define PUEN0_PUEN_DU_DG4 BIT(8)
+#define PUEN0_PUEN_DU_DG3 BIT(7)
+#define PUEN0_PUEN_DU_DG2 BIT(6)
+#define PUEN0_PUEN_DU_DR7 BIT(5)
+#define PUEN0_PUEN_DU_DR6 BIT(4)
+#define PUEN0_PUEN_DU_DR5 BIT(3)
+#define PUEN0_PUEN_DU_DR4 BIT(2)
+#define PUEN0_PUEN_DU_DR3 BIT(1)
+#define PUEN0_PUEN_DU_DR2 BIT(0)
+
+#define PUEN1_PUEN_VI1_DATA11 BIT(31)
+#define PUEN1_PUEN_VI1_DATA10 BIT(30)
+#define PUEN1_PUEN_VI1_DATA9 BIT(29)
+#define PUEN1_PUEN_VI1_DATA8 BIT(28)
+#define PUEN1_PUEN_VI1_DATA7 BIT(27)
+#define PUEN1_PUEN_VI1_DATA6 BIT(26)
+#define PUEN1_PUEN_VI1_DATA5 BIT(25)
+#define PUEN1_PUEN_VI1_DATA4 BIT(24)
+#define PUEN1_PUEN_VI1_DATA3 BIT(23)
+#define PUEN1_PUEN_VI1_DATA2 BIT(22)
+#define PUEN1_PUEN_VI1_DATA1 BIT(21)
+#define PUEN1_PUEN_VI1_DATA0 BIT(20)
+#define PUEN1_PUEN_VI1_VSYNC_N BIT(19)
+#define PUEN1_PUEN_VI1_HSYNC_N BIT(18)
+#define PUEN1_PUEN_VI1_CLKENB BIT(17)
+#define PUEN1_PUEN_VI1_CLK BIT(16)
+#define PUEN1_PUEN_VI0_FIELD BIT(15)
+#define PUEN1_PUEN_VI0_DATA11 BIT(14)
+#define PUEN1_PUEN_VI0_DATA10 BIT(13)
+#define PUEN1_PUEN_VI0_DATA9 BIT(12)
+#define PUEN1_PUEN_VI0_DATA8 BIT(11)
+#define PUEN1_PUEN_VI0_DATA7 BIT(10)
+#define PUEN1_PUEN_VI0_DATA6 BIT(9)
+#define PUEN1_PUEN_VI0_DATA5 BIT(8)
+#define PUEN1_PUEN_VI0_DATA4 BIT(7)
+#define PUEN1_PUEN_VI0_DATA3 BIT(6)
+#define PUEN1_PUEN_VI0_DATA2 BIT(5)
+#define PUEN1_PUEN_VI0_DATA1 BIT(4)
+#define PUEN1_PUEN_VI0_DATA0 BIT(3)
+#define PUEN1_PUEN_VI0_VSYNC_N BIT(2)
+#define PUEN1_PUEN_VI0_HSYNC_N BIT(1)
+#define PUEN1_PUEN_VI0_CLKENB BIT(0)
+
+#define PUEN2_PUEN_CANFD_CLK BIT(31)
+#define PUEN2_PUEN_CANFD1_RX BIT(30)
+#define PUEN2_PUEN_CANFD1_TX BIT(29)
+#define PUEN2_PUEN_CANFD0_RX BIT(28)
+#define PUEN2_PUEN_CANFD0_TX BIT(27)
+#define PUEN2_PUEN_AVB0_AVTP_CAPTURE BIT(26)
+#define PUEN2_PUEN_AVB0_AVTP_MATCH BIT(25)
+#define PUEN2_PUEN_AVB0_LINK BIT(24)
+#define PUEN2_PUEN_AVB0_PHY_INT BIT(23)
+#define PUEN2_PUEN_AVB0_MAGIC BIT(22)
+#define PUEN2_PUEN_AVB0_MDC BIT(21)
+#define PUEN2_PUEN_AVB0_MDIO BIT(20)
+#define PUEN2_PUEN_AVB0_TXCREFCLK BIT(19)
+#define PUEN2_PUEN_AVB0_TD3 BIT(18)
+#define PUEN2_PUEN_AVB0_TD2 BIT(17)
+#define PUEN2_PUEN_AVB0_TD1 BIT(16)
+#define PUEN2_PUEN_AVB0_TD0 BIT(15)
+#define PUEN2_PUEN_AVB0_TXC BIT(14)
+#define PUEN2_PUEN_AVB0_TX_CTL BIT(13)
+#define PUEN2_PUEN_AVB0_RD3 BIT(12)
+#define PUEN2_PUEN_AVB0_RD2 BIT(11)
+#define PUEN2_PUEN_AVB0_RD1 BIT(10)
+#define PUEN2_PUEN_AVB0_RD0 BIT(9)
+#define PUEN2_PUEN_AVB0_RXC BIT(8)
+#define PUEN2_PUEN_AVB0_RX_CTL BIT(7)
+#define PUEN2_PUEN_SDA2 BIT(6)
+#define PUEN2_PUEN_SCL2 BIT(5)
+#define PUEN2_PUEN_SDA1 BIT(4)
+#define PUEN2_PUEN_SCL1 BIT(3)
+#define PUEN2_PUEN_SDA0 BIT(2)
+#define PUEN2_PUEN_SCL0 BIT(1)
+#define PUEN2_PUEN_VI1_FIELD BIT(0)
+
+#define PUEN3_PUEN_DIGRF_CLKOUT BIT(16)
+#define PUEN3_PUEN_DIGRF_CLKIN BIT(15)
+#define PUEN3_PUEN_RPC_INT_N BIT(14)
+#define PUEN3_PUEN_RPC_WP_N BIT(13)
+#define PUEN3_PUEN_RPC_RESET_N BIT(12)
+#define PUEN3_PUEN_QSPI1_SSL BIT(11)
+#define PUEN3_PUEN_QSPI1_IO3 BIT(10)
+#define PUEN3_PUEN_QSPI1_IO2 BIT(9)
+#define PUEN3_PUEN_QSPI1_MISO_IO1 BIT(8)
+#define PUEN3_PUEN_QSPI1_MOSI_IO0 BIT(7)
+#define PUEN3_PUEN_QSPI1_SPCLK BIT(6)
+#define PUEN3_PUEN_QSPI0_SSL BIT(5)
+#define PUEN3_PUEN_QSPI0_IO3 BIT(4)
+#define PUEN3_PUEN_QSPI0_IO2 BIT(3)
+#define PUEN3_PUEN_QSPI0_MISO_IO1 BIT(2)
+#define PUEN3_PUEN_QSPI0_MOSI_IO0 BIT(1)
+#define PUEN3_PUEN_QSPI0_SPCLK BIT(0)
+
+#define PUD0_PUD_VI0_CLK BIT(31)
+#define PUD0_PUD_IRQ0 BIT(26)
+#define PUD0_PUD_FSCLKST_N BIT(25)
+#define PUD0_PUD_PRESETOUT_N BIT(23)
+#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
+#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC BIT(20)
+#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC BIT(19)
+#define PUD0_PUD_DU_DOTCLKOUT BIT(18)
+#define PUD0_PUD_DU_DB7 BIT(17)
+#define PUD0_PUD_DU_DB6 BIT(16)
+#define PUD0_PUD_DU_DB5 BIT(15)
+#define PUD0_PUD_DU_DB4 BIT(14)
+#define PUD0_PUD_DU_DB3 BIT(13)
+#define PUD0_PUD_DU_DB2 BIT(12)
+#define PUD0_PUD_DU_DG7 BIT(11)
+#define PUD0_PUD_DU_DG6 BIT(10)
+#define PUD0_PUD_DU_DG5 BIT(9)
+#define PUD0_PUD_DU_DG4 BIT(8)
+#define PUD0_PUD_DU_DG3 BIT(7)
+#define PUD0_PUD_DU_DG2 BIT(6)
+#define PUD0_PUD_DU_DR7 BIT(5)
+#define PUD0_PUD_DU_DR6 BIT(4)
+#define PUD0_PUD_DU_DR5 BIT(3)
+#define PUD0_PUD_DU_DR4 BIT(2)
+#define PUD0_PUD_DU_DR3 BIT(1)
+#define PUD0_PUD_DU_DR2 BIT(0)
+
+#define PUD1_PUD_VI1_DATA11 BIT(31)
+#define PUD1_PUD_VI1_DATA10 BIT(30)
+#define PUD1_PUD_VI1_DATA9 BIT(29)
+#define PUD1_PUD_VI1_DATA8 BIT(28)
+#define PUD1_PUD_VI1_DATA7 BIT(27)
+#define PUD1_PUD_VI1_DATA6 BIT(26)
+#define PUD1_PUD_VI1_DATA5 BIT(25)
+#define PUD1_PUD_VI1_DATA4 BIT(24)
+#define PUD1_PUD_VI1_DATA3 BIT(23)
+#define PUD1_PUD_VI1_DATA2 BIT(22)
+#define PUD1_PUD_VI1_DATA1 BIT(21)
+#define PUD1_PUD_VI1_DATA0 BIT(20)
+#define PUD1_PUD_VI1_VSYNC_N BIT(19)
+#define PUD1_PUD_VI1_HSYNC_N BIT(18)
+#define PUD1_PUD_VI1_CLKENB BIT(17)
+#define PUD1_PUD_VI1_CLK BIT(16)
+#define PUD1_PUD_VI0_FIELD BIT(15)
+#define PUD1_PUD_VI0_DATA11 BIT(14)
+#define PUD1_PUD_VI0_DATA10 BIT(13)
+#define PUD1_PUD_VI0_DATA9 BIT(12)
+#define PUD1_PUD_VI0_DATA8 BIT(11)
+#define PUD1_PUD_VI0_DATA7 BIT(10)
+#define PUD1_PUD_VI0_DATA6 BIT(9)
+#define PUD1_PUD_VI0_DATA5 BIT(8)
+#define PUD1_PUD_VI0_DATA4 BIT(7)
+#define PUD1_PUD_VI0_DATA3 BIT(6)
+#define PUD1_PUD_VI0_DATA2 BIT(5)
+#define PUD1_PUD_VI0_DATA1 BIT(4)
+#define PUD1_PUD_VI0_DATA0 BIT(3)
+#define PUD1_PUD_VI0_VSYNC_N BIT(2)
+#define PUD1_PUD_VI0_HSYNC_N BIT(1)
+#define PUD1_PUD_VI0_CLKENB BIT(0)
+
+#define PUD2_PUD_CANFD_CLK BIT(31)
+#define PUD2_PUD_CANFD1_RX BIT(30)
+#define PUD2_PUD_CANFD1_TX BIT(29)
+#define PUD2_PUD_CANFD0_RX BIT(28)
+#define PUD2_PUD_CANFD0_TX BIT(27)
+#define PUD2_PUD_AVB0_AVTP_CAPTURE BIT(26)
+#define PUD2_PUD_AVB0_AVTP_MATCH BIT(25)
+#define PUD2_PUD_AVB0_LINK BIT(24)
+#define PUD2_PUD_AVB0_PHY_INT BIT(23)
+#define PUD2_PUD_AVB0_MAGIC BIT(22)
+#define PUD2_PUD_AVB0_MDC BIT(21)
+#define PUD2_PUD_AVB0_MDIO BIT(20)
+#define PUD2_PUD_AVB0_TXCREFCLK BIT(19)
+#define PUD2_PUD_AVB0_TD3 BIT(18)
+#define PUD2_PUD_AVB0_TD2 BIT(17)
+#define PUD2_PUD_AVB0_TD1 BIT(16)
+#define PUD2_PUD_AVB0_TD0 BIT(15)
+#define PUD2_PUD_AVB0_TXC BIT(14)
+#define PUD2_PUD_AVB0_TX_CTL BIT(13)
+#define PUD2_PUD_AVB0_RD3 BIT(12)
+#define PUD2_PUD_AVB0_RD2 BIT(11)
+#define PUD2_PUD_AVB0_RD1 BIT(10)
+#define PUD2_PUD_AVB0_RD0 BIT(9)
+#define PUD2_PUD_AVB0_RXC BIT(8)
+#define PUD2_PUD_AVB0_RX_CTL BIT(7)
+#define PUD2_PUD_SDA2 BIT(6)
+#define PUD2_PUD_SCL2 BIT(5)
+#define PUD2_PUD_SDA1 BIT(4)
+#define PUD2_PUD_SCL1 BIT(3)
+#define PUD2_PUD_SDA0 BIT(2)
+#define PUD2_PUD_SCL0 BIT(1)
+#define PUD2_PUD_VI1_FIELD BIT(0)
+
+#define PUD3_PUD_DIGRF_CLKOUT BIT(16)
+#define PUD3_PUD_DIGRF_CLKIN BIT(15)
+#define PUD3_PUD_RPC_INT_N BIT(14)
+#define PUD3_PUD_RPC_WP_N BIT(13)
+#define PUD3_PUD_RPC_RESET_N BIT(12)
+#define PUD3_PUD_QSPI1_SSL BIT(11)
+#define PUD3_PUD_QSPI1_IO3 BIT(10)
+#define PUD3_PUD_QSPI1_IO2 BIT(9)
+#define PUD3_PUD_QSPI1_MISO_IO1 BIT(8)
+#define PUD3_PUD_QSPI1_MOSI_IO0 BIT(7)
+#define PUD3_PUD_QSPI1_SPCLK BIT(6)
+#define PUD3_PUD_QSPI0_SSL BIT(5)
+#define PUD3_PUD_QSPI0_IO3 BIT(4)
+#define PUD3_PUD_QSPI0_IO2 BIT(3)
+#define PUD3_PUD_QSPI0_MISO_IO1 BIT(2)
+#define PUD3_PUD_QSPI0_MOSI_IO0 BIT(1)
+#define PUD3_PUD_QSPI0_SPCLK BIT(0)
+
+#define MOD_SEL0_sel_hscif0 BIT(10)
+#define MOD_SEL0_sel_scif1 BIT(9)
+#define MOD_SEL0_sel_canfd0 BIT(8)
+#define MOD_SEL0_sel_pwm4 BIT(7)
+#define MOD_SEL0_sel_pwm3 BIT(6)
+#define MOD_SEL0_sel_pwm2 BIT(5)
+#define MOD_SEL0_sel_pwm1 BIT(4)
+#define MOD_SEL0_sel_pwm0 BIT(3)
+#define MOD_SEL0_sel_rfso BIT(2)
+#define MOD_SEL0_sel_rsp BIT(1)
+#define MOD_SEL0_sel_tmu BIT(0)
+
+/* SCIF3 Registers for Dummy write */
+#define SCIF3_BASE (0xE6C50000U)
+#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U)
+#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU)
+#define SCFCR_DATA (0x0000U)
+
+/* Realtime module stop control */
+#define CPG_BASE (0xE6150000U)
+#define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
+#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U)
+#define RMSTPCR0_RTDMAC (0x00200000U)
+
+/* RT-DMAC Registers */
+#define RTDMAC_CH (0U) /* choose 0 to 15 */
+
+#define RTDMAC_BASE (0xFFC10000U)
+#define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U)
+#define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U)
+#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x)))
+#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x)))
+#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x)))
+#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x)))
+#define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x)))
+#define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x)))
+#define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U)
+#define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U)
+#define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U)
+#define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U)
+
+#define RDMOR_DME (0x0001U) /* DMA Master Enable */
+#define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */
+#define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */
+#define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */
+#define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */
+#define RDMCHCR_DE (0x00000001U) /* DMA Enable */
+#define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */
+#define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */
+#define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ mmio_write_32(PFC_PMMR, ~data);
+ mmio_write_32((uintptr_t)addr, data);
+}
+
+static void start_rtdma0_descriptor(void)
+{
+ uint32_t reg;
+
+ /* Module stop clear */
+ while ((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
+ reg = mmio_read_32(CPG_RMSTPCR0);
+ reg &= ~RMSTPCR0_RTDMAC;
+ cpg_write(CPG_RMSTPCR0, reg);
+ }
+
+ /* Initialize ch0, Reset Descriptor */
+ mmio_write_32(RTDMAC_RDMCHCLR, BIT(RTDMAC_CH));
+ mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
+
+ /* Enable DMA */
+ mmio_write_16(RTDMAC_RDMOR, RDMOR_DME);
+
+ /* Set first transfer */
+ mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR);
+ mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR);
+ mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U);
+
+ /* Set descriptor */
+ mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U);
+ mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U);
+ mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U);
+ mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256);
+ mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE
+ | RDMDPBASE_SEL_EXT);
+
+ /* Set transfer parameter, Start transfer */
+ mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
+ | RDMCHCR_RPT_TCR
+ | RDMCHCR_TS_2
+ | RDMCHCR_RS_AUTO
+ | RDMCHCR_DE);
+}
+
+void pfc_init_v3m(void)
+{
+ /* Work around for PFC eratta */
+ start_rtdma0_descriptor();
+
+ // pin function
+ // md[4:1]!=0000
+ /* initialize GPIO/perihperal function select */
+
+ pfc_reg_write(PFC_GPSR0, 0x00000000);
+
+ pfc_reg_write(PFC_GPSR1, GPSR1_CANFD_CLK);
+
+ pfc_reg_write(PFC_GPSR2, 0x00000000);
+
+ pfc_reg_write(PFC_GPSR3, 0x00000000);
+
+ pfc_reg_write(PFC_GPSR4, GPSR4_SDA2
+ | GPSR4_SCL2);
+
+ pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL
+ | GPSR5_QSPI1_IO3
+ | GPSR5_QSPI1_IO2
+ | GPSR5_QSPI1_MISO_IO1
+ | GPSR5_QSPI1_MOSI_IO0
+ | GPSR5_QSPI1_SPCLK
+ | GPSR5_QSPI0_SSL
+ | GPSR5_QSPI0_IO3
+ | GPSR5_QSPI0_IO2
+ | GPSR5_QSPI0_MISO_IO1
+ | GPSR5_QSPI0_MOSI_IO0
+ | GPSR5_QSPI0_SPCLK);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(0)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(4)
+ | IPSR_20_FUNC(4)
+ | IPSR_16_FUNC(4)
+ | IPSR_12_FUNC(4)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)
+ | IPSR_24_FUNC(0)
+ | IPSR_20_FUNC(0)
+ | IPSR_16_FUNC(4)
+ | IPSR_12_FUNC(0)
+ | IPSR_8_FUNC(0)
+ | IPSR_4_FUNC(0)
+ | IPSR_0_FUNC(0));
+
+ /* initialize POC Control */
+
+ pfc_reg_write(PFC_POCCTRL0, IOCTRL30_POC_VI0_DATA5
+ | IOCTRL30_POC_VI0_DATA4
+ | IOCTRL30_POC_VI0_DATA3
+ | IOCTRL30_POC_VI0_DATA2
+ | IOCTRL30_POC_VI0_DATA1
+ | IOCTRL30_POC_VI0_DATA0
+ | IOCTRL30_POC_VI0_VSYNC_N
+ | IOCTRL30_POC_VI0_HSYNC_N
+ | IOCTRL30_POC_VI0_CLKENB
+ | IOCTRL30_POC_VI0_CLK
+ | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE
+ | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC
+ | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC
+ | IOCTRL30_POC_DU_DOTCLKOUT
+ | IOCTRL30_POC_DU_DB7
+ | IOCTRL30_POC_DU_DB6
+ | IOCTRL30_POC_DU_DB5
+ | IOCTRL30_POC_DU_DB4
+ | IOCTRL30_POC_DU_DB3
+ | IOCTRL30_POC_DU_DB2
+ | IOCTRL30_POC_DU_DG7
+ | IOCTRL30_POC_DU_DG6
+ | IOCTRL30_POC_DU_DG5
+ | IOCTRL30_POC_DU_DG4
+ | IOCTRL30_POC_DU_DG3
+ | IOCTRL30_POC_DU_DG2
+ | IOCTRL30_POC_DU_DR7
+ | IOCTRL30_POC_DU_DR6
+ | IOCTRL30_POC_DU_DR5
+ | IOCTRL30_POC_DU_DR4
+ | IOCTRL30_POC_DU_DR3
+ | IOCTRL30_POC_DU_DR2);
+
+ pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_DUMMY_31
+ | IOCTRL31_POC_DUMMY_30
+ | IOCTRL31_POC_DUMMY_29
+ | IOCTRL31_POC_DUMMY_28
+ | IOCTRL31_POC_DUMMY_27
+ | IOCTRL31_POC_DUMMY_26
+ | IOCTRL31_POC_DUMMY_25
+ | IOCTRL31_POC_DUMMY_24
+ | IOCTRL31_POC_VI1_FIELD
+ | IOCTRL31_POC_VI1_DATA11
+ | IOCTRL31_POC_VI1_DATA10
+ | IOCTRL31_POC_VI1_DATA9
+ | IOCTRL31_POC_VI1_DATA8
+ | IOCTRL31_POC_VI1_DATA7
+ | IOCTRL31_POC_VI1_DATA6
+ | IOCTRL31_POC_VI1_DATA5
+ | IOCTRL31_POC_VI1_DATA4
+ | IOCTRL31_POC_VI1_DATA3
+ | IOCTRL31_POC_VI1_DATA2
+ | IOCTRL31_POC_VI1_DATA1
+ | IOCTRL31_POC_VI1_DATA0
+ | IOCTRL31_POC_VI1_VSYNC_N
+ | IOCTRL31_POC_VI1_HSYNC_N
+ | IOCTRL31_POC_VI1_CLKENB
+ | IOCTRL31_POC_VI1_CLK
+ | IOCTRL31_POC_VI0_FIELD
+ | IOCTRL31_POC_VI0_DATA11
+ | IOCTRL31_POC_VI0_DATA10
+ | IOCTRL31_POC_VI0_DATA9
+ | IOCTRL31_POC_VI0_DATA8
+ | IOCTRL31_POC_VI0_DATA7
+ | IOCTRL31_POC_VI0_DATA6);
+
+ pfc_reg_write(PFC_POCCTRL2, 0x00000000);
+
+ pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);
+
+ /* initialize Pull enable */
+ pfc_reg_write(PFC_PUEN0, PUEN0_PUEN_VI0_CLK
+ | PUEN0_PUEN_TDI
+ | PUEN0_PUEN_TMS
+ | PUEN0_PUEN_TCK
+ | PUEN0_PUEN_TRST_N
+ | PUEN0_PUEN_IRQ0
+ | PUEN0_PUEN_FSCLKST_N
+ | PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC
+ | PUEN0_PUEN_DU_DOTCLKOUT
+ | PUEN0_PUEN_DU_DB7
+ | PUEN0_PUEN_DU_DB6
+ | PUEN0_PUEN_DU_DB5
+ | PUEN0_PUEN_DU_DB4
+ | PUEN0_PUEN_DU_DB3
+ | PUEN0_PUEN_DU_DB2
+ | PUEN0_PUEN_DU_DG7
+ | PUEN0_PUEN_DU_DG6
+ | PUEN0_PUEN_DU_DG5
+ | PUEN0_PUEN_DU_DG4
+ | PUEN0_PUEN_DU_DG3
+ | PUEN0_PUEN_DU_DG2
+ | PUEN0_PUEN_DU_DR7
+ | PUEN0_PUEN_DU_DR6
+ | PUEN0_PUEN_DU_DR5
+ | PUEN0_PUEN_DU_DR4
+ | PUEN0_PUEN_DU_DR3
+ | PUEN0_PUEN_DU_DR2);
+
+ pfc_reg_write(PFC_PUEN1, PUEN1_PUEN_VI1_DATA11
+ | PUEN1_PUEN_VI1_DATA10
+ | PUEN1_PUEN_VI1_DATA9
+ | PUEN1_PUEN_VI1_DATA8
+ | PUEN1_PUEN_VI1_DATA7
+ | PUEN1_PUEN_VI1_DATA6
+ | PUEN1_PUEN_VI1_DATA5
+ | PUEN1_PUEN_VI1_DATA4
+ | PUEN1_PUEN_VI1_DATA3
+ | PUEN1_PUEN_VI1_DATA2
+ | PUEN1_PUEN_VI1_DATA1
+ | PUEN1_PUEN_VI1_DATA0
+ | PUEN1_PUEN_VI1_VSYNC_N
+ | PUEN1_PUEN_VI1_HSYNC_N
+ | PUEN1_PUEN_VI1_CLKENB
+ | PUEN1_PUEN_VI1_CLK
+ | PUEN1_PUEN_VI0_DATA11
+ | PUEN1_PUEN_VI0_DATA10
+ | PUEN1_PUEN_VI0_DATA9
+ | PUEN1_PUEN_VI0_DATA8
+ | PUEN1_PUEN_VI0_DATA7
+ | PUEN1_PUEN_VI0_DATA6
+ | PUEN1_PUEN_VI0_DATA5
+ | PUEN1_PUEN_VI0_DATA4
+ | PUEN1_PUEN_VI0_DATA3
+ | PUEN1_PUEN_VI0_DATA2
+ | PUEN1_PUEN_VI0_DATA1);
+
+ pfc_reg_write(PFC_PUEN2, PUEN2_PUEN_CANFD_CLK
+ | PUEN2_PUEN_CANFD1_RX
+ | PUEN2_PUEN_CANFD1_TX
+ | PUEN2_PUEN_CANFD0_RX
+ | PUEN2_PUEN_CANFD0_TX
+ | PUEN2_PUEN_AVB0_AVTP_CAPTURE
+ | PUEN2_PUEN_AVB0_AVTP_MATCH
+ | PUEN2_PUEN_AVB0_LINK
+ | PUEN2_PUEN_AVB0_PHY_INT
+ | PUEN2_PUEN_AVB0_MAGIC
+ | PUEN2_PUEN_AVB0_TXCREFCLK
+ | PUEN2_PUEN_AVB0_TD3
+ | PUEN2_PUEN_AVB0_TD2
+ | PUEN2_PUEN_AVB0_TD1
+ | PUEN2_PUEN_AVB0_TD0
+ | PUEN2_PUEN_AVB0_TXC
+ | PUEN2_PUEN_AVB0_TX_CTL
+ | PUEN2_PUEN_AVB0_RD3
+ | PUEN2_PUEN_AVB0_RD2
+ | PUEN2_PUEN_AVB0_RD1
+ | PUEN2_PUEN_AVB0_RD0
+ | PUEN2_PUEN_AVB0_RXC
+ | PUEN2_PUEN_AVB0_RX_CTL
+ | PUEN2_PUEN_VI1_FIELD);
+
+ pfc_reg_write(PFC_PUEN3, PUEN3_PUEN_DIGRF_CLKOUT
+ | PUEN3_PUEN_DIGRF_CLKIN);
+
+ /* initialize PUD Control */
+ pfc_reg_write(PFC_PUD0, PUD0_PUD_VI0_CLK
+ | PUD0_PUD_IRQ0
+ | PUD0_PUD_FSCLKST_N
+ | PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE
+ | PUD0_PUD_DU_EXVSYNC_DU_VSYNC
+ | PUD0_PUD_DU_EXHSYNC_DU_HSYNC
+ | PUD0_PUD_DU_DOTCLKOUT
+ | PUD0_PUD_DU_DB7
+ | PUD0_PUD_DU_DB6
+ | PUD0_PUD_DU_DB5
+ | PUD0_PUD_DU_DB4
+ | PUD0_PUD_DU_DB3
+ | PUD0_PUD_DU_DB2
+ | PUD0_PUD_DU_DG7
+ | PUD0_PUD_DU_DG6
+ | PUD0_PUD_DU_DG5
+ | PUD0_PUD_DU_DG4
+ | PUD0_PUD_DU_DG3
+ | PUD0_PUD_DU_DG2
+ | PUD0_PUD_DU_DR7
+ | PUD0_PUD_DU_DR6
+ | PUD0_PUD_DU_DR5
+ | PUD0_PUD_DU_DR4
+ | PUD0_PUD_DU_DR3
+ | PUD0_PUD_DU_DR2);
+
+ pfc_reg_write(PFC_PUD1, PUD1_PUD_VI1_DATA11
+ | PUD1_PUD_VI1_DATA10
+ | PUD1_PUD_VI1_DATA9
+ | PUD1_PUD_VI1_DATA8
+ | PUD1_PUD_VI1_DATA7
+ | PUD1_PUD_VI1_DATA6
+ | PUD1_PUD_VI1_DATA5
+ | PUD1_PUD_VI1_DATA4
+ | PUD1_PUD_VI1_DATA3
+ | PUD1_PUD_VI1_DATA2
+ | PUD1_PUD_VI1_DATA1
+ | PUD1_PUD_VI1_DATA0
+ | PUD1_PUD_VI1_VSYNC_N
+ | PUD1_PUD_VI1_HSYNC_N
+ | PUD1_PUD_VI1_CLKENB
+ | PUD1_PUD_VI1_CLK
+ | PUD1_PUD_VI0_DATA11
+ | PUD1_PUD_VI0_DATA10
+ | PUD1_PUD_VI0_DATA9
+ | PUD1_PUD_VI0_DATA8
+ | PUD1_PUD_VI0_DATA7
+ | PUD1_PUD_VI0_DATA6
+ | PUD1_PUD_VI0_DATA5
+ | PUD1_PUD_VI0_DATA4
+ | PUD1_PUD_VI0_DATA3
+ | PUD1_PUD_VI0_DATA2
+ | PUD1_PUD_VI0_DATA1
+ | PUD1_PUD_VI0_DATA0
+ | PUD1_PUD_VI0_VSYNC_N
+ | PUD1_PUD_VI0_HSYNC_N
+ | PUD1_PUD_VI0_CLKENB);
+
+ pfc_reg_write(PFC_PUD2, PUD2_PUD_CANFD_CLK
+ | PUD2_PUD_CANFD1_RX
+ | PUD2_PUD_CANFD1_TX
+ | PUD2_PUD_CANFD0_RX
+ | PUD2_PUD_CANFD0_TX
+ | PUD2_PUD_AVB0_AVTP_CAPTURE
+ | PUD2_PUD_VI1_FIELD);
+
+ pfc_reg_write(PFC_PUD3, PUD3_PUD_DIGRF_CLKOUT
+ | PUD3_PUD_DIGRF_CLKIN);
+
+ /* initialize Module Select */
+ pfc_reg_write(PFC_MOD_SEL0, 0x00000000);
+
+ // gpio
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT0, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
+}
diff --git a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.h b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.h
new file mode 100644
index 0000000..7bab92f
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_V3M_H
+#define PFC_INIT_V3M_H
+
+void pfc_init_v3m(void);
+
+#endif /* PFC_INIT_V3M_H */
diff --git a/drivers/renesas/rcar/pfc/pfc.mk b/drivers/renesas/rcar/pfc/pfc.mk
new file mode 100644
index 0000000..f1dd92c
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/pfc.mk
@@ -0,0 +1,69 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_AUTO})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+ BL2_SOURCES += drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+ BL2_SOURCES += drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+ BL2_SOURCES += drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+
+else ifdef RCAR_LSI_CUT_COMPAT
+ ifeq (${RCAR_LSI},${RCAR_H3})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_H3N})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_M3})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_M3N})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_V3M})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_E3})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_D3})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
+ endif
+else
+ ifeq (${RCAR_LSI},${RCAR_H3})
+ ifeq (${LSI_CUT},10)
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+ else ifeq (${LSI_CUT},11)
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+ else
+# LSI_CUT 20 or later
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+ endif
+ endif
+ ifeq (${RCAR_LSI},${RCAR_H3N})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_M3})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_M3N})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_V3M})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_E3})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
+ endif
+ ifeq (${RCAR_LSI},${RCAR_D3})
+ BL2_SOURCES += drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
+ endif
+endif
+
+BL2_SOURCES += drivers/renesas/rcar/pfc/pfc_init.c
diff --git a/drivers/renesas/rcar/pfc/pfc_init.c b/drivers/renesas/rcar/pfc/pfc_init.c
new file mode 100644
index 0000000..8810667
--- /dev/null
+++ b/drivers/renesas/rcar/pfc/pfc_init.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "rcar_def.h"
+#if RCAR_LSI == RCAR_AUTO
+#include "H3/pfc_init_h3_v1.h"
+#include "H3/pfc_init_h3_v2.h"
+#include "M3/pfc_init_m3.h"
+#include "M3N/pfc_init_m3n.h"
+#include "V3M/pfc_init_v3m.h"
+#endif
+#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) /* H3 */
+#include "H3/pfc_init_h3_v1.h"
+#include "H3/pfc_init_h3_v2.h"
+#endif
+#if RCAR_LSI == RCAR_M3 /* M3 */
+#include "M3/pfc_init_m3.h"
+#endif
+#if RCAR_LSI == RCAR_M3N /* M3N */
+#include "M3N/pfc_init_m3n.h"
+#endif
+#if RCAR_LSI == RCAR_V3M /* V3M */
+#include "V3M/pfc_init_v3m.h"
+#endif
+#if RCAR_LSI == RCAR_E3 /* E3 */
+#include "E3/pfc_init_e3.h"
+#endif
+#if RCAR_LSI == RCAR_D3 /* D3 */
+#include "D3/pfc_init_d3.h"
+#endif
+
+#define PRR_PRODUCT_ERR(reg) \
+ do { \
+ ERROR("LSI Product ID(PRR=0x%x) PFC initialize not supported.\n", \
+ reg); \
+ panic(); \
+ } while (0)
+
+#define PRR_CUT_ERR(reg) \
+ do { \
+ ERROR("LSI Cut ID(PRR=0x%x) PFC initialize not supported.\n", \
+ reg); \
+ panic();\
+ } while (0)
+
+void rcar_pfc_init(void)
+{
+ uint32_t reg;
+
+ reg = mmio_read_32(RCAR_PRR);
+#if RCAR_LSI == RCAR_AUTO
+ switch (reg & PRR_PRODUCT_MASK) {
+ case PRR_PRODUCT_H3:
+ switch (reg & PRR_CUT_MASK) {
+ case PRR_PRODUCT_10: /* H3 Ver.1.0 */
+ pfc_init_h3_v1();
+ break;
+ case PRR_PRODUCT_11: /* H3 Ver.1.1 */
+ pfc_init_h3_v1();
+ break;
+ default: /* H3 Ver.2.0 or later */
+ pfc_init_h3_v2();
+ break;
+ }
+ break;
+ case PRR_PRODUCT_M3:
+ pfc_init_m3();
+ break;
+ case PRR_PRODUCT_M3N:
+ pfc_init_m3n();
+ break;
+ case PRR_PRODUCT_V3M:
+ pfc_init_v3m();
+ break;
+ default:
+ PRR_PRODUCT_ERR(reg);
+ break;
+ }
+
+#elif RCAR_LSI_CUT_COMPAT
+ switch (reg & PRR_PRODUCT_MASK) {
+ case PRR_PRODUCT_H3:
+#if (RCAR_LSI != RCAR_H3) && (RCAR_LSI != RCAR_H3N)
+ PRR_PRODUCT_ERR(reg);
+#else
+ switch (reg & PRR_CUT_MASK) {
+ case PRR_PRODUCT_10: /* H3 Ver.1.0 */
+ pfc_init_h3_v1();
+ break;
+ case PRR_PRODUCT_11: /* H3 Ver.1.1 */
+ pfc_init_h3_v1();
+ break;
+ default: /* H3 Ver.2.0 or later */
+ pfc_init_h3_v2();
+ break;
+ }
+#endif
+ break;
+ case PRR_PRODUCT_M3:
+#if RCAR_LSI != RCAR_M3
+ PRR_PRODUCT_ERR(reg);
+#else
+ pfc_init_m3();
+#endif
+ break;
+ case PRR_PRODUCT_M3N:
+#if RCAR_LSI != RCAR_M3N
+ PRR_PRODUCT_ERR(reg);
+#else
+ pfc_init_m3n();
+#endif
+ break;
+ case PRR_PRODUCT_V3M:
+#if RCAR_LSI != RCAR_V3M
+ PRR_PRODUCT_ERR(reg);
+#else
+ pfc_init_v3m();
+#endif
+ break;
+ case PRR_PRODUCT_E3:
+#if RCAR_LSI != RCAR_E3
+ PRR_PRODUCT_ERR(reg);
+#else
+ pfc_init_e3();
+#endif
+ break;
+ case PRR_PRODUCT_D3:
+#if RCAR_LSI != RCAR_D3
+ PRR_PRODUCT_ERR(reg);
+#else
+ pfc_init_d3();
+#endif
+ break;
+ default:
+ PRR_PRODUCT_ERR(reg);
+ break;
+ }
+
+#else
+#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) /* H3 */
+#if RCAR_LSI_CUT == RCAR_CUT_10
+ /* H3 Ver.1.0 */
+ if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10)
+ != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_h3_v1();
+#elif RCAR_LSI_CUT == RCAR_CUT_11
+ /* H3 Ver.1.1 */
+ if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11)
+ != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_h3_v1();
+#else
+ /* H3 Ver.2.0 or later */
+ if (PRR_PRODUCT_H3 != (reg & PRR_PRODUCT_MASK)) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_h3_v2();
+#endif
+#elif RCAR_LSI == RCAR_M3 /* M3 */
+ if ((PRR_PRODUCT_M3) != (reg & PRR_PRODUCT_MASK)) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_m3();
+#elif RCAR_LSI == RCAR_M3N /* M3N */
+ if ((PRR_PRODUCT_M3N) != (reg & PRR_PRODUCT_MASK)) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_m3n();
+#elif RCAR_LSI == RCAR_V3M /* V3M */
+ if ((PRR_PRODUCT_V3M) != (reg & PRR_PRODUCT_MASK)) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_v3m();
+#elif RCAR_LSI == RCAR_E3 /* E3 */
+ if ((PRR_PRODUCT_E3) != (reg & PRR_PRODUCT_MASK)) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_e3();
+#elif RCAR_LSI == RCAR_D3 /* D3 */
+ if ((PRR_PRODUCT_D3) != (reg & PRR_PRODUCT_MASK)) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_d3();
+#else
+#error "Don't have PFC initialize routine(unknown)."
+#endif
+#endif
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 11:01:50 +0000