diff options
Diffstat (limited to 'include/lib/cpus/aarch64/cortex_x3.h')
-rw-r--r-- | include/lib/cpus/aarch64/cortex_x3.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h new file mode 100644 index 0000000..076a87b --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x3.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X3_H +#define CORTEX_X3_H + +#define CORTEX_X3_MIDR U(0x410FD4E0) + +/* Cortex-X3 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X3_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) + +#endif /* CORTEX_X3_H */ |