diff options
Diffstat (limited to 'plat/allwinner/sun50i_r329')
| -rw-r--r-- | plat/allwinner/sun50i_r329/include/sunxi_ccu.h | 14 | ||||
| -rw-r--r-- | plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h | 31 | ||||
| -rw-r--r-- | plat/allwinner/sun50i_r329/include/sunxi_mmap.h | 55 | ||||
| -rw-r--r-- | plat/allwinner/sun50i_r329/include/sunxi_spc.h | 17 | ||||
| -rw-r--r-- | plat/allwinner/sun50i_r329/platform.mk | 20 | ||||
| -rw-r--r-- | plat/allwinner/sun50i_r329/sunxi_idle_states.c | 11 | ||||
| -rw-r--r-- | plat/allwinner/sun50i_r329/sunxi_power.c | 27 |
7 files changed, 175 insertions, 0 deletions
diff --git a/plat/allwinner/sun50i_r329/include/sunxi_ccu.h b/plat/allwinner/sun50i_r329/include/sunxi_ccu.h new file mode 100644 index 0000000..0e6b543 --- /dev/null +++ b/plat/allwinner/sun50i_r329/include/sunxi_ccu.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 Sipeed + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_CCU_H +#define SUNXI_CCU_H + +#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x0f00) + +#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x0290) + +#endif /* SUNXI_CCU_H */ diff --git a/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h new file mode 100644 index 0000000..9478f32 --- /dev/null +++ b/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021 Sipeed + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_CPUCFG_H +#define SUNXI_CPUCFG_H + +#include <sunxi_mmap.h> + +/* c = cluster, n = core */ +#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010) +#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014) +#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024) +#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0) + +#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000) +#define SUNXI_CPUCFG_GEN_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000) +#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) +#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) + +#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4) +#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4) +#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ + (c) * 0x10 + (n) * 4) + +#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0 +#define SUNXI_AA64nAA32_OFFSET 4 + +#endif /* SUNXI_CPUCFG_H */ diff --git a/plat/allwinner/sun50i_r329/include/sunxi_mmap.h b/plat/allwinner/sun50i_r329/include/sunxi_mmap.h new file mode 100644 index 0000000..a4469b5 --- /dev/null +++ b/plat/allwinner/sun50i_r329/include/sunxi_mmap.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_MMAP_H +#define SUNXI_MMAP_H + +/* Memory regions */ +#define SUNXI_ROM_BASE 0x00000000 +#define SUNXI_ROM_SIZE 0x00010000 +/* + * In fact all SRAM from 0x100000 is SRAM A2. However as it's too big for + * firmware, and the user manual gives a tip on a 2*64K/27*64K partition, + * only use the first 2*64K for firmwares now, with the SPL using the first + * 64K and BL3-1 using the second one. + * + * Only the used 2*64K SRAM is defined here, to prevent a gaint translation + * table to be generated. + */ +#define SUNXI_SRAM_BASE 0x00100000 +#define SUNXI_SRAM_SIZE 0x00020000 +#define SUNXI_SRAM_A1_BASE 0x00100000 +#define SUNXI_SRAM_A1_SIZE 0x00010000 +#define SUNXI_SRAM_A2_BASE 0x00110000 +#define SUNXI_SRAM_A2_BL31_OFFSET 0x00000000 +#define SUNXI_SRAM_A2_SIZE 0x00010000 +#define SUNXI_DEV_BASE 0x01000000 +#define SUNXI_DEV_SIZE 0x09000000 +#define SUNXI_DRAM_BASE 0x40000000 +#define SUNXI_DRAM_VIRT_BASE 0x0a000000 + +/* Memory-mapped devices */ +#define SUNXI_WDOG_BASE 0x020000a0 +#define SUNXI_R_WDOG_BASE SUNXI_WDOG_BASE +#define SUNXI_PIO_BASE 0x02000400 +#define SUNXI_SPC_BASE 0x02000800 +#define SUNXI_CCU_BASE 0x02001000 +#define SUNXI_UART0_BASE 0x02500000 +#define SUNXI_SYSCON_BASE 0x03000000 +#define SUNXI_DMA_BASE 0x03002000 +#define SUNXI_SID_BASE 0x03006000 +#define SUNXI_GICD_BASE 0x03021000 +#define SUNXI_GICC_BASE 0x03022000 +#define SUNXI_SPI0_BASE 0x04025000 +#define SUNXI_R_CPUCFG_BASE 0x07000400 +#define SUNXI_R_PRCM_BASE 0x07010000 +#define SUNXI_R_PIO_BASE 0x07022000 +#define SUNXI_R_UART_BASE 0x07080000 +#define SUNXI_R_I2C_BASE 0x07081400 +#define SUNXI_CPUCFG_BASE 0x08100000 +#define SUNXI_C0_CPUXCFG_BASE 0x09010000 + +#endif /* SUNXI_MMAP_H */ diff --git a/plat/allwinner/sun50i_r329/include/sunxi_spc.h b/plat/allwinner/sun50i_r329/include/sunxi_spc.h new file mode 100644 index 0000000..2c87bca --- /dev/null +++ b/plat/allwinner/sun50i_r329/include/sunxi_spc.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2021 Sipeed + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_SPC_H +#define SUNXI_SPC_H + +/* Get by REing stock ATF and checking initialization loop boundary */ +#define SUNXI_SPC_NUM_PORTS 11 + +#define SUNXI_SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + 0x0000 + 0x10 * (p)) +#define SUNXI_SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + 0x0004 + 0x10 * (p)) +#define SUNXI_SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + 0x0008 + 0x10 * (p)) + +#endif /* SUNXI_SPC_H */ diff --git a/plat/allwinner/sun50i_r329/platform.mk b/plat/allwinner/sun50i_r329/platform.mk new file mode 100644 index 0000000..05d7cde --- /dev/null +++ b/plat/allwinner/sun50i_r329/platform.mk @@ -0,0 +1,20 @@ +# +# Copyright (c) 2021 Sipeed +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Without a management processor there is no SCPI support. +SUNXI_PSCI_USE_SCPI := 0 +SUNXI_PSCI_USE_NATIVE := 1 + +# The differences between the platforms are covered by the include files. +include plat/allwinner/common/allwinner-common.mk + +# the above could be overwritten on the command line +ifeq (${SUNXI_PSCI_USE_SCPI}, 1) + $(error "R329 does not support SCPI PSCI ops") +endif + +# Put NOBITS memory in the first 64K of SRAM A2, overwriting U-Boot's SPL. +SEPARATE_NOBITS_REGION := 1 diff --git a/plat/allwinner/sun50i_r329/sunxi_idle_states.c b/plat/allwinner/sun50i_r329/sunxi_idle_states.c new file mode 100644 index 0000000..4339bcd --- /dev/null +++ b/plat/allwinner/sun50i_r329/sunxi_idle_states.c @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <sunxi_private.h> + +const struct psci_cpu_idle_state sunxi_idle_states[] = { + {} +}; diff --git a/plat/allwinner/sun50i_r329/sunxi_power.c b/plat/allwinner/sun50i_r329/sunxi_power.c new file mode 100644 index 0000000..96a24d5 --- /dev/null +++ b/plat/allwinner/sun50i_r329/sunxi_power.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021 Sipeed + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform_def.h> + +#include <sunxi_mmap.h> +#include <sunxi_cpucfg.h> +#include <sunxi_private.h> + +int sunxi_pmic_setup(uint16_t socid, const void *fdt) +{ + /* Currently known hardware has no PMIC */ + + return 0; +} + +void sunxi_power_down(void) +{ +} + +void sunxi_cpu_power_off_self(void) +{ + /* TODO: It's still unknown whether CPUIDLE exists on R329 */ +} |