diff options
Diffstat (limited to 'plat/imx/imx8m/imx8mn')
| -rw-r--r-- | plat/imx/imx8m/imx8mn/gpc.c | 207 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c | 249 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/imx8mn_psci.c | 44 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/include/gpc_reg.h | 111 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/include/imx_sec_def.h | 210 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/include/platform_def.h | 162 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/platform.mk | 77 |
7 files changed, 1060 insertions, 0 deletions
diff --git a/plat/imx/imx8m/imx8mn/gpc.c b/plat/imx/imx8m/imx8mn/gpc.c new file mode 100644 index 0000000..4e05297 --- /dev/null +++ b/plat/imx/imx8m/imx8mn/gpc.c @@ -0,0 +1,207 @@ +/* + * Copyright 2019-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <stdint.h> +#include <stdlib.h> + +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/psci/psci.h> +#include <lib/smccc.h> +#include <services/std_svc.h> + +#include <gpc.h> +#include <imx_sip_svc.h> +#include <platform_def.h> + +#define CCGR(x) (0x4000 + (x) * 0x10) + +#define MIPI_PWR_REQ BIT(0) +#define OTG1_PWR_REQ BIT(2) +#define HSIOMIX_PWR_REQ BIT(4) +#define GPUMIX_PWR_REQ BIT(7) +#define DISPMIX_PWR_REQ BIT(10) + +#define HSIOMIX_ADB400_SYNC BIT(5) +#define DISPMIX_ADB400_SYNC BIT(7) +#define GPUMIX_ADB400_SYNC (0x5 << 9) +#define HSIOMIX_ADB400_ACK BIT(23) +#define DISPMIX_ADB400_ACK BIT(25) +#define GPUMIX_ADB400_ACK (0x5 << 27) + +#define MIPI_PGC 0xc00 +#define OTG1_PGC 0xc80 +#define HSIOMIX_PGC 0xd00 +#define GPUMIX_PGC 0xdc0 +#define DISPMIX_PGC 0xe80 + +enum pu_domain_id { + HSIOMIX, + OTG1 = 2, + GPUMIX = 4, + DISPMIX = 9, + MIPI, +}; + +/* PU domain, add some hole to minimize the uboot change */ +static struct imx_pwr_domain pu_domains[11] = { + [HSIOMIX] = IMX_MIX_DOMAIN(HSIOMIX, false), + [OTG1] = IMX_PD_DOMAIN(OTG1, true), + [GPUMIX] = IMX_MIX_DOMAIN(GPUMIX, false), + [DISPMIX] = IMX_MIX_DOMAIN(DISPMIX, false), + [MIPI] = IMX_PD_DOMAIN(MIPI, true), +}; + +static unsigned int pu_domain_status; + +void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) +{ + if (domain_id > MIPI) { + return; + } + + struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; + + if (on) { + if (pwr_domain->need_sync) { + pu_domain_status |= (1 << domain_id); + } + + /* HSIOMIX has no PU bit, so skip for it */ + if (domain_id != HSIOMIX) { + /* clear the PGC bit */ + mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); + + /* power up the domain */ + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { + ; + } + } + + if (domain_id == DISPMIX) { + /* de-reset bus_blk clk and + * enable bus_blk clk + */ + mmio_write_32(0x32e28000, 0x100); + mmio_write_32(0x32e28004, 0x100); + } + + /* handle the ADB400 sync */ + if (pwr_domain->need_sync) { + /* clear adb power down request */ + mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); + + /* wait for adb power request ack */ + while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { + ; + } + } + } else { + pu_domain_status &= ~(1 << domain_id); + + if (domain_id == OTG1) { + return; + } + + /* handle the ADB400 sync */ + if (pwr_domain->need_sync) { + + /* set adb power down request */ + mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); + + /* wait for adb power request ack */ + while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { + ; + } + } + + /* HSIOMIX has no PU bit, so skip for it */ + if (domain_id != HSIOMIX) { + /* set the PGC bit */ + mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); + + /* power down the domain */ + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { + ; + } + } + } +} + +void imx_gpc_init(void) +{ + unsigned int val; + int i; + + /* mask all the wakeup irq by default */ + for (i = 0; i < 4; i++) { + mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); + mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); + mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); + mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); + mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); + } + + val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); + /* use GIC wake_request to wakeup C0~C3 from LPM */ + val |= CORE_WKUP_FROM_GIC; + /* clear the MASTER0 LPM handshake */ + val &= ~MASTER0_LPM_HSK; + mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); + + /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */ + mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | + MASTER2_MAPPING)); + + /* set all mix/PU in A53 domain */ + mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff); + + /* + * Set the CORE & SCU power up timing: + * SW = 0x1, SW2ISO = 0x1; + * the CPU CORE and SCU power up timming counter + * is drived by 32K OSC, each domain's power up + * latency is (SW + SW2ISO) / 32768 + */ + mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401); + mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401); + mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401); + mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401); + mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401); + mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, + (0x59 << TMC_TMR_SHIFT) | 0x5B | (0x2 << TRC1_TMC_SHIFT)); + + /* set DUMMY PDN/PUP ACK by default for A53 domain */ + mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, + A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK); + + /* clear DSM by default */ + val = mmio_read_32(IMX_GPC_BASE + SLPCR); + val &= ~SLPCR_EN_DSM; + /* enable the fast wakeup wait mode */ + val |= SLPCR_A53_FASTWUP_WAIT_MODE; + /* clear the RBC */ + val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT); + /* set the STBY_COUNT to 0x5, (128 * 30)us */ + val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT); + val |= (0x5 << SLPCR_STBY_COUNT_SHFT); + mmio_write_32(IMX_GPC_BASE + SLPCR, val); + + /* + * USB PHY power up needs to make sure RESET bit in SRC is clear, + * otherwise, the PU power up bit in GPC will NOT self-cleared. + * only need to do it once. + */ + mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); +} diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c new file mode 100644 index 0000000..eff198d --- /dev/null +++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c @@ -0,0 +1,249 @@ +/* + * Copyright 2019-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <stdbool.h> + +#include <arch_helpers.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <context.h> +#include <drivers/arm/tzc380.h> +#include <drivers/console.h> +#include <drivers/generic_delay_timer.h> +#include <lib/el3_runtime/context_mgmt.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> + +#include <dram.h> +#include <gpc.h> +#include <imx_aipstz.h> +#include <imx_uart.h> +#include <imx_rdc.h> +#include <imx8m_caam.h> +#include <imx8m_csu.h> +#include <platform_def.h> +#include <plat_imx8.h> + +#define TRUSTY_PARAMS_LEN_BYTES (4096*2) + +static const mmap_region_t imx_mmap[] = { + GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, + CAAM_RAM_MAP, NS_OCRAM_MAP, ROM_MAP, DRAM_MAP, + {0}, +}; + +static const struct aipstz_cfg aipstz[] = { + {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, + {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, + {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, + {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, + {0}, +}; + +static const struct imx_rdc_cfg rdc[] = { + /* Master domain assignment */ + RDC_MDAn(RDC_MDA_M7, DID1), + + /* peripherals domain permission */ + RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), + RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), + + /* memory region */ + RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff), + RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff), + RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff), + + /* Sentinel */ + {0}, +}; + +static const struct imx_csu_cfg csu_cfg[] = { + /* peripherals csl setting */ + CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), + CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), + + /* master HP0~1 */ + + /* SA setting */ + + /* HP control setting */ + + /* Sentinel */ + {0} +}; + + +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/* get SPSR for BL33 entry */ +static uint32_t get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned long mode; + uint32_t spsr; + + /* figure out what mode we enter the non-secure world */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} + +static void bl31_tzc380_setup(void) +{ + unsigned int val; + + val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); + if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) + return; + + tzc380_init(IMX_TZASC_BASE); + + /* + * Need to substact offset 0x40000000 from CPU address when + * programming tzasc region for i.mx8mn. + */ + + /* Enable 1G-5G S/NS RW */ + tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | + TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); +} + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + static console_t console; + unsigned int val; + int i; + + /* Enable CSU NS access permission */ + for (i = 0; i < 64; i++) { + mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); + } + + imx_aipstz_init(aipstz); + + imx_rdc_init(rdc); + + imx_csu_init(csu_cfg); + + /* config the ocram memory range for secure access */ + mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4c1); + val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); + mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); + + console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + IMX_CONSOLE_BAUDRATE, &console); + /* This console is only used for boot stage */ + console_set_scope(&console, CONSOLE_FLAG_BOOT); + + imx8m_caam_init(); + + /* + * tell BL3-1 where the non-secure software image is located + * and the entry state information. + */ + bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; + bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + +#if defined(SPD_opteed) || defined(SPD_trusty) + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = 0; + + /* Pass TEE base and size to bl33 */ + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; + +#ifdef SPD_trusty + bl32_image_ep_info.args.arg0 = BL32_SIZE; + bl32_image_ep_info.args.arg1 = BL32_BASE; +#else + /* Make sure memory is clean */ + mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); + bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; + bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; +#endif +#endif + + bl31_tzc380_setup(); +} + +#define MAP_BL31_TOTAL \ + MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) +#define MAP_BL31_RO \ + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) +#define MAP_COHERENT_MEM \ + MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#define MAP_BL32_TOTAL \ + MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) + +void bl31_plat_arch_setup(void) +{ + const mmap_region_t bl_regions[] = { + MAP_BL31_TOTAL, + MAP_BL31_RO, +#if USE_COHERENT_MEM + MAP_COHERENT_MEM, +#endif + /* Map TEE memory */ + MAP_BL32_TOTAL, + {0} + }; + + setup_page_tables(bl_regions, imx_mmap); + enable_mmu_el3(0); +} + +void bl31_platform_setup(void) +{ + generic_delay_timer_init(); + + /* select the CKIL source to 32K OSC */ + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); + + /* Init the dram info */ + dram_info_init(SAVED_DRAM_TIMING_BASE); + + plat_gic_driver_init(); + plat_gic_init(); + + imx_gpc_init(); +} + +entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) +{ + if (type == NON_SECURE) + return &bl33_image_ep_info; + if (type == SECURE) + return &bl32_image_ep_info; + + return NULL; +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return COUNTER_FREQUENCY; +} + +#ifdef SPD_trusty +void plat_trusty_set_boot_args(aapcs64_params_t *args) +{ + args->arg0 = BL32_SIZE; + args->arg1 = BL32_BASE; + args->arg2 = TRUSTY_PARAMS_LEN_BYTES; +} +#endif diff --git a/plat/imx/imx8m/imx8mn/imx8mn_psci.c b/plat/imx/imx8m/imx8mn/imx8mn_psci.c new file mode 100644 index 0000000..f541fc1 --- /dev/null +++ b/plat/imx/imx8m/imx8mn/imx8mn_psci.c @@ -0,0 +1,44 @@ +/* + * Copyright 2019-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> + +#include <arch.h> +#include <arch_helpers.h> +#include <common/debug.h> +#include <lib/mmio.h> +#include <lib/psci/psci.h> + +#include <gpc.h> +#include <imx8m_psci.h> +#include <plat_imx8.h> + +static const plat_psci_ops_t imx_plat_psci_ops = { + .pwr_domain_on = imx_pwr_domain_on, + .pwr_domain_on_finish = imx_pwr_domain_on_finish, + .pwr_domain_off = imx_pwr_domain_off, + .validate_ns_entrypoint = imx_validate_ns_entrypoint, + .validate_power_state = imx_validate_power_state, + .cpu_standby = imx_cpu_standby, + .pwr_domain_suspend = imx_domain_suspend, + .pwr_domain_suspend_finish = imx_domain_suspend_finish, + .pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi, + .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, + .system_reset = imx_system_reset, + .system_off = imx_system_off, +}; + +/* export the platform specific psci ops */ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + /* sec_entrypoint is used for warm reset */ + imx_mailbox_init(sec_entrypoint); + + *psci_ops = &imx_plat_psci_ops; + + return 0; +} diff --git a/plat/imx/imx8m/imx8mn/include/gpc_reg.h b/plat/imx/imx8m/imx8mn/include/gpc_reg.h new file mode 100644 index 0000000..8a81368 --- /dev/null +++ b/plat/imx/imx8m/imx8mn/include/gpc_reg.h @@ -0,0 +1,111 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GPC_REG_H +#define GPC_REG_H + +#define LPCR_A53_BSC 0x0 +#define LPCR_A53_BSC2 0x108 +#define LPCR_A53_AD 0x4 +#define LPCR_M4 0x8 +#define SLPCR 0x14 +#define MST_CPU_MAPPING 0x18 +#define MLPCR 0x20 +#define PGC_ACK_SEL_A53 0x24 +#define IMR1_CORE0_A53 0x30 +#define IMR1_CORE1_A53 0x40 +#define IMR1_CORE2_A53 0x1C0 +#define IMR1_CORE3_A53 0x1D0 +#define IMR1_CORE0_M4 0x50 +#define SLT0_CFG 0xB0 +#define GPC_PU_PWRHSK 0x1FC +#define PGC_CPU_0_1_MAPPING 0xEC +#define CPU_PGC_UP_TRG 0xF0 +#define PU_PGC_UP_TRG 0xF8 +#define CPU_PGC_DN_TRG 0xFC +#define PU_PGC_DN_TRG 0x104 +#define LPS_CPU1 0x114 +#define A53_CORE0_PGC 0x800 +#define A53_PLAT_PGC 0x900 +#define PLAT_PGC_PCR 0x900 +#define NOC_PGC_PCR 0xa40 +#define PGC_SCU_TIMING 0x910 + +#define MASK_DSM_TRIGGER_A53 BIT(31) +#define IRQ_SRC_A53_WUP BIT(30) +#define IRQ_SRC_A53_WUP_SHIFT 30 +#define IRQ_SRC_C1 BIT(29) +#define IRQ_SRC_C0 BIT(28) +#define IRQ_SRC_C3 BIT(23) +#define IRQ_SRC_C2 BIT(22) +#define CPU_CLOCK_ON_LPM BIT(14) +#define A53_CLK_ON_LPM BIT(14) +#define MASTER0_LPM_HSK BIT(6) +#define MASTER1_LPM_HSK BIT(7) +#define MASTER2_LPM_HSK BIT(8) + +#define L2PGE BIT(31) +#define EN_L2_WFI_PDN BIT(5) +#define EN_PLAT_PDN BIT(4) + +#define SLPCR_EN_DSM BIT(31) +#define SLPCR_RBC_EN BIT(30) +#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17) +#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16) +#define SLPCR_VSTBY BIT(2) +#define SLPCR_SBYOS BIT(1) +#define SLPCR_BYPASS_PMIC_READY BIT(0) +#define SLPCR_RBC_COUNT_SHIFT 24 +#define SLPCR_STBY_COUNT_SHFT 3 + +#define A53_DUMMY_PDN_ACK BIT(15) +#define A53_DUMMY_PUP_ACK BIT(31) +#define A53_PLAT_PDN_ACK BIT(2) +#define A53_PLAT_PUP_ACK BIT(18) +#define NOC_PDN_SLT_CTRL BIT(10) +#define NOC_PUP_SLT_CTRL BIT(11) +#define NOC_PGC_PDN_ACK BIT(3) +#define NOC_PGC_PUP_ACK BIT(19) + +#define PLAT_PUP_SLT_CTRL BIT(9) +#define PLAT_PDN_SLT_CTRL BIT(8) + +#define SLT_PLAT_PDN BIT(8) +#define SLT_PLAT_PUP BIT(9) + +#define MASTER1_MAPPING BIT(1) +#define MASTER2_MAPPING BIT(2) + +#define TMR_TCD2_SHIFT 0 +#define TMC_TMR_SHIFT 10 +#define TRC1_TMC_SHIFT 20 + +#define MIPI_PWR_REQ BIT(0) +#define OTG1_PWR_REQ BIT(2) +#define HSIOMIX_PWR_REQ BIT(4) +#define DDRMIX_PWR_REQ BIT(5) +#define GPUMIX_PWR_REQ BIT(7) +#define DISPMIX_PWR_REQ BIT(10) + +#define DDRMIX_ADB400_SYNC BIT(2) +#define HSIOMIX_ADB400_SYNC BIT(5) +#define DISPMIX_ADB400_SYNC BIT(7) +#define GPUMIX_ADB400_SYNC (0x5 << 9) +#define DDRMIX_ADB400_ACK BIT(20) +#define HSIOMIX_ADB400_ACK BIT(23) +#define DISPMIX_ADB400_ACK BIT(25) +#define GPUMIX_ADB400_ACK (0x5 << 27) + +#define MIPI_PGC 0xc00 +#define OTG1_PGC 0xc80 +#define HSIOMIX_PGC 0xd00 +#define DDRMIX_PGC 0xd40 +#define GPUMIX_PGC 0xdc0 +#define DISPMIX_PGC 0xe80 + +#define IRQ_IMR_NUM U(4) + +#endif /* GPC_REG_H */ diff --git a/plat/imx/imx8m/imx8mn/include/imx_sec_def.h b/plat/imx/imx8m/imx8mn/include/imx_sec_def.h new file mode 100644 index 0000000..0ef14a9 --- /dev/null +++ b/plat/imx/imx8m/imx8mn/include/imx_sec_def.h @@ -0,0 +1,210 @@ +/* + * Copyright 2020-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX_SEC_DEF_H +#define IMX_SEC_DEF_H + +/* RDC MDA index */ +enum rdc_mda_idx { + RDC_MDA_A53 = 0, + RDC_MDA_M7 = 1, + RDC_MDA_SDMA3p = 3, + RDC_MDA_LCDIF = 5, + RDC_MDA_ISI = 6, + RDC_MDA_SDMA3b = 7, + RDC_MDA_Coresight = 8, + RDC_MDA_DAP = 9, + RDC_MDA_CAAM = 10, + RDC_MDA_SDMA1p = 11, + RDC_MDA_SDMA1b = 12, + RDC_MDA_APBHDMA = 13, + RDC_MDA_RAWNAND = 14, + RDC_MDA_uSDHC1 = 15, + RDC_MDA_uSDHC2 = 16, + RDC_MDA_uSDHC3 = 17, + RDC_MDA_GPU = 18, + RDC_MDA_USB1 = 19, + RDC_MDA_TESTPORT = 21, + RDC_MDA_ENET1_TX = 22, + RDC_MDA_ENET1_RX = 23, + RDC_MDA_SDMA2 = 24, +}; + +/* RDC Peripherals index */ +enum rdc_pdap_idx { + RDC_PDAP_GPIO1 = 0, + RDC_PDAP_GPIO2 = 1, + RDC_PDAP_GPIO3 = 2, + RDC_PDAP_GPIO4 = 3, + RDC_PDAP_GPIO5 = 4, + RDC_PDAP_ANA_TSENSOR = 6, + RDC_PDAP_ANA_OSC = 7, + RDC_PDAP_WDOG1 = 8, + RDC_PDAP_WDOG2 = 9, + RDC_PDAP_WDOG3 = 10, + RDC_PDAP_SDMA3 = 11, + RDC_PDAP_SDMA2 = 12, + RDC_PDAP_GPT1 = 13, + RDC_PDAP_GPT2 = 14, + RDC_PDAP_GPT3 = 15, + RDC_PDAP_ROMCP = 17, + RDC_PDAP_IOMUXC = 19, + RDC_PDAP_IOMUXC_GPR = 20, + RDC_PDAP_OCOTP_CTRL = 21, + RDC_PDAP_ANA_PLL = 22, + RDC_PDAP_SNVS_HP = 23, + RDC_PDAP_CCM = 24, + RDC_PDAP_SRC = 25, + RDC_PDAP_GPC = 26, + RDC_PDAP_SEMAPHORE1 = 27, + RDC_PDAP_SEMAPHORE2 = 28, + RDC_PDAP_RDC = 29, + RDC_PDAP_CSU = 30, + RDC_PDAP_LCDIF = 32, + RDC_PDAP_MIPI_DSI = 33, + RDC_PDAP_ISI = 34, + RDC_PDAP_MIPI_CSI = 35, + RDC_PDAP_USB1 = 36, + RDC_PDAP_PWM1 = 38, + RDC_PDAP_PWM2 = 39, + RDC_PDAP_PWM3 = 40, + RDC_PDAP_PWM4 = 41, + RDC_PDAP_System_Counter_RD = 42, + RDC_PDAP_System_Counter_CMP = 43, + RDC_PDAP_System_Counter_CTRL = 44, + RDC_PDAP_GPT6 = 46, + RDC_PDAP_GPT5 = 47, + RDC_PDAP_GPT4 = 48, + RDC_PDAP_TZASC = 56, + RDC_PDAP_PERFMON1 = 60, + RDC_PDAP_PERFMON2 = 61, + RDC_PDAP_PLATFORM_CTRL = 62, + RDC_PDAP_QoSC = 63, + RDC_PDAP_I2C1 = 66, + RDC_PDAP_I2C2 = 67, + RDC_PDAP_I2C3 = 68, + RDC_PDAP_I2C4 = 69, + RDC_PDAP_UART4 = 70, + RDC_PDAP_MU_A = 74, + RDC_PDAP_MU_B = 75, + RDC_PDAP_SEMAPHORE_HS = 76, + RDC_PDAP_SAI2 = 79, + RDC_PDAP_SAI3 = 80, + RDC_PDAP_SAI5 = 82, + RDC_PDAP_SAI6 = 83, + RDC_PDAP_uSDHC1 = 84, + RDC_PDAP_uSDHC2 = 85, + RDC_PDAP_uSDHC3 = 86, + RDC_PDAP_SAI7 = 87, + RDC_PDAP_SPBA2 = 90, + RDC_PDAP_QSPI = 91, + RDC_PDAP_SDMA1 = 93, + RDC_PDAP_ENET1 = 94, + RDC_PDAP_SPDIF1 = 97, + RDC_PDAP_eCSPI1 = 98, + RDC_PDAP_eCSPI2 = 99, + RDC_PDAP_eCSPI3 = 100, + RDC_PDAP_MICFIL = 101, + RDC_PDAP_UART1 = 102, + RDC_PDAP_UART3 = 104, + RDC_PDAP_UART2 = 105, + RDC_PDAP_ASRC = 107, + RDC_PDAP_SPBA1 = 111, + RDC_PDAP_CAAM = 114, +}; + +enum csu_csl_idx { + CSU_CSL_GPIO1 = 0, + CSU_CSL_GPIO2 = 1, + CSU_CSL_GPIO3 = 2, + CSU_CSL_GPIO4 = 3, + CSU_CSL_GPIO5 = 4, + CSU_CSL_ANA_TSENSOR = 6, + CSU_CSL_ANA_OSC = 7, + CSU_CSL_WDOG1 = 8, + CSU_CSL_WDOG2 = 9, + CSU_CSL_WDOG3 = 10, + CSU_CSL_SDMA2 = 12, + CSU_CSL_GPT1 = 13, + CSU_CSL_GPT2 = 14, + CSU_CSL_GPT3 = 15, + CSU_CSL_ROMCP = 17, + CSU_CSL_LCDIF = 18, + CSU_CSL_IOMUXC = 19, + CSU_CSL_IOMUXC_GPR = 20, + CSU_CSL_OCOTP_CTRL = 21, + CSU_CSL_ANA_PLL = 22, + CSU_CSL_SNVS_HP = 23, + CSU_CSL_CCM = 24, + CSU_CSL_SRC = 25, + CSU_CSL_GPC = 26, + CSU_CSL_SEMAPHORE1 = 27, + CSU_CSL_SEMAPHORE2 = 28, + CSU_CSL_RDC = 29, + CSU_CSL_CSU = 30, + CSU_CSL_DC_MST0 = 32, + CSU_CSL_DC_MST1 = 33, + CSU_CSL_DC_MST2 = 34, + CSU_CSL_DC_MST3 = 35, + CSU_CSL_PWM1 = 38, + CSU_CSL_PWM2 = 39, + CSU_CSL_PWM3 = 40, + CSU_CSL_PWM4 = 41, + CSU_CSL_System_Counter_RD = 42, + CSU_CSL_System_Counter_CMP = 43, + CSU_CSL_System_Counter_CTRL = 44, + CSU_CSL_GPT6 = 46, + CSU_CSL_GPT5 = 47, + CSU_CSL_GPT4 = 48, + CSU_CSL_TZASC = 56, + CSU_CSL_MTR = 59, + CSU_CSL_PERFMON1 = 60, + CSU_CSL_PERFMON2 = 61, + CSU_CSL_PLATFORM_CTRL = 62, + CSU_CSL_QoSC = 63, + CSU_CSL_MIPI_PHY = 64, + CSU_CSL_MIPI_DSI = 65, + CSU_CSL_I2C1 = 66, + CSU_CSL_I2C2 = 67, + CSU_CSL_I2C3 = 68, + CSU_CSL_I2C4 = 69, + CSU_CSL_UART4 = 70, + CSU_CSL_MIPI_CSI1 = 71, + CSU_CSL_MIPI_CSI_PHY1 = 72, + CSU_CSL_CSI1 = 73, + CSU_CSL_MU_A = 74, + CSU_CSL_MU_B = 75, + CSU_CSL_SEMAPHORE_HS = 76, + CSU_CSL_SAI1 = 78, + CSU_CSL_SAI6 = 80, + CSU_CSL_SAI5 = 81, + CSU_CSL_SAI4 = 82, + CSU_CSL_uSDHC1 = 84, + CSU_CSL_uSDHC2 = 85, + CSU_CSL_MIPI_CSI2 = 86, + CSU_CSL_MIPI_CSI_PHY2 = 87, + CSU_CSL_CSI2 = 88, + CSU_CSL_SPBA2 = 90, + CSU_CSL_QSPI = 91, + CSU_CSL_SDMA1 = 93, + CSU_CSL_ENET1 = 94, + CSU_CSL_SPDIF1 = 97, + CSU_CSL_eCSPI1 = 98, + CSU_CSL_eCSPI2 = 99, + CSU_CSL_eCSPI3 = 100, + CSU_CSL_UART1 = 102, + CSU_CSL_UART3 = 104, + CSU_CSL_UART2 = 105, + CSU_CSL_SPDIF2 = 106, + CSU_CSL_SAI2 = 107, + CSU_CSL_SAI3 = 108, + CSU_CSL_SPBA1 = 111, + CSU_CSL_CAAM = 114, + CSU_CSL_OCRAM = 118, + CSU_CSL_OCRAM_S = 119, +}; + +#endif /* IMX_SEC_DEF_H */ diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h new file mode 100644 index 0000000..c75e250 --- /dev/null +++ b/plat/imx/imx8m/imx8mn/include/platform_def.h @@ -0,0 +1,162 @@ +/* + * Copyright 2020-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/common_def.h> + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define PLATFORM_STACK_SIZE 0xB00 +#define CACHE_WRITEBACK_GRANULE 64 + +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) + +#define IMX_PWR_LVL0 MPIDR_AFFLVL0 +#define IMX_PWR_LVL1 MPIDR_AFFLVL1 +#define IMX_PWR_LVL2 MPIDR_AFFLVL2 + +#define PWR_DOMAIN_AT_MAX_LVL U(1) +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_OFF_STATE U(4) +#define PLAT_MAX_RET_STATE U(2) + +#define PLAT_WAIT_RET_STATE U(1) +#define PLAT_STOP_OFF_STATE U(3) + +#define PLAT_PRI_BITS U(3) +#define PLAT_SDEI_CRITICAL_PRI 0x10 +#define PLAT_SDEI_NORMAL_PRI 0x20 +#define PLAT_SDEI_SGI_PRIVATE U(9) + +#define BL31_BASE U(0x960000) +#define BL31_SIZE SZ_128K +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* non-secure uboot base */ +#define PLAT_NS_IMAGE_OFFSET U(0x40200000) + +#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) + +/* GICv3 base address */ +#define PLAT_GICD_BASE U(0x38800000) +#define PLAT_GICR_BASE U(0x38880000) + +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) + +#define MAX_XLAT_TABLES 8 +#define MAX_MMAP_REGIONS 16 + +#define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */ + +#define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */ +#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE +#define PLAT_CRASH_UART_CLK_IN_HZ 24000000 +#define IMX_CONSOLE_BAUDRATE 115200 + +#define IMX_AIPSTZ1 U(0x301f0000) +#define IMX_AIPSTZ2 U(0x305f0000) +#define IMX_AIPSTZ3 U(0x309f0000) +#define IMX_AIPSTZ4 U(0x32df0000) + +#define IMX_AIPS_BASE U(0x30000000) +#define IMX_AIPS_SIZE U(0x3000000) +#define IMX_GPV_BASE U(0x32000000) +#define IMX_GPV_SIZE U(0x800000) +#define IMX_AIPS1_BASE U(0x30200000) +#define IMX_AIPS4_BASE U(0x32c00000) +#define IMX_ANAMIX_BASE U(0x30360000) +#define IMX_CCM_BASE U(0x30380000) +#define IMX_SRC_BASE U(0x30390000) +#define IMX_GPC_BASE U(0x303a0000) +#define IMX_RDC_BASE U(0x303d0000) +#define IMX_CSU_BASE U(0x303e0000) +#define IMX_WDOG_BASE U(0x30280000) +#define IMX_SNVS_BASE U(0x30370000) +#define IMX_NOC_BASE U(0x32700000) +#define IMX_TZASC_BASE U(0x32F80000) +#define IMX_IOMUX_GPR_BASE U(0x30340000) +#define IMX_CAAM_BASE U(0x30900000) +#define IMX_DDRC_BASE U(0x3d400000) +#define IMX_DDRPHY_BASE U(0x3c000000) +#define IMX_DDR_IPS_BASE U(0x3d000000) +#define IMX_DDR_IPS_SIZE U(0x1800000) +#define IMX_ROM_BASE U(0x0) +#define IMX_ROM_SIZE U(0x40000) +#define IMX_NS_OCRAM_BASE U(0x900000) +#define IMX_NS_OCRAM_SIZE U(0x60000) +#define IMX_CAAM_RAM_BASE U(0x100000) +#define IMX_CAAM_RAM_SIZE U(0x10000) +#define IMX_DRAM_BASE U(0x40000000) +#define IMX_DRAM_SIZE U(0xc0000000) + +#define IMX_GIC_BASE PLAT_GICD_BASE +#define IMX_GIC_SIZE U(0x200000) + +#define WDOG_WSR U(0x2) +#define WDOG_WCR_WDZST BIT(0) +#define WDOG_WCR_WDBG BIT(1) +#define WDOG_WCR_WDE BIT(2) +#define WDOG_WCR_WDT BIT(3) +#define WDOG_WCR_SRS BIT(4) +#define WDOG_WCR_WDA BIT(5) +#define WDOG_WCR_SRE BIT(6) +#define WDOG_WCR_WDW BIT(7) + +#define SRC_A53RCR0 U(0x4) +#define SRC_A53RCR1 U(0x8) +#define SRC_OTG1PHY_SCR U(0x20) +#define SRC_GPR1_OFFSET U(0x74) + +#define SNVS_LPCR U(0x38) +#define SNVS_LPCR_SRTC_ENV BIT(0) +#define SNVS_LPCR_DP_EN BIT(5) +#define SNVS_LPCR_TOP BIT(6) + +#define IOMUXC_GPR10 U(0x28) +#define GPR_TZASC_EN BIT(0) +#define GPR_TZASC_EN_LOCK BIT(16) + +#define ANAMIX_MISC_CTL U(0x124) +#define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) + +#define MAX_CSU_NUM U(64) + +#define OCRAM_S_BASE U(0x00180000) +#define OCRAM_S_SIZE U(0x8000) +#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) +#define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE + +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define IMX_WDOG_B_RESET + +#define GIC_MAP MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW) +#define AIPS_MAP MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW) /* AIPS map */ +#define OCRAM_S_MAP MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW) /* OCRAM_S */ +#define DDRC_MAP MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW) /* DDRMIX */ +#define CAAM_RAM_MAP MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW) /* CAMM RAM */ +#define NS_OCRAM_MAP MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW) /* NS OCRAM */ +#define ROM_MAP MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO) /* ROM code */ + +/* + * Note: DRAM region is mapped with entire size available and uses MT_RW + * attributes. + * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section + * for explanation of this mapping scheme. + */ +#define DRAM_MAP MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS) /* DRAM */ + +#endif /* platform_def.h */ diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk new file mode 100644 index 0000000..1c0ad4f --- /dev/null +++ b/plat/imx/imx8m/imx8mn/platform.mk @@ -0,0 +1,77 @@ +# +# Copyright 2019-2022 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# + +PLAT_INCLUDES := -Iplat/imx/common/include \ + -Iplat/imx/imx8m/include \ + -Iplat/imx/imx8m/imx8mn/include +# Translation tables library +include lib/xlat_tables_v2/xlat_tables.mk + +# Include GICv3 driver files +include drivers/arm/gic/v3/gicv3.mk + +IMX_DRAM_SOURCES := plat/imx/imx8m/ddr/dram.c \ + plat/imx/imx8m/ddr/clock.c \ + plat/imx/imx8m/ddr/dram_retention.c \ + plat/imx/imx8m/ddr/ddr4_dvfs.c \ + plat/imx/imx8m/ddr/lpddr4_dvfs.c + + +IMX_GIC_SOURCES := ${GICV3_SOURCES} \ + plat/common/plat_gicv3.c \ + plat/common/plat_psci_common.c \ + plat/imx/common/plat_imx8_gic.c + +BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + plat/imx/imx8m/gpc_common.c \ + plat/imx/imx8m/imx_hab.c \ + plat/imx/imx8m/imx_aipstz.c \ + plat/imx/imx8m/imx_rdc.c \ + plat/imx/imx8m/imx8m_caam.c \ + plat/imx/imx8m/imx8m_csu.c \ + plat/imx/imx8m/imx8m_psci_common.c \ + plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c \ + plat/imx/imx8m/imx8mn/imx8mn_psci.c \ + plat/imx/imx8m/imx8mn/gpc.c \ + plat/imx/common/imx8_topology.c \ + plat/imx/common/imx_sip_handler.c \ + plat/imx/common/imx_sip_svc.c \ + plat/imx/common/imx_uart_console.S \ + lib/cpus/aarch64/cortex_a53.S \ + drivers/arm/tzc/tzc380.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + ${IMX_DRAM_SOURCES} \ + ${IMX_GIC_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} + +ENABLE_PIE := 1 +USE_COHERENT_MEM := 1 +RESET_TO_BL31 := 1 +A53_DISABLE_NON_TEMPORAL_HINT := 0 + +ERRATA_A53_835769 := 1 +ERRATA_A53_843419 := 1 +ERRATA_A53_855873 := 1 + +BL32_BASE ?= 0xbe000000 +$(eval $(call add_define,BL32_BASE)) + +BL32_SIZE ?= 0x2000000 +$(eval $(call add_define,BL32_SIZE)) + +IMX_BOOT_UART_BASE ?= 0x30890000 +$(eval $(call add_define,IMX_BOOT_UART_BASE)) + +EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT) +ifeq (${SDEI_SUPPORT}, 1) +BL31_SOURCES += plat/imx/common/imx_ehf.c \ + plat/imx/common/imx_sdei.c +endif + +ifeq (${SPD},trusty) + BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 +endif |