diff options
Diffstat (limited to 'plat/mediatek/mt8186/drivers/dfd')
| -rw-r--r-- | plat/mediatek/mt8186/drivers/dfd/plat_dfd.c | 98 | ||||
| -rw-r--r-- | plat/mediatek/mt8186/drivers/dfd/plat_dfd.h | 64 |
2 files changed, 162 insertions, 0 deletions
diff --git a/plat/mediatek/mt8186/drivers/dfd/plat_dfd.c b/plat/mediatek/mt8186/drivers/dfd/plat_dfd.c new file mode 100644 index 0000000..ade0837 --- /dev/null +++ b/plat/mediatek/mt8186/drivers/dfd/plat_dfd.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <common/debug.h> +#include <lib/mmio.h> +#include <mtk_sip_svc.h> +#include <plat_dfd.h> + +static bool dfd_enabled; +static uint64_t dfd_base_addr; +static uint64_t dfd_chain_length; +static uint64_t dfd_cache_dump; + +static void dfd_setup(uint64_t base_addr, uint64_t chain_length, + uint64_t cache_dump) +{ + mmio_write_32(MCUSYS_DFD_MAP, base_addr >> 24); + mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_0); + + sync_writel(DFD_INTERNAL_CTL, (BIT(0) | BIT(2))); + + mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); + mmio_setbits_32(DFD_INTERNAL_CTL, BIT(3)); + mmio_setbits_32(DFD_INTERNAL_CTL, (BIT(19) | BIT(20))); + mmio_write_32(DFD_INTERNAL_PWR_ON, (BIT(0) | BIT(1) | BIT(3))); + mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); + mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0); + mmio_write_32(DFD_INTERNAL_TEST_SO_0, DFD_INTERNAL_TEST_SO_0_VAL); + mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 1); + + mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_VAL); + mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL); + + sync_writel(DFD_V30_CTL, 1); + + mmio_write_32(DFD_V30_BASE_ADDR, (base_addr & 0xFFF00000)); + + /* setup global variables for suspend and resume */ + dfd_enabled = true; + dfd_base_addr = base_addr; + dfd_chain_length = chain_length; + dfd_cache_dump = cache_dump; + + if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { + mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_1); + sync_writel(DFD_V35_ENALBE, 1); + sync_writel(DFD_V35_TAP_NUMBER, DFD_V35_TAP_NUMBER_VAL); + sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); + sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); + + if (cache_dump & DFD_PARITY_ERR_TRIGGER) { + sync_writel(DFD_HW_TRIGGER_MASK, DFD_HW_TRIGGER_MASK_VAL); + mmio_setbits_32(DFD_INTERNAL_CTL, BIT(4)); + } + } + dsbsy(); +} + +void dfd_resume(void) +{ + if (dfd_enabled == true) { + dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); + } +} + +uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, + uint64_t arg2, uint64_t arg3) +{ + uint64_t ret = 0L; + + switch (arg0) { + case PLAT_MTK_DFD_SETUP_MAGIC: + INFO("[%s] DFD setup call from kernel\n", __func__); + dfd_setup(arg1, arg2, arg3); + break; + case PLAT_MTK_DFD_READ_MAGIC: + /* only allow to access DFD register base + 0x200 */ + if (arg1 <= 0x200) { + ret = mmio_read_32(MISC1_CFG_BASE + arg1); + } + break; + case PLAT_MTK_DFD_WRITE_MAGIC: + /* only allow to access DFD register base + 0x200 */ + if (arg1 <= 0x200) { + sync_writel(MISC1_CFG_BASE + arg1, arg2); + } + break; + default: + ret = MTK_SIP_E_INVALID_PARAM; + break; + } + + return ret; +} diff --git a/plat/mediatek/mt8186/drivers/dfd/plat_dfd.h b/plat/mediatek/mt8186/drivers/dfd/plat_dfd.h new file mode 100644 index 0000000..1901ec9 --- /dev/null +++ b/plat/mediatek/mt8186/drivers/dfd/plat_dfd.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DFD_H +#define PLAT_DFD_H + +#include <arch_helpers.h> +#include <lib/mmio.h> +#include <platform_def.h> + +#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \ + dsbsy(); \ + } while (0) + +#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150) +#define PLAT_MTK_DFD_READ_MAGIC (0x99716151) +#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152) + +#define MCU_BIU_BASE (MCUCFG_BASE) +#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xA040) + +#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) +#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08) +#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C) +#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10) +#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28) +#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30) +#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48) +#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C) +#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58) +#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C) +#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC) + +#define DFD_V35_ENALBE (MCU_BIU_BASE + 0xA0A8) +#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xA0AC) +#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xA0B0) +#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xA0C0) +#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xA0C4) + +#define DFD_CACHE_DUMP_ENABLE (1U) +#define DFD_PARITY_ERR_TRIGGER (2U) + +#define MCUSYS_DFD_MAP (0x10001390) +#define WDT_DEBUG_CTL (0x10007048) + +#define WDT_DEBUG_CTL_VAL_0 (0x950603A0) +#define DFD_INTERNAL_TEST_SO_0_VAL (0x3B) +#define DFD_TEST_SI_0_VAL (0x108) +#define DFD_TEST_SI_1_VAL (0x20200000) + +#define WDT_DEBUG_CTL_VAL_1 (0x95063E80) +#define DFD_V35_TAP_NUMBER_VAL (0xA) +#define DFD_V35_TAP_EN_VAL (0x3FF) +#define DFD_V35_SEQ0_0_VAL (0x63668820) +#define DFD_HW_TRIGGER_MASK_VAL (0xC) + +void dfd_resume(void); +uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, + uint64_t arg2, uint64_t arg3); + +#endif /* PLAT_DFD_H */ |