Adding upstream version 15.1.upstream/15.1upstream

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

1 files changed, 164 insertions, 0 deletions

diff --git a/isa-list b/isa-list
new file mode 100644
index 0000000..1a357bc
--- /dev/null
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+# Recognized fields:
+# "Name": the isa extension name, the package will be ${Name}-support
+# "Architecture": archs to build the package on, wildcards are ok
+# "Test": how to detect it, defaults to return !__builtin_cpu_supports("$Name");
+#     If the test program dies (SIGILL/etc), that's ok, the answer is "no".
+# CFLAGS: passed to the C compiler, can include link-time flags too.
+# Description: added to package's description.
+
+Name: SSE2
+Architecture: any-i386
+qemu-good: qemu-$DEB_HOST_ARCH -cpu "qemu$DEB_HOST_ARCH_BITS"
+qemu-bad: qemu-$DEB_HOST_ARCH -cpu "qemu$DEB_HOST_ARCH_BITS",-see2,-sse3,-ssse3,-sse4.1,-sse4.2
+Description:
+ Streaming SIMD Extensions (SSE) is a single instruction, multiple data
+ (SIMD) instruction set extension.
+ .
+ SSE2 was an incremental upgrade to SSE intended to fully replace the earlier
+ MMX instruction set. It is available on processors from Pentium 4 onward,
+ including all 64-bit capable ones, but not on Pentium 3, Athlon XP, Via C3,
+ Quark, or older processors.
+
+Name: SSE3
+Architecture: any-i386 any-amd64
+qemu-good: qemu-$DEB_HOST_ARCH -cpu "qemu$DEB_HOST_ARCH_BITS"
+qemu-bad: qemu-$DEB_HOST_ARCH -cpu "qemu$DEB_HOST_ARCH_BITS",-sse3,-ssse3,-sse4.1,-sse4.2
+Description:
+ Streaming SIMD Extensions (SSE) is a single instruction, multiple data
+ (SIMD) instruction set extension.
+ .
+ SSE3, also called PNI (Prescott New Instructions), is an incremental upgrade
+ to SSE2, adding a handful of new operations useful for processing media. It
+ is available on almost any 64-bit-capable processor except for some early
+ AMD models (Sledgehammer and Clawhammer), but is not available on most
+ 32-bit-only hardware.
+
+Name: SSE4.1
+Architecture: any-i386 any-amd64
+qemu-good: qemu-$DEB_HOST_ARCH -cpu "qemu$DEB_HOST_ARCH_BITS"
+qemu-bad: qemu-$DEB_HOST_ARCH -cpu "qemu$DEB_HOST_ARCH_BITS",-sse4.1,-sse4.2
+Description:
+ Streaming SIMD Extensions (SSE) is a single instruction, multiple data
+ (SIMD) instruction set extension.
+ .
+ SSE4.1 added a dot product instruction and additional integer instructions.
+ It is available on Intel processors since Penryn (circa 2008), but notably
+ not on anything AMD until the Bulldozer (15h, in 2011) and Jaguar (16h, in
+ 2013) families.
+
+Name: SSE4.2
+Architecture: any-i386 any-amd64
+qemu-good: qemu-$DEB_HOST_ARCH -cpu "qemu$DEB_HOST_ARCH_BITS"
+qemu-bad: qemu-$DEB_HOST_ARCH -cpu "qemu$DEB_HOST_ARCH_BITS",-sse4.2
+Description:
+ SSE4.2 added string and text processing instructions that perform character
+ searches and comparison on two operands of 16 bytes at a time. It is
+ available on Intel processors since Nehalem (circa 2008), but notably not
+ on anything AMD until the Bulldozer (15h, in 2011) and Jaguar (16h, in
+ 2013) families.
+
+Name: altivec
+Architecture: powerpc
+Test: asm volatile("vsldoi %v1,%v1,%v1,0");
+Description:
+ AltiVec is a single-precision floating point and integer SIMD instruction
+ set. It is a standard part of the Power ISA v.2.03 specification.
+# gcc-16 has __builtin_cpu_supports("altivec") but it's not reliable: silently
+# gives wrong answer on qemu, wrong versions of glibc, non-glibc, etc.
+# Thus, let's use SIGILL instead.
+
+Name: neon
+Architecture: armhf
+CFLAGS: -mfpu=neon
+Test: asm volatile("VMUL.I16 q0,q0,q1");
+Description:
+ This is a mostly dummy package which checks for Neon and refuses to install
+ on unsupported hardware.
+ .
+ Neon, also known as MPE (Media Processing Engine) or Advanced SIMD, is a
+ combined 64- and 128-bit SIMD instruction set that provides standardised
+ acceleration for media and signal processing applications. It is available
+ on the vast majority of armhf devices but not guaranteed before the 64-bit
+ capable ARMv8.
+
+Name: ARMv6
+Architecture: armel
+Test: return !need_armv_version(6);
+Description:
+ The ARMv6 architecture (not to be confused with product family ARM6) uses
+ physically addressed cache, solving many cache aliasing problems and
+ reducing context switch overhead. Unaligned and mixed-endian data access is
+ supported. This architecture includes the first version of Thumb
+ technology.
+ .
+ This feature is not guaranteed by the architecture baseline, but is
+ available for newer armel machines in the ARM11 product family, including
+ ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, ARM1136EJ(F)-S, and
+ ARM11MPCore processors. Boards include the Raspberry Pi model 1 and
+ Raspberry Pi Zero.
+
+Name: ARMv6K
+Architecture: armel
+Test: return !(need_armv_version(6) && (getauxval(AT_HWCAP) & HWCAP_ARM_TLS));
+Description:
+ ARMv6k is a subarchitecture of ARMV6 adding Symmetric MultiProcessing
+ and Thread Local Storage instruction sets. It is not guaranteed by the
+ architecture baseline, but is available for newer armel machines in the
+ ARM11 product family; boards include the Raspberry Pi model 1 and
+ Raspberry Pi Zero.
+
+Name: ARMv7
+Architecture: armel
+Test: return !need_armv_version(7);
+Description:
+ ARMv7 (not to be confused with product family ARM7) includes Thumb-2
+ technology, adding 32-bit instructions into compressed Thumb mode. It is
+ not guaranteed by the architecture baseline, but is available for newer
+ armel machines (including CPUs that support armhf) since the Cortex-A
+ product family, including Cortex-A5, -A7, -A8, -A9, -A12, -A15, and -A17
+ processors. Boards include the Raspberry Pi 2.
+
+Name: ARMv8
+Architecture: armel armhf
+Test: return !need_armv_version(8);
+Description:
+ ARMv8 (not to be confused with product family ARM8) introduced a large
+ number of ISA enhancements. It is not guaranteed by the architecture
+ baseline, but is available for newer armel machines (including CPUs that
+ support armhf) since the Cortex-A product family, including Cortex-A32, as
+ well as all arm64 processors. Boards include the Raspberry Pi 3 and 4.
+
+Name: VFP
+Architecture: armel
+Test: return !(getauxval(AT_HWCAP) & HWCAP_ARM_VFP)
+Description:
+ VFP (Vector Floating Point) technology is a floating-point unit (FPU)
+ coprocessor extension to the ARM architecture. It provides single- and
+ double-precision floating-point computation fully compliant with IEEE
+ 754-1985.
+
+Name: VFPv2
+Architecture: armel
+Test: return !(need_armv_version(5) && (getauxval(AT_HWCAP) & HWCAP_ARM_VFP))
+Description:
+ VFP (Vector Floating Point) technology is a floating-point unit (FPU)
+ coprocessor extension to the ARM architecture. It provides single- and
+ double-precision floating-point computation fully compliant with IEEE
+ 754-1985.
+ .
+ VFPv2 has 16 64-bit FPU registers. It is available for some ARMv5 and
+ all ARMv6 cores.
+
+Name: VFPv3
+Architecture: armel
+Test: return !(getauxval(AT_HWCAP) & HWCAP_ARM_VFPv3)
+Description:
+ VFP (Vector Floating Point) technology is a floating-point unit (FPU)
+ coprocessor extension to the ARM architecture. It provides single- and
+ double-precision floating-point computation fully compliant with IEEE
+ 754-1985.
+ .
+ VFPv3 has 32 64-bit FPU registers as standard, adds VCVT instructions to
+ convert between scalar, float, and double, and adds immediate mode to VMOV,
+ allowing constants to be loaded into FPU registers. It is available on most
+ Cortex-A8 and -A9 ARMv7 processors.