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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-28 07:24:57 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-28 07:24:57 +0000
commit070852d8604cece0c31f28ff3eb8d21d9ba415fb (patch)
tree9097175a6a5b8b7e37af9a96269ac0b61a0189cd /decoder/tests/snapshots/a57_single_step/device1.ini
parentInitial commit. (diff)
downloadlibopencsd-070852d8604cece0c31f28ff3eb8d21d9ba415fb.tar.xz
libopencsd-070852d8604cece0c31f28ff3eb8d21d9ba415fb.zip
Adding upstream version 1.3.3.upstream/1.3.3upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'decoder/tests/snapshots/a57_single_step/device1.ini')
-rw-r--r--decoder/tests/snapshots/a57_single_step/device1.ini451
1 files changed, 451 insertions, 0 deletions
diff --git a/decoder/tests/snapshots/a57_single_step/device1.ini b/decoder/tests/snapshots/a57_single_step/device1.ini
new file mode 100644
index 0000000..3a2e24d
--- /dev/null
+++ b/decoder/tests/snapshots/a57_single_step/device1.ini
@@ -0,0 +1,451 @@
+[device]
+name=Cortex-A57_0
+class=core
+type=Cortex-A57
+
+[regs]
+X0(size:64)=0x00000000002971C8
+X1(size:64)=0x00000000910163E0
+X2(size:64)=0x00000000FFD0C1C4
+X3(size:64)=0x0000000000345000
+X4(size:64)=0x0000000000000004
+X5(size:64)=0x00000000FC01EB50
+X6(size:64)=0x00000000FC01EB4C
+X7(size:64)=0x0000000000000000
+X8(size:64)=0x00000000FC01E9C8
+X9(size:64)=0xFFFFFFFFFFFFFFFF
+X10(size:64)=0x0000000000000006
+X11(size:64)=0x0000000000000000
+X12(size:64)=0x00000000407FE0FA
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+X18(size:64)=0x0000000000000000
+X19(size:64)=0x00000000C2800290
+X20(size:64)=0x0000000000000000
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+X27(size:64)=0x0000000000000000
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+X29(size:64)=0x0000000000000000
+LR(size:64)=0x00000000FFFEAF48
+PC(size:64)=0x00000000FFFEB44C
+SP(size:64)=0x00000000FC01EBA0
+W0=0x002971C8
+W1=0x910163E0
+W2=0xFFD0C1C4
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+W4=0x00000004
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+DBGBVR3_EL1(size:64)=0x0000000000000000
+DBGBVR4_EL1(size:64)=0x0000000000000000
+DBGBVR5_EL1(size:64)=0x0000000000000000
+DBGCLAIMCLR_EL1=0x00000000
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+DBGWVR2_EL1(size:64)=0x0000000000000000
+DBGWVR3_EL1(size:64)=0x0000000000000000
+MDCCINT_EL1=0x00000000
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+MDCR_EL3=0x00000000
+MDRAR_EL1(size:64)=0x0000000410000003
+MDSCR_EL1=0x00004000
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+OSDTRTX_EL1=0x00000000
+OSECCR_EL1=0x00000000
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+AFSR0_EL3=0x00000000
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+ESR_EL1=0x00000000
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+FAR_EL1(size:64)=0x0000000000000000
+FAR_EL2(size:64)=0x0000000000000000
+FAR_EL3(size:64)=0x0000000000000000
+HPFAR_EL2(size:64)=0x0000000000000000
+ISR_EL1=0x00000000
+VBAR_EL1(size:64)=0x0000000000000000
+VBAR_EL2(size:64)=0x00000000C0007000
+VBAR_EL3(size:64)=0x0000000000000000
+FPCR=0x00000000
+FPSR=0x00000000
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+ICC_AP0R0_EL1=0x00000000
+ICC_AP1R0_EL1=0x00000000
+S_ICC_AP1R0_EL1=0x00000000
+N_ICC_AP1R0_EL1=0x00000000
+ICC_BPR0_EL1=0x00000002
+ICC_BPR1_EL1=0x00000003
+S_ICC_BPR1_EL1=0x00000002
+N_ICC_BPR1_EL1=0x00000003
+ICC_CTLR_EL1=0x00004400
+S_ICC_CTLR_EL1=0x00004400
+N_ICC_CTLR_EL1=0x00004400
+ICC_CTLR_EL3=0x00004400
+ICC_HPPIR0_EL1=0x000003FF
+ICC_HPPIR1_EL1=0x000003FF
+ICC_IAR0_EL1=0x000003FF
+ICC_IAR1_EL1=0x000003FF
+ICC_IGRPEN0_EL1=0x00000000
+ICC_IGRPEN1_EL1=0x00000000
+S_ICC_IGRPEN1_EL1=0x00000000
+N_ICC_IGRPEN1_EL1=0x00000000
+ICC_IGRPEN1_EL3=0x00000000
+ICC_PMR_EL1=0x00000000
+ICC_RPR_EL1=0x000000FF
+ICC_SRE_EL1=0x00000007
+S_ICC_SRE_EL1=0x00000007
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+ICC_SRE_EL2=0x0000000F
+ICC_SRE_EL3=0x0000000F
+ICH_AP0R0_EL2=0x00000000
+ICH_AP1R0_EL2=0x00000000
+ICH_EISR_EL2=0x00000000
+ICH_ELRSR_EL2=0x000000FF
+ICH_HCR_EL2=0x00000000
+ICH_LR0_EL2(size:64)=0x0000000000000000
+ICH_LR1_EL2(size:64)=0x0000000000000000
+ICH_LR2_EL2(size:64)=0x0000000000000000
+ICH_LR3_EL2(size:64)=0x0000000000000000
+ICH_LR4_EL2(size:64)=0x0000000000000000
+ICH_LR5_EL2(size:64)=0x0000000000000000
+ICH_LR6_EL2(size:64)=0x0000000000000000
+ICH_LR7_EL2(size:64)=0x0000000000000000
+ICH_MISR_EL2=0x00000000
+ICH_VMCR_EL2=0x004C0008
+ICH_VTR_EL2=0x90580007
+AIDR_EL1=0x00000000
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+CLIDR_EL1(size:64)=0x000000000B200123
+CSSELR_EL1=0x00000000
+CTR_EL0=0x8444C004
+DCZID_EL0=0x00000004
+ID_AA64AFR0_EL1(size:64)=0x0000000000000000
+ID_AA64AFR1_EL1(size:64)=0x0000000000000000
+ID_AA64DFR0_EL1(size:64)=0x0000000010305407
+ID_AA64DFR1_EL1(size:64)=0x0000000000000000
+ID_AA64ISAR0_EL1(size:64)=0x0000000010211120
+ID_AA64ISAR1_EL1(size:64)=0x0000000000000000
+ID_AA64MMFR0_EL1(size:64)=0x0000000000001124
+ID_AA64MMFR1_EL1(size:64)=0x0000000001111120
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+VMPIDR_EL2(size:64)=0x0000000080000000
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+ACTLR_EL1(size:64)=0x0000000000000000
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+TCR_EL1(size:64)=0x0000000080000000
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+TTBR0_EL2(size:64)=0x00000000FFFFD000
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+TTBR1_EL1(size:64)=0x0000000000000000
+VTCR_EL2=0x80000000
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+CPACR_EL1=0x00000000
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+SCTLR_EL2=0x30401805
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+PMCCFILTR_EL0=0x00000000
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+RVBAR_EL3(size:64)=0x0000000000000000
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+SCR_EL3=0x00000531
+ELR_EL1(size:64)=0x0000000000000000
+ELR_EL2(size:64)=0x0000000000000000
+ELR_EL3(size:64)=0x0000000000000000
+SPSR_EL1=0x00000000
+SPSR_EL2=0x00000000
+SPSR_EL3=0x00000000
+SPSR_ABT=0x00000000
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+SPSR_IRQ=0x00000000
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+SP_EL3(size:64)=0x0000000000000000
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+TPIDR_EL0(size:64)=0x0000000000000000
+TPIDR_EL1(size:64)=0x0000000000000000
+TPIDR_EL2(size:64)=0x0000000000000000
+TPIDR_EL3(size:64)=0x0000000000000000
+CNTFRQ_EL0=0x05F5E100
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+CNTHP_TVAL_EL2=0xFBDEF81B
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+CNTPS_CVAL_EL1(size:64)=0x0000000000000000
+CNTPS_TVAL_EL1=0xFBDE0D61
+CNTP_CTL_EL0=0x00000000
+CNTP_CVAL_EL0(size:64)=0x0000000000000000
+CNTP_TVAL_EL0=0xFBDD778C
+CNTVCT_EL0(size:64)=0x000000000422AE1E
+CNTVOFF_EL2(size:64)=0x0000000000000000
+CNTV_CTL_EL0=0x00000000
+CNTV_CVAL_EL0(size:64)=0x0000000000000000
+CNTV_TVAL_EL0=0xFBDCA814
+CPTR_EL2=0x00000000
+HCR_EL2(size:64)=0x000000008000003A
+HSTR_EL2=0x00000000
+CPSR=0x200003C9
+
+[dump1]
+space=EL2
+address=0xFFFEB448
+file=mem_Cortex-A57_0.bin
+