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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:45 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:45 +0000
commit2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch)
tree848558de17fb3008cdf4d861b01ac7781903ce39 /arch/mips/pci/fixup-ip32.c
parentInitial commit. (diff)
downloadlinux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz
linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip
Adding upstream version 6.1.76.upstream/6.1.76
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/mips/pci/fixup-ip32.c')
-rw-r--r--arch/mips/pci/fixup-ip32.c52
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/mips/pci/fixup-ip32.c b/arch/mips/pci/fixup-ip32.c
new file mode 100644
index 000000000..d091ffc53
--- /dev/null
+++ b/arch/mips/pci/fixup-ip32.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <asm/ip32/ip32_ints.h>
+/*
+ * O2 has up to 5 PCI devices connected into the MACE bridge. The device
+ * map looks like this:
+ *
+ * 0 aic7xxx 0
+ * 1 aic7xxx 1
+ * 2 expansion slot
+ * 3 N/C
+ * 4 N/C
+ */
+
+#define SCSI0 MACEPCI_SCSI0_IRQ
+#define SCSI1 MACEPCI_SCSI1_IRQ
+#define INTA0 MACEPCI_SLOT0_IRQ
+#define INTA1 MACEPCI_SLOT1_IRQ
+#define INTA2 MACEPCI_SLOT2_IRQ
+#define INTB MACEPCI_SHARED0_IRQ
+#define INTC MACEPCI_SHARED1_IRQ
+#define INTD MACEPCI_SHARED2_IRQ
+static char irq_tab_mace[][5] = {
+ /* Dummy INT#A INT#B INT#C INT#D */
+ {0, 0, 0, 0, 0}, /* This is placeholder row - never used */
+ {0, SCSI0, SCSI0, SCSI0, SCSI0},
+ {0, SCSI1, SCSI1, SCSI1, SCSI1},
+ {0, INTA0, INTB, INTC, INTD},
+ {0, INTA1, INTC, INTD, INTB},
+ {0, INTA2, INTD, INTB, INTC},
+};
+
+
+/*
+ * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
+ * the device (1-4 => A-D), tell what irq to use. Note that we don't
+ * in theory have slots 4 and 5, and we never normally use the shared
+ * irqs. I suppose a device without a pin A will thank us for doing it
+ * right if there exists such a broken piece of crap.
+ */
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ return irq_tab_mace[slot][pin];
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ return 0;
+}