diff options
Diffstat (limited to 'arch/parisc/mm')
| -rw-r--r-- | arch/parisc/mm/Makefile | 7 | ||||
| -rw-r--r-- | arch/parisc/mm/fault.c | 521 | ||||
| -rw-r--r-- | arch/parisc/mm/fixmap.c | 41 | ||||
| -rw-r--r-- | arch/parisc/mm/hugetlbpage.c | 193 | ||||
| -rw-r--r-- | arch/parisc/mm/init.c | 893 | ||||
| -rw-r--r-- | arch/parisc/mm/ioremap.c | 100 |
6 files changed, 1755 insertions, 0 deletions
diff --git a/arch/parisc/mm/Makefile b/arch/parisc/mm/Makefile new file mode 100644 index 000000000..ffdb5c0a8 --- /dev/null +++ b/arch/parisc/mm/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for arch/parisc/mm +# + +obj-y := init.o fault.o ioremap.o fixmap.o +obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c new file mode 100644 index 000000000..b00aa98b5 --- /dev/null +++ b/arch/parisc/mm/fault.c @@ -0,0 +1,521 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * + * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle + * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) + * Copyright 1999 Hewlett Packard Co. + * + */ + +#include <linux/mm.h> +#include <linux/ptrace.h> +#include <linux/sched.h> +#include <linux/sched/debug.h> +#include <linux/interrupt.h> +#include <linux/extable.h> +#include <linux/uaccess.h> +#include <linux/hugetlb.h> +#include <linux/perf_event.h> + +#include <asm/traps.h> + +#define DEBUG_NATLB 0 + +/* Various important other fields */ +#define bit22set(x) (x & 0x00000200) +#define bits23_25set(x) (x & 0x000001c0) +#define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80) + /* extended opcode is 0x6a */ + +#define BITSSET 0x1c0 /* for identifying LDCW */ + + +int show_unhandled_signals = 1; + +/* + * parisc_acctyp(unsigned int inst) -- + * Given a PA-RISC memory access instruction, determine if the + * instruction would perform a memory read or memory write + * operation. + * + * This function assumes that the given instruction is a memory access + * instruction (i.e. you should really only call it if you know that + * the instruction has generated some sort of a memory access fault). + * + * Returns: + * VM_READ if read operation + * VM_WRITE if write operation + * VM_EXEC if execute operation + */ +unsigned long +parisc_acctyp(unsigned long code, unsigned int inst) +{ + if (code == 6 || code == 16) + return VM_EXEC; + + switch (inst & 0xf0000000) { + case 0x40000000: /* load */ + case 0x50000000: /* new load */ + return VM_READ; + + case 0x60000000: /* store */ + case 0x70000000: /* new store */ + return VM_WRITE; + + case 0x20000000: /* coproc */ + case 0x30000000: /* coproc2 */ + if (bit22set(inst)) + return VM_WRITE; + fallthrough; + + case 0x0: /* indexed/memory management */ + if (bit22set(inst)) { + /* + * Check for the 'Graphics Flush Read' instruction. + * It resembles an FDC instruction, except for bits + * 20 and 21. Any combination other than zero will + * utilize the block mover functionality on some + * older PA-RISC platforms. The case where a block + * move is performed from VM to graphics IO space + * should be treated as a READ. + * + * The significance of bits 20,21 in the FDC + * instruction is: + * + * 00 Flush data cache (normal instruction behavior) + * 01 Graphics flush write (IO space -> VM) + * 10 Graphics flush read (VM -> IO space) + * 11 Graphics flush read/write (VM <-> IO space) + */ + if (isGraphicsFlushRead(inst)) + return VM_READ; + return VM_WRITE; + } else { + /* + * Check for LDCWX and LDCWS (semaphore instructions). + * If bits 23 through 25 are all 1's it is one of + * the above two instructions and is a write. + * + * Note: With the limited bits we are looking at, + * this will also catch PROBEW and PROBEWI. However, + * these should never get in here because they don't + * generate exceptions of the type: + * Data TLB miss fault/data page fault + * Data memory protection trap + */ + if (bits23_25set(inst) == BITSSET) + return VM_WRITE; + } + return VM_READ; /* Default */ + } + return VM_READ; /* Default */ +} + +#undef bit22set +#undef bits23_25set +#undef isGraphicsFlushRead +#undef BITSSET + + +#if 0 +/* This is the treewalk to find a vma which is the highest that has + * a start < addr. We're using find_vma_prev instead right now, but + * we might want to use this at some point in the future. Probably + * not, but I want it committed to CVS so I don't lose it :-) + */ + while (tree != vm_avl_empty) { + if (tree->vm_start > addr) { + tree = tree->vm_avl_left; + } else { + prev = tree; + if (prev->vm_next == NULL) + break; + if (prev->vm_next->vm_start > addr) + break; + tree = tree->vm_avl_right; + } + } +#endif + +int fixup_exception(struct pt_regs *regs) +{ + const struct exception_table_entry *fix; + + fix = search_exception_tables(regs->iaoq[0]); + if (fix) { + /* + * Fix up get_user() and put_user(). + * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant + * bit in the relative address of the fixup routine to indicate + * that gr[ASM_EXCEPTIONTABLE_REG] should be loaded with + * -EFAULT to report a userspace access error. + */ + if (fix->fixup & 1) { + regs->gr[ASM_EXCEPTIONTABLE_REG] = -EFAULT; + + /* zero target register for get_user() */ + if (parisc_acctyp(0, regs->iir) == VM_READ) { + int treg = regs->iir & 0x1f; + BUG_ON(treg == 0); + regs->gr[treg] = 0; + } + } + + regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup; + regs->iaoq[0] &= ~3; + /* + * NOTE: In some cases the faulting instruction + * may be in the delay slot of a branch. We + * don't want to take the branch, so we don't + * increment iaoq[1], instead we set it to be + * iaoq[0]+4, and clear the B bit in the PSW + */ + regs->iaoq[1] = regs->iaoq[0] + 4; + regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */ + + return 1; + } + + return 0; +} + +/* + * parisc hardware trap list + * + * Documented in section 3 "Addressing and Access Control" of the + * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual" + * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf + * + * For implementation see handle_interruption() in traps.c + */ +static const char * const trap_description[] = { + [1] "High-priority machine check (HPMC)", + [2] "Power failure interrupt", + [3] "Recovery counter trap", + [5] "Low-priority machine check", + [6] "Instruction TLB miss fault", + [7] "Instruction access rights / protection trap", + [8] "Illegal instruction trap", + [9] "Break instruction trap", + [10] "Privileged operation trap", + [11] "Privileged register trap", + [12] "Overflow trap", + [13] "Conditional trap", + [14] "FP Assist Exception trap", + [15] "Data TLB miss fault", + [16] "Non-access ITLB miss fault", + [17] "Non-access DTLB miss fault", + [18] "Data memory protection/unaligned access trap", + [19] "Data memory break trap", + [20] "TLB dirty bit trap", + [21] "Page reference trap", + [22] "Assist emulation trap", + [25] "Taken branch trap", + [26] "Data memory access rights trap", + [27] "Data memory protection ID trap", + [28] "Unaligned data reference trap", +}; + +const char *trap_name(unsigned long code) +{ + const char *t = NULL; + + if (code < ARRAY_SIZE(trap_description)) + t = trap_description[code]; + + return t ? t : "Unknown trap"; +} + +/* + * Print out info about fatal segfaults, if the show_unhandled_signals + * sysctl is set: + */ +static inline void +show_signal_msg(struct pt_regs *regs, unsigned long code, + unsigned long address, struct task_struct *tsk, + struct vm_area_struct *vma) +{ + if (!unhandled_signal(tsk, SIGSEGV)) + return; + + if (!printk_ratelimit()) + return; + + pr_warn("\n"); + pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx", + tsk->comm, code, address); + print_vma_addr(KERN_CONT " in ", regs->iaoq[0]); + + pr_cont("\ntrap #%lu: %s%c", code, trap_name(code), + vma ? ',':'\n'); + + if (vma) + pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n", + vma->vm_start, vma->vm_end); + + show_regs(regs); +} + +void do_page_fault(struct pt_regs *regs, unsigned long code, + unsigned long address) +{ + struct vm_area_struct *vma, *prev_vma; + struct task_struct *tsk; + struct mm_struct *mm; + unsigned long acc_type; + vm_fault_t fault = 0; + unsigned int flags; + char *msg; + + tsk = current; + mm = tsk->mm; + if (!mm) { + msg = "Page fault: no context"; + goto no_context; + } + + flags = FAULT_FLAG_DEFAULT; + if (user_mode(regs)) + flags |= FAULT_FLAG_USER; + + acc_type = parisc_acctyp(code, regs->iir); + if (acc_type & VM_WRITE) + flags |= FAULT_FLAG_WRITE; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address); +retry: + mmap_read_lock(mm); + vma = find_vma_prev(mm, address, &prev_vma); + if (!vma || address < vma->vm_start) { + if (!prev_vma || !(prev_vma->vm_flags & VM_GROWSUP)) + goto bad_area; + vma = expand_stack(mm, address); + if (!vma) + goto bad_area_nosemaphore; + } + +/* + * Ok, we have a good vm_area for this memory access. We still need to + * check the access permissions. + */ + + if ((vma->vm_flags & acc_type) != acc_type) + goto bad_area; + + /* + * If for any reason at all we couldn't handle the fault, make + * sure we exit gracefully rather than endlessly redo the + * fault. + */ + + fault = handle_mm_fault(vma, address, flags, regs); + + if (fault_signal_pending(fault, regs)) + return; + + /* The fault is fully completed (including releasing mmap lock) */ + if (fault & VM_FAULT_COMPLETED) + return; + + if (unlikely(fault & VM_FAULT_ERROR)) { + /* + * We hit a shared mapping outside of the file, or some + * other thing happened to us that made us unable to + * handle the page fault gracefully. + */ + if (fault & VM_FAULT_OOM) + goto out_of_memory; + else if (fault & VM_FAULT_SIGSEGV) + goto bad_area; + else if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON| + VM_FAULT_HWPOISON_LARGE)) + goto bad_area; + BUG(); + } + if (fault & VM_FAULT_RETRY) { + /* + * No need to mmap_read_unlock(mm) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + flags |= FAULT_FLAG_TRIED; + goto retry; + } + mmap_read_unlock(mm); + return; + +/* + * Something tried to access memory that isn't in our memory map.. + */ +bad_area: + mmap_read_unlock(mm); + +bad_area_nosemaphore: + if (user_mode(regs)) { + int signo, si_code; + + switch (code) { + case 15: /* Data TLB miss fault/Data page fault */ + /* send SIGSEGV when outside of vma */ + if (!vma || + address < vma->vm_start || address >= vma->vm_end) { + signo = SIGSEGV; + si_code = SEGV_MAPERR; + break; + } + + /* send SIGSEGV for wrong permissions */ + if ((vma->vm_flags & acc_type) != acc_type) { + signo = SIGSEGV; + si_code = SEGV_ACCERR; + break; + } + + /* probably address is outside of mapped file */ + fallthrough; + case 17: /* NA data TLB miss / page fault */ + case 18: /* Unaligned access - PCXS only */ + signo = SIGBUS; + si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR; + break; + case 16: /* Non-access instruction TLB miss fault */ + case 26: /* PCXL: Data memory access rights trap */ + default: + signo = SIGSEGV; + si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR; + break; + } +#ifdef CONFIG_MEMORY_FAILURE + if (fault & (VM_FAULT_HWPOISON|VM_FAULT_HWPOISON_LARGE)) { + unsigned int lsb = 0; + printk(KERN_ERR + "MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n", + tsk->comm, tsk->pid, address); + /* + * Either small page or large page may be poisoned. + * In other words, VM_FAULT_HWPOISON_LARGE and + * VM_FAULT_HWPOISON are mutually exclusive. + */ + if (fault & VM_FAULT_HWPOISON_LARGE) + lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); + else if (fault & VM_FAULT_HWPOISON) + lsb = PAGE_SHIFT; + + force_sig_mceerr(BUS_MCEERR_AR, (void __user *) address, + lsb); + return; + } +#endif + show_signal_msg(regs, code, address, tsk, vma); + + force_sig_fault(signo, si_code, (void __user *) address); + return; + } + msg = "Page fault: bad address"; + +no_context: + + if (!user_mode(regs) && fixup_exception(regs)) { + return; + } + + parisc_terminate(msg, regs, code, address); + +out_of_memory: + mmap_read_unlock(mm); + if (!user_mode(regs)) { + msg = "Page fault: out of memory"; + goto no_context; + } + pagefault_out_of_memory(); +} + +/* Handle non-access data TLB miss faults. + * + * For probe instructions, accesses to userspace are considered allowed + * if they lie in a valid VMA and the access type matches. We are not + * allowed to handle MM faults here so there may be situations where an + * actual access would fail even though a probe was successful. + */ +int +handle_nadtlb_fault(struct pt_regs *regs) +{ + unsigned long insn = regs->iir; + int breg, treg, xreg, val = 0; + struct vm_area_struct *vma; + struct task_struct *tsk; + struct mm_struct *mm; + unsigned long address; + unsigned long acc_type; + + switch (insn & 0x380) { + case 0x280: + /* FDC instruction */ + fallthrough; + case 0x380: + /* PDC and FIC instructions */ + if (DEBUG_NATLB && printk_ratelimit()) { + pr_warn("WARNING: nullifying cache flush/purge instruction\n"); + show_regs(regs); + } + if (insn & 0x20) { + /* Base modification */ + breg = (insn >> 21) & 0x1f; + xreg = (insn >> 16) & 0x1f; + if (breg && xreg) + regs->gr[breg] += regs->gr[xreg]; + } + regs->gr[0] |= PSW_N; + return 1; + + case 0x180: + /* PROBE instruction */ + treg = insn & 0x1f; + if (regs->isr) { + tsk = current; + mm = tsk->mm; + if (mm) { + /* Search for VMA */ + address = regs->ior; + mmap_read_lock(mm); + vma = vma_lookup(mm, address); + mmap_read_unlock(mm); + + /* + * Check if access to the VMA is okay. + * We don't allow for stack expansion. + */ + acc_type = (insn & 0x40) ? VM_WRITE : VM_READ; + if (vma + && (vma->vm_flags & acc_type) == acc_type) + val = 1; + } + } + if (treg) + regs->gr[treg] = val; + regs->gr[0] |= PSW_N; + return 1; + + case 0x300: + /* LPA instruction */ + if (insn & 0x20) { + /* Base modification */ + breg = (insn >> 21) & 0x1f; + xreg = (insn >> 16) & 0x1f; + if (breg && xreg) + regs->gr[breg] += regs->gr[xreg]; + } + treg = insn & 0x1f; + if (treg) + regs->gr[treg] = 0; + regs->gr[0] |= PSW_N; + return 1; + + default: + break; + } + + return 0; +} diff --git a/arch/parisc/mm/fixmap.c b/arch/parisc/mm/fixmap.c new file mode 100644 index 000000000..cc15d737f --- /dev/null +++ b/arch/parisc/mm/fixmap.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * fixmaps for parisc + * + * Copyright (c) 2019 Sven Schnelle <svens@stackframe.org> + */ + +#include <linux/kprobes.h> +#include <linux/mm.h> +#include <asm/cacheflush.h> +#include <asm/fixmap.h> + +void notrace set_fixmap(enum fixed_addresses idx, phys_addr_t phys) +{ + unsigned long vaddr = __fix_to_virt(idx); + pgd_t *pgd = pgd_offset_k(vaddr); + p4d_t *p4d = p4d_offset(pgd, vaddr); + pud_t *pud = pud_offset(p4d, vaddr); + pmd_t *pmd = pmd_offset(pud, vaddr); + pte_t *pte; + + if (pmd_none(*pmd)) + pte = pte_alloc_kernel(pmd, vaddr); + + pte = pte_offset_kernel(pmd, vaddr); + set_pte_at(&init_mm, vaddr, pte, __mk_pte(phys, PAGE_KERNEL_RWX)); + flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); +} + +void notrace clear_fixmap(enum fixed_addresses idx) +{ + unsigned long vaddr = __fix_to_virt(idx); + pte_t *pte = virt_to_kpte(vaddr); + + if (WARN_ON(pte_none(*pte))) + return; + + pte_clear(&init_mm, vaddr, pte); + + flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); +} diff --git a/arch/parisc/mm/hugetlbpage.c b/arch/parisc/mm/hugetlbpage.c new file mode 100644 index 000000000..d1d3990b8 --- /dev/null +++ b/arch/parisc/mm/hugetlbpage.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PARISC64 Huge TLB page support. + * + * This parisc implementation is heavily based on the SPARC and x86 code. + * + * Copyright (C) 2015 Helge Deller <deller@gmx.de> + */ + +#include <linux/fs.h> +#include <linux/mm.h> +#include <linux/sched/mm.h> +#include <linux/hugetlb.h> +#include <linux/pagemap.h> +#include <linux/sysctl.h> + +#include <asm/mman.h> +#include <asm/tlb.h> +#include <asm/tlbflush.h> +#include <asm/cacheflush.h> +#include <asm/mmu_context.h> + + +unsigned long +hugetlb_get_unmapped_area(struct file *file, unsigned long addr, + unsigned long len, unsigned long pgoff, unsigned long flags) +{ + struct hstate *h = hstate_file(file); + + if (len & ~huge_page_mask(h)) + return -EINVAL; + if (len > TASK_SIZE) + return -ENOMEM; + + if (flags & MAP_FIXED) + if (prepare_hugepage_range(file, addr, len)) + return -EINVAL; + + if (addr) + addr = ALIGN(addr, huge_page_size(h)); + + /* we need to make sure the colouring is OK */ + return arch_get_unmapped_area(file, addr, len, pgoff, flags); +} + + +pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma, + unsigned long addr, unsigned long sz) +{ + pgd_t *pgd; + p4d_t *p4d; + pud_t *pud; + pmd_t *pmd; + pte_t *pte = NULL; + + /* We must align the address, because our caller will run + * set_huge_pte_at() on whatever we return, which writes out + * all of the sub-ptes for the hugepage range. So we have + * to give it the first such sub-pte. + */ + addr &= HPAGE_MASK; + + pgd = pgd_offset(mm, addr); + p4d = p4d_offset(pgd, addr); + pud = pud_alloc(mm, p4d, addr); + if (pud) { + pmd = pmd_alloc(mm, pud, addr); + if (pmd) + pte = pte_alloc_map(mm, pmd, addr); + } + return pte; +} + +pte_t *huge_pte_offset(struct mm_struct *mm, + unsigned long addr, unsigned long sz) +{ + pgd_t *pgd; + p4d_t *p4d; + pud_t *pud; + pmd_t *pmd; + pte_t *pte = NULL; + + addr &= HPAGE_MASK; + + pgd = pgd_offset(mm, addr); + if (!pgd_none(*pgd)) { + p4d = p4d_offset(pgd, addr); + if (!p4d_none(*p4d)) { + pud = pud_offset(p4d, addr); + if (!pud_none(*pud)) { + pmd = pmd_offset(pud, addr); + if (!pmd_none(*pmd)) + pte = pte_offset_map(pmd, addr); + } + } + } + return pte; +} + +/* Purge data and instruction TLB entries. Must be called holding + * the pa_tlb_lock. The TLB purge instructions are slow on SMP + * machines since the purge must be broadcast to all CPUs. + */ +static inline void purge_tlb_entries_huge(struct mm_struct *mm, unsigned long addr) +{ + int i; + + /* We may use multiple physical huge pages (e.g. 2x1 MB) to emulate + * Linux standard huge pages (e.g. 2 MB) */ + BUILD_BUG_ON(REAL_HPAGE_SHIFT > HPAGE_SHIFT); + + addr &= HPAGE_MASK; + addr |= _HUGE_PAGE_SIZE_ENCODING_DEFAULT; + + for (i = 0; i < (1 << (HPAGE_SHIFT-REAL_HPAGE_SHIFT)); i++) { + purge_tlb_entries(mm, addr); + addr += (1UL << REAL_HPAGE_SHIFT); + } +} + +/* __set_huge_pte_at() must be called holding the pa_tlb_lock. */ +static void __set_huge_pte_at(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t entry) +{ + unsigned long addr_start; + int i; + + addr &= HPAGE_MASK; + addr_start = addr; + + for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) { + set_pte(ptep, entry); + ptep++; + + addr += PAGE_SIZE; + pte_val(entry) += PAGE_SIZE; + } + + purge_tlb_entries_huge(mm, addr_start); +} + +void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t entry) +{ + __set_huge_pte_at(mm, addr, ptep, entry); +} + + +pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, + pte_t *ptep) +{ + pte_t entry; + + entry = *ptep; + __set_huge_pte_at(mm, addr, ptep, __pte(0)); + + return entry; +} + + +void huge_ptep_set_wrprotect(struct mm_struct *mm, + unsigned long addr, pte_t *ptep) +{ + pte_t old_pte; + + old_pte = *ptep; + __set_huge_pte_at(mm, addr, ptep, pte_wrprotect(old_pte)); +} + +int huge_ptep_set_access_flags(struct vm_area_struct *vma, + unsigned long addr, pte_t *ptep, + pte_t pte, int dirty) +{ + int changed; + struct mm_struct *mm = vma->vm_mm; + + changed = !pte_same(*ptep, pte); + if (changed) { + __set_huge_pte_at(mm, addr, ptep, pte); + } + return changed; +} + + +int pmd_huge(pmd_t pmd) +{ + return 0; +} + +int pud_huge(pud_t pud) +{ + return 0; +} diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c new file mode 100644 index 000000000..b0c43f3b0 --- /dev/null +++ b/arch/parisc/mm/init.c @@ -0,0 +1,893 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/arch/parisc/mm/init.c + * + * Copyright (C) 1995 Linus Torvalds + * Copyright 1999 SuSE GmbH + * changed by Philipp Rumpf + * Copyright 1999 Philipp Rumpf (prumpf@tux.org) + * Copyright 2004 Randolph Chung (tausq@debian.org) + * Copyright 2006-2007 Helge Deller (deller@gmx.de) + * + */ + + +#include <linux/module.h> +#include <linux/mm.h> +#include <linux/memblock.h> +#include <linux/gfp.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/initrd.h> +#include <linux/swap.h> +#include <linux/unistd.h> +#include <linux/nodemask.h> /* for node_online_map */ +#include <linux/pagemap.h> /* for release_pages */ +#include <linux/compat.h> + +#include <asm/pgalloc.h> +#include <asm/tlb.h> +#include <asm/pdc_chassis.h> +#include <asm/mmzone.h> +#include <asm/sections.h> +#include <asm/msgbuf.h> +#include <asm/sparsemem.h> + +extern int data_start; +extern void parisc_kernel_start(void); /* Kernel entry point in head.S */ + +#if CONFIG_PGTABLE_LEVELS == 3 +pmd_t pmd0[PTRS_PER_PMD] __section(".data..vm0.pmd") __attribute__ ((aligned(PAGE_SIZE))); +#endif + +pgd_t swapper_pg_dir[PTRS_PER_PGD] __section(".data..vm0.pgd") __attribute__ ((aligned(PAGE_SIZE))); +pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __section(".data..vm0.pte") __attribute__ ((aligned(PAGE_SIZE))); + +static struct resource data_resource = { + .name = "Kernel data", + .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM, +}; + +static struct resource code_resource = { + .name = "Kernel code", + .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM, +}; + +static struct resource pdcdata_resource = { + .name = "PDC data (Page Zero)", + .start = 0, + .end = 0x9ff, + .flags = IORESOURCE_BUSY | IORESOURCE_MEM, +}; + +static struct resource sysram_resources[MAX_PHYSMEM_RANGES] __ro_after_init; + +/* The following array is initialized from the firmware specific + * information retrieved in kernel/inventory.c. + */ + +physmem_range_t pmem_ranges[MAX_PHYSMEM_RANGES] __initdata; +int npmem_ranges __initdata; + +#ifdef CONFIG_64BIT +#define MAX_MEM (1UL << MAX_PHYSMEM_BITS) +#else /* !CONFIG_64BIT */ +#define MAX_MEM (3584U*1024U*1024U) +#endif /* !CONFIG_64BIT */ + +static unsigned long mem_limit __read_mostly = MAX_MEM; + +static void __init mem_limit_func(void) +{ + char *cp, *end; + unsigned long limit; + + /* We need this before __setup() functions are called */ + + limit = MAX_MEM; + for (cp = boot_command_line; *cp; ) { + if (memcmp(cp, "mem=", 4) == 0) { + cp += 4; + limit = memparse(cp, &end); + if (end != cp) + break; + cp = end; + } else { + while (*cp != ' ' && *cp) + ++cp; + while (*cp == ' ') + ++cp; + } + } + + if (limit < mem_limit) + mem_limit = limit; +} + +#define MAX_GAP (0x40000000UL >> PAGE_SHIFT) + +static void __init setup_bootmem(void) +{ + unsigned long mem_max; +#ifndef CONFIG_SPARSEMEM + physmem_range_t pmem_holes[MAX_PHYSMEM_RANGES - 1]; + int npmem_holes; +#endif + int i, sysram_resource_count; + + disable_sr_hashing(); /* Turn off space register hashing */ + + /* + * Sort the ranges. Since the number of ranges is typically + * small, and performance is not an issue here, just do + * a simple insertion sort. + */ + + for (i = 1; i < npmem_ranges; i++) { + int j; + + for (j = i; j > 0; j--) { + if (pmem_ranges[j-1].start_pfn < + pmem_ranges[j].start_pfn) { + + break; + } + swap(pmem_ranges[j-1], pmem_ranges[j]); + } + } + +#ifndef CONFIG_SPARSEMEM + /* + * Throw out ranges that are too far apart (controlled by + * MAX_GAP). + */ + + for (i = 1; i < npmem_ranges; i++) { + if (pmem_ranges[i].start_pfn - + (pmem_ranges[i-1].start_pfn + + pmem_ranges[i-1].pages) > MAX_GAP) { + npmem_ranges = i; + printk("Large gap in memory detected (%ld pages). " + "Consider turning on CONFIG_SPARSEMEM\n", + pmem_ranges[i].start_pfn - + (pmem_ranges[i-1].start_pfn + + pmem_ranges[i-1].pages)); + break; + } + } +#endif + + /* Print the memory ranges */ + pr_info("Memory Ranges:\n"); + + for (i = 0; i < npmem_ranges; i++) { + struct resource *res = &sysram_resources[i]; + unsigned long start; + unsigned long size; + + size = (pmem_ranges[i].pages << PAGE_SHIFT); + start = (pmem_ranges[i].start_pfn << PAGE_SHIFT); + pr_info("%2d) Start 0x%016lx End 0x%016lx Size %6ld MB\n", + i, start, start + (size - 1), size >> 20); + + /* request memory resource */ + res->name = "System RAM"; + res->start = start; + res->end = start + size - 1; + res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY; + request_resource(&iomem_resource, res); + } + + sysram_resource_count = npmem_ranges; + + /* + * For 32 bit kernels we limit the amount of memory we can + * support, in order to preserve enough kernel address space + * for other purposes. For 64 bit kernels we don't normally + * limit the memory, but this mechanism can be used to + * artificially limit the amount of memory (and it is written + * to work with multiple memory ranges). + */ + + mem_limit_func(); /* check for "mem=" argument */ + + mem_max = 0; + for (i = 0; i < npmem_ranges; i++) { + unsigned long rsize; + + rsize = pmem_ranges[i].pages << PAGE_SHIFT; + if ((mem_max + rsize) > mem_limit) { + printk(KERN_WARNING "Memory truncated to %ld MB\n", mem_limit >> 20); + if (mem_max == mem_limit) + npmem_ranges = i; + else { + pmem_ranges[i].pages = (mem_limit >> PAGE_SHIFT) + - (mem_max >> PAGE_SHIFT); + npmem_ranges = i + 1; + mem_max = mem_limit; + } + break; + } + mem_max += rsize; + } + + printk(KERN_INFO "Total Memory: %ld MB\n",mem_max >> 20); + +#ifndef CONFIG_SPARSEMEM + /* Merge the ranges, keeping track of the holes */ + { + unsigned long end_pfn; + unsigned long hole_pages; + + npmem_holes = 0; + end_pfn = pmem_ranges[0].start_pfn + pmem_ranges[0].pages; + for (i = 1; i < npmem_ranges; i++) { + + hole_pages = pmem_ranges[i].start_pfn - end_pfn; + if (hole_pages) { + pmem_holes[npmem_holes].start_pfn = end_pfn; + pmem_holes[npmem_holes++].pages = hole_pages; + end_pfn += hole_pages; + } + end_pfn += pmem_ranges[i].pages; + } + + pmem_ranges[0].pages = end_pfn - pmem_ranges[0].start_pfn; + npmem_ranges = 1; + } +#endif + + /* + * Initialize and free the full range of memory in each range. + */ + + max_pfn = 0; + for (i = 0; i < npmem_ranges; i++) { + unsigned long start_pfn; + unsigned long npages; + unsigned long start; + unsigned long size; + + start_pfn = pmem_ranges[i].start_pfn; + npages = pmem_ranges[i].pages; + + start = start_pfn << PAGE_SHIFT; + size = npages << PAGE_SHIFT; + + /* add system RAM memblock */ + memblock_add(start, size); + + if ((start_pfn + npages) > max_pfn) + max_pfn = start_pfn + npages; + } + + /* + * We can't use memblock top-down allocations because we only + * created the initial mapping up to KERNEL_INITIAL_SIZE in + * the assembly bootup code. + */ + memblock_set_bottom_up(true); + + /* IOMMU is always used to access "high mem" on those boxes + * that can support enough mem that a PCI device couldn't + * directly DMA to any physical addresses. + * ISA DMA support will need to revisit this. + */ + max_low_pfn = max_pfn; + + /* reserve PAGE0 pdc memory, kernel text/data/bss & bootmap */ + +#define PDC_CONSOLE_IO_IODC_SIZE 32768 + + memblock_reserve(0UL, (unsigned long)(PAGE0->mem_free + + PDC_CONSOLE_IO_IODC_SIZE)); + memblock_reserve(__pa(KERNEL_BINARY_TEXT_START), + (unsigned long)(_end - KERNEL_BINARY_TEXT_START)); + +#ifndef CONFIG_SPARSEMEM + + /* reserve the holes */ + + for (i = 0; i < npmem_holes; i++) { + memblock_reserve((pmem_holes[i].start_pfn << PAGE_SHIFT), + (pmem_holes[i].pages << PAGE_SHIFT)); + } +#endif + +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) { + printk(KERN_INFO "initrd: %08lx-%08lx\n", initrd_start, initrd_end); + if (__pa(initrd_start) < mem_max) { + unsigned long initrd_reserve; + + if (__pa(initrd_end) > mem_max) { + initrd_reserve = mem_max - __pa(initrd_start); + } else { + initrd_reserve = initrd_end - initrd_start; + } + initrd_below_start_ok = 1; + printk(KERN_INFO "initrd: reserving %08lx-%08lx (mem_max %08lx)\n", __pa(initrd_start), __pa(initrd_start) + initrd_reserve, mem_max); + + memblock_reserve(__pa(initrd_start), initrd_reserve); + } + } +#endif + + data_resource.start = virt_to_phys(&data_start); + data_resource.end = virt_to_phys(_end) - 1; + code_resource.start = virt_to_phys(_text); + code_resource.end = virt_to_phys(&data_start)-1; + + /* We don't know which region the kernel will be in, so try + * all of them. + */ + for (i = 0; i < sysram_resource_count; i++) { + struct resource *res = &sysram_resources[i]; + request_resource(res, &code_resource); + request_resource(res, &data_resource); + } + request_resource(&sysram_resources[0], &pdcdata_resource); + + /* Initialize Page Deallocation Table (PDT) and check for bad memory. */ + pdc_pdt_init(); + + memblock_allow_resize(); + memblock_dump_all(); +} + +static bool kernel_set_to_readonly; + +static void __ref map_pages(unsigned long start_vaddr, + unsigned long start_paddr, unsigned long size, + pgprot_t pgprot, int force) +{ + pmd_t *pmd; + pte_t *pg_table; + unsigned long end_paddr; + unsigned long start_pmd; + unsigned long start_pte; + unsigned long tmp1; + unsigned long tmp2; + unsigned long address; + unsigned long vaddr; + unsigned long ro_start; + unsigned long ro_end; + unsigned long kernel_start, kernel_end; + + ro_start = __pa((unsigned long)_text); + ro_end = __pa((unsigned long)&data_start); + kernel_start = __pa((unsigned long)&__init_begin); + kernel_end = __pa((unsigned long)&_end); + + end_paddr = start_paddr + size; + + /* for 2-level configuration PTRS_PER_PMD is 0 so start_pmd will be 0 */ + start_pmd = ((start_vaddr >> PMD_SHIFT) & (PTRS_PER_PMD - 1)); + start_pte = ((start_vaddr >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); + + address = start_paddr; + vaddr = start_vaddr; + while (address < end_paddr) { + pgd_t *pgd = pgd_offset_k(vaddr); + p4d_t *p4d = p4d_offset(pgd, vaddr); + pud_t *pud = pud_offset(p4d, vaddr); + +#if CONFIG_PGTABLE_LEVELS == 3 + if (pud_none(*pud)) { + pmd = memblock_alloc(PAGE_SIZE << PMD_TABLE_ORDER, + PAGE_SIZE << PMD_TABLE_ORDER); + if (!pmd) + panic("pmd allocation failed.\n"); + pud_populate(NULL, pud, pmd); + } +#endif + + pmd = pmd_offset(pud, vaddr); + for (tmp1 = start_pmd; tmp1 < PTRS_PER_PMD; tmp1++, pmd++) { + if (pmd_none(*pmd)) { + pg_table = memblock_alloc(PAGE_SIZE, PAGE_SIZE); + if (!pg_table) + panic("page table allocation failed\n"); + pmd_populate_kernel(NULL, pmd, pg_table); + } + + pg_table = pte_offset_kernel(pmd, vaddr); + for (tmp2 = start_pte; tmp2 < PTRS_PER_PTE; tmp2++, pg_table++) { + pte_t pte; + pgprot_t prot; + bool huge = false; + + if (force) { + prot = pgprot; + } else if (address < kernel_start || address >= kernel_end) { + /* outside kernel memory */ + prot = PAGE_KERNEL; + } else if (!kernel_set_to_readonly) { + /* still initializing, allow writing to RO memory */ + prot = PAGE_KERNEL_RWX; + huge = true; + } else if (address >= ro_start) { + /* Code (ro) and Data areas */ + prot = (address < ro_end) ? + PAGE_KERNEL_EXEC : PAGE_KERNEL; + huge = true; + } else { + prot = PAGE_KERNEL; + } + + pte = __mk_pte(address, prot); + if (huge) + pte = pte_mkhuge(pte); + + if (address >= end_paddr) + break; + + set_pte(pg_table, pte); + + address += PAGE_SIZE; + vaddr += PAGE_SIZE; + } + start_pte = 0; + + if (address >= end_paddr) + break; + } + start_pmd = 0; + } +} + +void __init set_kernel_text_rw(int enable_read_write) +{ + unsigned long start = (unsigned long) __init_begin; + unsigned long end = (unsigned long) &data_start; + + map_pages(start, __pa(start), end-start, + PAGE_KERNEL_RWX, enable_read_write ? 1:0); + + /* force the kernel to see the new page table entries */ + flush_cache_all(); + flush_tlb_all(); +} + +void free_initmem(void) +{ + unsigned long init_begin = (unsigned long)__init_begin; + unsigned long init_end = (unsigned long)__init_end; + unsigned long kernel_end = (unsigned long)&_end; + + /* Remap kernel text and data, but do not touch init section yet. */ + kernel_set_to_readonly = true; + map_pages(init_end, __pa(init_end), kernel_end - init_end, + PAGE_KERNEL, 0); + + /* The init text pages are marked R-X. We have to + * flush the icache and mark them RW- + * + * Do a dummy remap of the data section first (the data + * section is already PAGE_KERNEL) to pull in the TLB entries + * for map_kernel */ + map_pages(init_begin, __pa(init_begin), init_end - init_begin, + PAGE_KERNEL_RWX, 1); + /* now remap at PAGE_KERNEL since the TLB is pre-primed to execute + * map_pages */ + map_pages(init_begin, __pa(init_begin), init_end - init_begin, + PAGE_KERNEL, 1); + + /* force the kernel to see the new TLB entries */ + __flush_tlb_range(0, init_begin, kernel_end); + + /* finally dump all the instructions which were cached, since the + * pages are no-longer executable */ + flush_icache_range(init_begin, init_end); + + free_initmem_default(POISON_FREE_INITMEM); + + /* set up a new led state on systems shipped LED State panel */ + pdc_chassis_send_status(PDC_CHASSIS_DIRECT_BCOMPLETE); +} + + +#ifdef CONFIG_STRICT_KERNEL_RWX +void mark_rodata_ro(void) +{ + /* rodata memory was already mapped with KERNEL_RO access rights by + pagetable_init() and map_pages(). No need to do additional stuff here */ + unsigned long roai_size = __end_ro_after_init - __start_ro_after_init; + + pr_info("Write protected read-only-after-init data: %luk\n", roai_size >> 10); +} +#endif + + +/* + * Just an arbitrary offset to serve as a "hole" between mapping areas + * (between top of physical memory and a potential pcxl dma mapping + * area, and below the vmalloc mapping area). + * + * The current 32K value just means that there will be a 32K "hole" + * between mapping areas. That means that any out-of-bounds memory + * accesses will hopefully be caught. The vmalloc() routines leaves + * a hole of 4kB between each vmalloced area for the same reason. + */ + + /* Leave room for gateway page expansion */ +#if KERNEL_MAP_START < GATEWAY_PAGE_SIZE +#error KERNEL_MAP_START is in gateway reserved region +#endif +#define MAP_START (KERNEL_MAP_START) + +#define VM_MAP_OFFSET (32*1024) +#define SET_MAP_OFFSET(x) ((void *)(((unsigned long)(x) + VM_MAP_OFFSET) \ + & ~(VM_MAP_OFFSET-1))) + +void *parisc_vmalloc_start __ro_after_init; +EXPORT_SYMBOL(parisc_vmalloc_start); + +#ifdef CONFIG_PA11 +unsigned long pcxl_dma_start __ro_after_init; +#endif + +void __init mem_init(void) +{ + /* Do sanity checks on IPC (compat) structures */ + BUILD_BUG_ON(sizeof(struct ipc64_perm) != 48); +#ifndef CONFIG_64BIT + BUILD_BUG_ON(sizeof(struct semid64_ds) != 80); + BUILD_BUG_ON(sizeof(struct msqid64_ds) != 104); + BUILD_BUG_ON(sizeof(struct shmid64_ds) != 104); +#endif +#ifdef CONFIG_COMPAT + BUILD_BUG_ON(sizeof(struct compat_ipc64_perm) != sizeof(struct ipc64_perm)); + BUILD_BUG_ON(sizeof(struct compat_semid64_ds) != 80); + BUILD_BUG_ON(sizeof(struct compat_msqid64_ds) != 104); + BUILD_BUG_ON(sizeof(struct compat_shmid64_ds) != 104); +#endif + + /* Do sanity checks on page table constants */ + BUILD_BUG_ON(PTE_ENTRY_SIZE != sizeof(pte_t)); + BUILD_BUG_ON(PMD_ENTRY_SIZE != sizeof(pmd_t)); + BUILD_BUG_ON(PGD_ENTRY_SIZE != sizeof(pgd_t)); + BUILD_BUG_ON(PAGE_SHIFT + BITS_PER_PTE + BITS_PER_PMD + BITS_PER_PGD + > BITS_PER_LONG); +#if CONFIG_PGTABLE_LEVELS == 3 + BUILD_BUG_ON(PT_INITIAL > PTRS_PER_PMD); +#else + BUILD_BUG_ON(PT_INITIAL > PTRS_PER_PGD); +#endif + +#ifdef CONFIG_64BIT + /* avoid ldil_%L() asm statements to sign-extend into upper 32-bits */ + BUILD_BUG_ON(__PAGE_OFFSET >= 0x80000000); + BUILD_BUG_ON(TMPALIAS_MAP_START >= 0x80000000); +#endif + + high_memory = __va((max_pfn << PAGE_SHIFT)); + set_max_mapnr(max_low_pfn); + memblock_free_all(); + +#ifdef CONFIG_PA11 + if (boot_cpu_data.cpu_type == pcxl2 || boot_cpu_data.cpu_type == pcxl) { + pcxl_dma_start = (unsigned long)SET_MAP_OFFSET(MAP_START); + parisc_vmalloc_start = SET_MAP_OFFSET(pcxl_dma_start + + PCXL_DMA_MAP_SIZE); + } else +#endif + parisc_vmalloc_start = SET_MAP_OFFSET(MAP_START); + +#if 0 + /* + * Do not expose the virtual kernel memory layout to userspace. + * But keep code for debugging purposes. + */ + printk("virtual kernel memory layout:\n" + " vmalloc : 0x%px - 0x%px (%4ld MB)\n" + " fixmap : 0x%px - 0x%px (%4ld kB)\n" + " memory : 0x%px - 0x%px (%4ld MB)\n" + " .init : 0x%px - 0x%px (%4ld kB)\n" + " .data : 0x%px - 0x%px (%4ld kB)\n" + " .text : 0x%px - 0x%px (%4ld kB)\n", + + (void*)VMALLOC_START, (void*)VMALLOC_END, + (VMALLOC_END - VMALLOC_START) >> 20, + + (void *)FIXMAP_START, (void *)(FIXMAP_START + FIXMAP_SIZE), + (unsigned long)(FIXMAP_SIZE / 1024), + + __va(0), high_memory, + ((unsigned long)high_memory - (unsigned long)__va(0)) >> 20, + + __init_begin, __init_end, + ((unsigned long)__init_end - (unsigned long)__init_begin) >> 10, + + _etext, _edata, + ((unsigned long)_edata - (unsigned long)_etext) >> 10, + + _text, _etext, + ((unsigned long)_etext - (unsigned long)_text) >> 10); +#endif +} + +unsigned long *empty_zero_page __ro_after_init; +EXPORT_SYMBOL(empty_zero_page); + +/* + * pagetable_init() sets up the page tables + * + * Note that gateway_init() places the Linux gateway page at page 0. + * Since gateway pages cannot be dereferenced this has the desirable + * side effect of trapping those pesky NULL-reference errors in the + * kernel. + */ +static void __init pagetable_init(void) +{ + int range; + + /* Map each physical memory range to its kernel vaddr */ + + for (range = 0; range < npmem_ranges; range++) { + unsigned long start_paddr; + unsigned long end_paddr; + unsigned long size; + + start_paddr = pmem_ranges[range].start_pfn << PAGE_SHIFT; + size = pmem_ranges[range].pages << PAGE_SHIFT; + end_paddr = start_paddr + size; + + map_pages((unsigned long)__va(start_paddr), start_paddr, + size, PAGE_KERNEL, 0); + } + +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_end && initrd_end > mem_limit) { + printk(KERN_INFO "initrd: mapping %08lx-%08lx\n", initrd_start, initrd_end); + map_pages(initrd_start, __pa(initrd_start), + initrd_end - initrd_start, PAGE_KERNEL, 0); + } +#endif + + empty_zero_page = memblock_alloc(PAGE_SIZE, PAGE_SIZE); + if (!empty_zero_page) + panic("zero page allocation failed.\n"); + +} + +static void __init gateway_init(void) +{ + unsigned long linux_gateway_page_addr; + /* FIXME: This is 'const' in order to trick the compiler + into not treating it as DP-relative data. */ + extern void * const linux_gateway_page; + + linux_gateway_page_addr = LINUX_GATEWAY_ADDR & PAGE_MASK; + + /* + * Setup Linux Gateway page. + * + * The Linux gateway page will reside in kernel space (on virtual + * page 0), so it doesn't need to be aliased into user space. + */ + + map_pages(linux_gateway_page_addr, __pa(&linux_gateway_page), + PAGE_SIZE, PAGE_GATEWAY, 1); +} + +static void __init parisc_bootmem_free(void) +{ + unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0, }; + + max_zone_pfn[0] = memblock_end_of_DRAM(); + + free_area_init(max_zone_pfn); +} + +void __init paging_init(void) +{ + setup_bootmem(); + pagetable_init(); + gateway_init(); + flush_cache_all_local(); /* start with known state */ + flush_tlb_all_local(NULL); + + sparse_init(); + parisc_bootmem_free(); +} + +#ifdef CONFIG_PA20 + +/* + * Currently, all PA20 chips have 18 bit protection IDs, which is the + * limiting factor (space ids are 32 bits). + */ + +#define NR_SPACE_IDS 262144 + +#else + +/* + * Currently we have a one-to-one relationship between space IDs and + * protection IDs. Older parisc chips (PCXS, PCXT, PCXL, PCXL2) only + * support 15 bit protection IDs, so that is the limiting factor. + * PCXT' has 18 bit protection IDs, but only 16 bit spaceids, so it's + * probably not worth the effort for a special case here. + */ + +#define NR_SPACE_IDS 32768 + +#endif /* !CONFIG_PA20 */ + +#define RECYCLE_THRESHOLD (NR_SPACE_IDS / 2) +#define SID_ARRAY_SIZE (NR_SPACE_IDS / (8 * sizeof(long))) + +static unsigned long space_id[SID_ARRAY_SIZE] = { 1 }; /* disallow space 0 */ +static unsigned long dirty_space_id[SID_ARRAY_SIZE]; +static unsigned long space_id_index; +static unsigned long free_space_ids = NR_SPACE_IDS - 1; +static unsigned long dirty_space_ids; + +static DEFINE_SPINLOCK(sid_lock); + +unsigned long alloc_sid(void) +{ + unsigned long index; + + spin_lock(&sid_lock); + + if (free_space_ids == 0) { + if (dirty_space_ids != 0) { + spin_unlock(&sid_lock); + flush_tlb_all(); /* flush_tlb_all() calls recycle_sids() */ + spin_lock(&sid_lock); + } + BUG_ON(free_space_ids == 0); + } + + free_space_ids--; + + index = find_next_zero_bit(space_id, NR_SPACE_IDS, space_id_index); + space_id[BIT_WORD(index)] |= BIT_MASK(index); + space_id_index = index; + + spin_unlock(&sid_lock); + + return index << SPACEID_SHIFT; +} + +void free_sid(unsigned long spaceid) +{ + unsigned long index = spaceid >> SPACEID_SHIFT; + unsigned long *dirty_space_offset, mask; + + dirty_space_offset = &dirty_space_id[BIT_WORD(index)]; + mask = BIT_MASK(index); + + spin_lock(&sid_lock); + + BUG_ON(*dirty_space_offset & mask); /* attempt to free space id twice */ + + *dirty_space_offset |= mask; + dirty_space_ids++; + + spin_unlock(&sid_lock); +} + + +#ifdef CONFIG_SMP +static void get_dirty_sids(unsigned long *ndirtyptr,unsigned long *dirty_array) +{ + int i; + + /* NOTE: sid_lock must be held upon entry */ + + *ndirtyptr = dirty_space_ids; + if (dirty_space_ids != 0) { + for (i = 0; i < SID_ARRAY_SIZE; i++) { + dirty_array[i] = dirty_space_id[i]; + dirty_space_id[i] = 0; + } + dirty_space_ids = 0; + } + + return; +} + +static void recycle_sids(unsigned long ndirty,unsigned long *dirty_array) +{ + int i; + + /* NOTE: sid_lock must be held upon entry */ + + if (ndirty != 0) { + for (i = 0; i < SID_ARRAY_SIZE; i++) { + space_id[i] ^= dirty_array[i]; + } + + free_space_ids += ndirty; + space_id_index = 0; + } +} + +#else /* CONFIG_SMP */ + +static void recycle_sids(void) +{ + int i; + + /* NOTE: sid_lock must be held upon entry */ + + if (dirty_space_ids != 0) { + for (i = 0; i < SID_ARRAY_SIZE; i++) { + space_id[i] ^= dirty_space_id[i]; + dirty_space_id[i] = 0; + } + + free_space_ids += dirty_space_ids; + dirty_space_ids = 0; + space_id_index = 0; + } +} +#endif + +/* + * flush_tlb_all() calls recycle_sids(), since whenever the entire tlb is + * purged, we can safely reuse the space ids that were released but + * not flushed from the tlb. + */ + +#ifdef CONFIG_SMP + +static unsigned long recycle_ndirty; +static unsigned long recycle_dirty_array[SID_ARRAY_SIZE]; +static unsigned int recycle_inuse; + +void flush_tlb_all(void) +{ + int do_recycle; + + do_recycle = 0; + spin_lock(&sid_lock); + __inc_irq_stat(irq_tlb_count); + if (dirty_space_ids > RECYCLE_THRESHOLD) { + BUG_ON(recycle_inuse); /* FIXME: Use a semaphore/wait queue here */ + get_dirty_sids(&recycle_ndirty,recycle_dirty_array); + recycle_inuse++; + do_recycle++; + } + spin_unlock(&sid_lock); + on_each_cpu(flush_tlb_all_local, NULL, 1); + if (do_recycle) { + spin_lock(&sid_lock); + recycle_sids(recycle_ndirty,recycle_dirty_array); + recycle_inuse = 0; + spin_unlock(&sid_lock); + } +} +#else +void flush_tlb_all(void) +{ + spin_lock(&sid_lock); + __inc_irq_stat(irq_tlb_count); + flush_tlb_all_local(NULL); + recycle_sids(); + spin_unlock(&sid_lock); +} +#endif + +static const pgprot_t protection_map[16] = { + [VM_NONE] = PAGE_NONE, + [VM_READ] = PAGE_READONLY, + [VM_WRITE] = PAGE_NONE, + [VM_WRITE | VM_READ] = PAGE_READONLY, + [VM_EXEC] = PAGE_EXECREAD, + [VM_EXEC | VM_READ] = PAGE_EXECREAD, + [VM_EXEC | VM_WRITE] = PAGE_EXECREAD, + [VM_EXEC | VM_WRITE | VM_READ] = PAGE_EXECREAD, + [VM_SHARED] = PAGE_NONE, + [VM_SHARED | VM_READ] = PAGE_READONLY, + [VM_SHARED | VM_WRITE] = PAGE_WRITEONLY, + [VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED, + [VM_SHARED | VM_EXEC] = PAGE_EXECREAD, + [VM_SHARED | VM_EXEC | VM_READ] = PAGE_EXECREAD, + [VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_RWX, + [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_RWX +}; +DECLARE_VM_GET_PAGE_PROT diff --git a/arch/parisc/mm/ioremap.c b/arch/parisc/mm/ioremap.c new file mode 100644 index 000000000..345ff0b66 --- /dev/null +++ b/arch/parisc/mm/ioremap.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * arch/parisc/mm/ioremap.c + * + * (C) Copyright 1995 1996 Linus Torvalds + * (C) Copyright 2001-2019 Helge Deller <deller@gmx.de> + * (C) Copyright 2005 Kyle McMartin <kyle@parisc-linux.org> + */ + +#include <linux/vmalloc.h> +#include <linux/errno.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/mm.h> + +/* + * Generic mapping function (not visible outside): + */ + +/* + * Remap an arbitrary physical address space into the kernel virtual + * address space. + * + * NOTE! We need to allow non-page-aligned mappings too: we will obviously + * have to convert them into an offset in a page-aligned mapping, but the + * caller shouldn't need to know that small detail. + */ +void __iomem *ioremap(unsigned long phys_addr, unsigned long size) +{ + void __iomem *addr; + struct vm_struct *area; + unsigned long offset, last_addr; + pgprot_t pgprot; + +#ifdef CONFIG_EISA + unsigned long end = phys_addr + size - 1; + /* Support EISA addresses */ + if ((phys_addr >= 0x00080000 && end < 0x000fffff) || + (phys_addr >= 0x00500000 && end < 0x03bfffff)) + phys_addr |= F_EXTEND(0xfc000000); +#endif + + /* Don't allow wraparound or zero size */ + last_addr = phys_addr + size - 1; + if (!size || last_addr < phys_addr) + return NULL; + + /* + * Don't allow anybody to remap normal RAM that we're using.. + */ + if (phys_addr < virt_to_phys(high_memory)) { + char *t_addr, *t_end; + struct page *page; + + t_addr = __va(phys_addr); + t_end = t_addr + (size - 1); + + for (page = virt_to_page(t_addr); + page <= virt_to_page(t_end); page++) { + if(!PageReserved(page)) + return NULL; + } + } + + pgprot = __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | + _PAGE_ACCESSED | _PAGE_NO_CACHE); + + /* + * Mappings have to be page-aligned + */ + offset = phys_addr & ~PAGE_MASK; + phys_addr &= PAGE_MASK; + size = PAGE_ALIGN(last_addr + 1) - phys_addr; + + /* + * Ok, go for it.. + */ + area = get_vm_area(size, VM_IOREMAP); + if (!area) + return NULL; + + addr = (void __iomem *) area->addr; + if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size, + phys_addr, pgprot)) { + vunmap(addr); + return NULL; + } + + return (void __iomem *) (offset + (char __iomem *)addr); +} +EXPORT_SYMBOL(ioremap); + +void iounmap(const volatile void __iomem *io_addr) +{ + unsigned long addr = (unsigned long)io_addr & PAGE_MASK; + + if (is_vmalloc_addr((void *)addr)) + vunmap((void *)addr); +} +EXPORT_SYMBOL(iounmap); |