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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
maintainers:
- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
description: |
The CS2000-CP is an extremely versatile system clocking device that
utilizes a programmable phase lock loop.
Link: https://www.cirrus.com/products/cs2000/
properties:
compatible:
enum:
- cirrus,cs2000-cp
clocks:
description:
Common clock binding for CLK_IN, XTI/REF_CLK
maxItems: 2
clock-names:
items:
- const: clk_in
- const: ref_clk
'#clock-cells':
const: 0
reg:
maxItems: 1
cirrus,aux-output-source:
description:
Specifies the function of the auxiliary clock output pin
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
- 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input
- 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output
- 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status
default: 0
cirrus,clock-skip:
description:
This mode allows the PLL to maintain lock even when CLK_IN
has missing pulses for up to 20 ms.
$ref: /schemas/types.yaml#/definitions/flag
cirrus,dynamic-mode:
description:
In dynamic mode, the CLK_IN input is used to drive the
digital PLL of the silicon.
If not given, the static mode shall be used to derive the
output signal directly from the REF_CLK input.
$ref: /schemas/types.yaml#/definitions/flag
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/cirrus,cs2000-cp.h>
i2c@0 {
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clock-controller@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&rcar_sound 0>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>;
};
};
|
