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|
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Multimedia Clock & Reset Controller Binding
maintainers:
- Jeffrey Hugo <quic_jhugo@quicinc.com>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm multimedia clock control module which supports the clocks, resets and
power domains.
properties:
compatible:
enum:
- qcom,mmcc-apq8064
- qcom,mmcc-apq8084
- qcom,mmcc-msm8226
- qcom,mmcc-msm8660
- qcom,mmcc-msm8960
- qcom,mmcc-msm8974
- qcom,mmcc-msm8992
- qcom,mmcc-msm8994
- qcom,mmcc-msm8996
- qcom,mmcc-msm8998
- qcom,mmcc-sdm630
- qcom,mmcc-sdm660
clocks:
minItems: 8
maxItems: 10
clock-names:
minItems: 8
maxItems: 10
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding
vdd-gfx-supply:
description:
Regulator supply for the GPU_GX GDSC
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-apq8064
- qcom,mmcc-msm8960
then:
properties:
clocks:
items:
- description: Board PXO source
- description: PLL 3 clock
- description: PLL 3 Vote clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: DSI phy instance 2 dsi clock
- description: DSI phy instance 2 byte clock
- description: HDMI phy PLL clock
clock-names:
items:
- const: pxo
- const: pll3
- const: pll8_vote
- const: dsi1pll
- const: dsi1pllbyte
- const: dsi2pll
- const: dsi2pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-msm8994
- qcom,mmcc-msm8998
- qcom,mmcc-sdm630
- qcom,mmcc-sdm660
then:
required:
- clocks
- clock-names
- if:
properties:
compatible:
contains:
const: qcom,mmcc-msm8994
then:
properties:
clocks:
items:
- description: Board XO source
- description: Global PLL 0 clock
- description: MMSS NoC AHB clock
- description: GFX3D clock
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: HDMI phy PLL clock
clock-names:
items:
- const: xo
- const: gpll0
- const: mmssnoc_ahb
- const: oxili_gfx3d_clk_src
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
const: qcom,mmcc-msm8996
then:
properties:
clocks:
items:
- description: Board XO source
- description: Global PLL 0 clock
- description: MMSS NoC AHB clock
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: HDMI phy PLL clock
clock-names:
items:
- const: xo
- const: gpll0
- const: gcc_mmss_noc_cfg_ahb_clk
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
const: qcom,mmcc-msm8998
then:
properties:
clocks:
items:
- description: Board XO source
- description: Global PLL 0 clock
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: HDMI phy PLL clock
- description: DisplayPort phy PLL link clock
- description: DisplayPort phy PLL vco clock
- description: Test clock
clock-names:
items:
- const: xo
- const: gpll0
- const: dsi0dsi
- const: dsi0byte
- const: dsi1dsi
- const: dsi1byte
- const: hdmipll
- const: dplink
- const: dpvco
- const: core_bi_pll_test_se
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-sdm630
- qcom,mmcc-sdm660
then:
properties:
clocks:
items:
- description: Board XO source
- description: Board sleep source
- description: Global PLL 0 clock
- description: Global PLL 0 DIV clock
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: DisplayPort phy PLL link clock
- description: DisplayPort phy PLL vco clock
clock-names:
items:
- const: xo
- const: sleep_clk
- const: gpll0
- const: gpll0_div
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
- const: dp_link_2x_clk_divsel_five
- const: dp_vco_divided_clk_src_mux
examples:
# Example for MMCC for MSM8960:
- |
clock-controller@4000000 {
compatible = "qcom,mmcc-msm8960";
reg = <0x4000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
|
