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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car MIPI DSI/CSI-2 Encoder
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
description: |
This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
to four data lanes.
properties:
compatible:
enum:
- renesas,r8a779a0-dsi-csi2-tx # for V3U
reg:
maxItems: 1
clocks:
items:
- description: Functional clock
- description: DSI (and CSI-2) functional clock
- description: PLL reference clock
clock-names:
items:
- const: fck
- const: dsi
- const: pll
power-domains:
maxItems: 1
resets:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Parallel input port
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: DSI/CSI-2 output port
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
required:
- port@0
- port@1
required:
- compatible
- reg
- clocks
- power-domains
- resets
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
#include <dt-bindings/power/r8a779a0-sysc.h>
dsi0: dsi-encoder@fed80000 {
compatible = "renesas,r8a779a0-dsi-csi2-tx";
reg = <0xfed80000 0x10000>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
clocks = <&cpg CPG_MOD 415>,
<&cpg CPG_CORE R8A779A0_CLK_DSI>,
<&cpg CPG_CORE R8A779A0_CLK_CP>;
clock-names = "fck", "dsi", "pll";
resets = <&cpg 415>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&du_out_dsi0>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&sn65dsi86_in>;
};
};
};
};
...
|
