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|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
DECON (Display and Enhancement Controller) is the Display Controller for the
Exynos7 series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
properties:
compatible:
const: samsung,exynos7-decon
clocks:
maxItems: 4
clock-names:
items:
- const: pclk_decon0
- const: aclk_decon0
- const: decon0_eclk
- const: decon0_vclk
display-timings:
$ref: ../panel/display-timings.yaml#
i80-if-timings:
type: object
additionalProperties: false
description: timing configuration for lcd i80 interface support
properties:
cs-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of address signal is enabled until
chip select is enabled.
default: 0
wr-active:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is enabled.
default: 1
wr-hold:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is disabled until write
signal is disabled.
default: 0
wr-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS signal is enabled until
write signal is enabled.
default: 0
interrupts:
items:
- description: FIFO level
- description: VSYNC
- description: LCD system
interrupt-names:
items:
- const: fifo
- const: vsync
- const: lcd_sys
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- interrupts
- interrupt-names
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos7-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
display-controller@13930000 {
compatible = "samsung,exynos7-decon";
reg = <0x13930000 0x1000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
<&clock_disp 101>, /* ACLK_DECON_INT */
<&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
<&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
clock-names = "pclk_decon0",
"aclk_decon0",
"decon0_eclk",
"decon0_vclk";
pinctrl-0 = <&lcd_clk &pwm1_out>;
pinctrl-names = "default";
};
|
