blob: 72c1d9e82c897cc1848cc58cece8298640d4603d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek ADSP mailbox
maintainers:
- Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
description: |
The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
to communicate with ADSP by passing messages through two mailbox channels.
The MTK ADSP mailbox IPC also provides the ability for one processor to
signal the other processor using interrupts.
properties:
compatible:
enum:
- mediatek,mt8195-adsp-mbox
- mediatek,mt8186-adsp-mbox
"#mbox-cells":
const: 0
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- "#mbox-cells"
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
adsp_mailbox0:mailbox@10816000 {
compatible = "mediatek,mt8195-adsp-mbox";
#mbox-cells = <0>;
reg = <0x10816000 0x1000>;
interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
};
|
