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|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm CAMSS ISP
maintainers:
- Robert Foss <robert.foss@linaro.org>
- Todor Tomov <todor.too@gmail.com>
description: |
The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
properties:
compatible:
const: qcom,msm8996-camss
clocks:
minItems: 36
maxItems: 36
clock-names:
items:
- const: top_ahb
- const: ispif_ahb
- const: csiphy0_timer
- const: csiphy1_timer
- const: csiphy2_timer
- const: csi0_ahb
- const: csi0
- const: csi0_phy
- const: csi0_pix
- const: csi0_rdi
- const: csi1_ahb
- const: csi1
- const: csi1_phy
- const: csi1_pix
- const: csi1_rdi
- const: csi2_ahb
- const: csi2
- const: csi2_phy
- const: csi2_pix
- const: csi2_rdi
- const: csi3_ahb
- const: csi3
- const: csi3_phy
- const: csi3_pix
- const: csi3_rdi
- const: ahb
- const: vfe0
- const: csi_vfe0
- const: vfe0_ahb
- const: vfe0_stream
- const: vfe1
- const: csi_vfe1
- const: vfe1_ahb
- const: vfe1_stream
- const: vfe_ahb
- const: vfe_axi
interrupts:
minItems: 10
maxItems: 10
interrupt-names:
items:
- const: csiphy0
- const: csiphy1
- const: csiphy2
- const: csid0
- const: csid1
- const: csid2
- const: csid3
- const: ispif
- const: vfe0
- const: vfe1
iommus:
maxItems: 4
power-domains:
items:
- description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
- description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
CSI input ports.
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
description:
An array of physical data lanes indexes.
Position of an entry determines the logical
lane number, while the value of an entry
indicates physical lane index. Lane swapping
is supported. Physical lane indexes are;
0, 1, 2, 3
minItems: 1
maxItems: 4
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
port@2:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
port@3:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
reg:
minItems: 14
maxItems: 14
reg-names:
items:
- const: csiphy0
- const: csiphy0_clk_mux
- const: csiphy1
- const: csiphy1_clk_mux
- const: csiphy2
- const: csiphy2_clk_mux
- const: csid0
- const: csid1
- const: csid2
- const: csid3
- const: ispif
- const: csi_clk_mux
- const: vfe0
- const: vfe1
vdda-supply:
description:
Definition of the regulator used as analog power supply.
required:
- clock-names
- clocks
- compatible
- interrupt-names
- interrupts
- iommus
- power-domains
- reg
- reg-names
- vdda-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
camss: camss@a00000 {
compatible = "qcom,msm8996-camss";
clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
<&mmcc CAMSS_ISPIF_AHB_CLK>,
<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
<&mmcc CAMSS_CSI0_AHB_CLK>,
<&mmcc CAMSS_CSI0_CLK>,
<&mmcc CAMSS_CSI0PHY_CLK>,
<&mmcc CAMSS_CSI0PIX_CLK>,
<&mmcc CAMSS_CSI0RDI_CLK>,
<&mmcc CAMSS_CSI1_AHB_CLK>,
<&mmcc CAMSS_CSI1_CLK>,
<&mmcc CAMSS_CSI1PHY_CLK>,
<&mmcc CAMSS_CSI1PIX_CLK>,
<&mmcc CAMSS_CSI1RDI_CLK>,
<&mmcc CAMSS_CSI2_AHB_CLK>,
<&mmcc CAMSS_CSI2_CLK>,
<&mmcc CAMSS_CSI2PHY_CLK>,
<&mmcc CAMSS_CSI2PIX_CLK>,
<&mmcc CAMSS_CSI2RDI_CLK>,
<&mmcc CAMSS_CSI3_AHB_CLK>,
<&mmcc CAMSS_CSI3_CLK>,
<&mmcc CAMSS_CSI3PHY_CLK>,
<&mmcc CAMSS_CSI3PIX_CLK>,
<&mmcc CAMSS_CSI3RDI_CLK>,
<&mmcc CAMSS_AHB_CLK>,
<&mmcc CAMSS_VFE0_CLK>,
<&mmcc CAMSS_CSI_VFE0_CLK>,
<&mmcc CAMSS_VFE0_AHB_CLK>,
<&mmcc CAMSS_VFE0_STREAM_CLK>,
<&mmcc CAMSS_VFE1_CLK>,
<&mmcc CAMSS_CSI_VFE1_CLK>,
<&mmcc CAMSS_VFE1_AHB_CLK>,
<&mmcc CAMSS_VFE1_STREAM_CLK>,
<&mmcc CAMSS_VFE_AHB_CLK>,
<&mmcc CAMSS_VFE_AXI_CLK>;
clock-names = "top_ahb",
"ispif_ahb",
"csiphy0_timer",
"csiphy1_timer",
"csiphy2_timer",
"csi0_ahb",
"csi0",
"csi0_phy",
"csi0_pix",
"csi0_rdi",
"csi1_ahb",
"csi1",
"csi1_phy",
"csi1_pix",
"csi1_rdi",
"csi2_ahb",
"csi2",
"csi2_phy",
"csi2_pix",
"csi2_rdi",
"csi3_ahb",
"csi3",
"csi3_phy",
"csi3_pix",
"csi3_rdi",
"ahb",
"vfe0",
"csi_vfe0",
"vfe0_ahb",
"vfe0_stream",
"vfe1",
"csi_vfe1",
"vfe1_ahb",
"vfe1_stream",
"vfe_ahb",
"vfe_axi";
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0",
"csiphy1",
"csiphy2",
"csid0",
"csid1",
"csid2",
"csid3",
"ispif",
"vfe0",
"vfe1";
iommus = <&vfe_smmu 0>,
<&vfe_smmu 1>,
<&vfe_smmu 2>,
<&vfe_smmu 3>;
power-domains = <&mmcc VFE0_GDSC>,
<&mmcc VFE1_GDSC>;
reg = <0x00a34000 0x1000>,
<0x00a00030 0x4>,
<0x00a35000 0x1000>,
<0x00a00038 0x4>,
<0x00a36000 0x1000>,
<0x00a00040 0x4>,
<0x00a30000 0x100>,
<0x00a30400 0x100>,
<0x00a30800 0x100>,
<0x00a30c00 0x100>,
<0x00a31000 0x500>,
<0x00a00020 0x10>,
<0x00a10000 0x1000>,
<0x00a14000 0x1000>;
reg-names = "csiphy0",
"csiphy0_clk_mux",
"csiphy1",
"csiphy1_clk_mux",
"csiphy2",
"csiphy2_clk_mux",
"csid0",
"csid1",
"csid2",
"csid3",
"ispif",
"csi_clk_mux",
"vfe0",
"vfe1";
vdda-supply = <®_2v8>;
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
|
