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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title:
Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
Storage Host Controller
maintainers:
- Jaehoon Chung <jh80.chung@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
enum:
- samsung,exynos4210-dw-mshc
- samsung,exynos4412-dw-mshc
- samsung,exynos5250-dw-mshc
- samsung,exynos5420-dw-mshc
- samsung,exynos5420-dw-mshc-smu
- samsung,exynos7-dw-mshc
- samsung,exynos7-dw-mshc-smu
- axis,artpec8-dw-mshc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 2
description:
Handle to "biu" and "ciu" clocks for the
bus interface unit clock and the card interface unit clock.
clock-names:
items:
- const: biu
- const: ciu
samsung,dw-mshc-ciu-div:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
description:
The divider value for the card interface unit (ciu) clock.
samsung,dw-mshc-ddr-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: CIU clock phase shift value for tx mode
minimum: 0
maximum: 7
- description: CIU clock phase shift value for rx mode
minimum: 0
maximum: 7
description:
The value of CUI clock phase shift value in transmit mode and CIU clock
phase shift value in receive mode for double data rate mode operation.
See also samsung,dw-mshc-hs400-timing property.
samsung,dw-mshc-hs400-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: CIU clock phase shift value for tx mode
minimum: 0
maximum: 7
- description: CIU clock phase shift value for rx mode
minimum: 0
maximum: 7
description: |
The value of CIU TX and RX clock phase shift value for HS400 mode
operation.
Valid values for SDR and DDR CIU clock timing::
- valid value for tx phase shift and rx phase shift is 0 to 7.
- when CIU clock divider value is set to 3, all possible 8 phase shift
values can be used.
- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
phase shift clocks should be 0.
If missing, values from samsung,dw-mshc-ddr-timing property are used.
samsung,dw-mshc-sdr-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: CIU clock phase shift value for tx mode
minimum: 0
maximum: 7
- description: CIU clock phase shift value for rx mode
minimum: 0
maximum: 7
description:
The value of CIU clock phase shift value in transmit mode and CIU clock
phase shift value in receive mode for single data rate mode operation.
See also samsung,dw-mshc-hs400-timing property.
samsung,read-strobe-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
line in Read path). If missing, default from hardware is used.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- samsung,dw-mshc-ddr-timing
- samsung,dw-mshc-sdr-timing
allOf:
- $ref: "synopsys-dw-mshc-common.yaml#"
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5250-dw-mshc
- samsung,exynos5420-dw-mshc
- samsung,exynos7-dw-mshc
- samsung,exynos7-dw-mshc-smu
- axis,artpec8-dw-mshc
then:
required:
- samsung,dw-mshc-ciu-div
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5420.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mmc@12220000 {
compatible = "samsung,exynos5420-dw-mshc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <200000000>;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
|
