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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mixel LVDS PHY for Freescale i.MX8qm SoC
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
It converts two groups of four 7/10 bits of CMOS data into two
groups of four data lanes of LVDS data streams. A phase-locked
transmit clock is transmitted in parallel with each group of
data streams over a fifth LVDS link. Every cycle of the transmit
clock, 56/80 bits of input data are sampled and transmitted
through the two groups of LVDS data streams. Together with the
transmit clocks, the two groups of LVDS data streams form two
LVDS channels.
The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
by Control and Status Registers(CSR) module in the SoC. The CSR
module, as a system controller, contains the PHY's registers.
properties:
compatible:
enum:
- fsl,imx8qm-lvds-phy
- mixel,28fdsoi-lvds-1250-8ch-tx-pll
"#phy-cells":
const: 1
description: |
Cell allows setting the LVDS channel index of the PHY.
Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
clocks:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- "#phy-cells"
- clocks
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/firmware/imx/rsrc.h>
phy {
compatible = "fsl,imx8qm-lvds-phy";
#phy-cells = <1>;
clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
power-domains = <&pd IMX_SC_R_LVDS_0>;
};
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