1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
|
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
maintainers:
- Mark Brown <broonie@kernel.org>
allOf:
- $ref: "spi-controller.yaml#"
- if:
properties:
compatible:
contains:
enum:
- mscc,ocelot-spi
- mscc,jaguar2-spi
then:
properties:
reg:
minItems: 2
- if:
properties:
compatible:
contains:
enum:
- baikal,bt1-sys-ssi
then:
properties:
mux-controls:
maxItems: 1
required:
- mux-controls
else:
required:
- interrupts
properties:
compatible:
oneOf:
- description: Generic DW SPI Controller
enum:
- snps,dw-apb-ssi
- snps,dwc-ssi-1.01a
- description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
items:
- enum:
- mscc,ocelot-spi
- mscc,jaguar2-spi
- const: snps,dw-apb-ssi
- description: Microchip Sparx5 SoC SPI Controller
const: microchip,sparx5-spi
- description: Amazon Alpine SPI Controller
const: amazon,alpine-dw-apb-ssi
- description: Renesas RZ/N1 SPI Controller
items:
- const: renesas,rzn1-spi
- const: snps,dw-apb-ssi
- description: Intel Keem Bay SPI Controller
const: intel,keembay-ssi
- description: Intel Thunder Bay SPI Controller
const: intel,thunderbay-ssi
- description: Baikal-T1 SPI Controller
const: baikal,bt1-ssi
- description: Baikal-T1 System Boot SPI Controller
const: baikal,bt1-sys-ssi
- description: Canaan Kendryte K210 SoS SPI Controller
const: canaan,k210-spi
- description: Renesas RZ/N1 SPI Controller
items:
- enum:
- renesas,r9a06g032-spi # RZ/N1D
- renesas,r9a06g033-spi # RZ/N1S
- const: renesas,rzn1-spi # RZ/N1
reg:
minItems: 1
items:
- description: DW APB SSI controller memory mapped registers
- description: SPI MST region map or directly mapped SPI ROM
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: SPI Controller reference clock source
- description: APB interface clock source
clock-names:
minItems: 1
items:
- const: ssi_clk
- const: pclk
resets:
maxItems: 1
reset-names:
const: spi
reg-io-width:
description: I/O register width (in bytes) implemented by this device
default: 4
enum: [ 2, 4 ]
num-cs:
default: 4
minimum: 1
maximum: 4
dmas:
items:
- description: TX DMA Channel
- description: RX DMA Channel
dma-names:
items:
- const: tx
- const: rx
rx-sample-delay-ns:
default: 0
description: |
Default value of the rx-sample-delay-ns property.
This value will be used if the property is not explicitly defined
for a SPI slave device.
SPI Rx sample delay offset, unit is nanoseconds.
The delay from the default sample time before the actual sample of the
rxd input signal occurs. The "rx_sample_delay" is an optional feature
of the designware controller, and the upper limit is also subject to
controller configuration.
patternProperties:
"^.*@[0-9a-f]+$":
type: object
properties:
reg:
minimum: 0
maximum: 3
unevaluatedProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- clocks
examples:
- |
spi@fff00000 {
compatible = "snps,dw-apb-ssi";
reg = <0xfff00000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 154 4>;
clocks = <&spi_m_clk>;
num-cs = <2>;
cs-gpios = <&gpio0 13 0>,
<&gpio0 14 0>;
rx-sample-delay-ns = <3>;
flash@1 {
compatible = "spi-nand";
reg = <1>;
rx-sample-delay-ns = <7>;
};
};
- |
spi@1f040100 {
compatible = "baikal,bt1-sys-ssi";
reg = <0x1f040100 0x900>,
<0x1c000000 0x1000000>;
#address-cells = <1>;
#size-cells = <0>;
mux-controls = <&boot_mux>;
clocks = <&ccu_sys>;
clock-names = "ssi_clk";
};
...
|