1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Linaro Ltd.
* Copyright (c) 2013 HiSilicon Limited.
*/
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include "core.h"
/* Sysctrl registers in Hi3620 SoC */
#define SCISOEN 0xc0
#define SCISODIS 0xc4
#define SCPERPWREN 0xd0
#define SCPERPWRDIS 0xd4
#define SCCPUCOREEN 0xf4
#define SCCPUCOREDIS 0xf8
#define SCPERCTRL0 0x200
#define SCCPURSTEN 0x410
#define SCCPURSTDIS 0x414
/*
* bit definition in SCISOEN/SCPERPWREN/...
*
* CPU2_ISO_CTRL (1 << 5)
* CPU3_ISO_CTRL (1 << 6)
* ...
*/
#define CPU2_ISO_CTRL (1 << 5)
/*
* bit definition in SCPERCTRL0
*
* CPU0_WFI_MASK_CFG (1 << 28)
* CPU1_WFI_MASK_CFG (1 << 29)
* ...
*/
#define CPU0_WFI_MASK_CFG (1 << 28)
/*
* bit definition in SCCPURSTEN/...
*
* CPU0_SRST_REQ_EN (1 << 0)
* CPU1_SRST_REQ_EN (1 << 1)
* ...
*/
#define CPU0_HPM_SRST_REQ_EN (1 << 22)
#define CPU0_DBG_SRST_REQ_EN (1 << 12)
#define CPU0_NEON_SRST_REQ_EN (1 << 4)
#define CPU0_SRST_REQ_EN (1 << 0)
#define HIX5HD2_PERI_CRG20 0x50
#define CRG20_CPU1_RESET (1 << 17)
#define HIX5HD2_PERI_PMC0 0x1000
#define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
#define PMC0_CPU1_PMC_ENABLE (1 << 7)
#define PMC0_CPU1_POWERDOWN (1 << 3)
#define HIP01_PERI9 0x50
#define PERI9_CPU1_RESET (1 << 1)
enum {
HI3620_CTRL,
ERROR_CTRL,
};
static void __iomem *ctrl_base;
static int id;
static void set_cpu_hi3620(int cpu, bool enable)
{
u32 val = 0;
if (enable) {
/* MTCMOS set */
if ((cpu == 2) || (cpu == 3))
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCPERPWREN);
udelay(100);
/* Enable core */
writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
/* unreset */
val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
| CPU0_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
/* reset */
val |= CPU0_HPM_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
/* ISO disable */
if ((cpu == 2) || (cpu == 3))
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCISODIS);
udelay(1);
/* WFI Mask */
val = readl_relaxed(ctrl_base + SCPERCTRL0);
val &= ~(CPU0_WFI_MASK_CFG << cpu);
writel_relaxed(val, ctrl_base + SCPERCTRL0);
/* Unreset */
val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
} else {
/* wfi mask */
val = readl_relaxed(ctrl_base + SCPERCTRL0);
val |= (CPU0_WFI_MASK_CFG << cpu);
writel_relaxed(val, ctrl_base + SCPERCTRL0);
/* disable core*/
writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
if ((cpu == 2) || (cpu == 3)) {
/* iso enable */
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCISOEN);
udelay(1);
}
/* reset */
val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
if ((cpu == 2) || (cpu == 3)) {
/* MTCMOS unset */
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCPERPWRDIS);
udelay(100);
}
}
}
static int hi3xxx_hotplug_init(void)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!node) {
id = ERROR_CTRL;
return -ENOENT;
}
ctrl_base = of_iomap(node, 0);
of_node_put(node);
if (!ctrl_base) {
id = ERROR_CTRL;
return -ENOMEM;
}
id = HI3620_CTRL;
return 0;
}
void hi3xxx_set_cpu(int cpu, bool enable)
{
if (!ctrl_base) {
if (hi3xxx_hotplug_init() < 0)
return;
}
if (id == HI3620_CTRL)
set_cpu_hi3620(cpu, enable);
}
static bool hix5hd2_hotplug_init(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
if (!np)
return false;
ctrl_base = of_iomap(np, 0);
of_node_put(np);
if (!ctrl_base)
return false;
return true;
}
void hix5hd2_set_cpu(int cpu, bool enable)
{
u32 val = 0;
if (!ctrl_base)
if (!hix5hd2_hotplug_init())
BUG();
if (enable) {
/* power on cpu1 */
val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
val |= PMC0_CPU1_PMC_ENABLE;
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
/* unreset */
val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
val &= ~CRG20_CPU1_RESET;
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
} else {
/* power down cpu1 */
val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
/* reset */
val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
val |= CRG20_CPU1_RESET;
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
}
}
void hip01_set_cpu(int cpu, bool enable)
{
unsigned int temp;
struct device_node *np;
if (!ctrl_base) {
np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
BUG_ON(!np);
ctrl_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!ctrl_base);
}
if (enable) {
/* reset on CPU1 */
temp = readl_relaxed(ctrl_base + HIP01_PERI9);
temp |= PERI9_CPU1_RESET;
writel_relaxed(temp, ctrl_base + HIP01_PERI9);
udelay(50);
/* unreset on CPU1 */
temp = readl_relaxed(ctrl_base + HIP01_PERI9);
temp &= ~PERI9_CPU1_RESET;
writel_relaxed(temp, ctrl_base + HIP01_PERI9);
}
}
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
flush_cache_all();
/*
* Turn off coherency and L1 D-cache
*/
asm volatile(
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, #0x40\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, #0x04\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0)
: "cc");
}
#ifdef CONFIG_HOTPLUG_CPU
void hi3xxx_cpu_die(unsigned int cpu)
{
cpu_enter_lowpower();
hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
cpu_do_idle();
/* We should have never returned from idle */
panic("cpu %d unexpectedly exit from shutdown\n", cpu);
}
int hi3xxx_cpu_kill(unsigned int cpu)
{
unsigned long timeout = jiffies + msecs_to_jiffies(50);
while (hi3xxx_get_cpu_jump(cpu))
if (time_after(jiffies, timeout))
return 0;
hi3xxx_set_cpu(cpu, false);
return 1;
}
void hix5hd2_cpu_die(unsigned int cpu)
{
flush_cache_all();
hix5hd2_set_cpu(cpu, false);
}
#endif
|
