1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
|
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dc_bios_types.h"
#include "dcn30_vpg.h"
#include "reg_helper.h"
#define DC_LOGGER \
vpg3->base.ctx->logger
#define REG(reg)\
(vpg3->regs->reg)
#undef FN
#define FN(reg_name, field_name) \
vpg3->vpg_shift->field_name, vpg3->vpg_mask->field_name
#define CTX \
vpg3->base.ctx
void vpg3_update_generic_info_packet(
struct vpg *vpg,
uint32_t packet_index,
const struct dc_info_packet *info_packet,
bool immediate_update)
{
struct dcn30_vpg *vpg3 = DCN30_VPG_FROM_VPG(vpg);
uint32_t i;
/* TODOFPGA Figure out a proper number for max_retries polling for lock
* use 50 for now.
*/
uint32_t max_retries = 50;
if (packet_index > 14)
ASSERT(0);
/* poll dig_update_lock is not locked -> asic internal signal
* assume otg master lock will unlock it
*/
/* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
* 0, 10, max_retries);
*/
/* TODO: Check if this is required */
/* check if HW reading GSP memory */
REG_WAIT(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED,
0, 10, max_retries);
/* HW does is not reading GSP memory not reading too long ->
* something wrong. clear GPS memory access and notify?
* hw SW is writing to GSP memory
*/
REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1);
/* choose which generic packet to use */
REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL,
VPG_GENERIC_DATA_INDEX, packet_index*9);
/* write generic packet header
* (4th byte is for GENERIC0 only)
*/
REG_SET_4(VPG_GENERIC_PACKET_DATA, 0,
VPG_GENERIC_DATA_BYTE0, info_packet->hb0,
VPG_GENERIC_DATA_BYTE1, info_packet->hb1,
VPG_GENERIC_DATA_BYTE2, info_packet->hb2,
VPG_GENERIC_DATA_BYTE3, info_packet->hb3);
/* write generic packet contents
* (we never use last 4 bytes)
* there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
*/
{
const uint32_t *content =
(const uint32_t *) &info_packet->sb[0];
for (i = 0; i < 8; i++) {
REG_WRITE(VPG_GENERIC_PACKET_DATA, *content++);
}
}
/* atomically update double-buffered GENERIC0 registers in immediate mode
* (update at next block_update when block_update_lock == 0).
*/
if (immediate_update) {
switch (packet_index) {
case 0:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC0_IMMEDIATE_UPDATE, 1);
break;
case 1:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC1_IMMEDIATE_UPDATE, 1);
break;
case 2:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC2_IMMEDIATE_UPDATE, 1);
break;
case 3:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC3_IMMEDIATE_UPDATE, 1);
break;
case 4:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC4_IMMEDIATE_UPDATE, 1);
break;
case 5:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC5_IMMEDIATE_UPDATE, 1);
break;
case 6:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC6_IMMEDIATE_UPDATE, 1);
break;
case 7:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC7_IMMEDIATE_UPDATE, 1);
break;
case 8:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC8_IMMEDIATE_UPDATE, 1);
break;
case 9:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC9_IMMEDIATE_UPDATE, 1);
break;
case 10:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC10_IMMEDIATE_UPDATE, 1);
break;
case 11:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC11_IMMEDIATE_UPDATE, 1);
break;
case 12:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC12_IMMEDIATE_UPDATE, 1);
break;
case 13:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC13_IMMEDIATE_UPDATE, 1);
break;
case 14:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC14_IMMEDIATE_UPDATE, 1);
break;
default:
break;
}
} else {
switch (packet_index) {
case 0:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC0_FRAME_UPDATE, 1);
break;
case 1:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC1_FRAME_UPDATE, 1);
break;
case 2:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC2_FRAME_UPDATE, 1);
break;
case 3:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC3_FRAME_UPDATE, 1);
break;
case 4:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC4_FRAME_UPDATE, 1);
break;
case 5:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC5_FRAME_UPDATE, 1);
break;
case 6:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC6_FRAME_UPDATE, 1);
break;
case 7:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC7_FRAME_UPDATE, 1);
break;
case 8:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC8_FRAME_UPDATE, 1);
break;
case 9:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC9_FRAME_UPDATE, 1);
break;
case 10:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC10_FRAME_UPDATE, 1);
break;
case 11:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC11_FRAME_UPDATE, 1);
break;
case 12:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC12_FRAME_UPDATE, 1);
break;
case 13:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC13_FRAME_UPDATE, 1);
break;
case 14:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC14_FRAME_UPDATE, 1);
break;
default:
break;
}
}
}
static struct vpg_funcs dcn30_vpg_funcs = {
.update_generic_info_packet = vpg3_update_generic_info_packet,
};
void vpg3_construct(struct dcn30_vpg *vpg3,
struct dc_context *ctx,
uint32_t inst,
const struct dcn30_vpg_registers *vpg_regs,
const struct dcn30_vpg_shift *vpg_shift,
const struct dcn30_vpg_mask *vpg_mask)
{
vpg3->base.ctx = ctx;
vpg3->base.inst = inst;
vpg3->base.funcs = &dcn30_vpg_funcs;
vpg3->regs = vpg_regs;
vpg3->vpg_shift = vpg_shift;
vpg3->vpg_mask = vpg_mask;
}
|
