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-rw-r--r--arch/arm/boot/dts/dra72-evm.dts127
1 files changed, 127 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
new file mode 100644
index 000000000..5f62f92eb
--- /dev/null
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#include "dra72-evm-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
+/ {
+ model = "TI DRA722";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_memory_region: dsp1-memory@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
+ evm_1v8_sw: fixedregulator-evm_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&smps4_reg>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&i2c1 {
+ tps65917: tps65917@58 {
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+ };
+};
+
+#include "dra72-evm-tps65917.dtsi"
+
+&hdmi {
+ vdda-supply = <&ldo3_reg>;
+};
+
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&mac_sw {
+ mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&cpsw_port1 {
+ phy-handle = <&ethphy0>;
+ phy-mode = "rgmii";
+ ti,dual-emac-pvid = <1>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&davinci_mdio_sw {
+ ethphy0: ethernet-phy@3 {
+ reg = <3>;
+ };
+};
+
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
+ vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev10>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
+ vmmc-supply = <&evm_1v8_sw>;
+};
+
+&ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_memory_region>;
+};
+
+&ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_memory_region>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_memory_region>;
+};