Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Xilinx LogiCORE Partial Reconfig Decoupler Softcore

The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
decouplers / fpga bridges.
The controller can decouple/disable the bridges which prevents signal
changes from passing through the bridge.  The controller can also
couple / enable the bridges which allows traffic to pass through the
bridge normally.

The Driver supports only MMIO handling. A PR region can have multiple
PR Decouplers which can be handled independently or chained via decouple/
decouple_status signals.

Required properties:
- compatible		: Should contain "xlnx,pr-decoupler-1.00" followed by
                          "xlnx,pr-decoupler"
- regs			: base address and size for decoupler module
- clocks		: input clock to IP
- clock-names		: should contain "aclk"

See Documentation/devicetree/bindings/fpga/fpga-region.txt and
Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.

Example:
	fpga-bridge@100000450 {
		compatible = "xlnx,pr-decoupler-1.00",
			     "xlnx-pr-decoupler";
		regs = <0x10000045 0x10>;
		clocks = <&clkc 15>;
		clock-names = "aclk";
		bridge-enable = <0>;
	};