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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 13:14:44 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-27 13:14:44 +0000 |
| commit | 30ff6afe596eddafacf22b1a5b2d1a3d6254ea15 (patch) | |
| tree | 9b788335f92174baf7ee18f03ca8330b8c19ce2b /tests/expected/lscpu/lscpu-x86_64-dell_e4310 | |
| parent | Initial commit. (diff) | |
| download | util-linux-30ff6afe596eddafacf22b1a5b2d1a3d6254ea15.tar.xz util-linux-30ff6afe596eddafacf22b1a5b2d1a3d6254ea15.zip | |
Adding upstream version 2.36.1.upstream/2.36.1upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'tests/expected/lscpu/lscpu-x86_64-dell_e4310')
| -rw-r--r-- | tests/expected/lscpu/lscpu-x86_64-dell_e4310 | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/tests/expected/lscpu/lscpu-x86_64-dell_e4310 b/tests/expected/lscpu/lscpu-x86_64-dell_e4310 new file mode 100644 index 0000000..f62bc3f --- /dev/null +++ b/tests/expected/lscpu/lscpu-x86_64-dell_e4310 @@ -0,0 +1,42 @@ +CPU op-mode(s): 32-bit, 64-bit +Address sizes: 36 bits physical, 48 bits virtual +CPU(s): 4 +On-line CPU(s) list: 0-3 +Thread(s) per core: 2 +Core(s) per socket: 2 +Socket(s): 1 +NUMA node(s): 1 +Vendor ID: GenuineIntel +CPU family: 6 +Model: 37 +Model name: Intel(R) Core(TM) i5 CPU M 560 @ 2.67GHz +Stepping: 5 +CPU MHz: 1199.000 +CPU max MHz: 2667.0000 +CPU min MHz: 1199.0000 +BogoMIPS: 5319.92 +Virtualization: VT-x +L1d cache: 64 KiB +L1i cache: 64 KiB +L2 cache: 512 KiB +L3 cache: 3 MiB +NUMA node0 CPU(s): 0-3 +Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 popcnt aes lahf_lm ida arat dts tpr_shadow vnmi flexpriority ept vpid + +# The following is the parsable format, which can be fed to other +# programs. Each different item in every column has an unique ID +# starting from zero. +# CPU,Core,Socket,Node,,L1d,L1i,L2,L3 +0,0,0,0,,0,0,0,0 +1,1,0,0,,1,1,1,0 +2,0,0,0,,0,0,0,0 +3,1,0,0,,1,1,1,0 + +# The following is the parsable format, which can be fed to other +# programs. Each different item in every column has an unique ID +# starting from zero. +# CPU,Core,Socket,Node,,L1d,L1i,L2,L3 +0,0,0,0,,0,0,0,0 +1,2,0,0,,1,1,1,0 +2,0,0,0,,0,0,0,0 +3,2,0,0,,1,1,1,0 |